2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
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8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
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12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
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18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
59 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
60 (1 << PROGRAM_CONSTANT) | \
61 (1 << PROGRAM_UNIFORM))
63 #define MAX_GLSL_TEXTURE_OFFSET 4
68 static int swizzle_for_size(int size
);
70 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
72 unsigned num_elements
= 4;
75 type
= type
->without_array();
76 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
77 num_elements
= type
->vector_elements
;
80 int swizzle
= swizzle_for_size(num_elements
);
81 assert(num_elements
+ component
<= 4);
83 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
88 * This struct is a corresponding struct to TGSI ureg_src.
92 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
93 int component
= 0, unsigned array_id
= 0)
95 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
98 this->swizzle
= swizzle_for_type(type
, component
);
101 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
102 this->reladdr
= NULL
;
103 this->reladdr2
= NULL
;
104 this->has_index2
= false;
105 this->double_reg2
= false;
106 this->array_id
= array_id
;
107 this->is_double_vertex_input
= false;
110 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
112 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
117 this->swizzle
= SWIZZLE_XYZW
;
119 this->reladdr
= NULL
;
120 this->reladdr2
= NULL
;
121 this->has_index2
= false;
122 this->double_reg2
= false;
124 this->is_double_vertex_input
= false;
127 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
129 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
133 this->index2D
= index2D
;
134 this->swizzle
= SWIZZLE_XYZW
;
136 this->reladdr
= NULL
;
137 this->reladdr2
= NULL
;
138 this->has_index2
= false;
139 this->double_reg2
= false;
141 this->is_double_vertex_input
= false;
146 this->type
= GLSL_TYPE_ERROR
;
147 this->file
= PROGRAM_UNDEFINED
;
152 this->reladdr
= NULL
;
153 this->reladdr2
= NULL
;
154 this->has_index2
= false;
155 this->double_reg2
= false;
157 this->is_double_vertex_input
= false;
160 explicit st_src_reg(st_dst_reg reg
);
162 gl_register_file file
; /**< PROGRAM_* from Mesa */
163 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
165 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
166 int negate
; /**< NEGATE_XYZW mask from mesa */
167 enum glsl_base_type type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
168 /** Register index should be offset by the integer in this reg. */
170 st_src_reg
*reladdr2
;
173 * Is this the second half of a double register pair?
174 * currently used for input mapping only.
178 bool is_double_vertex_input
;
183 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
185 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
189 this->writemask
= writemask
;
190 this->reladdr
= NULL
;
191 this->reladdr2
= NULL
;
192 this->has_index2
= false;
197 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
199 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
203 this->writemask
= writemask
;
204 this->reladdr
= NULL
;
205 this->reladdr2
= NULL
;
206 this->has_index2
= false;
213 this->type
= GLSL_TYPE_ERROR
;
214 this->file
= PROGRAM_UNDEFINED
;
218 this->reladdr
= NULL
;
219 this->reladdr2
= NULL
;
220 this->has_index2
= false;
224 explicit st_dst_reg(st_src_reg reg
);
226 gl_register_file file
; /**< PROGRAM_* from Mesa */
227 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
229 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
230 enum glsl_base_type type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
231 /** Register index should be offset by the integer in this reg. */
233 st_src_reg
*reladdr2
;
238 st_src_reg::st_src_reg(st_dst_reg reg
)
240 this->type
= reg
.type
;
241 this->file
= reg
.file
;
242 this->index
= reg
.index
;
243 this->swizzle
= SWIZZLE_XYZW
;
245 this->reladdr
= reg
.reladdr
;
246 this->index2D
= reg
.index2D
;
247 this->reladdr2
= reg
.reladdr2
;
248 this->has_index2
= reg
.has_index2
;
249 this->double_reg2
= false;
250 this->array_id
= reg
.array_id
;
251 this->is_double_vertex_input
= false;
254 st_dst_reg::st_dst_reg(st_src_reg reg
)
256 this->type
= reg
.type
;
257 this->file
= reg
.file
;
258 this->index
= reg
.index
;
259 this->writemask
= WRITEMASK_XYZW
;
260 this->reladdr
= reg
.reladdr
;
261 this->index2D
= reg
.index2D
;
262 this->reladdr2
= reg
.reladdr2
;
263 this->has_index2
= reg
.has_index2
;
264 this->array_id
= reg
.array_id
;
267 class glsl_to_tgsi_instruction
: public exec_node
{
269 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
274 /** Pointer to the ir source this tree came from for debugging */
276 GLboolean cond_update
;
278 bool is_64bit_expanded
;
279 st_src_reg sampler
; /**< sampler register */
281 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
282 int tex_target
; /**< One of TEXTURE_*_INDEX */
283 glsl_base_type tex_type
;
284 GLboolean tex_shadow
;
285 unsigned image_format
;
287 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
288 unsigned tex_offset_num_offset
;
289 int dead_mask
; /**< Used in dead code elimination */
291 st_src_reg buffer
; /**< buffer register */
292 unsigned buffer_access
; /**< buffer access type */
294 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
295 const struct tgsi_opcode_info
*info
;
298 class variable_storage
: public exec_node
{
300 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
301 unsigned array_id
= 0)
302 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
304 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
307 gl_register_file file
;
310 /* Explicit component location. This is given in terms of the GLSL-style
311 * swizzles where each double is a single component, i.e. for 64-bit types
312 * it can only be 0 or 1.
315 ir_variable
*var
; /* variable that maps to this, if any */
319 class immediate_storage
: public exec_node
{
321 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
323 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
324 this->size32
= size32
;
328 /* doubles are stored across 2 gl_constant_values */
329 gl_constant_value values
[4];
330 int size32
; /**< Number of 32-bit components (1-4) */
331 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
334 class function_entry
: public exec_node
{
336 ir_function_signature
*sig
;
339 * identifier of this function signature used by the program.
341 * At the point that TGSI instructions for function calls are
342 * generated, we don't know the address of the first instruction of
343 * the function body. So we make the BranchTarget that is called a
344 * small integer and rewrite them during set_branchtargets().
349 * Pointer to first instruction of the function body.
351 * Set during function body emits after main() is processed.
353 glsl_to_tgsi_instruction
*bgn_inst
;
356 * Index of the first instruction of the function body in actual TGSI.
358 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
362 /** Storage for the return value. */
363 st_src_reg return_reg
;
366 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
367 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
371 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
373 enum glsl_base_type base_type
;
374 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
377 static struct inout_decl
*
378 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
380 assert(array_id
!= 0);
382 for (unsigned i
= 0; i
< count
; i
++) {
383 struct inout_decl
*decl
= &decls
[i
];
385 if (array_id
== decl
->array_id
) {
393 static enum glsl_base_type
394 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
397 return GLSL_TYPE_ERROR
;
398 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
400 return decl
->base_type
;
401 return GLSL_TYPE_ERROR
;
404 struct rename_reg_pair
{
409 struct glsl_to_tgsi_visitor
: public ir_visitor
{
411 glsl_to_tgsi_visitor();
412 ~glsl_to_tgsi_visitor();
414 function_entry
*current_function
;
416 struct gl_context
*ctx
;
417 struct gl_program
*prog
;
418 struct gl_shader_program
*shader_program
;
419 struct gl_linked_shader
*shader
;
420 struct gl_shader_compiler_options
*options
;
424 unsigned *array_sizes
;
425 unsigned max_num_arrays
;
428 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
430 unsigned num_input_arrays
;
431 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
432 unsigned num_outputs
;
433 unsigned num_output_arrays
;
435 int num_address_regs
;
436 uint32_t samplers_used
;
437 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
438 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
441 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
442 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
443 bool indirect_addr_consts
;
444 int wpos_transform_const
;
447 bool native_integers
;
450 bool use_shared_memory
;
452 variable_storage
*find_variable_storage(ir_variable
*var
);
454 int add_constant(gl_register_file file
, gl_constant_value values
[8],
455 int size
, int datatype
, GLuint
*swizzle_out
);
457 function_entry
*get_function_signature(ir_function_signature
*sig
);
459 st_src_reg
get_temp(const glsl_type
*type
);
460 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
462 st_src_reg
st_src_reg_for_double(double val
);
463 st_src_reg
st_src_reg_for_float(float val
);
464 st_src_reg
st_src_reg_for_int(int val
);
465 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
468 * \name Visit methods
470 * As typical for the visitor pattern, there must be one \c visit method for
471 * each concrete subclass of \c ir_instruction. Virtual base classes within
472 * the hierarchy should not have \c visit methods.
475 virtual void visit(ir_variable
*);
476 virtual void visit(ir_loop
*);
477 virtual void visit(ir_loop_jump
*);
478 virtual void visit(ir_function_signature
*);
479 virtual void visit(ir_function
*);
480 virtual void visit(ir_expression
*);
481 virtual void visit(ir_swizzle
*);
482 virtual void visit(ir_dereference_variable
*);
483 virtual void visit(ir_dereference_array
*);
484 virtual void visit(ir_dereference_record
*);
485 virtual void visit(ir_assignment
*);
486 virtual void visit(ir_constant
*);
487 virtual void visit(ir_call
*);
488 virtual void visit(ir_return
*);
489 virtual void visit(ir_discard
*);
490 virtual void visit(ir_texture
*);
491 virtual void visit(ir_if
*);
492 virtual void visit(ir_emit_vertex
*);
493 virtual void visit(ir_end_primitive
*);
494 virtual void visit(ir_barrier
*);
497 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
499 void visit_atomic_counter_intrinsic(ir_call
*);
500 void visit_ssbo_intrinsic(ir_call
*);
501 void visit_membar_intrinsic(ir_call
*);
502 void visit_shared_intrinsic(ir_call
*);
503 void visit_image_intrinsic(ir_call
*);
507 /** List of variable_storage */
510 /** List of immediate_storage */
511 exec_list immediates
;
512 unsigned num_immediates
;
514 /** List of function_entry */
515 exec_list function_signatures
;
516 int next_signature_id
;
518 /** List of glsl_to_tgsi_instruction */
519 exec_list instructions
;
521 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
522 st_dst_reg dst
= undef_dst
,
523 st_src_reg src0
= undef_src
,
524 st_src_reg src1
= undef_src
,
525 st_src_reg src2
= undef_src
,
526 st_src_reg src3
= undef_src
);
528 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
529 st_dst_reg dst
, st_dst_reg dst1
,
530 st_src_reg src0
= undef_src
,
531 st_src_reg src1
= undef_src
,
532 st_src_reg src2
= undef_src
,
533 st_src_reg src3
= undef_src
);
535 unsigned get_opcode(unsigned op
,
537 st_src_reg src0
, st_src_reg src1
);
540 * Emit the correct dot-product instruction for the type of arguments
542 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
548 void emit_scalar(ir_instruction
*ir
, unsigned op
,
549 st_dst_reg dst
, st_src_reg src0
);
551 void emit_scalar(ir_instruction
*ir
, unsigned op
,
552 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
554 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
556 void get_deref_offsets(ir_dereference
*ir
,
557 unsigned *array_size
,
562 void calc_deref_offsets(ir_dereference
*head
,
563 ir_dereference
*tail
,
564 unsigned *array_elements
,
567 st_src_reg
*indirect
,
569 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
571 bool try_emit_mad(ir_expression
*ir
,
573 bool try_emit_mad_for_and_not(ir_expression
*ir
,
576 void emit_swz(ir_expression
*ir
);
578 bool process_move_condition(ir_rvalue
*ir
);
580 void simplify_cmp(void);
582 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
583 void get_first_temp_read(int *first_reads
);
584 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
585 void get_last_temp_write(int *last_writes
);
587 void copy_propagate(void);
588 int eliminate_dead_code(void);
590 void merge_two_dsts(void);
591 void merge_registers(void);
592 void renumber_registers(void);
594 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
595 st_dst_reg
*l
, st_src_reg
*r
,
596 st_src_reg
*cond
, bool cond_swap
);
601 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
602 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
603 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
606 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
609 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
613 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
616 prog
->LinkStatus
= GL_FALSE
;
620 swizzle_for_size(int size
)
622 static const int size_swizzles
[4] = {
623 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
624 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
625 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
626 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
629 assert((size
>= 1) && (size
<= 4));
630 return size_swizzles
[size
- 1];
634 is_resource_instruction(unsigned opcode
)
637 case TGSI_OPCODE_RESQ
:
638 case TGSI_OPCODE_LOAD
:
639 case TGSI_OPCODE_ATOMUADD
:
640 case TGSI_OPCODE_ATOMXCHG
:
641 case TGSI_OPCODE_ATOMCAS
:
642 case TGSI_OPCODE_ATOMAND
:
643 case TGSI_OPCODE_ATOMOR
:
644 case TGSI_OPCODE_ATOMXOR
:
645 case TGSI_OPCODE_ATOMUMIN
:
646 case TGSI_OPCODE_ATOMUMAX
:
647 case TGSI_OPCODE_ATOMIMIN
:
648 case TGSI_OPCODE_ATOMIMAX
:
656 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
658 return op
->info
->num_dst
;
662 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
664 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
665 op
->info
->num_src
- 1 : op
->info
->num_src
;
668 glsl_to_tgsi_instruction
*
669 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
670 st_dst_reg dst
, st_dst_reg dst1
,
671 st_src_reg src0
, st_src_reg src1
,
672 st_src_reg src2
, st_src_reg src3
)
674 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
675 int num_reladdr
= 0, i
, j
;
676 bool dst_is_64bit
[2];
678 op
= get_opcode(op
, dst
, src0
, src1
);
680 /* If we have to do relative addressing, we want to load the ARL
681 * reg directly for one of the regs, and preload the other reladdr
682 * sources into temps.
684 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
685 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
686 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
687 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
688 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
689 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
691 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
692 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
693 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
694 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
696 if (dst
.reladdr
|| dst
.reladdr2
) {
698 emit_arl(ir
, address_reg
, *dst
.reladdr
);
700 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
704 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
707 assert(num_reladdr
== 0);
710 inst
->info
= tgsi_get_opcode_info(op
);
717 inst
->is_64bit_expanded
= false;
720 /* default to float, for paths where this is not initialized
721 * (since 0==UINT which is likely wrong):
723 inst
->tex_type
= GLSL_TYPE_FLOAT
;
725 inst
->function
= NULL
;
727 /* Update indirect addressing status used by TGSI */
728 if (dst
.reladdr
|| dst
.reladdr2
) {
730 case PROGRAM_STATE_VAR
:
731 case PROGRAM_CONSTANT
:
732 case PROGRAM_UNIFORM
:
733 this->indirect_addr_consts
= true;
735 case PROGRAM_IMMEDIATE
:
736 assert(!"immediates should not have indirect addressing");
743 for (i
= 0; i
< 4; i
++) {
744 if(inst
->src
[i
].reladdr
) {
745 switch(inst
->src
[i
].file
) {
746 case PROGRAM_STATE_VAR
:
747 case PROGRAM_CONSTANT
:
748 case PROGRAM_UNIFORM
:
749 this->indirect_addr_consts
= true;
751 case PROGRAM_IMMEDIATE
:
752 assert(!"immediates should not have indirect addressing");
762 * This section contains the double processing.
763 * GLSL just represents doubles as single channel values,
764 * however most HW and TGSI represent doubles as pairs of register channels.
766 * so we have to fixup destination writemask/index and src swizzle/indexes.
767 * dest writemasks need to translate from single channel write mask
768 * to a dual-channel writemask, but also need to modify the index,
769 * if we are touching the Z,W fields in the pre-translated writemask.
771 * src channels have similiar index modifications along with swizzle
772 * changes to we pick the XY, ZW pairs from the correct index.
774 * GLSL [0].x -> TGSI [0].xy
775 * GLSL [0].y -> TGSI [0].zw
776 * GLSL [0].z -> TGSI [1].xy
777 * GLSL [0].w -> TGSI [1].zw
779 for (j
= 0; j
< 2; j
++) {
780 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
781 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
782 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
783 if (glsl_base_type_is_64bit(type
))
784 dst_is_64bit
[j
] = true;
788 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
789 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
790 glsl_to_tgsi_instruction
*dinst
= NULL
;
791 int initial_src_swz
[4], initial_src_idx
[4];
792 int initial_dst_idx
[2], initial_dst_writemask
[2];
793 /* select the writemask for dst0 or dst1 */
794 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
796 /* copy out the writemask, index and swizzles for all src/dsts. */
797 for (j
= 0; j
< 2; j
++) {
798 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
799 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
802 for (j
= 0; j
< 4; j
++) {
803 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
804 initial_src_idx
[j
] = inst
->src
[j
].index
;
808 * scan all the components in the dst writemask
809 * generate an instruction for each of them if required.
814 int i
= u_bit_scan(&writemask
);
816 /* before emitting the instruction, see if we have to adjust store
818 if (i
> 1 && inst
->op
== TGSI_OPCODE_STORE
&&
819 addr
.file
== PROGRAM_UNDEFINED
) {
820 /* We have to advance the buffer address by 16 */
821 addr
= get_temp(glsl_type::uint_type
);
822 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
823 inst
->src
[0], st_src_reg_for_int(16));
827 /* first time use previous instruction */
831 /* create a new instructions for subsequent attempts */
832 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
837 this->instructions
.push_tail(dinst
);
838 dinst
->is_64bit_expanded
= true;
840 /* modify the destination if we are splitting */
841 for (j
= 0; j
< 2; j
++) {
842 if (dst_is_64bit
[j
]) {
843 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
844 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
846 if (dinst
->op
== TGSI_OPCODE_STORE
) {
847 dinst
->src
[0] = addr
;
849 dinst
->dst
[j
].index
++;
853 /* if we aren't writing to a double, just get the bit of the initial writemask
855 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
859 /* modify the src registers */
860 for (j
= 0; j
< 4; j
++) {
861 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
863 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
864 dinst
->src
[j
].index
= initial_src_idx
[j
];
866 dinst
->src
[j
].double_reg2
= true;
867 dinst
->src
[j
].index
++;
871 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
873 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
876 /* some opcodes are special case in what they use as sources
877 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
878 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
879 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
880 op
== TGSI_OPCODE_DLDEXP
||
881 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
882 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
889 this->instructions
.push_tail(inst
);
896 glsl_to_tgsi_instruction
*
897 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
899 st_src_reg src0
, st_src_reg src1
,
900 st_src_reg src2
, st_src_reg src3
)
902 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
906 * Determines whether to use an integer, unsigned integer, or float opcode
907 * based on the operands and input opcode, then emits the result.
910 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
912 st_src_reg src0
, st_src_reg src1
)
914 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
916 if (op
== TGSI_OPCODE_MOV
)
919 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
920 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
921 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
922 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
924 if (is_resource_instruction(op
))
926 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
927 type
= GLSL_TYPE_DOUBLE
;
928 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
929 type
= GLSL_TYPE_FLOAT
;
930 else if (native_integers
)
931 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
933 #define case5(c, f, i, u, d) \
934 case TGSI_OPCODE_##c: \
935 if (type == GLSL_TYPE_DOUBLE) \
936 op = TGSI_OPCODE_##d; \
937 else if (type == GLSL_TYPE_INT) \
938 op = TGSI_OPCODE_##i; \
939 else if (type == GLSL_TYPE_UINT) \
940 op = TGSI_OPCODE_##u; \
942 op = TGSI_OPCODE_##f; \
945 #define case4(c, f, i, u) \
946 case TGSI_OPCODE_##c: \
947 if (type == GLSL_TYPE_INT) \
948 op = TGSI_OPCODE_##i; \
949 else if (type == GLSL_TYPE_UINT) \
950 op = TGSI_OPCODE_##u; \
952 op = TGSI_OPCODE_##f; \
955 #define case3(f, i, u) case4(f, f, i, u)
956 #define case4d(f, i, u, d) case5(f, f, i, u, d)
957 #define case3fid(f, i, d) case5(f, f, i, i, d)
958 #define case2fi(f, i) case4(f, f, i, i)
959 #define case2iu(i, u) case4(i, LAST, i, u)
961 #define casecomp(c, f, i, u, d) \
962 case TGSI_OPCODE_##c: \
963 if (type == GLSL_TYPE_DOUBLE) \
964 op = TGSI_OPCODE_##d; \
965 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
966 op = TGSI_OPCODE_##i; \
967 else if (type == GLSL_TYPE_UINT) \
968 op = TGSI_OPCODE_##u; \
969 else if (native_integers) \
970 op = TGSI_OPCODE_##f; \
972 op = TGSI_OPCODE_##c; \
976 case3fid(ADD
, UADD
, DADD
);
977 case3fid(MUL
, UMUL
, DMUL
);
978 case3fid(MAD
, UMAD
, DMAD
);
979 case3fid(FMA
, UMAD
, DFMA
);
980 case3(DIV
, IDIV
, UDIV
);
981 case4d(MAX
, IMAX
, UMAX
, DMAX
);
982 case4d(MIN
, IMIN
, UMIN
, DMIN
);
985 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
986 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
987 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
988 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
992 case3fid(SSG
, ISSG
, DSSG
);
993 case3fid(ABS
, IABS
, DABS
);
997 case2iu(IMUL_HI
, UMUL_HI
);
999 case3fid(SQRT
, SQRT
, DSQRT
);
1001 case3fid(RCP
, RCP
, DRCP
);
1002 case3fid(RSQ
, RSQ
, DRSQ
);
1004 case3fid(FRC
, FRC
, DFRAC
);
1005 case3fid(TRUNC
, TRUNC
, DTRUNC
);
1006 case3fid(CEIL
, CEIL
, DCEIL
);
1007 case3fid(FLR
, FLR
, DFLR
);
1008 case3fid(ROUND
, ROUND
, DROUND
);
1010 case2iu(ATOMIMAX
, ATOMUMAX
);
1011 case2iu(ATOMIMIN
, ATOMUMIN
);
1016 assert(op
!= TGSI_OPCODE_LAST
);
1020 glsl_to_tgsi_instruction
*
1021 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
1022 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1025 static const unsigned dot_opcodes
[] = {
1026 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1029 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1033 * Emits TGSI scalar opcodes to produce unique answers across channels.
1035 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1036 * channel determines the result across all channels. So to do a vec4
1037 * of this operation, we want to emit a scalar per source channel used
1038 * to produce dest channels.
1041 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1043 st_src_reg orig_src0
, st_src_reg orig_src1
)
1046 int done_mask
= ~dst
.writemask
;
1048 /* TGSI RCP is a scalar operation splatting results to all channels,
1049 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1052 for (i
= 0; i
< 4; i
++) {
1053 GLuint this_mask
= (1 << i
);
1054 st_src_reg src0
= orig_src0
;
1055 st_src_reg src1
= orig_src1
;
1057 if (done_mask
& this_mask
)
1060 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1061 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1062 for (j
= i
+ 1; j
< 4; j
++) {
1063 /* If there is another enabled component in the destination that is
1064 * derived from the same inputs, generate its value on this pass as
1067 if (!(done_mask
& (1 << j
)) &&
1068 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1069 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1070 this_mask
|= (1 << j
);
1073 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1074 src0_swiz
, src0_swiz
);
1075 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1076 src1_swiz
, src1_swiz
);
1078 dst
.writemask
= this_mask
;
1079 emit_asm(ir
, op
, dst
, src0
, src1
);
1080 done_mask
|= this_mask
;
1085 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1086 st_dst_reg dst
, st_src_reg src0
)
1088 st_src_reg undef
= undef_src
;
1090 undef
.swizzle
= SWIZZLE_XXXX
;
1092 emit_scalar(ir
, op
, dst
, src0
, undef
);
1096 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1097 st_dst_reg dst
, st_src_reg src0
)
1099 int op
= TGSI_OPCODE_ARL
;
1101 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1102 op
= TGSI_OPCODE_UARL
;
1104 assert(dst
.file
== PROGRAM_ADDRESS
);
1105 if (dst
.index
>= this->num_address_regs
)
1106 this->num_address_regs
= dst
.index
+ 1;
1108 emit_asm(NULL
, op
, dst
, src0
);
1112 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1113 gl_constant_value values
[8], int size
, int datatype
,
1114 GLuint
*swizzle_out
)
1116 if (file
== PROGRAM_CONSTANT
) {
1117 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1118 size
, datatype
, swizzle_out
);
1121 assert(file
== PROGRAM_IMMEDIATE
);
1124 immediate_storage
*entry
;
1125 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1128 /* Search immediate storage to see if we already have an identical
1129 * immediate that we can use instead of adding a duplicate entry.
1131 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1132 immediate_storage
*tmp
= entry
;
1134 for (i
= 0; i
* 4 < size32
; i
++) {
1135 int slot_size
= MIN2(size32
- (i
* 4), 4);
1136 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1138 if (memcmp(tmp
->values
, &values
[i
* 4],
1139 slot_size
* sizeof(gl_constant_value
)))
1142 /* Everything matches, keep going until the full size is matched */
1143 tmp
= (immediate_storage
*)tmp
->next
;
1146 /* The full value matched */
1147 if (i
* 4 >= size32
)
1153 for (i
= 0; i
* 4 < size32
; i
++) {
1154 int slot_size
= MIN2(size32
- (i
* 4), 4);
1155 /* Add this immediate to the list. */
1156 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1157 this->immediates
.push_tail(entry
);
1158 this->num_immediates
++;
1164 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1166 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1167 union gl_constant_value uval
;
1170 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1176 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1178 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1179 union gl_constant_value uval
[2];
1181 memcpy(uval
, &val
, sizeof(uval
));
1182 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1183 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1188 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1190 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1191 union gl_constant_value uval
;
1193 assert(native_integers
);
1196 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1202 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1204 if (native_integers
)
1205 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1206 st_src_reg_for_int(val
);
1208 return st_src_reg_for_float(val
);
1212 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1214 return st_glsl_attrib_type_size(type
, is_vs_input
);
1218 type_size(const struct glsl_type
*type
)
1220 return st_glsl_type_size(type
);
1224 * If the given GLSL type is an array or matrix or a structure containing
1225 * an array/matrix member, return true. Else return false.
1227 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1228 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1229 * we have an array that might be indexed with a variable, we need to use
1230 * the later storage type.
1233 type_has_array_or_matrix(const glsl_type
*type
)
1235 if (type
->is_array() || type
->is_matrix())
1238 if (type
->is_record()) {
1239 for (unsigned i
= 0; i
< type
->length
; i
++) {
1240 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1251 * In the initial pass of codegen, we assign temporary numbers to
1252 * intermediate results. (not SSA -- variable assignments will reuse
1256 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1260 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1264 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1265 if (next_array
>= max_num_arrays
) {
1266 max_num_arrays
+= 32;
1267 array_sizes
= (unsigned*)
1268 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1271 src
.file
= PROGRAM_ARRAY
;
1273 src
.array_id
= next_array
+ 1;
1274 array_sizes
[next_array
] = type_size(type
);
1278 src
.file
= PROGRAM_TEMPORARY
;
1279 src
.index
= next_temp
;
1280 next_temp
+= type_size(type
);
1283 if (type
->is_array() || type
->is_record()) {
1284 src
.swizzle
= SWIZZLE_NOOP
;
1286 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1293 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1296 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1297 if (entry
->var
== var
)
1305 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1307 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1308 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1310 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1311 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1314 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1316 const ir_state_slot
*const slots
= ir
->get_state_slots();
1317 assert(slots
!= NULL
);
1319 /* Check if this statevar's setup in the STATE file exactly
1320 * matches how we'll want to reference it as a
1321 * struct/array/whatever. If not, then we need to move it into
1322 * temporary storage and hope that it'll get copy-propagated
1325 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1326 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1331 variable_storage
*storage
;
1333 if (i
== ir
->get_num_state_slots()) {
1334 /* We'll set the index later. */
1335 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1336 this->variables
.push_tail(storage
);
1340 /* The variable_storage constructor allocates slots based on the size
1341 * of the type. However, this had better match the number of state
1342 * elements that we're going to copy into the new temporary.
1344 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1346 dst
= st_dst_reg(get_temp(ir
->type
));
1348 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1351 this->variables
.push_tail(storage
);
1355 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1356 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1357 (gl_state_index
*)slots
[i
].tokens
);
1359 if (storage
->file
== PROGRAM_STATE_VAR
) {
1360 if (storage
->index
== -1) {
1361 storage
->index
= index
;
1363 assert(index
== storage
->index
+ (int)i
);
1366 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1367 * the data being moved since MOV does not care about the type of
1368 * data it is moving, and we don't want to declare registers with
1369 * array or struct types.
1371 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1372 src
.swizzle
= slots
[i
].swizzle
;
1373 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1374 /* even a float takes up a whole vec4 reg in a struct/array. */
1379 if (storage
->file
== PROGRAM_TEMPORARY
&&
1380 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1381 fail_link(this->shader_program
,
1382 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1383 ir
->name
, dst
.index
- storage
->index
,
1384 type_size(ir
->type
));
1390 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1392 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1394 visit_exec_list(&ir
->body_instructions
, this);
1396 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1400 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1403 case ir_loop_jump::jump_break
:
1404 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1406 case ir_loop_jump::jump_continue
:
1407 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1414 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1421 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1423 /* Ignore function bodies other than main() -- we shouldn't see calls to
1424 * them since they should all be inlined before we get to glsl_to_tgsi.
1426 if (strcmp(ir
->name
, "main") == 0) {
1427 const ir_function_signature
*sig
;
1430 sig
= ir
->matching_signature(NULL
, &empty
, false);
1434 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1441 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1443 int nonmul_operand
= 1 - mul_operand
;
1445 st_dst_reg result_dst
;
1447 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1448 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1451 expr
->operands
[0]->accept(this);
1453 expr
->operands
[1]->accept(this);
1455 ir
->operands
[nonmul_operand
]->accept(this);
1458 this->result
= get_temp(ir
->type
);
1459 result_dst
= st_dst_reg(this->result
);
1460 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1461 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1467 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1469 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1470 * implemented using multiplication, and logical-or is implemented using
1471 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1472 * As result, the logical expression (a & !b) can be rewritten as:
1476 * - (a * 1) - (a * b)
1480 * This final expression can be implemented as a single MAD(a, -b, a)
1484 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1486 const int other_operand
= 1 - try_operand
;
1489 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1490 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1493 ir
->operands
[other_operand
]->accept(this);
1495 expr
->operands
[0]->accept(this);
1498 b
.negate
= ~b
.negate
;
1500 this->result
= get_temp(ir
->type
);
1501 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1507 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1508 st_src_reg
*reg
, int *num_reladdr
)
1510 if (!reg
->reladdr
&& !reg
->reladdr2
)
1513 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1514 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1516 if (*num_reladdr
!= 1) {
1517 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1519 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1527 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1529 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1531 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1533 if (ir
->operation
== ir_binop_add
) {
1534 if (try_emit_mad(ir
, 1))
1536 if (try_emit_mad(ir
, 0))
1540 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1542 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1543 if (try_emit_mad_for_and_not(ir
, 1))
1545 if (try_emit_mad_for_and_not(ir
, 0))
1549 if (ir
->operation
== ir_quadop_vector
)
1550 assert(!"ir_quadop_vector should have been lowered");
1552 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1553 this->result
.file
= PROGRAM_UNDEFINED
;
1554 ir
->operands
[operand
]->accept(this);
1555 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1556 printf("Failed to get tree for expression operand:\n");
1557 ir
->operands
[operand
]->print();
1561 op
[operand
] = this->result
;
1563 /* Matrix expression operands should have been broken down to vector
1564 * operations already.
1566 assert(!ir
->operands
[operand
]->type
->is_matrix());
1569 visit_expression(ir
, op
);
1572 /* The non-recursive part of the expression visitor lives in a separate
1573 * function and should be prevented from being inlined, to avoid a stack
1574 * explosion when deeply nested expressions are visited.
1577 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1579 st_src_reg result_src
;
1580 st_dst_reg result_dst
;
1582 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1583 if (ir
->operands
[1]) {
1584 vector_elements
= MAX2(vector_elements
,
1585 ir
->operands
[1]->type
->vector_elements
);
1588 this->result
.file
= PROGRAM_UNDEFINED
;
1590 /* Storage for our result. Ideally for an assignment we'd be using
1591 * the actual storage for the result here, instead.
1593 result_src
= get_temp(ir
->type
);
1594 /* convenience for the emit functions below. */
1595 result_dst
= st_dst_reg(result_src
);
1596 /* Limit writes to the channels that will be used by result_src later.
1597 * This does limit this temp's use as a temporary for multi-instruction
1600 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1602 switch (ir
->operation
) {
1603 case ir_unop_logic_not
:
1604 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1605 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1607 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1608 * older GPUs implement SEQ using multiple instructions (i915 uses two
1609 * SGE instructions and a MUL instruction). Since our logic values are
1610 * 0.0 and 1.0, 1-x also implements !x.
1612 op
[0].negate
= ~op
[0].negate
;
1613 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1617 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1618 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1619 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1620 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1622 op
[0].negate
= ~op
[0].negate
;
1626 case ir_unop_subroutine_to_int
:
1627 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1630 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1633 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1636 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1640 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1644 assert(!"not reached: should be handled by ir_explog_to_explog2");
1647 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1650 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1653 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1655 case ir_unop_saturate
: {
1656 glsl_to_tgsi_instruction
*inst
;
1657 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1658 inst
->saturate
= true;
1663 case ir_unop_dFdx_coarse
:
1664 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1666 case ir_unop_dFdx_fine
:
1667 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1670 case ir_unop_dFdy_coarse
:
1671 case ir_unop_dFdy_fine
:
1673 /* The X component contains 1 or -1 depending on whether the framebuffer
1674 * is a FBO or the window system buffer, respectively.
1675 * It is then multiplied with the source operand of DDY.
1677 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1678 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1680 unsigned transform_y_index
=
1681 _mesa_add_state_reference(this->prog
->Parameters
,
1684 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1686 glsl_type::vec4_type
);
1687 transform_y
.swizzle
= SWIZZLE_XXXX
;
1689 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1691 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1692 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1693 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1697 case ir_unop_frexp_sig
:
1698 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1701 case ir_unop_frexp_exp
:
1702 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1705 case ir_unop_noise
: {
1706 /* At some point, a motivated person could add a better
1707 * implementation of noise. Currently not even the nvidia
1708 * binary drivers do anything more than this. In any case, the
1709 * place to do this is in the GL state tracker, not the poor
1712 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1717 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1720 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1724 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1727 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1728 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1730 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1733 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1734 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1736 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1740 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1742 case ir_binop_greater
:
1743 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1745 case ir_binop_lequal
:
1746 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1748 case ir_binop_gequal
:
1749 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1751 case ir_binop_equal
:
1752 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1754 case ir_binop_nequal
:
1755 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1757 case ir_binop_all_equal
:
1758 /* "==" operator producing a scalar boolean. */
1759 if (ir
->operands
[0]->type
->is_vector() ||
1760 ir
->operands
[1]->type
->is_vector()) {
1761 st_src_reg temp
= get_temp(native_integers
?
1762 glsl_type::uvec4_type
:
1763 glsl_type::vec4_type
);
1765 if (native_integers
) {
1766 st_dst_reg temp_dst
= st_dst_reg(temp
);
1767 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1769 if (ir
->operands
[0]->type
->is_boolean() &&
1770 ir
->operands
[1]->as_constant() &&
1771 ir
->operands
[1]->as_constant()->is_one()) {
1772 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1774 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1777 /* Emit 1-3 AND operations to combine the SEQ results. */
1778 switch (ir
->operands
[0]->type
->vector_elements
) {
1782 temp_dst
.writemask
= WRITEMASK_Y
;
1783 temp1
.swizzle
= SWIZZLE_YYYY
;
1784 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1785 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1788 temp_dst
.writemask
= WRITEMASK_X
;
1789 temp1
.swizzle
= SWIZZLE_XXXX
;
1790 temp2
.swizzle
= SWIZZLE_YYYY
;
1791 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1792 temp_dst
.writemask
= WRITEMASK_Y
;
1793 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1794 temp2
.swizzle
= SWIZZLE_WWWW
;
1795 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1798 temp1
.swizzle
= SWIZZLE_XXXX
;
1799 temp2
.swizzle
= SWIZZLE_YYYY
;
1800 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1802 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1804 /* After the dot-product, the value will be an integer on the
1805 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1807 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1809 /* Negating the result of the dot-product gives values on the range
1810 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1811 * This is achieved using SGE.
1813 st_src_reg sge_src
= result_src
;
1814 sge_src
.negate
= ~sge_src
.negate
;
1815 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1818 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1821 case ir_binop_any_nequal
:
1822 /* "!=" operator producing a scalar boolean. */
1823 if (ir
->operands
[0]->type
->is_vector() ||
1824 ir
->operands
[1]->type
->is_vector()) {
1825 st_src_reg temp
= get_temp(native_integers
?
1826 glsl_type::uvec4_type
:
1827 glsl_type::vec4_type
);
1828 if (ir
->operands
[0]->type
->is_boolean() &&
1829 ir
->operands
[1]->as_constant() &&
1830 ir
->operands
[1]->as_constant()->is_zero()) {
1831 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1833 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1836 if (native_integers
) {
1837 st_dst_reg temp_dst
= st_dst_reg(temp
);
1838 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1840 /* Emit 1-3 OR operations to combine the SNE results. */
1841 switch (ir
->operands
[0]->type
->vector_elements
) {
1845 temp_dst
.writemask
= WRITEMASK_Y
;
1846 temp1
.swizzle
= SWIZZLE_YYYY
;
1847 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1848 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1851 temp_dst
.writemask
= WRITEMASK_X
;
1852 temp1
.swizzle
= SWIZZLE_XXXX
;
1853 temp2
.swizzle
= SWIZZLE_YYYY
;
1854 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1855 temp_dst
.writemask
= WRITEMASK_Y
;
1856 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1857 temp2
.swizzle
= SWIZZLE_WWWW
;
1858 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1861 temp1
.swizzle
= SWIZZLE_XXXX
;
1862 temp2
.swizzle
= SWIZZLE_YYYY
;
1863 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1865 /* After the dot-product, the value will be an integer on the
1866 * range [0,4]. Zero stays zero, and positive values become 1.0.
1868 glsl_to_tgsi_instruction
*const dp
=
1869 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1870 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1871 /* The clamping to [0,1] can be done for free in the fragment
1872 * shader with a saturate.
1874 dp
->saturate
= true;
1876 /* Negating the result of the dot-product gives values on the range
1877 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1878 * achieved using SLT.
1880 st_src_reg slt_src
= result_src
;
1881 slt_src
.negate
= ~slt_src
.negate
;
1882 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1886 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1890 case ir_binop_logic_xor
:
1891 if (native_integers
)
1892 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1894 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1897 case ir_binop_logic_or
: {
1898 if (native_integers
) {
1899 /* If integers are used as booleans, we can use an actual "or"
1902 assert(native_integers
);
1903 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1905 /* After the addition, the value will be an integer on the
1906 * range [0,2]. Zero stays zero, and positive values become 1.0.
1908 glsl_to_tgsi_instruction
*add
=
1909 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1910 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1911 /* The clamping to [0,1] can be done for free in the fragment
1912 * shader with a saturate if floats are being used as boolean values.
1914 add
->saturate
= true;
1916 /* Negating the result of the addition gives values on the range
1917 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1918 * is achieved using SLT.
1920 st_src_reg slt_src
= result_src
;
1921 slt_src
.negate
= ~slt_src
.negate
;
1922 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1928 case ir_binop_logic_and
:
1929 /* If native integers are disabled, the bool args are stored as float 0.0
1930 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1931 * actual AND opcode.
1933 if (native_integers
)
1934 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1936 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1940 assert(ir
->operands
[0]->type
->is_vector());
1941 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1942 emit_dp(ir
, result_dst
, op
[0], op
[1],
1943 ir
->operands
[0]->type
->vector_elements
);
1948 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1950 /* This is the only instruction sequence that makes the game "Risen"
1951 * render correctly. ABS is not required for the game, but since GLSL
1952 * declares negative values as "undefined", allowing us to do whatever
1953 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1956 emit_scalar(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1957 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, result_src
);
1958 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1962 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1965 if (native_integers
) {
1966 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1969 /* fallthrough to next case otherwise */
1971 if (native_integers
) {
1972 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1975 /* fallthrough to next case otherwise */
1978 /* Converting between signed and unsigned integers is a no-op. */
1980 result_src
.type
= result_dst
.type
;
1983 if (native_integers
) {
1984 /* Booleans are stored as integers using ~0 for true and 0 for false.
1985 * GLSL requires that int(bool) return 1 for true and 0 for false.
1986 * This conversion is done with AND, but it could be done with NEG.
1988 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1990 /* Booleans and integers are both stored as floats when native
1991 * integers are disabled.
1997 if (native_integers
)
1998 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2000 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2003 if (native_integers
)
2004 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2006 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2008 case ir_unop_bitcast_f2i
:
2009 case ir_unop_bitcast_f2u
:
2010 /* Make sure we don't propagate the negate modifier to integer opcodes. */
2012 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2015 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2018 case ir_unop_bitcast_i2f
:
2019 case ir_unop_bitcast_u2f
:
2021 result_src
.type
= GLSL_TYPE_FLOAT
;
2024 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2027 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2030 if (native_integers
)
2031 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2033 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2036 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2039 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2042 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2044 case ir_unop_round_even
:
2045 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2048 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2052 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2055 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2058 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2061 case ir_unop_bit_not
:
2062 if (native_integers
) {
2063 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2067 if (native_integers
) {
2068 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2071 case ir_binop_lshift
:
2072 if (native_integers
) {
2073 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2076 case ir_binop_rshift
:
2077 if (native_integers
) {
2078 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2081 case ir_binop_bit_and
:
2082 if (native_integers
) {
2083 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2086 case ir_binop_bit_xor
:
2087 if (native_integers
) {
2088 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2091 case ir_binop_bit_or
:
2092 if (native_integers
) {
2093 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2097 assert(!"GLSL 1.30 features unsupported");
2100 case ir_binop_ubo_load
: {
2101 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2102 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2103 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2104 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2105 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2108 cbuf
.type
= ir
->type
->base_type
;
2109 cbuf
.file
= PROGRAM_CONSTANT
;
2111 cbuf
.reladdr
= NULL
;
2114 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2116 if (const_offset_ir
) {
2117 /* Constant index into constant buffer */
2118 cbuf
.reladdr
= NULL
;
2119 cbuf
.index
= const_offset
/ 16;
2122 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2123 st_src_reg offset
= op
[1];
2125 /* The OpenGL spec is written in such a way that accesses with
2126 * non-constant offset are almost always vec4-aligned. The only
2127 * exception to this are members of structs in arrays of structs:
2128 * each struct in an array of structs is at least vec4-aligned,
2129 * but single-element and [ui]vec2 members of the struct may be at
2130 * an offset that is not a multiple of 16 bytes.
2132 * Here, we extract that offset, relying on previous passes to always
2133 * generate offset expressions of the form (+ expr constant_offset).
2135 * Note that the std430 layout, which allows more cases of alignment
2136 * less than vec4 in arrays, is not supported for uniform blocks, so
2137 * we do not have to deal with it here.
2139 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2140 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2141 if (const_offset_ir
) {
2142 const_offset
= const_offset_ir
->value
.u
[0];
2143 cbuf
.index
= const_offset
/ 16;
2144 offset_expr
->operands
[0]->accept(this);
2145 offset
= this->result
;
2149 /* Relative/variable index into constant buffer */
2150 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2151 st_src_reg_for_int(4));
2152 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2153 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2156 if (const_uniform_block
) {
2157 /* Constant constant buffer */
2158 cbuf
.reladdr2
= NULL
;
2159 cbuf
.index2D
= const_block
;
2160 cbuf
.has_index2
= true;
2163 /* Relative/variable constant buffer */
2164 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2166 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2167 cbuf
.has_index2
= true;
2170 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2171 if (glsl_base_type_is_64bit(cbuf
.type
))
2172 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2173 const_offset
% 16 / 8,
2174 const_offset
% 16 / 8,
2175 const_offset
% 16 / 8);
2177 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2178 const_offset
% 16 / 4,
2179 const_offset
% 16 / 4,
2180 const_offset
% 16 / 4);
2182 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2183 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2185 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2190 /* note: we have to reorder the three args here */
2191 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2194 if (this->ctx
->Const
.NativeIntegers
)
2195 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2197 op
[0].negate
= ~op
[0].negate
;
2198 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2201 case ir_triop_bitfield_extract
:
2202 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2204 case ir_quadop_bitfield_insert
:
2205 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2207 case ir_unop_bitfield_reverse
:
2208 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2210 case ir_unop_bit_count
:
2211 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2213 case ir_unop_find_msb
:
2214 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2216 case ir_unop_find_lsb
:
2217 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2219 case ir_binop_imul_high
:
2220 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2223 /* In theory, MAD is incorrect here. */
2225 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2227 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2229 case ir_unop_interpolate_at_centroid
:
2230 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2232 case ir_binop_interpolate_at_offset
: {
2233 /* The y coordinate needs to be flipped for the default fb */
2234 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2235 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2237 unsigned transform_y_index
=
2238 _mesa_add_state_reference(this->prog
->Parameters
,
2241 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2243 glsl_type::vec4_type
);
2244 transform_y
.swizzle
= SWIZZLE_XXXX
;
2246 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2247 st_dst_reg temp_dst
= st_dst_reg(temp
);
2249 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2250 temp_dst
.writemask
= WRITEMASK_Y
;
2251 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2252 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2255 case ir_binop_interpolate_at_sample
:
2256 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2260 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2263 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2266 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2269 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2272 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2275 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2277 case ir_unop_unpack_double_2x32
:
2278 case ir_unop_pack_double_2x32
:
2279 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2282 case ir_binop_ldexp
:
2283 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2284 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2286 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2290 case ir_unop_pack_half_2x16
:
2291 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2293 case ir_unop_unpack_half_2x16
:
2294 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2297 case ir_unop_get_buffer_size
: {
2298 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2301 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2302 (const_offset
? const_offset
->value
.u
[0] : 0),
2304 if (!const_offset
) {
2305 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2306 *buffer
.reladdr
= op
[0];
2307 emit_arl(ir
, sampler_reladdr
, op
[0]);
2309 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->buffer
= buffer
;
2313 case ir_unop_vote_any
:
2314 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2316 case ir_unop_vote_all
:
2317 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2319 case ir_unop_vote_eq
:
2320 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2323 case ir_unop_pack_snorm_2x16
:
2324 case ir_unop_pack_unorm_2x16
:
2325 case ir_unop_pack_snorm_4x8
:
2326 case ir_unop_pack_unorm_4x8
:
2328 case ir_unop_unpack_snorm_2x16
:
2329 case ir_unop_unpack_unorm_2x16
:
2330 case ir_unop_unpack_snorm_4x8
:
2331 case ir_unop_unpack_unorm_4x8
:
2333 case ir_quadop_vector
:
2334 case ir_binop_vector_extract
:
2335 case ir_triop_vector_insert
:
2336 case ir_binop_carry
:
2337 case ir_binop_borrow
:
2338 case ir_unop_ssbo_unsized_array_length
:
2339 /* This operation is not supported, or should have already been handled.
2341 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2345 this->result
= result_src
;
2350 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2356 /* Note that this is only swizzles in expressions, not those on the left
2357 * hand side of an assignment, which do write masking. See ir_assignment
2361 ir
->val
->accept(this);
2363 assert(src
.file
!= PROGRAM_UNDEFINED
);
2364 assert(ir
->type
->vector_elements
> 0);
2366 for (i
= 0; i
< 4; i
++) {
2367 if (i
< ir
->type
->vector_elements
) {
2370 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2373 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2376 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2379 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2383 /* If the type is smaller than a vec4, replicate the last
2386 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2390 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2395 /* Test if the variable is an array. Note that geometry and
2396 * tessellation shader inputs are outputs are always arrays (except
2397 * for patch inputs), so only the array element type is considered.
2400 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2402 const glsl_type
*type
= var
->type
;
2404 *remove_array
= false;
2406 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2407 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2410 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2411 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2412 stage
== MESA_SHADER_TESS_CTRL
) &&
2414 if (!var
->type
->is_array())
2415 return false; /* a system value probably */
2417 type
= var
->type
->fields
.array
;
2418 *remove_array
= true;
2421 return type
->is_array() || type
->is_matrix();
2425 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2427 variable_storage
*entry
= find_variable_storage(ir
->var
);
2428 ir_variable
*var
= ir
->var
;
2432 switch (var
->data
.mode
) {
2433 case ir_var_uniform
:
2434 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2435 var
->data
.param_index
);
2436 this->variables
.push_tail(entry
);
2438 case ir_var_shader_in
: {
2439 /* The linker assigns locations for varyings and attributes,
2440 * including deprecated builtins (like gl_Color), user-assign
2441 * generic attributes (glBindVertexLocation), and
2442 * user-defined varyings.
2444 assert(var
->data
.location
!= -1);
2446 const glsl_type
*type_without_array
= var
->type
->without_array();
2447 struct inout_decl
*decl
= &inputs
[num_inputs
];
2448 unsigned component
= var
->data
.location_frac
;
2449 unsigned num_components
;
2452 if (type_without_array
->is_64bit())
2453 component
= component
/ 2;
2454 if (type_without_array
->vector_elements
)
2455 num_components
= type_without_array
->vector_elements
;
2459 decl
->mesa_index
= var
->data
.location
;
2460 decl
->base_type
= type_without_array
->base_type
;
2461 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2463 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2464 decl
->array_id
= num_input_arrays
+ 1;
2471 decl
->size
= type_size(var
->type
->fields
.array
);
2473 decl
->size
= type_size(var
->type
);
2475 entry
= new(mem_ctx
) variable_storage(var
,
2479 entry
->component
= component
;
2481 this->variables
.push_tail(entry
);
2484 case ir_var_shader_out
: {
2485 assert(var
->data
.location
!= -1);
2487 const glsl_type
*type_without_array
= var
->type
->without_array();
2488 struct inout_decl
*decl
= &outputs
[num_outputs
];
2489 unsigned component
= var
->data
.location_frac
;
2490 unsigned num_components
;
2493 if (type_without_array
->is_64bit())
2494 component
= component
/ 2;
2495 if (type_without_array
->vector_elements
)
2496 num_components
= type_without_array
->vector_elements
;
2500 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2501 decl
->base_type
= type_without_array
->base_type
;
2502 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2504 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2505 decl
->array_id
= num_output_arrays
+ 1;
2506 num_output_arrays
++;
2512 decl
->size
= type_size(var
->type
->fields
.array
);
2514 decl
->size
= type_size(var
->type
);
2516 entry
= new(mem_ctx
) variable_storage(var
,
2520 entry
->component
= component
;
2522 this->variables
.push_tail(entry
);
2525 case ir_var_system_value
:
2526 entry
= new(mem_ctx
) variable_storage(var
,
2527 PROGRAM_SYSTEM_VALUE
,
2528 var
->data
.location
);
2531 case ir_var_temporary
:
2532 st_src_reg src
= get_temp(var
->type
);
2534 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2536 this->variables
.push_tail(entry
);
2542 printf("Failed to make storage for %s\n", var
->name
);
2547 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2548 entry
->component
, entry
->array_id
);
2549 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2550 this->result
.is_double_vertex_input
= true;
2551 if (!native_integers
)
2552 this->result
.type
= GLSL_TYPE_FLOAT
;
2556 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2557 GLbitfield64
* usage_mask
,
2558 GLbitfield64 double_usage_mask
,
2559 GLbitfield
* patch_usage_mask
)
2564 /* Fix array declarations by removing unused array elements at both ends
2565 * of the arrays. For example, mat4[3] where only mat[1] is used.
2567 for (i
= 0; i
< count
; i
++) {
2568 struct inout_decl
*decl
= &decls
[i
];
2569 if (!decl
->array_id
)
2572 /* Shrink the beginning. */
2573 for (j
= 0; j
< (int)decl
->size
; j
++) {
2574 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2575 if (*patch_usage_mask
&
2576 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2580 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2582 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2591 /* Shrink the end. */
2592 for (j
= decl
->size
-1; j
>= 0; j
--) {
2593 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2594 if (*patch_usage_mask
&
2595 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2599 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2601 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2608 /* When not all entries of an array are accessed, we mark them as used
2609 * here anyway, to ensure that the input/output mapping logic doesn't get
2612 * TODO This happens when an array isn't used via indirect access, which
2613 * some game ports do (at least eON-based). There is an optimization
2614 * opportunity here by replacing the array declaration with non-array
2615 * declarations of those slots that are actually used.
2617 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2618 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2619 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2621 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2627 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2631 int element_size
= type_size(ir
->type
);
2634 index
= ir
->array_index
->constant_expression_value();
2636 ir
->array
->accept(this);
2639 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2640 switch (this->prog
->Target
) {
2641 case GL_TESS_CONTROL_PROGRAM_NV
:
2642 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2643 !ir
->variable_referenced()->data
.patch
;
2645 case GL_TESS_EVALUATION_PROGRAM_NV
:
2646 is_2D
= src
.file
== PROGRAM_INPUT
&&
2647 !ir
->variable_referenced()->data
.patch
;
2649 case GL_GEOMETRY_PROGRAM_NV
:
2650 is_2D
= src
.file
== PROGRAM_INPUT
;
2660 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2661 src
.file
== PROGRAM_INPUT
)
2662 element_size
= attrib_type_size(ir
->type
, true);
2664 src
.index2D
= index
->value
.i
[0];
2665 src
.has_index2
= true;
2667 src
.index
+= index
->value
.i
[0] * element_size
;
2669 /* Variable index array dereference. It eats the "vec4" of the
2670 * base of the array and an index that offsets the TGSI register
2673 ir
->array_index
->accept(this);
2675 st_src_reg index_reg
;
2677 if (element_size
== 1) {
2678 index_reg
= this->result
;
2680 index_reg
= get_temp(native_integers
?
2681 glsl_type::int_type
: glsl_type::float_type
);
2683 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2684 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2687 /* If there was already a relative address register involved, add the
2688 * new and the old together to get the new offset.
2690 if (!is_2D
&& src
.reladdr
!= NULL
) {
2691 st_src_reg accum_reg
= get_temp(native_integers
?
2692 glsl_type::int_type
: glsl_type::float_type
);
2694 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2695 index_reg
, *src
.reladdr
);
2697 index_reg
= accum_reg
;
2701 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2702 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2704 src
.has_index2
= true;
2706 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2707 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2711 /* Change the register type to the element type of the array. */
2712 src
.type
= ir
->type
->base_type
;
2718 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2721 const glsl_type
*struct_type
= ir
->record
->type
;
2724 ir
->record
->accept(this);
2726 for (i
= 0; i
< struct_type
->length
; i
++) {
2727 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2729 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2732 /* If the type is smaller than a vec4, replicate the last channel out. */
2733 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2734 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2736 this->result
.swizzle
= SWIZZLE_NOOP
;
2738 this->result
.index
+= offset
;
2739 this->result
.type
= ir
->type
->base_type
;
2743 * We want to be careful in assignment setup to hit the actual storage
2744 * instead of potentially using a temporary like we might with the
2745 * ir_dereference handler.
2748 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2750 /* The LHS must be a dereference. If the LHS is a variable indexed array
2751 * access of a vector, it must be separated into a series conditional moves
2752 * before reaching this point (see ir_vec_index_to_cond_assign).
2754 assert(ir
->as_dereference());
2755 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2757 assert(!deref_array
->array
->type
->is_vector());
2760 /* Use the rvalue deref handler for the most part. We write swizzles using
2761 * the writemask, but we do extract the base component for enhanced layouts
2762 * from the source swizzle.
2765 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2766 return st_dst_reg(v
->result
);
2770 * Process the condition of a conditional assignment
2772 * Examines the condition of a conditional assignment to generate the optimal
2773 * first operand of a \c CMP instruction. If the condition is a relational
2774 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2775 * used as the source for the \c CMP instruction. Otherwise the comparison
2776 * is processed to a boolean result, and the boolean result is used as the
2777 * operand to the CMP instruction.
2780 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2782 ir_rvalue
*src_ir
= ir
;
2784 bool switch_order
= false;
2786 ir_expression
*const expr
= ir
->as_expression();
2788 if (native_integers
) {
2789 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2790 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2791 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2792 type
== GLSL_TYPE_BOOL
) {
2793 if (expr
->operation
== ir_binop_equal
) {
2794 if (expr
->operands
[0]->is_zero()) {
2795 src_ir
= expr
->operands
[1];
2796 switch_order
= true;
2798 else if (expr
->operands
[1]->is_zero()) {
2799 src_ir
= expr
->operands
[0];
2800 switch_order
= true;
2803 else if (expr
->operation
== ir_binop_nequal
) {
2804 if (expr
->operands
[0]->is_zero()) {
2805 src_ir
= expr
->operands
[1];
2807 else if (expr
->operands
[1]->is_zero()) {
2808 src_ir
= expr
->operands
[0];
2814 src_ir
->accept(this);
2815 return switch_order
;
2818 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2819 bool zero_on_left
= false;
2821 if (expr
->operands
[0]->is_zero()) {
2822 src_ir
= expr
->operands
[1];
2823 zero_on_left
= true;
2824 } else if (expr
->operands
[1]->is_zero()) {
2825 src_ir
= expr
->operands
[0];
2826 zero_on_left
= false;
2830 * (a < 0) T F F ( a < 0) T F F
2831 * (0 < a) F F T (-a < 0) F F T
2832 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2833 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2834 * (a > 0) F F T (-a < 0) F F T
2835 * (0 > a) T F F ( a < 0) T F F
2836 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2837 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2839 * Note that exchanging the order of 0 and 'a' in the comparison simply
2840 * means that the value of 'a' should be negated.
2843 switch (expr
->operation
) {
2845 switch_order
= false;
2846 negate
= zero_on_left
;
2849 case ir_binop_greater
:
2850 switch_order
= false;
2851 negate
= !zero_on_left
;
2854 case ir_binop_lequal
:
2855 switch_order
= true;
2856 negate
= !zero_on_left
;
2859 case ir_binop_gequal
:
2860 switch_order
= true;
2861 negate
= zero_on_left
;
2865 /* This isn't the right kind of comparison afterall, so make sure
2866 * the whole condition is visited.
2874 src_ir
->accept(this);
2876 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2877 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2878 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2879 * computing the condition.
2882 this->result
.negate
= ~this->result
.negate
;
2884 return switch_order
;
2888 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2889 st_dst_reg
*l
, st_src_reg
*r
,
2890 st_src_reg
*cond
, bool cond_swap
)
2892 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2893 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2894 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2900 if (type
->is_array()) {
2901 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2902 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2907 if (type
->is_matrix()) {
2908 const struct glsl_type
*vec_type
;
2910 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2911 type
->vector_elements
, 1);
2913 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2914 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2919 assert(type
->is_scalar() || type
->is_vector());
2921 r
->type
= type
->base_type
;
2923 st_src_reg l_src
= st_src_reg(*l
);
2924 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2926 if (native_integers
) {
2927 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2928 cond_swap
? l_src
: *r
,
2929 cond_swap
? *r
: l_src
);
2931 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2932 cond_swap
? l_src
: *r
,
2933 cond_swap
? *r
: l_src
);
2936 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2940 if (type
->is_dual_slot()) {
2942 if (r
->is_double_vertex_input
== false)
2948 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2954 ir
->rhs
->accept(this);
2957 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2961 int first_enabled_chan
= 0;
2963 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2965 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2966 variable
->data
.mode
== ir_var_shader_out
&&
2967 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2968 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2969 assert(ir
->lhs
->type
->is_scalar());
2970 assert(ir
->write_mask
== WRITEMASK_X
);
2972 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2973 l
.writemask
= WRITEMASK_Z
;
2975 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2976 l
.writemask
= WRITEMASK_Y
;
2978 } else if (ir
->write_mask
== 0) {
2979 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2981 if (ir
->lhs
->type
->is_array() || ir
->lhs
->type
->is_matrix()) {
2982 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2983 l
.writemask
= u_bit_consecutive(0, num_elements
);
2985 l
.writemask
= WRITEMASK_XYZW
;
2988 l
.writemask
= ir
->write_mask
;
2991 for (int i
= 0; i
< 4; i
++) {
2992 if (l
.writemask
& (1 << i
)) {
2993 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2998 l
.writemask
= l
.writemask
<< dst_component
;
3000 /* Swizzle a small RHS vector into the channels being written.
3002 * glsl ir treats write_mask as dictating how many channels are
3003 * present on the RHS while TGSI treats write_mask as just
3004 * showing which channels of the vec4 RHS get written.
3006 for (int i
= 0; i
< 4; i
++) {
3007 if (l
.writemask
& (1 << i
))
3008 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3010 swizzles
[i
] = first_enabled_chan
;
3012 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3013 swizzles
[2], swizzles
[3]);
3016 assert(l
.file
!= PROGRAM_UNDEFINED
);
3017 assert(r
.file
!= PROGRAM_UNDEFINED
);
3019 if (ir
->condition
) {
3020 const bool switch_order
= this->process_move_condition(ir
->condition
);
3021 st_src_reg condition
= this->result
;
3023 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3024 } else if (ir
->rhs
->as_expression() &&
3025 this->instructions
.get_tail() &&
3026 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3027 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3028 type_size(ir
->lhs
->type
) == 1 &&
3029 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3030 /* To avoid emitting an extra MOV when assigning an expression to a
3031 * variable, emit the last instruction of the expression again, but
3032 * replace the destination register with the target of the assignment.
3033 * Dead code elimination will remove the original instruction.
3035 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3036 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3037 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3038 new_inst
->saturate
= inst
->saturate
;
3039 inst
->dead_mask
= inst
->dst
[0].writemask
;
3041 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3047 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3050 GLdouble stack_vals
[4] = { 0 };
3051 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3052 GLenum gl_type
= GL_NONE
;
3054 static int in_array
= 0;
3055 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3057 /* Unfortunately, 4 floats is all we can get into
3058 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3059 * aggregate constant and move each constant value into it. If we
3060 * get lucky, copy propagation will eliminate the extra moves.
3062 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
3063 st_src_reg temp_base
= get_temp(ir
->type
);
3064 st_dst_reg temp
= st_dst_reg(temp_base
);
3066 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3067 int size
= type_size(field_value
->type
);
3071 field_value
->accept(this);
3074 for (i
= 0; i
< (unsigned int)size
; i
++) {
3075 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3081 this->result
= temp_base
;
3085 if (ir
->type
->is_array()) {
3086 st_src_reg temp_base
= get_temp(ir
->type
);
3087 st_dst_reg temp
= st_dst_reg(temp_base
);
3088 int size
= type_size(ir
->type
->fields
.array
);
3093 for (i
= 0; i
< ir
->type
->length
; i
++) {
3094 ir
->array_elements
[i
]->accept(this);
3096 for (int j
= 0; j
< size
; j
++) {
3097 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3103 this->result
= temp_base
;
3108 if (ir
->type
->is_matrix()) {
3109 st_src_reg mat
= get_temp(ir
->type
);
3110 st_dst_reg mat_column
= st_dst_reg(mat
);
3112 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3113 switch (ir
->type
->base_type
) {
3114 case GLSL_TYPE_FLOAT
:
3115 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3117 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3118 src
.index
= add_constant(file
,
3120 ir
->type
->vector_elements
,
3123 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3125 case GLSL_TYPE_DOUBLE
:
3126 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3127 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3128 src
.index
= add_constant(file
,
3130 ir
->type
->vector_elements
,
3133 if (ir
->type
->vector_elements
>= 2) {
3134 mat_column
.writemask
= WRITEMASK_XY
;
3135 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3136 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3138 mat_column
.writemask
= WRITEMASK_X
;
3139 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3140 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3143 if (ir
->type
->vector_elements
> 2) {
3144 if (ir
->type
->vector_elements
== 4) {
3145 mat_column
.writemask
= WRITEMASK_ZW
;
3146 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3147 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3149 mat_column
.writemask
= WRITEMASK_Z
;
3150 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3151 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3152 mat_column
.writemask
= WRITEMASK_XYZW
;
3153 src
.swizzle
= SWIZZLE_XYZW
;
3159 unreachable("Illegal matrix constant type.\n");
3168 switch (ir
->type
->base_type
) {
3169 case GLSL_TYPE_FLOAT
:
3171 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3172 values
[i
].f
= ir
->value
.f
[i
];
3175 case GLSL_TYPE_DOUBLE
:
3176 gl_type
= GL_DOUBLE
;
3177 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3178 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3181 case GLSL_TYPE_UINT
:
3182 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3183 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3184 if (native_integers
)
3185 values
[i
].u
= ir
->value
.u
[i
];
3187 values
[i
].f
= ir
->value
.u
[i
];
3191 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3192 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3193 if (native_integers
)
3194 values
[i
].i
= ir
->value
.i
[i
];
3196 values
[i
].f
= ir
->value
.i
[i
];
3199 case GLSL_TYPE_BOOL
:
3200 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3201 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3202 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3206 assert(!"Non-float/uint/int/bool constant");
3209 this->result
= st_src_reg(file
, -1, ir
->type
);
3210 this->result
.index
= add_constant(file
,
3212 ir
->type
->vector_elements
,
3214 &this->result
.swizzle
);
3218 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
3220 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
3221 if (entry
->sig
== sig
)
3225 entry
= ralloc(mem_ctx
, function_entry
);
3227 entry
->sig_id
= this->next_signature_id
++;
3228 entry
->bgn_inst
= NULL
;
3230 /* Allocate storage for all the parameters. */
3231 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
3232 variable_storage
*storage
;
3234 storage
= find_variable_storage(param
);
3237 st_src_reg src
= get_temp(param
->type
);
3239 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
3240 this->variables
.push_tail(storage
);
3243 if (!sig
->return_type
->is_void()) {
3244 entry
->return_reg
= get_temp(sig
->return_type
);
3246 entry
->return_reg
= undef_src
;
3249 this->function_signatures
.push_tail(entry
);
3254 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3256 exec_node
*param
= ir
->actual_parameters
.get_head();
3257 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3258 ir_variable
*location
= deref
->variable_referenced();
3261 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3263 /* Calculate the surface offset */
3265 unsigned array_size
= 0, base
= 0, index
= 0;
3267 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3269 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3270 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3271 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3272 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3273 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3275 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3278 ir
->return_deref
->accept(this);
3279 st_dst_reg
dst(this->result
);
3280 dst
.writemask
= WRITEMASK_X
;
3282 glsl_to_tgsi_instruction
*inst
;
3284 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3285 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3286 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3287 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3288 st_src_reg_for_int(1));
3289 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3290 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3291 st_src_reg_for_int(-1));
3292 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3294 param
= param
->get_next();
3295 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3298 st_src_reg data
= this->result
, data2
= undef_src
;
3300 switch (ir
->callee
->intrinsic_id
) {
3301 case ir_intrinsic_atomic_counter_add
:
3302 opcode
= TGSI_OPCODE_ATOMUADD
;
3304 case ir_intrinsic_atomic_counter_min
:
3305 opcode
= TGSI_OPCODE_ATOMIMIN
;
3307 case ir_intrinsic_atomic_counter_max
:
3308 opcode
= TGSI_OPCODE_ATOMIMAX
;
3310 case ir_intrinsic_atomic_counter_and
:
3311 opcode
= TGSI_OPCODE_ATOMAND
;
3313 case ir_intrinsic_atomic_counter_or
:
3314 opcode
= TGSI_OPCODE_ATOMOR
;
3316 case ir_intrinsic_atomic_counter_xor
:
3317 opcode
= TGSI_OPCODE_ATOMXOR
;
3319 case ir_intrinsic_atomic_counter_exchange
:
3320 opcode
= TGSI_OPCODE_ATOMXCHG
;
3322 case ir_intrinsic_atomic_counter_comp_swap
: {
3323 opcode
= TGSI_OPCODE_ATOMCAS
;
3324 param
= param
->get_next();
3325 val
= ((ir_instruction
*)param
)->as_rvalue();
3327 data2
= this->result
;
3331 assert(!"Unexpected intrinsic");
3335 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3338 inst
->buffer
= buffer
;
3342 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3344 exec_node
*param
= ir
->actual_parameters
.get_head();
3346 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3348 param
= param
->get_next();
3349 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3351 ir_constant
*const_block
= block
->as_constant();
3355 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3356 (const_block
? const_block
->value
.u
[0] : 0),
3360 block
->accept(this);
3361 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3362 *buffer
.reladdr
= this->result
;
3363 emit_arl(ir
, sampler_reladdr
, this->result
);
3366 /* Calculate the surface offset */
3367 offset
->accept(this);
3368 st_src_reg off
= this->result
;
3370 st_dst_reg dst
= undef_dst
;
3371 if (ir
->return_deref
) {
3372 ir
->return_deref
->accept(this);
3373 dst
= st_dst_reg(this->result
);
3374 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3377 glsl_to_tgsi_instruction
*inst
;
3379 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3380 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3381 if (dst
.type
== GLSL_TYPE_BOOL
)
3382 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3383 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3384 param
= param
->get_next();
3385 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3388 param
= param
->get_next();
3389 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3391 dst
.writemask
= write_mask
->value
.u
[0];
3393 dst
.type
= this->result
.type
;
3394 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3396 param
= param
->get_next();
3397 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3400 st_src_reg data
= this->result
, data2
= undef_src
;
3402 switch (ir
->callee
->intrinsic_id
) {
3403 case ir_intrinsic_ssbo_atomic_add
:
3404 opcode
= TGSI_OPCODE_ATOMUADD
;
3406 case ir_intrinsic_ssbo_atomic_min
:
3407 opcode
= TGSI_OPCODE_ATOMIMIN
;
3409 case ir_intrinsic_ssbo_atomic_max
:
3410 opcode
= TGSI_OPCODE_ATOMIMAX
;
3412 case ir_intrinsic_ssbo_atomic_and
:
3413 opcode
= TGSI_OPCODE_ATOMAND
;
3415 case ir_intrinsic_ssbo_atomic_or
:
3416 opcode
= TGSI_OPCODE_ATOMOR
;
3418 case ir_intrinsic_ssbo_atomic_xor
:
3419 opcode
= TGSI_OPCODE_ATOMXOR
;
3421 case ir_intrinsic_ssbo_atomic_exchange
:
3422 opcode
= TGSI_OPCODE_ATOMXCHG
;
3424 case ir_intrinsic_ssbo_atomic_comp_swap
:
3425 opcode
= TGSI_OPCODE_ATOMCAS
;
3426 param
= param
->get_next();
3427 val
= ((ir_instruction
*)param
)->as_rvalue();
3429 data2
= this->result
;
3432 assert(!"Unexpected intrinsic");
3436 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3439 param
= param
->get_next();
3440 ir_constant
*access
= NULL
;
3441 if (!param
->is_tail_sentinel()) {
3442 access
= ((ir_instruction
*)param
)->as_constant();
3446 /* The emit_asm() might have actually split the op into pieces, e.g. for
3447 * double stores. We have to go back and fix up all the generated ops.
3449 unsigned op
= inst
->op
;
3451 inst
->buffer
= buffer
;
3453 inst
->buffer_access
= access
->value
.u
[0];
3454 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3455 if (inst
->op
== TGSI_OPCODE_UADD
)
3456 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3457 } while (inst
&& inst
->op
== op
&& inst
->buffer
.file
== PROGRAM_UNDEFINED
);
3461 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3463 switch (ir
->callee
->intrinsic_id
) {
3464 case ir_intrinsic_memory_barrier
:
3465 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3466 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3467 TGSI_MEMBAR_ATOMIC_BUFFER
|
3468 TGSI_MEMBAR_SHADER_IMAGE
|
3469 TGSI_MEMBAR_SHARED
));
3471 case ir_intrinsic_memory_barrier_atomic_counter
:
3472 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3473 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3475 case ir_intrinsic_memory_barrier_buffer
:
3476 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3477 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3479 case ir_intrinsic_memory_barrier_image
:
3480 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3481 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3483 case ir_intrinsic_memory_barrier_shared
:
3484 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3485 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3487 case ir_intrinsic_group_memory_barrier
:
3488 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3489 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3490 TGSI_MEMBAR_ATOMIC_BUFFER
|
3491 TGSI_MEMBAR_SHADER_IMAGE
|
3492 TGSI_MEMBAR_SHARED
|
3493 TGSI_MEMBAR_THREAD_GROUP
));
3496 assert(!"Unexpected memory barrier intrinsic");
3501 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3503 exec_node
*param
= ir
->actual_parameters
.get_head();
3505 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3507 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3509 /* Calculate the surface offset */
3510 offset
->accept(this);
3511 st_src_reg off
= this->result
;
3513 st_dst_reg dst
= undef_dst
;
3514 if (ir
->return_deref
) {
3515 ir
->return_deref
->accept(this);
3516 dst
= st_dst_reg(this->result
);
3517 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3520 glsl_to_tgsi_instruction
*inst
;
3522 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3523 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3524 inst
->buffer
= buffer
;
3525 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3526 param
= param
->get_next();
3527 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3530 param
= param
->get_next();
3531 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3533 dst
.writemask
= write_mask
->value
.u
[0];
3535 dst
.type
= this->result
.type
;
3536 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3537 inst
->buffer
= buffer
;
3539 param
= param
->get_next();
3540 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3543 st_src_reg data
= this->result
, data2
= undef_src
;
3545 switch (ir
->callee
->intrinsic_id
) {
3546 case ir_intrinsic_shared_atomic_add
:
3547 opcode
= TGSI_OPCODE_ATOMUADD
;
3549 case ir_intrinsic_shared_atomic_min
:
3550 opcode
= TGSI_OPCODE_ATOMIMIN
;
3552 case ir_intrinsic_shared_atomic_max
:
3553 opcode
= TGSI_OPCODE_ATOMIMAX
;
3555 case ir_intrinsic_shared_atomic_and
:
3556 opcode
= TGSI_OPCODE_ATOMAND
;
3558 case ir_intrinsic_shared_atomic_or
:
3559 opcode
= TGSI_OPCODE_ATOMOR
;
3561 case ir_intrinsic_shared_atomic_xor
:
3562 opcode
= TGSI_OPCODE_ATOMXOR
;
3564 case ir_intrinsic_shared_atomic_exchange
:
3565 opcode
= TGSI_OPCODE_ATOMXCHG
;
3567 case ir_intrinsic_shared_atomic_comp_swap
:
3568 opcode
= TGSI_OPCODE_ATOMCAS
;
3569 param
= param
->get_next();
3570 val
= ((ir_instruction
*)param
)->as_rvalue();
3572 data2
= this->result
;
3575 assert(!"Unexpected intrinsic");
3579 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3580 inst
->buffer
= buffer
;
3585 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3587 exec_node
*param
= ir
->actual_parameters
.get_head();
3589 ir_dereference
*img
= (ir_dereference
*)param
;
3590 const ir_variable
*imgvar
= img
->variable_referenced();
3591 const glsl_type
*type
= imgvar
->type
->without_array();
3592 unsigned sampler_array_size
= 1, sampler_base
= 0;
3595 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3597 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3598 (unsigned int *)&image
.index
, &reladdr
, true);
3599 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3600 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3601 *image
.reladdr
= reladdr
;
3602 emit_arl(ir
, sampler_reladdr
, reladdr
);
3605 st_dst_reg dst
= undef_dst
;
3606 if (ir
->return_deref
) {
3607 ir
->return_deref
->accept(this);
3608 dst
= st_dst_reg(this->result
);
3609 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3612 glsl_to_tgsi_instruction
*inst
;
3614 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3615 dst
.writemask
= WRITEMASK_XYZ
;
3616 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3617 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3618 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3619 st_dst_reg dstres
= st_dst_reg(res
);
3620 dstres
.writemask
= WRITEMASK_W
;
3621 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3622 res
.swizzle
= SWIZZLE_WWWW
;
3623 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3625 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3627 st_dst_reg coord_dst
;
3628 coord
= get_temp(glsl_type::ivec4_type
);
3629 coord_dst
= st_dst_reg(coord
);
3630 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3631 param
= param
->get_next();
3632 ((ir_dereference
*)param
)->accept(this);
3633 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3634 coord
.swizzle
= SWIZZLE_XXXX
;
3635 switch (type
->coordinate_components()) {
3636 case 4: assert(!"unexpected coord count");
3638 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3640 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3643 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3644 param
= param
->get_next();
3645 ((ir_dereference
*)param
)->accept(this);
3646 st_src_reg sample
= this->result
;
3647 sample
.swizzle
= SWIZZLE_XXXX
;
3648 coord_dst
.writemask
= WRITEMASK_W
;
3649 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3650 coord
.swizzle
|= SWIZZLE_W
<< 9;
3653 param
= param
->get_next();
3654 if (!param
->is_tail_sentinel()) {
3655 ((ir_dereference
*)param
)->accept(this);
3656 arg1
= this->result
;
3657 param
= param
->get_next();
3660 if (!param
->is_tail_sentinel()) {
3661 ((ir_dereference
*)param
)->accept(this);
3662 arg2
= this->result
;
3663 param
= param
->get_next();
3666 assert(param
->is_tail_sentinel());
3669 switch (ir
->callee
->intrinsic_id
) {
3670 case ir_intrinsic_image_load
:
3671 opcode
= TGSI_OPCODE_LOAD
;
3673 case ir_intrinsic_image_store
:
3674 opcode
= TGSI_OPCODE_STORE
;
3676 case ir_intrinsic_image_atomic_add
:
3677 opcode
= TGSI_OPCODE_ATOMUADD
;
3679 case ir_intrinsic_image_atomic_min
:
3680 opcode
= TGSI_OPCODE_ATOMIMIN
;
3682 case ir_intrinsic_image_atomic_max
:
3683 opcode
= TGSI_OPCODE_ATOMIMAX
;
3685 case ir_intrinsic_image_atomic_and
:
3686 opcode
= TGSI_OPCODE_ATOMAND
;
3688 case ir_intrinsic_image_atomic_or
:
3689 opcode
= TGSI_OPCODE_ATOMOR
;
3691 case ir_intrinsic_image_atomic_xor
:
3692 opcode
= TGSI_OPCODE_ATOMXOR
;
3694 case ir_intrinsic_image_atomic_exchange
:
3695 opcode
= TGSI_OPCODE_ATOMXCHG
;
3697 case ir_intrinsic_image_atomic_comp_swap
:
3698 opcode
= TGSI_OPCODE_ATOMCAS
;
3701 assert(!"Unexpected intrinsic");
3705 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3706 if (opcode
== TGSI_OPCODE_STORE
)
3707 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3710 inst
->buffer
= image
;
3711 inst
->sampler_array_size
= sampler_array_size
;
3712 inst
->sampler_base
= sampler_base
;
3714 switch (type
->sampler_dimensionality
) {
3715 case GLSL_SAMPLER_DIM_1D
:
3716 inst
->tex_target
= (type
->sampler_array
)
3717 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3719 case GLSL_SAMPLER_DIM_2D
:
3720 inst
->tex_target
= (type
->sampler_array
)
3721 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3723 case GLSL_SAMPLER_DIM_3D
:
3724 inst
->tex_target
= TEXTURE_3D_INDEX
;
3726 case GLSL_SAMPLER_DIM_CUBE
:
3727 inst
->tex_target
= (type
->sampler_array
)
3728 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3730 case GLSL_SAMPLER_DIM_RECT
:
3731 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3733 case GLSL_SAMPLER_DIM_BUF
:
3734 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3736 case GLSL_SAMPLER_DIM_EXTERNAL
:
3737 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3739 case GLSL_SAMPLER_DIM_MS
:
3740 inst
->tex_target
= (type
->sampler_array
)
3741 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3744 assert(!"Should not get here.");
3747 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3748 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3750 if (imgvar
->data
.image_coherent
)
3751 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3752 if (imgvar
->data
.image_restrict
)
3753 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3754 if (imgvar
->data
.image_volatile
)
3755 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3759 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3761 glsl_to_tgsi_instruction
*call_inst
;
3762 ir_function_signature
*sig
= ir
->callee
;
3763 function_entry
*entry
;
3766 /* Filter out intrinsics */
3767 switch (sig
->intrinsic_id
) {
3768 case ir_intrinsic_invalid
:
3771 case ir_intrinsic_atomic_counter_read
:
3772 case ir_intrinsic_atomic_counter_increment
:
3773 case ir_intrinsic_atomic_counter_predecrement
:
3774 case ir_intrinsic_atomic_counter_add
:
3775 case ir_intrinsic_atomic_counter_min
:
3776 case ir_intrinsic_atomic_counter_max
:
3777 case ir_intrinsic_atomic_counter_and
:
3778 case ir_intrinsic_atomic_counter_or
:
3779 case ir_intrinsic_atomic_counter_xor
:
3780 case ir_intrinsic_atomic_counter_exchange
:
3781 case ir_intrinsic_atomic_counter_comp_swap
:
3782 visit_atomic_counter_intrinsic(ir
);
3785 case ir_intrinsic_ssbo_load
:
3786 case ir_intrinsic_ssbo_store
:
3787 case ir_intrinsic_ssbo_atomic_add
:
3788 case ir_intrinsic_ssbo_atomic_min
:
3789 case ir_intrinsic_ssbo_atomic_max
:
3790 case ir_intrinsic_ssbo_atomic_and
:
3791 case ir_intrinsic_ssbo_atomic_or
:
3792 case ir_intrinsic_ssbo_atomic_xor
:
3793 case ir_intrinsic_ssbo_atomic_exchange
:
3794 case ir_intrinsic_ssbo_atomic_comp_swap
:
3795 visit_ssbo_intrinsic(ir
);
3798 case ir_intrinsic_memory_barrier
:
3799 case ir_intrinsic_memory_barrier_atomic_counter
:
3800 case ir_intrinsic_memory_barrier_buffer
:
3801 case ir_intrinsic_memory_barrier_image
:
3802 case ir_intrinsic_memory_barrier_shared
:
3803 case ir_intrinsic_group_memory_barrier
:
3804 visit_membar_intrinsic(ir
);
3807 case ir_intrinsic_shared_load
:
3808 case ir_intrinsic_shared_store
:
3809 case ir_intrinsic_shared_atomic_add
:
3810 case ir_intrinsic_shared_atomic_min
:
3811 case ir_intrinsic_shared_atomic_max
:
3812 case ir_intrinsic_shared_atomic_and
:
3813 case ir_intrinsic_shared_atomic_or
:
3814 case ir_intrinsic_shared_atomic_xor
:
3815 case ir_intrinsic_shared_atomic_exchange
:
3816 case ir_intrinsic_shared_atomic_comp_swap
:
3817 visit_shared_intrinsic(ir
);
3820 case ir_intrinsic_image_load
:
3821 case ir_intrinsic_image_store
:
3822 case ir_intrinsic_image_atomic_add
:
3823 case ir_intrinsic_image_atomic_min
:
3824 case ir_intrinsic_image_atomic_max
:
3825 case ir_intrinsic_image_atomic_and
:
3826 case ir_intrinsic_image_atomic_or
:
3827 case ir_intrinsic_image_atomic_xor
:
3828 case ir_intrinsic_image_atomic_exchange
:
3829 case ir_intrinsic_image_atomic_comp_swap
:
3830 case ir_intrinsic_image_size
:
3831 case ir_intrinsic_image_samples
:
3832 visit_image_intrinsic(ir
);
3835 case ir_intrinsic_generic_load
:
3836 case ir_intrinsic_generic_store
:
3837 case ir_intrinsic_generic_atomic_add
:
3838 case ir_intrinsic_generic_atomic_and
:
3839 case ir_intrinsic_generic_atomic_or
:
3840 case ir_intrinsic_generic_atomic_xor
:
3841 case ir_intrinsic_generic_atomic_min
:
3842 case ir_intrinsic_generic_atomic_max
:
3843 case ir_intrinsic_generic_atomic_exchange
:
3844 case ir_intrinsic_generic_atomic_comp_swap
:
3845 case ir_intrinsic_shader_clock
:
3846 unreachable("Invalid intrinsic");
3849 entry
= get_function_signature(sig
);
3850 /* Process in parameters. */
3851 foreach_two_lists(formal_node
, &sig
->parameters
,
3852 actual_node
, &ir
->actual_parameters
) {
3853 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3854 ir_variable
*param
= (ir_variable
*) formal_node
;
3856 if (param
->data
.mode
== ir_var_function_in
||
3857 param
->data
.mode
== ir_var_function_inout
) {
3858 variable_storage
*storage
= find_variable_storage(param
);
3861 param_rval
->accept(this);
3862 st_src_reg r
= this->result
;
3865 l
.file
= storage
->file
;
3866 l
.index
= storage
->index
;
3868 l
.writemask
= WRITEMASK_XYZW
;
3870 for (i
= 0; i
< type_size(param
->type
); i
++) {
3871 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3878 /* Emit call instruction */
3879 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3880 call_inst
->function
= entry
;
3882 /* Process out parameters. */
3883 foreach_two_lists(formal_node
, &sig
->parameters
,
3884 actual_node
, &ir
->actual_parameters
) {
3885 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3886 ir_variable
*param
= (ir_variable
*) formal_node
;
3888 if (param
->data
.mode
== ir_var_function_out
||
3889 param
->data
.mode
== ir_var_function_inout
) {
3890 variable_storage
*storage
= find_variable_storage(param
);
3894 r
.file
= storage
->file
;
3895 r
.index
= storage
->index
;
3897 r
.swizzle
= SWIZZLE_NOOP
;
3900 param_rval
->accept(this);
3901 st_dst_reg l
= st_dst_reg(this->result
);
3903 for (i
= 0; i
< type_size(param
->type
); i
++) {
3904 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3911 /* Process return value. */
3912 this->result
= entry
->return_reg
;
3916 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*head
,
3917 ir_dereference
*tail
,
3918 unsigned *array_elements
,
3921 st_src_reg
*indirect
,
3924 switch (tail
->ir_type
) {
3925 case ir_type_dereference_record
: {
3926 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3927 const glsl_type
*struct_type
= deref_record
->record
->type
;
3928 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3930 calc_deref_offsets(head
, deref_record
->record
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3932 assert(field_index
>= 0);
3933 *location
+= struct_type
->record_location_offset(field_index
);
3937 case ir_type_dereference_array
: {
3938 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3939 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3942 st_src_reg temp_reg
;
3943 st_dst_reg temp_dst
;
3945 temp_reg
= get_temp(glsl_type::uint_type
);
3946 temp_dst
= st_dst_reg(temp_reg
);
3947 temp_dst
.writemask
= 1;
3949 deref_arr
->array_index
->accept(this);
3950 if (*array_elements
!= 1)
3951 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3953 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3955 if (indirect
->file
== PROGRAM_UNDEFINED
)
3956 *indirect
= temp_reg
;
3958 temp_dst
= st_dst_reg(*indirect
);
3959 temp_dst
.writemask
= 1;
3960 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3963 *index
+= array_index
->value
.u
[0] * *array_elements
;
3965 *array_elements
*= deref_arr
->array
->type
->length
;
3967 calc_deref_offsets(head
, deref_arr
->array
->as_dereference(), array_elements
, base
, index
, indirect
, location
);
3976 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3977 unsigned *array_size
,
3980 st_src_reg
*reladdr
,
3983 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3984 unsigned location
= 0;
3985 ir_variable
*var
= ir
->variable_referenced();
3987 memset(reladdr
, 0, sizeof(*reladdr
));
3988 reladdr
->file
= PROGRAM_UNDEFINED
;
3994 location
= var
->data
.location
;
3995 calc_deref_offsets(ir
, ir
, array_size
, base
, index
, reladdr
, &location
);
3998 * If we end up with no indirect then adjust the base to the index,
3999 * and set the array size to 1.
4001 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4007 assert(location
!= 0xffffffff);
4008 *base
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
4009 *index
+= this->shader_program
->UniformStorage
[location
].opaque
[shader
].index
;
4014 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4016 if (offset
.reladdr
|| offset
.reladdr2
) {
4017 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4018 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4019 tmp_dst
.writemask
= WRITEMASK_XY
;
4020 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4028 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4030 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4031 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4032 st_src_reg levels_src
, reladdr
;
4033 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4034 glsl_to_tgsi_instruction
*inst
= NULL
;
4035 unsigned opcode
= TGSI_OPCODE_NOP
;
4036 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4037 unsigned sampler_array_size
= 1, sampler_index
= 0, sampler_base
= 0;
4038 bool is_cube_array
= false;
4041 /* if we are a cube array sampler */
4042 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
4043 sampler_type
->sampler_array
)) {
4044 is_cube_array
= true;
4047 if (ir
->coordinate
) {
4048 ir
->coordinate
->accept(this);
4050 /* Put our coords in a temp. We'll need to modify them for shadow,
4051 * projection, or LOD, so the only case we'd use it as-is is if
4052 * we're doing plain old texturing. The optimization passes on
4053 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4055 coord
= get_temp(glsl_type::vec4_type
);
4056 coord_dst
= st_dst_reg(coord
);
4057 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4058 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4061 if (ir
->projector
) {
4062 ir
->projector
->accept(this);
4063 projector
= this->result
;
4066 /* Storage for our result. Ideally for an assignment we'd be using
4067 * the actual storage for the result here, instead.
4069 result_src
= get_temp(ir
->type
);
4070 result_dst
= st_dst_reg(result_src
);
4074 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4076 ir
->offset
->accept(this);
4077 offset
[0] = this->result
;
4081 if (is_cube_array
||
4082 sampler_type
== glsl_type::samplerCubeShadow_type
) {
4083 opcode
= TGSI_OPCODE_TXB2
;
4086 opcode
= TGSI_OPCODE_TXB
;
4088 ir
->lod_info
.bias
->accept(this);
4089 lod_info
= this->result
;
4091 ir
->offset
->accept(this);
4092 offset
[0] = this->result
;
4096 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4097 ir
->lod_info
.lod
->accept(this);
4098 lod_info
= this->result
;
4100 ir
->offset
->accept(this);
4101 offset
[0] = this->result
;
4105 opcode
= TGSI_OPCODE_TXD
;
4106 ir
->lod_info
.grad
.dPdx
->accept(this);
4108 ir
->lod_info
.grad
.dPdy
->accept(this);
4111 ir
->offset
->accept(this);
4112 offset
[0] = this->result
;
4116 opcode
= TGSI_OPCODE_TXQ
;
4117 ir
->lod_info
.lod
->accept(this);
4118 lod_info
= this->result
;
4120 case ir_query_levels
:
4121 opcode
= TGSI_OPCODE_TXQ
;
4122 lod_info
= undef_src
;
4123 levels_src
= get_temp(ir
->type
);
4126 opcode
= TGSI_OPCODE_TXF
;
4127 ir
->lod_info
.lod
->accept(this);
4128 lod_info
= this->result
;
4130 ir
->offset
->accept(this);
4131 offset
[0] = this->result
;
4135 opcode
= TGSI_OPCODE_TXF
;
4136 ir
->lod_info
.sample_index
->accept(this);
4137 sample_index
= this->result
;
4140 opcode
= TGSI_OPCODE_TG4
;
4141 ir
->lod_info
.component
->accept(this);
4142 component
= this->result
;
4144 ir
->offset
->accept(this);
4145 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4146 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4147 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4148 offset
[i
] = this->result
;
4149 offset
[i
].index
+= i
* type_size(elt_type
);
4150 offset
[i
].type
= elt_type
->base_type
;
4151 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4152 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4155 offset
[0] = canonicalize_gather_offset(this->result
);
4160 opcode
= TGSI_OPCODE_LODQ
;
4162 case ir_texture_samples
:
4163 opcode
= TGSI_OPCODE_TXQS
;
4165 case ir_samples_identical
:
4166 unreachable("Unexpected ir_samples_identical opcode");
4169 if (ir
->projector
) {
4170 if (opcode
== TGSI_OPCODE_TEX
) {
4171 /* Slot the projector in as the last component of the coord. */
4172 coord_dst
.writemask
= WRITEMASK_W
;
4173 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4174 coord_dst
.writemask
= WRITEMASK_XYZW
;
4175 opcode
= TGSI_OPCODE_TXP
;
4177 st_src_reg coord_w
= coord
;
4178 coord_w
.swizzle
= SWIZZLE_WWWW
;
4180 /* For the other TEX opcodes there's no projective version
4181 * since the last slot is taken up by LOD info. Do the
4182 * projective divide now.
4184 coord_dst
.writemask
= WRITEMASK_W
;
4185 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4187 /* In the case where we have to project the coordinates "by hand,"
4188 * the shadow comparator value must also be projected.
4190 st_src_reg tmp_src
= coord
;
4191 if (ir
->shadow_comparitor
) {
4192 /* Slot the shadow value in as the second to last component of the
4195 ir
->shadow_comparitor
->accept(this);
4197 tmp_src
= get_temp(glsl_type::vec4_type
);
4198 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4200 /* Projective division not allowed for array samplers. */
4201 assert(!sampler_type
->sampler_array
);
4203 tmp_dst
.writemask
= WRITEMASK_Z
;
4204 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4206 tmp_dst
.writemask
= WRITEMASK_XY
;
4207 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4210 coord_dst
.writemask
= WRITEMASK_XYZ
;
4211 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4213 coord_dst
.writemask
= WRITEMASK_XYZW
;
4214 coord
.swizzle
= SWIZZLE_XYZW
;
4218 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4219 * comparator was put in the correct place (and projected) by the code,
4220 * above, that handles by-hand projection.
4222 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4223 /* Slot the shadow value in as the second to last component of the
4226 ir
->shadow_comparitor
->accept(this);
4228 if (is_cube_array
) {
4229 cube_sc
= get_temp(glsl_type::float_type
);
4230 cube_sc_dst
= st_dst_reg(cube_sc
);
4231 cube_sc_dst
.writemask
= WRITEMASK_X
;
4232 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4233 cube_sc_dst
.writemask
= WRITEMASK_X
;
4236 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4237 sampler_type
->sampler_array
) ||
4238 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4239 coord_dst
.writemask
= WRITEMASK_W
;
4241 coord_dst
.writemask
= WRITEMASK_Z
;
4243 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4244 coord_dst
.writemask
= WRITEMASK_XYZW
;
4248 if (ir
->op
== ir_txf_ms
) {
4249 coord_dst
.writemask
= WRITEMASK_W
;
4250 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4251 coord_dst
.writemask
= WRITEMASK_XYZW
;
4252 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4253 opcode
== TGSI_OPCODE_TXF
) {
4254 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4255 coord_dst
.writemask
= WRITEMASK_W
;
4256 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4257 coord_dst
.writemask
= WRITEMASK_XYZW
;
4260 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4261 &sampler_index
, &reladdr
, true);
4262 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4263 emit_arl(ir
, sampler_reladdr
, reladdr
);
4265 if (opcode
== TGSI_OPCODE_TXD
)
4266 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4267 else if (opcode
== TGSI_OPCODE_TXQ
) {
4268 if (ir
->op
== ir_query_levels
) {
4269 /* the level is stored in W */
4270 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4271 result_dst
.writemask
= WRITEMASK_X
;
4272 levels_src
.swizzle
= SWIZZLE_WWWW
;
4273 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4275 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4276 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4277 inst
= emit_asm(ir
, opcode
, result_dst
);
4278 } else if (opcode
== TGSI_OPCODE_TXF
) {
4279 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4280 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4281 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4282 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4283 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4284 } else if (opcode
== TGSI_OPCODE_TG4
) {
4285 if (is_cube_array
&& ir
->shadow_comparitor
) {
4286 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4288 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4291 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4293 if (ir
->shadow_comparitor
)
4294 inst
->tex_shadow
= GL_TRUE
;
4296 inst
->sampler
.index
= sampler_index
;
4297 inst
->sampler_array_size
= sampler_array_size
;
4298 inst
->sampler_base
= sampler_base
;
4300 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4301 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4302 memcpy(inst
->sampler
.reladdr
, &reladdr
, sizeof(reladdr
));
4306 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4307 inst
->tex_offsets
[i
] = offset
[i
];
4308 inst
->tex_offset_num_offset
= i
;
4311 switch (sampler_type
->sampler_dimensionality
) {
4312 case GLSL_SAMPLER_DIM_1D
:
4313 inst
->tex_target
= (sampler_type
->sampler_array
)
4314 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4316 case GLSL_SAMPLER_DIM_2D
:
4317 inst
->tex_target
= (sampler_type
->sampler_array
)
4318 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4320 case GLSL_SAMPLER_DIM_3D
:
4321 inst
->tex_target
= TEXTURE_3D_INDEX
;
4323 case GLSL_SAMPLER_DIM_CUBE
:
4324 inst
->tex_target
= (sampler_type
->sampler_array
)
4325 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4327 case GLSL_SAMPLER_DIM_RECT
:
4328 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4330 case GLSL_SAMPLER_DIM_BUF
:
4331 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4333 case GLSL_SAMPLER_DIM_EXTERNAL
:
4334 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4336 case GLSL_SAMPLER_DIM_MS
:
4337 inst
->tex_target
= (sampler_type
->sampler_array
)
4338 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4341 assert(!"Should not get here.");
4344 inst
->tex_type
= ir
->type
->base_type
;
4346 this->result
= result_src
;
4350 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4352 if (ir
->get_value()) {
4356 assert(current_function
);
4358 ir
->get_value()->accept(this);
4359 st_src_reg r
= this->result
;
4361 l
= st_dst_reg(current_function
->return_reg
);
4363 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
4364 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
4370 emit_asm(ir
, TGSI_OPCODE_RET
);
4374 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4376 if (ir
->condition
) {
4377 ir
->condition
->accept(this);
4378 st_src_reg condition
= this->result
;
4380 /* Convert the bool condition to a float so we can negate. */
4381 if (native_integers
) {
4382 st_src_reg temp
= get_temp(ir
->condition
->type
);
4383 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4384 condition
, st_src_reg_for_float(1.0));
4388 condition
.negate
= ~condition
.negate
;
4389 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4391 /* unconditional kil */
4392 emit_asm(ir
, TGSI_OPCODE_KILL
);
4397 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4400 glsl_to_tgsi_instruction
*if_inst
;
4402 ir
->condition
->accept(this);
4403 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4405 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4407 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4409 this->instructions
.push_tail(if_inst
);
4411 visit_exec_list(&ir
->then_instructions
, this);
4413 if (!ir
->else_instructions
.is_empty()) {
4414 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4415 visit_exec_list(&ir
->else_instructions
, this);
4418 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4423 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4425 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4427 ir
->stream
->accept(this);
4428 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4432 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4434 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4436 ir
->stream
->accept(this);
4437 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4441 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4443 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4444 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4446 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4449 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4451 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4453 result
.file
= PROGRAM_UNDEFINED
;
4460 num_input_arrays
= 0;
4461 num_output_arrays
= 0;
4462 next_signature_id
= 1;
4464 current_function
= NULL
;
4465 num_address_regs
= 0;
4469 indirect_addr_consts
= false;
4470 wpos_transform_const
= -1;
4472 native_integers
= false;
4473 mem_ctx
= ralloc_context(NULL
);
4476 shader_program
= NULL
;
4481 use_shared_memory
= false;
4484 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4487 ralloc_free(mem_ctx
);
4490 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4497 * Count resources used by the given gpu program (number of texture
4501 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4503 v
->samplers_used
= 0;
4504 v
->buffers_used
= 0;
4507 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4508 if (inst
->info
->is_tex
) {
4509 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4510 unsigned idx
= inst
->sampler_base
+ i
;
4511 v
->samplers_used
|= 1u << idx
;
4513 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4514 v
->sampler_types
[idx
] = inst
->tex_type
;
4515 v
->sampler_targets
[idx
] =
4516 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4518 if (inst
->tex_shadow
) {
4519 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
4524 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4525 prog
->ExternalSamplersUsed
|= 1 << inst
->sampler
.index
;
4527 if (inst
->buffer
.file
!= PROGRAM_UNDEFINED
&& (
4528 is_resource_instruction(inst
->op
) ||
4529 inst
->op
== TGSI_OPCODE_STORE
)) {
4530 if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
4531 v
->buffers_used
|= 1 << inst
->buffer
.index
;
4532 } else if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
4533 v
->use_shared_memory
= true;
4535 assert(inst
->buffer
.file
== PROGRAM_IMAGE
);
4536 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4537 unsigned idx
= inst
->sampler_base
+ i
;
4538 v
->images_used
|= 1 << idx
;
4539 v
->image_targets
[idx
] =
4540 st_translate_texture_target(inst
->tex_target
, false);
4541 v
->image_formats
[idx
] = inst
->image_format
;
4546 prog
->SamplersUsed
= v
->samplers_used
;
4548 if (v
->shader_program
!= NULL
)
4549 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4553 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4554 * are read from the given src in this instruction
4557 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4559 int read_mask
= 0, comp
;
4561 /* Now, given the src swizzle and the written channels, find which
4562 * components are actually read
4564 for (comp
= 0; comp
< 4; ++comp
) {
4565 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4567 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4568 read_mask
|= 1 << coord
;
4575 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4576 * instruction is the first instruction to write to register T0. There are
4577 * several lowering passes done in GLSL IR (e.g. branches and
4578 * relative addressing) that create a large number of conditional assignments
4579 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4581 * Here is why this conversion is safe:
4582 * CMP T0, T1 T2 T0 can be expanded to:
4588 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4589 * as the original program. If (T1 < 0.0) evaluates to false, executing
4590 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4591 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4592 * because any instruction that was going to read from T0 after this was going
4593 * to read a garbage value anyway.
4596 glsl_to_tgsi_visitor::simplify_cmp(void)
4598 int tempWritesSize
= 0;
4599 unsigned *tempWrites
= NULL
;
4600 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4602 memset(outputWrites
, 0, sizeof(outputWrites
));
4604 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4605 unsigned prevWriteMask
= 0;
4607 /* Give up if we encounter relative addressing or flow control. */
4608 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4609 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4610 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4611 inst
->op
== TGSI_OPCODE_BGNSUB
||
4612 inst
->op
== TGSI_OPCODE_CONT
||
4613 inst
->op
== TGSI_OPCODE_END
||
4614 inst
->op
== TGSI_OPCODE_ENDSUB
||
4615 inst
->op
== TGSI_OPCODE_RET
) {
4619 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4620 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4621 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4622 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4623 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4624 if (inst
->dst
[0].index
>= tempWritesSize
) {
4625 const int inc
= 4096;
4627 tempWrites
= (unsigned*)
4629 (tempWritesSize
+ inc
) * sizeof(unsigned));
4633 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4634 tempWritesSize
+= inc
;
4637 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4638 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4642 /* For a CMP to be considered a conditional write, the destination
4643 * register and source register two must be the same. */
4644 if (inst
->op
== TGSI_OPCODE_CMP
4645 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4646 && inst
->src
[2].file
== inst
->dst
[0].file
4647 && inst
->src
[2].index
== inst
->dst
[0].index
4648 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4650 inst
->op
= TGSI_OPCODE_MOV
;
4651 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4652 inst
->src
[0] = inst
->src
[1];
4659 /* Replaces all references to a temporary register index with another index. */
4661 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4663 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4666 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4667 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4668 for (k
= 0; k
< num_renames
; k
++)
4669 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4670 inst
->src
[j
].index
= renames
[k
].new_reg
;
4673 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4674 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4675 for (k
= 0; k
< num_renames
; k
++)
4676 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4677 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4680 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4681 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4682 for (k
= 0; k
< num_renames
; k
++)
4683 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4684 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4690 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4692 int depth
= 0; /* loop depth */
4693 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4696 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4697 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4698 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4699 if (first_reads
[inst
->src
[j
].index
] == -1)
4700 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4703 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4704 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4705 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4706 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4709 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4712 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4722 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4724 int depth
= 0; /* loop depth */
4725 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4728 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4729 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4730 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4731 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4733 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4734 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4735 if (first_writes
[inst
->dst
[j
].index
] == -1)
4736 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4737 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4740 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4741 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4742 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4744 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4747 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4750 for (k
= 0; k
< this->next_temp
; k
++) {
4751 if (last_reads
[k
] == -2) {
4763 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4765 int depth
= 0; /* loop depth */
4769 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4770 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4771 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4772 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4775 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4777 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4779 for (k
= 0; k
< this->next_temp
; k
++) {
4780 if (last_writes
[k
] == -2) {
4791 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4792 * channels for copy propagation and updates following instructions to
4793 * use the original versions.
4795 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4796 * will occur. As an example, a TXP production before this pass:
4798 * 0: MOV TEMP[1], INPUT[4].xyyy;
4799 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4800 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4804 * 0: MOV TEMP[1], INPUT[4].xyyy;
4805 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4806 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4808 * which allows for dead code elimination on TEMP[1]'s writes.
4811 glsl_to_tgsi_visitor::copy_propagate(void)
4813 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4814 glsl_to_tgsi_instruction
*,
4815 this->next_temp
* 4);
4816 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4819 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4820 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4821 || inst
->dst
[0].index
< this->next_temp
);
4823 /* First, do any copy propagation possible into the src regs. */
4824 for (int r
= 0; r
< 3; r
++) {
4825 glsl_to_tgsi_instruction
*first
= NULL
;
4827 int acp_base
= inst
->src
[r
].index
* 4;
4829 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4830 inst
->src
[r
].reladdr
||
4831 inst
->src
[r
].reladdr2
)
4834 /* See if we can find entries in the ACP consisting of MOVs
4835 * from the same src register for all the swizzled channels
4836 * of this src register reference.
4838 for (int i
= 0; i
< 4; i
++) {
4839 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4840 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4847 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4852 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4853 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4854 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4855 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4863 /* We've now validated that we can copy-propagate to
4864 * replace this src register reference. Do it.
4866 inst
->src
[r
].file
= first
->src
[0].file
;
4867 inst
->src
[r
].index
= first
->src
[0].index
;
4868 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4869 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4870 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4871 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4874 for (int i
= 0; i
< 4; i
++) {
4875 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4876 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4877 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4879 inst
->src
[r
].swizzle
= swizzle
;
4884 case TGSI_OPCODE_BGNLOOP
:
4885 case TGSI_OPCODE_ENDLOOP
:
4886 /* End of a basic block, clear the ACP entirely. */
4887 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4890 case TGSI_OPCODE_IF
:
4891 case TGSI_OPCODE_UIF
:
4895 case TGSI_OPCODE_ENDIF
:
4896 case TGSI_OPCODE_ELSE
:
4897 /* Clear all channels written inside the block from the ACP, but
4898 * leaving those that were not touched.
4900 for (int r
= 0; r
< this->next_temp
; r
++) {
4901 for (int c
= 0; c
< 4; c
++) {
4902 if (!acp
[4 * r
+ c
])
4905 if (acp_level
[4 * r
+ c
] >= level
)
4906 acp
[4 * r
+ c
] = NULL
;
4909 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4914 /* Continuing the block, clear any written channels from
4917 for (int d
= 0; d
< 2; d
++) {
4918 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4919 /* Any temporary might be written, so no copy propagation
4920 * across this instruction.
4922 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4923 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4924 inst
->dst
[d
].reladdr
) {
4925 /* Any output might be written, so no copy propagation
4926 * from outputs across this instruction.
4928 for (int r
= 0; r
< this->next_temp
; r
++) {
4929 for (int c
= 0; c
< 4; c
++) {
4930 if (!acp
[4 * r
+ c
])
4933 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4934 acp
[4 * r
+ c
] = NULL
;
4937 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4938 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4939 /* Clear where it's used as dst. */
4940 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4941 for (int c
= 0; c
< 4; c
++) {
4942 if (inst
->dst
[d
].writemask
& (1 << c
))
4943 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4947 /* Clear where it's used as src. */
4948 for (int r
= 0; r
< this->next_temp
; r
++) {
4949 for (int c
= 0; c
< 4; c
++) {
4950 if (!acp
[4 * r
+ c
])
4953 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4955 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4956 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4957 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4958 acp
[4 * r
+ c
] = NULL
;
4967 /* If this is a copy, add it to the ACP. */
4968 if (inst
->op
== TGSI_OPCODE_MOV
&&
4969 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4970 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4971 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4972 !inst
->dst
[0].reladdr
&&
4973 !inst
->dst
[0].reladdr2
&&
4975 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4976 !inst
->src
[0].reladdr
&&
4977 !inst
->src
[0].reladdr2
&&
4978 !inst
->src
[0].negate
) {
4979 for (int i
= 0; i
< 4; i
++) {
4980 if (inst
->dst
[0].writemask
& (1 << i
)) {
4981 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4982 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4988 ralloc_free(acp_level
);
4993 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4996 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4997 * will occur. As an example, a TXP production after copy propagation but
5000 * 0: MOV TEMP[1], INPUT[4].xyyy;
5001 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5002 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5004 * and after this pass:
5006 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5009 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5011 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5012 glsl_to_tgsi_instruction
*,
5013 this->next_temp
* 4);
5014 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5018 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5019 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5020 || inst
->dst
[0].index
< this->next_temp
);
5023 case TGSI_OPCODE_BGNLOOP
:
5024 case TGSI_OPCODE_ENDLOOP
:
5025 case TGSI_OPCODE_CONT
:
5026 case TGSI_OPCODE_BRK
:
5027 /* End of a basic block, clear the write array entirely.
5029 * This keeps us from killing dead code when the writes are
5030 * on either side of a loop, even when the register isn't touched
5031 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5032 * dead code of this type, so it shouldn't make a difference as long as
5033 * the dead code elimination pass in the GLSL compiler does its job.
5035 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5038 case TGSI_OPCODE_ENDIF
:
5039 case TGSI_OPCODE_ELSE
:
5040 /* Promote the recorded level of all channels written inside the
5041 * preceding if or else block to the level above the if/else block.
5043 for (int r
= 0; r
< this->next_temp
; r
++) {
5044 for (int c
= 0; c
< 4; c
++) {
5045 if (!writes
[4 * r
+ c
])
5048 if (write_level
[4 * r
+ c
] == level
)
5049 write_level
[4 * r
+ c
] = level
-1;
5052 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5056 case TGSI_OPCODE_IF
:
5057 case TGSI_OPCODE_UIF
:
5059 /* fallthrough to default case to mark the condition as read */
5061 /* Continuing the block, clear any channels from the write array that
5062 * are read by this instruction.
5064 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5065 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5066 /* Any temporary might be read, so no dead code elimination
5067 * across this instruction.
5069 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5070 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5071 /* Clear where it's used as src. */
5072 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5073 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5074 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5075 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5077 for (int c
= 0; c
< 4; c
++) {
5078 if (src_chans
& (1 << c
))
5079 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5083 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5084 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5085 /* Any temporary might be read, so no dead code elimination
5086 * across this instruction.
5088 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5089 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5090 /* Clear where it's used as src. */
5091 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5092 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5093 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5094 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5096 for (int c
= 0; c
< 4; c
++) {
5097 if (src_chans
& (1 << c
))
5098 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5105 /* If this instruction writes to a temporary, add it to the write array.
5106 * If there is already an instruction in the write array for one or more
5107 * of the channels, flag that channel write as dead.
5109 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5110 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5111 !inst
->dst
[i
].reladdr
) {
5112 for (int c
= 0; c
< 4; c
++) {
5113 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5114 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5115 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5118 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5120 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5121 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5128 /* Anything still in the write array at this point is dead code. */
5129 for (int r
= 0; r
< this->next_temp
; r
++) {
5130 for (int c
= 0; c
< 4; c
++) {
5131 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5133 inst
->dead_mask
|= (1 << c
);
5137 /* Now actually remove the instructions that are completely dead and update
5138 * the writemask of other instructions with dead channels.
5140 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5141 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5143 /* No amount of dead masks should remove memory stores */
5144 if (inst
->info
->is_store
)
5147 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5152 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5153 if (inst
->dead_mask
== WRITEMASK_XY
||
5154 inst
->dead_mask
== WRITEMASK_ZW
)
5155 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5157 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5161 ralloc_free(write_level
);
5162 ralloc_free(writes
);
5167 /* merge DFRACEXP instructions into one. */
5169 glsl_to_tgsi_visitor::merge_two_dsts(void)
5171 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5172 glsl_to_tgsi_instruction
*inst2
;
5174 if (num_inst_dst_regs(inst
) != 2)
5177 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5178 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5181 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5184 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5185 inst
->src
[0].index
== inst2
->src
[0].index
&&
5186 inst
->src
[0].type
== inst2
->src
[0].type
&&
5187 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5189 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5195 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5197 inst
->dst
[0] = inst2
->dst
[0];
5198 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5199 inst
->dst
[1] = inst2
->dst
[1];
5210 /* Merges temporary registers together where possible to reduce the number of
5211 * registers needed to run a program.
5213 * Produces optimal code only after copy propagation and dead code elimination
5216 glsl_to_tgsi_visitor::merge_registers(void)
5218 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5219 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5220 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5222 int num_renames
= 0;
5224 /* Read the indices of the last read and first write to each temp register
5225 * into an array so that we don't have to traverse the instruction list as
5227 for (i
= 0; i
< this->next_temp
; i
++) {
5229 first_writes
[i
] = -1;
5231 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5233 /* Start looking for registers with non-overlapping usages that can be
5234 * merged together. */
5235 for (i
= 0; i
< this->next_temp
; i
++) {
5236 /* Don't touch unused registers. */
5237 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5239 for (j
= 0; j
< this->next_temp
; j
++) {
5240 /* Don't touch unused registers. */
5241 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5243 /* We can merge the two registers if the first write to j is after or
5244 * in the same instruction as the last read from i. Note that the
5245 * register at index i will always be used earlier or at the same time
5246 * as the register at index j. */
5247 if (first_writes
[i
] <= first_writes
[j
] &&
5248 last_reads
[i
] <= first_writes
[j
]) {
5249 renames
[num_renames
].old_reg
= j
;
5250 renames
[num_renames
].new_reg
= i
;
5253 /* Update the first_writes and last_reads arrays with the new
5254 * values for the merged register index, and mark the newly unused
5255 * register index as such. */
5256 assert(last_reads
[j
] >= last_reads
[i
]);
5257 last_reads
[i
] = last_reads
[j
];
5258 first_writes
[j
] = -1;
5264 rename_temp_registers(num_renames
, renames
);
5265 ralloc_free(renames
);
5266 ralloc_free(last_reads
);
5267 ralloc_free(first_writes
);
5270 /* Reassign indices to temporary registers by reusing unused indices created
5271 * by optimization passes. */
5273 glsl_to_tgsi_visitor::renumber_registers(void)
5277 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5278 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5279 int num_renames
= 0;
5280 for (i
= 0; i
< this->next_temp
; i
++) {
5281 first_reads
[i
] = -1;
5283 get_first_temp_read(first_reads
);
5285 for (i
= 0; i
< this->next_temp
; i
++) {
5286 if (first_reads
[i
] < 0) continue;
5287 if (i
!= new_index
) {
5288 renames
[num_renames
].old_reg
= i
;
5289 renames
[num_renames
].new_reg
= new_index
;
5295 rename_temp_registers(num_renames
, renames
);
5296 this->next_temp
= new_index
;
5297 ralloc_free(renames
);
5298 ralloc_free(first_reads
);
5301 /* ------------------------- TGSI conversion stuff -------------------------- */
5303 unsigned branch_target
;
5308 * Intermediate state used during shader translation.
5310 struct st_translate
{
5311 struct ureg_program
*ureg
;
5313 unsigned temps_size
;
5314 struct ureg_dst
*temps
;
5316 struct ureg_dst
*arrays
;
5317 unsigned num_temp_arrays
;
5318 struct ureg_src
*constants
;
5320 struct ureg_src
*immediates
;
5322 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5323 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5324 struct ureg_dst address
[3];
5325 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5326 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5327 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5328 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5329 struct ureg_src shared_memory
;
5330 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
5331 unsigned *array_sizes
;
5332 struct inout_decl
*input_decls
;
5333 unsigned num_input_decls
;
5334 struct inout_decl
*output_decls
;
5335 unsigned num_output_decls
;
5337 const GLuint
*inputMapping
;
5338 const GLuint
*outputMapping
;
5340 /* For every instruction that contains a label (eg CALL), keep
5341 * details so that we can go back afterwards and emit the correct
5342 * tgsi instruction number for each label.
5344 struct label
*labels
;
5345 unsigned labels_size
;
5346 unsigned labels_count
;
5348 /* Keep a record of the tgsi instruction number that each mesa
5349 * instruction starts at, will be used to fix up labels after
5354 unsigned insn_count
;
5356 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5361 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5363 _mesa_sysval_to_semantic(unsigned sysval
)
5367 case SYSTEM_VALUE_VERTEX_ID
:
5368 return TGSI_SEMANTIC_VERTEXID
;
5369 case SYSTEM_VALUE_INSTANCE_ID
:
5370 return TGSI_SEMANTIC_INSTANCEID
;
5371 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5372 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5373 case SYSTEM_VALUE_BASE_VERTEX
:
5374 return TGSI_SEMANTIC_BASEVERTEX
;
5375 case SYSTEM_VALUE_BASE_INSTANCE
:
5376 return TGSI_SEMANTIC_BASEINSTANCE
;
5377 case SYSTEM_VALUE_DRAW_ID
:
5378 return TGSI_SEMANTIC_DRAWID
;
5380 /* Geometry shader */
5381 case SYSTEM_VALUE_INVOCATION_ID
:
5382 return TGSI_SEMANTIC_INVOCATIONID
;
5384 /* Fragment shader */
5385 case SYSTEM_VALUE_FRAG_COORD
:
5386 return TGSI_SEMANTIC_POSITION
;
5387 case SYSTEM_VALUE_FRONT_FACE
:
5388 return TGSI_SEMANTIC_FACE
;
5389 case SYSTEM_VALUE_SAMPLE_ID
:
5390 return TGSI_SEMANTIC_SAMPLEID
;
5391 case SYSTEM_VALUE_SAMPLE_POS
:
5392 return TGSI_SEMANTIC_SAMPLEPOS
;
5393 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5394 return TGSI_SEMANTIC_SAMPLEMASK
;
5395 case SYSTEM_VALUE_HELPER_INVOCATION
:
5396 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5398 /* Tessellation shader */
5399 case SYSTEM_VALUE_TESS_COORD
:
5400 return TGSI_SEMANTIC_TESSCOORD
;
5401 case SYSTEM_VALUE_VERTICES_IN
:
5402 return TGSI_SEMANTIC_VERTICESIN
;
5403 case SYSTEM_VALUE_PRIMITIVE_ID
:
5404 return TGSI_SEMANTIC_PRIMID
;
5405 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5406 return TGSI_SEMANTIC_TESSOUTER
;
5407 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5408 return TGSI_SEMANTIC_TESSINNER
;
5410 /* Compute shader */
5411 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5412 return TGSI_SEMANTIC_THREAD_ID
;
5413 case SYSTEM_VALUE_WORK_GROUP_ID
:
5414 return TGSI_SEMANTIC_BLOCK_ID
;
5415 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5416 return TGSI_SEMANTIC_GRID_SIZE
;
5417 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5418 return TGSI_SEMANTIC_BLOCK_SIZE
;
5421 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5422 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5423 case SYSTEM_VALUE_VERTEX_CNT
:
5425 assert(!"Unexpected SYSTEM_VALUE_ enum");
5426 return TGSI_SEMANTIC_COUNT
;
5432 * Make note of a branch to a label in the TGSI code.
5433 * After we've emitted all instructions, we'll go over the list
5434 * of labels built here and patch the TGSI code with the actual
5435 * location of each label.
5437 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
5441 if (t
->labels_count
+ 1 >= t
->labels_size
) {
5442 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
5443 t
->labels
= (struct label
*)realloc(t
->labels
,
5444 t
->labels_size
* sizeof(struct label
));
5445 if (t
->labels
== NULL
) {
5446 static unsigned dummy
;
5452 i
= t
->labels_count
++;
5453 t
->labels
[i
].branch_target
= branch_target
;
5454 return &t
->labels
[i
].token
;
5458 * Called prior to emitting the TGSI code for each instruction.
5459 * Allocate additional space for instructions if needed.
5460 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
5461 * the next TGSI instruction.
5463 static void set_insn_start(struct st_translate
*t
, unsigned start
)
5465 if (t
->insn_count
+ 1 >= t
->insn_size
) {
5466 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
5467 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
5468 if (t
->insn
== NULL
) {
5474 t
->insn
[t
->insn_count
++] = start
;
5478 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5480 static struct ureg_src
5481 emit_immediate(struct st_translate
*t
,
5482 gl_constant_value values
[4],
5485 struct ureg_program
*ureg
= t
->ureg
;
5490 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5492 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5494 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5495 case GL_UNSIGNED_INT
:
5497 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5499 assert(!"should not get here - type must be float, int, uint, or bool");
5500 return ureg_src_undef();
5505 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5507 static struct ureg_dst
5508 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5514 case PROGRAM_UNDEFINED
:
5515 return ureg_dst_undef();
5517 case PROGRAM_TEMPORARY
:
5518 /* Allocate space for temporaries on demand. */
5519 if (index
>= t
->temps_size
) {
5520 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5522 t
->temps
= (struct ureg_dst
*)
5524 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5526 return ureg_dst_undef();
5528 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5529 t
->temps_size
+= inc
;
5532 if (ureg_dst_is_undef(t
->temps
[index
]))
5533 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5535 return t
->temps
[index
];
5538 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5539 array
= array_id
- 1;
5541 if (ureg_dst_is_undef(t
->arrays
[array
]))
5542 t
->arrays
[array
] = ureg_DECL_array_temporary(
5543 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5545 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5547 case PROGRAM_OUTPUT
:
5549 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5550 assert(index
< 2 * FRAG_RESULT_MAX
);
5551 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5552 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5553 assert(index
< VARYING_SLOT_TESS_MAX
);
5555 assert(index
< VARYING_SLOT_MAX
);
5557 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5558 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5559 return t
->outputs
[t
->outputMapping
[index
]];
5562 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5563 unsigned mesa_index
= decl
->mesa_index
;
5564 int slot
= t
->outputMapping
[mesa_index
];
5566 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5568 struct ureg_dst dst
= t
->outputs
[slot
];
5569 dst
.ArrayID
= array_id
;
5570 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5573 case PROGRAM_ADDRESS
:
5574 return t
->address
[index
];
5577 assert(!"unknown dst register file");
5578 return ureg_dst_undef();
5583 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5585 static struct ureg_src
5586 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5588 int index
= reg
->index
;
5589 int double_reg2
= reg
->double_reg2
? 1 : 0;
5592 case PROGRAM_UNDEFINED
:
5593 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5595 case PROGRAM_TEMPORARY
:
5597 case PROGRAM_OUTPUT
:
5598 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5600 case PROGRAM_UNIFORM
:
5601 assert(reg
->index
>= 0);
5602 return reg
->index
< t
->num_constants
?
5603 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5604 case PROGRAM_STATE_VAR
:
5605 case PROGRAM_CONSTANT
: /* ie, immediate */
5606 if (reg
->has_index2
)
5607 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5609 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5610 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5612 case PROGRAM_IMMEDIATE
:
5613 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5614 return t
->immediates
[reg
->index
];
5617 /* GLSL inputs are 64-bit containers, so we have to
5618 * map back to the original index and add the offset after
5620 index
-= double_reg2
;
5621 if (!reg
->array_id
) {
5622 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5623 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5624 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5627 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5628 unsigned mesa_index
= decl
->mesa_index
;
5629 int slot
= t
->inputMapping
[mesa_index
];
5631 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5633 struct ureg_src src
= t
->inputs
[slot
];
5634 src
.ArrayID
= reg
->array_id
;
5635 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5638 case PROGRAM_ADDRESS
:
5639 return ureg_src(t
->address
[reg
->index
]);
5641 case PROGRAM_SYSTEM_VALUE
:
5642 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5643 return t
->systemValues
[reg
->index
];
5646 assert(!"unknown src register file");
5647 return ureg_src_undef();
5652 * Create a TGSI ureg_dst register from an st_dst_reg.
5654 static struct ureg_dst
5655 translate_dst(struct st_translate
*t
,
5656 const st_dst_reg
*dst_reg
,
5659 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5662 if (dst
.File
== TGSI_FILE_NULL
)
5665 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5668 dst
= ureg_saturate(dst
);
5670 if (dst_reg
->reladdr
!= NULL
) {
5671 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5672 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5675 if (dst_reg
->has_index2
) {
5676 if (dst_reg
->reladdr2
)
5677 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5680 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5687 * Create a TGSI ureg_src register from an st_src_reg.
5689 static struct ureg_src
5690 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5692 struct ureg_src src
= src_register(t
, src_reg
);
5694 if (src_reg
->has_index2
) {
5695 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5696 * and UBO constant buffers (buffer, position).
5698 if (src_reg
->reladdr2
)
5699 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5702 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5705 src
= ureg_swizzle(src
,
5706 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5707 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5708 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5709 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5711 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5712 src
= ureg_negate(src
);
5714 if (src_reg
->reladdr
!= NULL
) {
5715 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5716 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5722 static struct tgsi_texture_offset
5723 translate_tex_offset(struct st_translate
*t
,
5724 const st_src_reg
*in_offset
)
5726 struct tgsi_texture_offset offset
;
5727 struct ureg_src src
= translate_src(t
, in_offset
);
5729 offset
.File
= src
.File
;
5730 offset
.Index
= src
.Index
;
5731 offset
.SwizzleX
= src
.SwizzleX
;
5732 offset
.SwizzleY
= src
.SwizzleY
;
5733 offset
.SwizzleZ
= src
.SwizzleZ
;
5736 assert(!src
.Indirect
);
5737 assert(!src
.DimIndirect
);
5738 assert(!src
.Dimension
);
5739 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5740 assert(!src
.Negate
);
5746 compile_tgsi_instruction(struct st_translate
*t
,
5747 const glsl_to_tgsi_instruction
*inst
)
5749 struct ureg_program
*ureg
= t
->ureg
;
5751 struct ureg_dst dst
[2];
5752 struct ureg_src src
[4];
5753 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5757 unsigned tex_target
= 0;
5759 num_dst
= num_inst_dst_regs(inst
);
5760 num_src
= num_inst_src_regs(inst
);
5762 for (i
= 0; i
< num_dst
; i
++)
5763 dst
[i
] = translate_dst(t
,
5767 for (i
= 0; i
< num_src
; i
++)
5768 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5771 case TGSI_OPCODE_BGNLOOP
:
5772 case TGSI_OPCODE_CAL
:
5773 case TGSI_OPCODE_ELSE
:
5774 case TGSI_OPCODE_ENDLOOP
:
5775 case TGSI_OPCODE_IF
:
5776 case TGSI_OPCODE_UIF
:
5777 assert(num_dst
== 0);
5778 ureg_label_insn(ureg
,
5782 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
5785 case TGSI_OPCODE_TEX
:
5786 case TGSI_OPCODE_TXB
:
5787 case TGSI_OPCODE_TXD
:
5788 case TGSI_OPCODE_TXL
:
5789 case TGSI_OPCODE_TXP
:
5790 case TGSI_OPCODE_TXQ
:
5791 case TGSI_OPCODE_TXQS
:
5792 case TGSI_OPCODE_TXF
:
5793 case TGSI_OPCODE_TEX2
:
5794 case TGSI_OPCODE_TXB2
:
5795 case TGSI_OPCODE_TXL2
:
5796 case TGSI_OPCODE_TG4
:
5797 case TGSI_OPCODE_LODQ
:
5798 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
5799 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5800 if (inst
->sampler
.reladdr
)
5802 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5804 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5805 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5807 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5813 texoffsets
, inst
->tex_offset_num_offset
,
5817 case TGSI_OPCODE_RESQ
:
5818 case TGSI_OPCODE_LOAD
:
5819 case TGSI_OPCODE_ATOMUADD
:
5820 case TGSI_OPCODE_ATOMXCHG
:
5821 case TGSI_OPCODE_ATOMCAS
:
5822 case TGSI_OPCODE_ATOMAND
:
5823 case TGSI_OPCODE_ATOMOR
:
5824 case TGSI_OPCODE_ATOMXOR
:
5825 case TGSI_OPCODE_ATOMUMIN
:
5826 case TGSI_OPCODE_ATOMUMAX
:
5827 case TGSI_OPCODE_ATOMIMIN
:
5828 case TGSI_OPCODE_ATOMIMAX
:
5829 for (i
= num_src
- 1; i
>= 0; i
--)
5830 src
[i
+ 1] = src
[i
];
5832 if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
5833 src
[0] = t
->shared_memory
;
5834 } else if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
5835 src
[0] = t
->buffers
[inst
->buffer
.index
];
5837 src
[0] = t
->images
[inst
->buffer
.index
];
5838 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5840 if (inst
->buffer
.reladdr
)
5841 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5842 assert(src
[0].File
!= TGSI_FILE_NULL
);
5843 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5844 inst
->buffer_access
,
5845 tex_target
, inst
->image_format
);
5848 case TGSI_OPCODE_STORE
:
5849 if (inst
->buffer
.file
== PROGRAM_MEMORY
) {
5850 dst
[0] = ureg_dst(t
->shared_memory
);
5851 } else if (inst
->buffer
.file
== PROGRAM_BUFFER
) {
5852 dst
[0] = ureg_dst(t
->buffers
[inst
->buffer
.index
]);
5854 dst
[0] = ureg_dst(t
->images
[inst
->buffer
.index
]);
5855 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5857 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5858 if (inst
->buffer
.reladdr
)
5859 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5860 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5861 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5862 inst
->buffer_access
,
5863 tex_target
, inst
->image_format
);
5866 case TGSI_OPCODE_SCS
:
5867 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5868 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5881 * Emit the TGSI instructions for inverting and adjusting WPOS.
5882 * This code is unavoidable because it also depends on whether
5883 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5886 emit_wpos_adjustment(struct gl_context
*ctx
,
5887 struct st_translate
*t
,
5888 int wpos_transform_const
,
5890 GLfloat adjX
, GLfloat adjY
[2])
5892 struct ureg_program
*ureg
= t
->ureg
;
5894 assert(wpos_transform_const
>= 0);
5896 /* Fragment program uses fragment position input.
5897 * Need to replace instances of INPUT[WPOS] with temp T
5898 * where T = INPUT[WPOS] is inverted by Y.
5900 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5901 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5902 struct ureg_src
*wpos
=
5903 ctx
->Const
.GLSLFragCoordIsSysVal
?
5904 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5905 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5906 struct ureg_src wpos_input
= *wpos
;
5908 /* First, apply the coordinate shift: */
5909 if (adjX
|| adjY
[0] || adjY
[1]) {
5910 if (adjY
[0] != adjY
[1]) {
5911 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5912 * depending on whether inversion is actually going to be applied
5913 * or not, which is determined by testing against the inversion
5914 * state variable used below, which will be either +1 or -1.
5916 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5918 ureg_CMP(ureg
, adj_temp
,
5919 ureg_scalar(wpostrans
, invert
? 2 : 0),
5920 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5921 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5922 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5924 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5925 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5927 wpos_input
= ureg_src(wpos_temp
);
5929 /* MOV wpos_temp, input[wpos]
5931 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5934 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5935 * inversion/identity, or the other way around if we're drawing to an FBO.
5938 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5941 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5943 ureg_scalar(wpostrans
, 0),
5944 ureg_scalar(wpostrans
, 1));
5946 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5949 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5951 ureg_scalar(wpostrans
, 2),
5952 ureg_scalar(wpostrans
, 3));
5955 /* Use wpos_temp as position input from here on:
5957 *wpos
= ureg_src(wpos_temp
);
5962 * Emit fragment position/ooordinate code.
5965 emit_wpos(struct st_context
*st
,
5966 struct st_translate
*t
,
5967 const struct gl_program
*program
,
5968 struct ureg_program
*ureg
,
5969 int wpos_transform_const
)
5971 const struct gl_fragment_program
*fp
=
5972 (const struct gl_fragment_program
*) program
;
5973 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5974 GLfloat adjX
= 0.0f
;
5975 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5976 boolean invert
= FALSE
;
5978 /* Query the pixel center conventions supported by the pipe driver and set
5979 * adjX, adjY to help out if it cannot handle the requested one internally.
5981 * The bias of the y-coordinate depends on whether y-inversion takes place
5982 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5983 * drawing to an FBO (causes additional inversion), and whether the pipe
5984 * driver origin and the requested origin differ (the latter condition is
5985 * stored in the 'invert' variable).
5987 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5989 * center shift only:
5994 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5995 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5996 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5997 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5999 * inversion and center shift:
6000 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6001 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6002 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6003 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6005 if (fp
->OriginUpperLeft
) {
6006 /* Fragment shader wants origin in upper-left */
6007 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6008 /* the driver supports upper-left origin */
6010 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6011 /* the driver supports lower-left origin, need to invert Y */
6012 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6013 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6020 /* Fragment shader wants origin in lower-left */
6021 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6022 /* the driver supports lower-left origin */
6023 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6024 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6025 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6026 /* the driver supports upper-left origin, need to invert Y */
6032 if (fp
->PixelCenterInteger
) {
6033 /* Fragment shader wants pixel center integer */
6034 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6035 /* the driver supports pixel center integer */
6037 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6038 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6040 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6041 /* the driver supports pixel center half integer, need to bias X,Y */
6050 /* Fragment shader wants pixel center half integer */
6051 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6052 /* the driver supports pixel center half integer */
6054 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6055 /* the driver supports pixel center integer, need to bias X,Y */
6056 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6057 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6058 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6064 /* we invert after adjustment so that we avoid the MOV to temporary,
6065 * and reuse the adjustment ADD instead */
6066 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6070 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6071 * TGSI uses +1 for front, -1 for back.
6072 * This function converts the TGSI value to the GL value. Simply clamping/
6073 * saturating the value to [0,1] does the job.
6076 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6078 struct ureg_program
*ureg
= t
->ureg
;
6079 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6080 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6082 if (ctx
->Const
.NativeIntegers
) {
6083 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6086 /* MOV_SAT face_temp, input[face] */
6087 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6090 /* Use face_temp as face input from here on: */
6091 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6095 emit_compute_block_size(const struct gl_program
*program
,
6096 struct ureg_program
*ureg
) {
6097 const struct gl_compute_program
*cp
=
6098 (const struct gl_compute_program
*)program
;
6100 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6102 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6104 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6109 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6110 * \param program the program to translate
6111 * \param numInputs number of input registers used
6112 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6114 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6115 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6117 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6118 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
6119 * \param numOutputs number of output registers used
6120 * \param outputMapping maps Mesa fragment program outputs to TGSI
6122 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6123 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6126 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6128 extern "C" enum pipe_error
6129 st_translate_program(
6130 struct gl_context
*ctx
,
6132 struct ureg_program
*ureg
,
6133 glsl_to_tgsi_visitor
*program
,
6134 const struct gl_program
*proginfo
,
6136 const GLuint inputMapping
[],
6137 const GLuint inputSlotToAttr
[],
6138 const ubyte inputSemanticName
[],
6139 const ubyte inputSemanticIndex
[],
6140 const GLuint interpMode
[],
6141 const GLuint interpLocation
[],
6143 const GLuint outputMapping
[],
6144 const GLuint outputSlotToAttr
[],
6145 const ubyte outputSemanticName
[],
6146 const ubyte outputSemanticIndex
[])
6148 struct st_translate
*t
;
6150 struct gl_program_constants
*frag_const
=
6151 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6152 enum pipe_error ret
= PIPE_OK
;
6154 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6155 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6157 t
= CALLOC_STRUCT(st_translate
);
6159 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6163 t
->procType
= procType
;
6164 t
->inputMapping
= inputMapping
;
6165 t
->outputMapping
= outputMapping
;
6167 t
->num_temp_arrays
= program
->next_array
;
6168 if (t
->num_temp_arrays
)
6169 t
->arrays
= (struct ureg_dst
*)
6170 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6173 * Declare input attributes.
6176 case PIPE_SHADER_FRAGMENT
:
6177 case PIPE_SHADER_GEOMETRY
:
6178 case PIPE_SHADER_TESS_EVAL
:
6179 case PIPE_SHADER_TESS_CTRL
:
6180 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6181 struct inout_decl
*decl
= &program
->inputs
[i
];
6182 unsigned slot
= inputMapping
[decl
->mesa_index
];
6183 struct ureg_src src
;
6184 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6186 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6187 if (tgsi_usage_mask
== 1)
6188 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6189 else if (tgsi_usage_mask
== 2)
6190 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6192 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6195 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6196 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6197 interpMode
? interpMode
[slot
] : 0, 0, interpLocation
? interpLocation
[slot
] : 0,
6198 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6200 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6201 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6202 /* The ArrayID is set up in dst_register */
6203 t
->inputs
[slot
+ j
] = src
;
6204 t
->inputs
[slot
+ j
].ArrayID
= 0;
6205 t
->inputs
[slot
+ j
].Index
+= j
;
6210 case PIPE_SHADER_VERTEX
:
6211 for (i
= 0; i
< numInputs
; i
++) {
6212 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6215 case PIPE_SHADER_COMPUTE
:
6222 * Declare output attributes.
6225 case PIPE_SHADER_FRAGMENT
:
6226 case PIPE_SHADER_COMPUTE
:
6228 case PIPE_SHADER_GEOMETRY
:
6229 case PIPE_SHADER_TESS_EVAL
:
6230 case PIPE_SHADER_TESS_CTRL
:
6231 case PIPE_SHADER_VERTEX
:
6232 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6233 struct inout_decl
*decl
= &program
->outputs
[i
];
6234 unsigned slot
= outputMapping
[decl
->mesa_index
];
6235 struct ureg_dst dst
;
6236 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6238 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6239 if (tgsi_usage_mask
== 1)
6240 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6241 else if (tgsi_usage_mask
== 2)
6242 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6244 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6247 dst
= ureg_DECL_output_layout(ureg
,
6248 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6249 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6251 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6252 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6253 /* The ArrayID is set up in dst_register */
6254 t
->outputs
[slot
+ j
] = dst
;
6255 t
->outputs
[slot
+ j
].ArrayID
= 0;
6256 t
->outputs
[slot
+ j
].Index
+= j
;
6265 if (procType
== PIPE_SHADER_FRAGMENT
) {
6266 if (program
->shader
->info
.EarlyFragmentTests
)
6267 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6269 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
6270 /* Must do this after setting up t->inputs. */
6271 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6272 program
->wpos_transform_const
);
6275 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
6276 emit_face_var(ctx
, t
);
6278 for (i
= 0; i
< numOutputs
; i
++) {
6279 switch (outputSemanticName
[i
]) {
6280 case TGSI_SEMANTIC_POSITION
:
6281 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6282 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6283 outputSemanticIndex
[i
]);
6284 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6286 case TGSI_SEMANTIC_STENCIL
:
6287 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6288 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6289 outputSemanticIndex
[i
]);
6290 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6292 case TGSI_SEMANTIC_COLOR
:
6293 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6294 TGSI_SEMANTIC_COLOR
,
6295 outputSemanticIndex
[i
]);
6297 case TGSI_SEMANTIC_SAMPLEMASK
:
6298 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6299 TGSI_SEMANTIC_SAMPLEMASK
,
6300 outputSemanticIndex
[i
]);
6301 /* TODO: If we ever support more than 32 samples, this will have
6302 * to become an array.
6304 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6307 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6308 ret
= PIPE_ERROR_BAD_INPUT
;
6313 else if (procType
== PIPE_SHADER_VERTEX
) {
6314 for (i
= 0; i
< numOutputs
; i
++) {
6315 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6316 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6318 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6319 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6320 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6325 if (procType
== PIPE_SHADER_COMPUTE
) {
6326 emit_compute_block_size(proginfo
, ureg
);
6329 /* Declare address register.
6331 if (program
->num_address_regs
> 0) {
6332 assert(program
->num_address_regs
<= 3);
6333 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6334 t
->address
[i
] = ureg_DECL_address(ureg
);
6337 /* Declare misc input registers
6340 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
6342 for (i
= 0; sysInputs
; i
++) {
6343 if (sysInputs
& (1 << i
)) {
6344 unsigned semName
= _mesa_sysval_to_semantic(i
);
6346 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6348 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6349 semName
== TGSI_SEMANTIC_VERTEXID
) {
6350 /* From Gallium perspective, these system values are always
6351 * integer, and require native integer support. However, if
6352 * native integer is supported on the vertex stage but not the
6353 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6354 * assumes these system values are floats. To resolve the
6355 * inconsistency, we insert a U2F.
6357 struct st_context
*st
= st_context(ctx
);
6358 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6359 assert(procType
== PIPE_SHADER_VERTEX
);
6360 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6362 if (!ctx
->Const
.NativeIntegers
) {
6363 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6364 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6365 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6369 if (procType
== PIPE_SHADER_FRAGMENT
&&
6370 semName
== TGSI_SEMANTIC_POSITION
)
6371 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6372 program
->wpos_transform_const
);
6374 sysInputs
&= ~(1 << i
);
6379 t
->array_sizes
= program
->array_sizes
;
6380 t
->input_decls
= program
->inputs
;
6381 t
->num_input_decls
= program
->num_inputs
;
6382 t
->output_decls
= program
->outputs
;
6383 t
->num_output_decls
= program
->num_outputs
;
6385 /* Emit constants and uniforms. TGSI uses a single index space for these,
6386 * so we put all the translated regs in t->constants.
6388 if (proginfo
->Parameters
) {
6389 t
->constants
= (struct ureg_src
*)
6390 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6391 if (t
->constants
== NULL
) {
6392 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6395 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6397 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6398 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6399 case PROGRAM_STATE_VAR
:
6400 case PROGRAM_UNIFORM
:
6401 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6404 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6405 * addressing of the const buffer.
6406 * FIXME: Be smarter and recognize param arrays:
6407 * indirect addressing is only valid within the referenced
6410 case PROGRAM_CONSTANT
:
6411 if (program
->indirect_addr_consts
)
6412 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6414 t
->constants
[i
] = emit_immediate(t
,
6415 proginfo
->Parameters
->ParameterValues
[i
],
6416 proginfo
->Parameters
->Parameters
[i
].DataType
,
6425 if (program
->shader
) {
6426 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
6428 for (i
= 0; i
< num_ubos
; i
++) {
6429 unsigned size
= program
->shader
->UniformBlocks
[i
]->UniformBufferSize
;
6430 unsigned num_const_vecs
= (size
+ 15) / 16;
6431 unsigned first
, last
;
6432 assert(num_const_vecs
> 0);
6434 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6435 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6439 /* Emit immediate values.
6441 t
->immediates
= (struct ureg_src
*)
6442 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6443 if (t
->immediates
== NULL
) {
6444 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6447 t
->num_immediates
= program
->num_immediates
;
6450 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6451 assert(i
< program
->num_immediates
);
6452 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6454 assert(i
== program
->num_immediates
);
6456 /* texture samplers */
6457 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6458 if (program
->samplers_used
& (1u << i
)) {
6461 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6463 switch (program
->sampler_types
[i
]) {
6465 type
= TGSI_RETURN_TYPE_SINT
;
6467 case GLSL_TYPE_UINT
:
6468 type
= TGSI_RETURN_TYPE_UINT
;
6470 case GLSL_TYPE_FLOAT
:
6471 type
= TGSI_RETURN_TYPE_FLOAT
;
6474 unreachable("not reached");
6477 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6478 type
, type
, type
, type
);
6482 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6483 if (program
->buffers_used
& (1 << i
)) {
6484 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6488 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6490 if (program
->buffers_used
& (1 << i
)) {
6491 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6495 if (program
->use_shared_memory
)
6496 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6498 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6499 if (program
->images_used
& (1 << i
)) {
6500 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6501 program
->image_targets
[i
],
6502 program
->image_formats
[i
],
6507 /* Emit each instruction in turn:
6509 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
6510 set_insn_start(t
, ureg_get_instruction_number(ureg
));
6511 compile_tgsi_instruction(t
, inst
);
6514 /* Fix up all emitted labels:
6516 for (i
= 0; i
< t
->labels_count
; i
++) {
6517 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
6518 t
->insn
[t
->labels
[i
].branch_target
]);
6521 /* Set the next shader stage hint for VS and TES. */
6523 case PIPE_SHADER_VERTEX
:
6524 case PIPE_SHADER_TESS_EVAL
:
6525 if (program
->shader_program
->SeparateShader
)
6528 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6529 if (program
->shader_program
->_LinkedShaders
[i
]) {
6533 case MESA_SHADER_TESS_CTRL
:
6534 next
= PIPE_SHADER_TESS_CTRL
;
6536 case MESA_SHADER_TESS_EVAL
:
6537 next
= PIPE_SHADER_TESS_EVAL
;
6539 case MESA_SHADER_GEOMETRY
:
6540 next
= PIPE_SHADER_GEOMETRY
;
6542 case MESA_SHADER_FRAGMENT
:
6543 next
= PIPE_SHADER_FRAGMENT
;
6550 ureg_set_next_shader_processor(ureg
, next
);
6564 t
->num_constants
= 0;
6565 free(t
->immediates
);
6566 t
->num_immediates
= 0;
6569 debug_printf("%s: translate error flag set\n", __func__
);
6577 /* ----------------------------- End TGSI code ------------------------------ */
6581 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6582 * generating Mesa IR.
6584 static struct gl_program
*
6585 get_mesa_program_tgsi(struct gl_context
*ctx
,
6586 struct gl_shader_program
*shader_program
,
6587 struct gl_linked_shader
*shader
)
6589 glsl_to_tgsi_visitor
* v
;
6590 struct gl_program
*prog
;
6591 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
6593 struct gl_shader_compiler_options
*options
=
6594 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6595 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6596 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6598 validate_ir_tree(shader
->ir
);
6600 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
6603 prog
->Parameters
= _mesa_new_parameter_list();
6604 v
= new glsl_to_tgsi_visitor();
6607 v
->shader_program
= shader_program
;
6609 v
->options
= options
;
6610 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6611 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6613 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6614 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6615 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6616 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6618 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
6619 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6622 /* Remove reads from output registers. */
6623 lower_output_reads(shader
->Stage
, shader
->ir
);
6625 /* Emit intermediate IR for main(). */
6626 visit_exec_list(shader
->ir
, v
);
6628 /* Now emit bodies for any functions that were used. */
6630 progress
= GL_FALSE
;
6632 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
6633 if (!entry
->bgn_inst
) {
6634 v
->current_function
= entry
;
6636 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
6637 entry
->bgn_inst
->function
= entry
;
6639 visit_exec_list(&entry
->sig
->body
, v
);
6641 glsl_to_tgsi_instruction
*last
;
6642 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
6643 if (last
->op
!= TGSI_OPCODE_RET
)
6644 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
6646 glsl_to_tgsi_instruction
*end
;
6647 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
6648 end
->function
= entry
;
6656 /* Print out some information (for debugging purposes) used by the
6657 * optimization passes. */
6660 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6661 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6662 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6663 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6665 for (i
= 0; i
< v
->next_temp
; i
++) {
6666 first_writes
[i
] = -1;
6667 first_reads
[i
] = -1;
6668 last_writes
[i
] = -1;
6671 v
->get_first_temp_read(first_reads
);
6672 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6673 v
->get_last_temp_write(last_writes
);
6674 for (i
= 0; i
< v
->next_temp
; i
++)
6675 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6679 ralloc_free(first_writes
);
6680 ralloc_free(first_reads
);
6681 ralloc_free(last_writes
);
6682 ralloc_free(last_reads
);
6686 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6689 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6690 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6691 v
->copy_propagate();
6693 while (v
->eliminate_dead_code());
6695 v
->merge_two_dsts();
6696 v
->merge_registers();
6697 v
->renumber_registers();
6699 /* Write the END instruction. */
6700 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6702 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6704 _mesa_log("GLSL IR for linked %s program %d:\n",
6705 _mesa_shader_stage_to_string(shader
->Stage
),
6706 shader_program
->Name
);
6707 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6711 prog
->Instructions
= NULL
;
6712 prog
->NumInstructions
= 0;
6714 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6715 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6716 &prog
->InputsRead
, prog
->DoubleInputsRead
, &prog
->PatchInputsRead
);
6717 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6718 &prog
->OutputsWritten
, 0ULL, &prog
->PatchOutputsWritten
);
6719 count_resources(v
, prog
);
6721 /* The GLSL IR won't be needed anymore. */
6722 ralloc_free(shader
->ir
);
6725 /* This must be done before the uniform storage is associated. */
6726 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6727 (prog
->InputsRead
& VARYING_BIT_POS
||
6728 prog
->SystemValuesRead
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6729 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6730 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6733 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6734 wposTransformState
);
6737 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
6739 /* Avoid reallocation of the program parameter list, because the uniform
6740 * storage is only associated with the original parameter list.
6741 * This should be enough for Bitmap and DrawPixels constants.
6743 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6745 /* This has to be done last. Any operation the can cause
6746 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6747 * program constant) has to happen before creating this linkage.
6749 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6750 if (!shader_program
->LinkStatus
) {
6751 free_glsl_to_tgsi_visitor(v
);
6755 struct st_vertex_program
*stvp
;
6756 struct st_fragment_program
*stfp
;
6757 struct st_geometry_program
*stgp
;
6758 struct st_tessctrl_program
*sttcp
;
6759 struct st_tesseval_program
*sttep
;
6760 struct st_compute_program
*stcp
;
6762 switch (shader
->Stage
) {
6763 case MESA_SHADER_VERTEX
:
6764 stvp
= (struct st_vertex_program
*)prog
;
6765 stvp
->glsl_to_tgsi
= v
;
6767 case MESA_SHADER_FRAGMENT
:
6768 stfp
= (struct st_fragment_program
*)prog
;
6769 stfp
->glsl_to_tgsi
= v
;
6771 case MESA_SHADER_GEOMETRY
:
6772 stgp
= (struct st_geometry_program
*)prog
;
6773 stgp
->glsl_to_tgsi
= v
;
6775 case MESA_SHADER_TESS_CTRL
:
6776 sttcp
= (struct st_tessctrl_program
*)prog
;
6777 sttcp
->glsl_to_tgsi
= v
;
6779 case MESA_SHADER_TESS_EVAL
:
6780 sttep
= (struct st_tesseval_program
*)prog
;
6781 sttep
->glsl_to_tgsi
= v
;
6783 case MESA_SHADER_COMPUTE
:
6784 stcp
= (struct st_compute_program
*)prog
;
6785 stcp
->glsl_to_tgsi
= v
;
6788 assert(!"should not be reached");
6796 set_affected_state_flags(uint64_t *states
,
6797 struct gl_program
*prog
,
6798 struct gl_linked_shader
*shader
,
6799 uint64_t new_constants
,
6800 uint64_t new_sampler_views
,
6801 uint64_t new_samplers
,
6802 uint64_t new_images
,
6805 uint64_t new_atomics
)
6807 if (prog
->Parameters
->NumParameters
)
6808 *states
|= new_constants
;
6810 if (shader
->num_samplers
)
6811 *states
|= new_sampler_views
| new_samplers
;
6813 if (shader
->NumImages
)
6814 *states
|= new_images
;
6816 if (shader
->NumUniformBlocks
)
6817 *states
|= new_ubos
;
6819 if (shader
->NumShaderStorageBlocks
)
6820 *states
|= new_ssbos
;
6822 if (shader
->NumAtomicBuffers
)
6823 *states
|= new_atomics
;
6826 static struct gl_program
*
6827 get_mesa_program(struct gl_context
*ctx
,
6828 struct gl_shader_program
*shader_program
,
6829 struct gl_linked_shader
*shader
)
6831 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6832 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6833 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6834 pscreen
->get_shader_param(pscreen
, ptarget
, PIPE_SHADER_CAP_PREFERRED_IR
);
6835 struct gl_program
*prog
= NULL
;
6837 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6838 /* TODO only for GLSL VS/FS for now: */
6839 switch (shader
->Stage
) {
6840 case MESA_SHADER_VERTEX
:
6841 case MESA_SHADER_FRAGMENT
:
6842 prog
= st_nir_get_mesa_program(ctx
, shader_program
, shader
);
6847 prog
= get_mesa_program_tgsi(ctx
, shader_program
, shader
);
6853 /* This determines which states will be updated when the shader is
6856 switch (shader
->Stage
) {
6857 case MESA_SHADER_VERTEX
:
6858 states
= &((struct st_vertex_program
*)prog
)->affected_states
;
6860 *states
= ST_NEW_VS_STATE
|
6862 ST_NEW_VERTEX_ARRAYS
;
6864 set_affected_state_flags(states
, prog
, shader
,
6865 ST_NEW_VS_CONSTANTS
,
6866 ST_NEW_VS_SAMPLER_VIEWS
,
6867 ST_NEW_RENDER_SAMPLERS
,
6874 case MESA_SHADER_TESS_CTRL
:
6875 states
= &((struct st_tessctrl_program
*)prog
)->affected_states
;
6877 *states
= ST_NEW_TCS_STATE
;
6879 set_affected_state_flags(states
, prog
, shader
,
6880 ST_NEW_TCS_CONSTANTS
,
6881 ST_NEW_TCS_SAMPLER_VIEWS
,
6882 ST_NEW_RENDER_SAMPLERS
,
6886 ST_NEW_TCS_ATOMICS
);
6889 case MESA_SHADER_TESS_EVAL
:
6890 states
= &((struct st_tesseval_program
*)prog
)->affected_states
;
6892 *states
= ST_NEW_TES_STATE
|
6895 set_affected_state_flags(states
, prog
, shader
,
6896 ST_NEW_TES_CONSTANTS
,
6897 ST_NEW_TES_SAMPLER_VIEWS
,
6898 ST_NEW_RENDER_SAMPLERS
,
6902 ST_NEW_TES_ATOMICS
);
6905 case MESA_SHADER_GEOMETRY
:
6906 states
= &((struct st_geometry_program
*)prog
)->affected_states
;
6908 *states
= ST_NEW_GS_STATE
|
6911 set_affected_state_flags(states
, prog
, shader
,
6912 ST_NEW_GS_CONSTANTS
,
6913 ST_NEW_GS_SAMPLER_VIEWS
,
6914 ST_NEW_RENDER_SAMPLERS
,
6921 case MESA_SHADER_FRAGMENT
:
6922 states
= &((struct st_fragment_program
*)prog
)->affected_states
;
6924 /* gl_FragCoord and glDrawPixels always use constants. */
6925 *states
= ST_NEW_FS_STATE
|
6926 ST_NEW_SAMPLE_SHADING
|
6927 ST_NEW_FS_CONSTANTS
;
6929 set_affected_state_flags(states
, prog
, shader
,
6930 ST_NEW_FS_CONSTANTS
,
6931 ST_NEW_FS_SAMPLER_VIEWS
,
6932 ST_NEW_RENDER_SAMPLERS
,
6939 case MESA_SHADER_COMPUTE
:
6940 states
= &((struct st_compute_program
*)prog
)->affected_states
;
6942 *states
= ST_NEW_CS_STATE
;
6944 set_affected_state_flags(states
, prog
, shader
,
6945 ST_NEW_CS_CONSTANTS
,
6946 ST_NEW_CS_SAMPLER_VIEWS
,
6955 unreachable("unhandled shader stage");
6967 * Called via ctx->Driver.LinkShader()
6968 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6969 * with code lowering and other optimizations.
6972 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6974 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6975 assert(prog
->LinkStatus
);
6977 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6978 if (prog
->_LinkedShaders
[i
] == NULL
)
6982 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6983 gl_shader_stage stage
= prog
->_LinkedShaders
[i
]->Stage
;
6984 const struct gl_shader_compiler_options
*options
=
6985 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6986 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
6987 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6988 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6989 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6990 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6992 /* If there are forms of indirect addressing that the driver
6993 * cannot handle, perform the lowering pass.
6995 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6996 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6997 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6998 options
->EmitNoIndirectInput
,
6999 options
->EmitNoIndirectOutput
,
7000 options
->EmitNoIndirectTemp
,
7001 options
->EmitNoIndirectUniform
);
7004 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7005 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7006 LOWER_UNPACK_SNORM_2x16
|
7007 LOWER_PACK_UNORM_2x16
|
7008 LOWER_UNPACK_UNORM_2x16
|
7009 LOWER_PACK_SNORM_4x8
|
7010 LOWER_UNPACK_SNORM_4x8
|
7011 LOWER_UNPACK_UNORM_4x8
|
7012 LOWER_PACK_UNORM_4x8
;
7014 if (ctx
->Extensions
.ARB_gpu_shader5
)
7015 lower_inst
|= LOWER_PACK_USE_BFI
|
7017 if (!ctx
->st
->has_half_float_packing
)
7018 lower_inst
|= LOWER_PACK_HALF_2x16
|
7019 LOWER_UNPACK_HALF_2x16
;
7021 lower_packing_builtins(ir
, lower_inst
);
7024 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7025 lower_offset_arrays(ir
);
7026 do_mat_op_to_vec(ir
);
7027 lower_instructions(ir
,
7033 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7036 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7037 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7038 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7039 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7040 /* Assume that if ARB_gpu_shader5 is not supported
7041 * then all of the extended integer functions need
7042 * lowering. It may be necessary to add some caps
7043 * for individual instructions.
7045 (!ctx
->Extensions
.ARB_gpu_shader5
7046 ? BIT_COUNT_TO_MATH
|
7050 FIND_LSB_TO_FLOAT_CAST
|
7051 FIND_MSB_TO_FLOAT_CAST
|
7055 do_vec_index_to_cond_assign(ir
);
7056 lower_vector_insert(ir
, true);
7057 lower_quadop_vector(ir
, false);
7059 if (options
->MaxIfDepth
== 0) {
7066 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
7068 progress
= do_common_optimization(ir
, true, true, options
,
7069 ctx
->Const
.NativeIntegers
)
7072 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
7076 validate_ir_tree(ir
);
7079 build_program_resource_list(ctx
, prog
);
7081 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7082 struct gl_program
*linked_prog
;
7084 if (prog
->_LinkedShaders
[i
] == NULL
)
7087 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
7090 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
7092 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7093 _mesa_shader_stage_to_program(i
),
7095 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
7097 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
7102 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
7109 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7110 const GLuint outputMapping
[],
7111 struct pipe_stream_output_info
*so
)
7113 struct gl_transform_feedback_info
*info
=
7114 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
7115 st_translate_stream_output_info2(info
, outputMapping
, so
);
7119 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7120 const GLuint outputMapping
[],
7121 struct pipe_stream_output_info
*so
)
7125 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7126 so
->output
[i
].register_index
=
7127 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7128 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7129 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7130 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7131 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7132 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7135 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7136 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7138 so
->num_outputs
= info
->NumOutputs
;