2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
60 #include "util/hash_table.h"
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
67 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static unsigned is_precise(const ir_variable
*ir
)
73 return ir
->data
.precise
|| ir
->data
.invariant
;
76 class variable_storage
{
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
80 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
81 unsigned array_id
= 0)
82 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
84 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
87 gl_register_file file
;
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
95 ir_variable
*var
; /* variable that maps to this, if any */
99 class immediate_storage
: public exec_node
{
101 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
103 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
104 this->size32
= size32
;
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values
[4];
110 int size32
; /**< Number of 32-bit components (1-4) */
111 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
114 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
115 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
119 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
122 unsigned gs_out_streams
;
123 enum glsl_interp_mode interp
;
124 enum glsl_base_type base_type
;
125 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
128 static struct inout_decl
*
129 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
131 assert(array_id
!= 0);
133 for (unsigned i
= 0; i
< count
; i
++) {
134 struct inout_decl
*decl
= &decls
[i
];
136 if (array_id
== decl
->array_id
) {
144 static enum glsl_base_type
145 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
148 return GLSL_TYPE_ERROR
;
149 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
151 return decl
->base_type
;
152 return GLSL_TYPE_ERROR
;
155 struct glsl_to_tgsi_visitor
: public ir_visitor
{
157 glsl_to_tgsi_visitor();
158 ~glsl_to_tgsi_visitor();
160 struct gl_context
*ctx
;
161 struct gl_program
*prog
;
162 struct gl_shader_program
*shader_program
;
163 struct gl_linked_shader
*shader
;
164 struct gl_shader_compiler_options
*options
;
168 unsigned *array_sizes
;
169 unsigned max_num_arrays
;
172 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
174 unsigned num_input_arrays
;
175 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
176 unsigned num_outputs
;
177 unsigned num_output_arrays
;
179 int num_address_regs
;
180 uint32_t samplers_used
;
181 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
182 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
184 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
185 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
186 bool indirect_addr_consts
;
187 int wpos_transform_const
;
189 bool native_integers
;
192 bool use_shared_memory
;
197 variable_storage
*find_variable_storage(ir_variable
*var
);
199 int add_constant(gl_register_file file
, gl_constant_value values
[8],
200 int size
, int datatype
, uint16_t *swizzle_out
);
202 st_src_reg
get_temp(const glsl_type
*type
);
203 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
205 st_src_reg
st_src_reg_for_double(double val
);
206 st_src_reg
st_src_reg_for_float(float val
);
207 st_src_reg
st_src_reg_for_int(int val
);
208 st_src_reg
st_src_reg_for_int64(int64_t val
);
209 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
212 * \name Visit methods
214 * As typical for the visitor pattern, there must be one \c visit method for
215 * each concrete subclass of \c ir_instruction. Virtual base classes within
216 * the hierarchy should not have \c visit methods.
219 virtual void visit(ir_variable
*);
220 virtual void visit(ir_loop
*);
221 virtual void visit(ir_loop_jump
*);
222 virtual void visit(ir_function_signature
*);
223 virtual void visit(ir_function
*);
224 virtual void visit(ir_expression
*);
225 virtual void visit(ir_swizzle
*);
226 virtual void visit(ir_dereference_variable
*);
227 virtual void visit(ir_dereference_array
*);
228 virtual void visit(ir_dereference_record
*);
229 virtual void visit(ir_assignment
*);
230 virtual void visit(ir_constant
*);
231 virtual void visit(ir_call
*);
232 virtual void visit(ir_return
*);
233 virtual void visit(ir_discard
*);
234 virtual void visit(ir_texture
*);
235 virtual void visit(ir_if
*);
236 virtual void visit(ir_emit_vertex
*);
237 virtual void visit(ir_end_primitive
*);
238 virtual void visit(ir_barrier
*);
241 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
243 void visit_atomic_counter_intrinsic(ir_call
*);
244 void visit_ssbo_intrinsic(ir_call
*);
245 void visit_membar_intrinsic(ir_call
*);
246 void visit_shared_intrinsic(ir_call
*);
247 void visit_image_intrinsic(ir_call
*);
248 void visit_generic_intrinsic(ir_call
*, unsigned op
);
252 /** List of variable_storage */
253 struct hash_table
*variables
;
255 /** List of immediate_storage */
256 exec_list immediates
;
257 unsigned num_immediates
;
259 /** List of glsl_to_tgsi_instruction */
260 exec_list instructions
;
262 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
263 st_dst_reg dst
= undef_dst
,
264 st_src_reg src0
= undef_src
,
265 st_src_reg src1
= undef_src
,
266 st_src_reg src2
= undef_src
,
267 st_src_reg src3
= undef_src
);
269 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
270 st_dst_reg dst
, st_dst_reg dst1
,
271 st_src_reg src0
= undef_src
,
272 st_src_reg src1
= undef_src
,
273 st_src_reg src2
= undef_src
,
274 st_src_reg src3
= undef_src
);
276 unsigned get_opcode(unsigned op
,
278 st_src_reg src0
, st_src_reg src1
);
281 * Emit the correct dot-product instruction for the type of arguments
283 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
289 void emit_scalar(ir_instruction
*ir
, unsigned op
,
290 st_dst_reg dst
, st_src_reg src0
);
292 void emit_scalar(ir_instruction
*ir
, unsigned op
,
293 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
295 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
297 void get_deref_offsets(ir_dereference
*ir
,
298 unsigned *array_size
,
303 void calc_deref_offsets(ir_dereference
*tail
,
304 unsigned *array_elements
,
306 st_src_reg
*indirect
,
308 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
310 bool try_emit_mad(ir_expression
*ir
,
312 bool try_emit_mad_for_and_not(ir_expression
*ir
,
315 void emit_swz(ir_expression
*ir
);
317 bool process_move_condition(ir_rvalue
*ir
);
319 void simplify_cmp(void);
321 void rename_temp_registers(struct rename_reg_pair
*renames
);
322 void get_first_temp_read(int *first_reads
);
323 void get_first_temp_write(int *first_writes
);
324 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
325 void get_last_temp_write(int *last_writes
);
327 void copy_propagate(void);
328 int eliminate_dead_code(void);
330 void merge_two_dsts(void);
331 void merge_registers(void);
332 void renumber_registers(void);
334 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
335 st_dst_reg
*l
, st_src_reg
*r
,
336 st_src_reg
*cond
, bool cond_swap
);
341 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
342 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
343 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
346 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
349 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
353 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
356 prog
->data
->LinkStatus
= linking_failure
;
360 swizzle_for_size(int size
)
362 static const int size_swizzles
[4] = {
363 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
364 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
365 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
366 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
369 assert((size
>= 1) && (size
<= 4));
370 return size_swizzles
[size
- 1];
374 glsl_to_tgsi_instruction
*
375 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
376 st_dst_reg dst
, st_dst_reg dst1
,
377 st_src_reg src0
, st_src_reg src1
,
378 st_src_reg src2
, st_src_reg src3
)
380 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
381 int num_reladdr
= 0, i
, j
;
382 bool dst_is_64bit
[2];
384 op
= get_opcode(op
, dst
, src0
, src1
);
386 /* If we have to do relative addressing, we want to load the ARL
387 * reg directly for one of the regs, and preload the other reladdr
388 * sources into temps.
390 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
391 assert(!dst1
.reladdr
); /* should be lowered in earlier passes */
392 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
393 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
394 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
395 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
397 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
398 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
399 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
400 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
402 if (dst
.reladdr
|| dst
.reladdr2
) {
404 emit_arl(ir
, address_reg
, *dst
.reladdr
);
406 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
410 assert(num_reladdr
== 0);
412 /* inst->op has only 8 bits. */
413 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
416 inst
->precise
= this->precise
;
417 inst
->info
= tgsi_get_opcode_info(op
);
424 inst
->is_64bit_expanded
= false;
427 inst
->tex_offsets
= NULL
;
428 inst
->tex_offset_num_offset
= 0;
430 inst
->tex_shadow
= 0;
431 /* default to float, for paths where this is not initialized
432 * (since 0==UINT which is likely wrong):
434 inst
->tex_type
= GLSL_TYPE_FLOAT
;
436 /* Update indirect addressing status used by TGSI */
437 if (dst
.reladdr
|| dst
.reladdr2
) {
439 case PROGRAM_STATE_VAR
:
440 case PROGRAM_CONSTANT
:
441 case PROGRAM_UNIFORM
:
442 this->indirect_addr_consts
= true;
444 case PROGRAM_IMMEDIATE
:
445 assert(!"immediates should not have indirect addressing");
452 for (i
= 0; i
< 4; i
++) {
453 if(inst
->src
[i
].reladdr
) {
454 switch(inst
->src
[i
].file
) {
455 case PROGRAM_STATE_VAR
:
456 case PROGRAM_CONSTANT
:
457 case PROGRAM_UNIFORM
:
458 this->indirect_addr_consts
= true;
460 case PROGRAM_IMMEDIATE
:
461 assert(!"immediates should not have indirect addressing");
471 * This section contains the double processing.
472 * GLSL just represents doubles as single channel values,
473 * however most HW and TGSI represent doubles as pairs of register channels.
475 * so we have to fixup destination writemask/index and src swizzle/indexes.
476 * dest writemasks need to translate from single channel write mask
477 * to a dual-channel writemask, but also need to modify the index,
478 * if we are touching the Z,W fields in the pre-translated writemask.
480 * src channels have similiar index modifications along with swizzle
481 * changes to we pick the XY, ZW pairs from the correct index.
483 * GLSL [0].x -> TGSI [0].xy
484 * GLSL [0].y -> TGSI [0].zw
485 * GLSL [0].z -> TGSI [1].xy
486 * GLSL [0].w -> TGSI [1].zw
488 for (j
= 0; j
< 2; j
++) {
489 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
490 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
491 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
492 if (glsl_base_type_is_64bit(type
))
493 dst_is_64bit
[j
] = true;
497 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
498 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
499 glsl_to_tgsi_instruction
*dinst
= NULL
;
500 int initial_src_swz
[4], initial_src_idx
[4];
501 int initial_dst_idx
[2], initial_dst_writemask
[2];
502 /* select the writemask for dst0 or dst1 */
503 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
505 /* copy out the writemask, index and swizzles for all src/dsts. */
506 for (j
= 0; j
< 2; j
++) {
507 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
508 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
511 for (j
= 0; j
< 4; j
++) {
512 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
513 initial_src_idx
[j
] = inst
->src
[j
].index
;
517 * scan all the components in the dst writemask
518 * generate an instruction for each of them if required.
523 int i
= u_bit_scan(&writemask
);
525 /* before emitting the instruction, see if we have to adjust load / store
527 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
528 addr
.file
== PROGRAM_UNDEFINED
) {
529 /* We have to advance the buffer address by 16 */
530 addr
= get_temp(glsl_type::uint_type
);
531 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
532 inst
->src
[0], st_src_reg_for_int(16));
535 /* first time use previous instruction */
539 /* create a new instructions for subsequent attempts */
540 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
545 this->instructions
.push_tail(dinst
);
546 dinst
->is_64bit_expanded
= true;
548 /* modify the destination if we are splitting */
549 for (j
= 0; j
< 2; j
++) {
550 if (dst_is_64bit
[j
]) {
551 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
552 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
554 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
555 dinst
->src
[0] = addr
;
556 if (dinst
->op
!= TGSI_OPCODE_STORE
)
557 dinst
->dst
[j
].index
++;
560 /* if we aren't writing to a double, just get the bit of the initial writemask
562 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
566 /* modify the src registers */
567 for (j
= 0; j
< 4; j
++) {
568 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
570 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
571 dinst
->src
[j
].index
= initial_src_idx
[j
];
573 dinst
->src
[j
].double_reg2
= true;
574 dinst
->src
[j
].index
++;
578 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
580 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
583 /* some opcodes are special case in what they use as sources
584 - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is integer src1 */
585 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
586 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
587 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
588 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
589 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
596 this->instructions
.push_tail(inst
);
603 glsl_to_tgsi_instruction
*
604 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
606 st_src_reg src0
, st_src_reg src1
,
607 st_src_reg src2
, st_src_reg src3
)
609 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
613 * Determines whether to use an integer, unsigned integer, or float opcode
614 * based on the operands and input opcode, then emits the result.
617 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
619 st_src_reg src0
, st_src_reg src1
)
621 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
623 if (op
== TGSI_OPCODE_MOV
)
626 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
627 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
628 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
629 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
631 if (is_resource_instruction(op
))
633 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
634 type
= GLSL_TYPE_INT64
;
635 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
636 type
= GLSL_TYPE_UINT64
;
637 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
638 type
= GLSL_TYPE_DOUBLE
;
639 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
640 type
= GLSL_TYPE_FLOAT
;
641 else if (native_integers
)
642 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
644 #define case7(c, f, i, u, d, i64, ui64) \
645 case TGSI_OPCODE_##c: \
646 if (type == GLSL_TYPE_UINT64) \
647 op = TGSI_OPCODE_##ui64; \
648 else if (type == GLSL_TYPE_INT64) \
649 op = TGSI_OPCODE_##i64; \
650 else if (type == GLSL_TYPE_DOUBLE) \
651 op = TGSI_OPCODE_##d; \
652 else if (type == GLSL_TYPE_INT) \
653 op = TGSI_OPCODE_##i; \
654 else if (type == GLSL_TYPE_UINT) \
655 op = TGSI_OPCODE_##u; \
657 op = TGSI_OPCODE_##f; \
660 #define casecomp(c, f, i, u, d, i64, ui64) \
661 case TGSI_OPCODE_##c: \
662 if (type == GLSL_TYPE_INT64) \
663 op = TGSI_OPCODE_##i64; \
664 else if (type == GLSL_TYPE_UINT64) \
665 op = TGSI_OPCODE_##ui64; \
666 else if (type == GLSL_TYPE_DOUBLE) \
667 op = TGSI_OPCODE_##d; \
668 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
669 op = TGSI_OPCODE_##i; \
670 else if (type == GLSL_TYPE_UINT) \
671 op = TGSI_OPCODE_##u; \
672 else if (native_integers) \
673 op = TGSI_OPCODE_##f; \
675 op = TGSI_OPCODE_##c; \
679 /* Some instructions are initially selected without considering the type.
680 * This fixes the type:
682 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
684 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
685 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
686 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
687 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
688 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
689 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
690 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
691 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
692 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
693 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
694 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
695 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
696 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
697 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
698 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
699 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
701 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
702 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
703 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
704 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
705 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
706 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
707 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
708 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
710 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
711 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
712 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
713 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
718 assert(op
!= TGSI_OPCODE_LAST
);
722 glsl_to_tgsi_instruction
*
723 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
724 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
727 static const unsigned dot_opcodes
[] = {
728 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
731 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
735 * Emits TGSI scalar opcodes to produce unique answers across channels.
737 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
738 * channel determines the result across all channels. So to do a vec4
739 * of this operation, we want to emit a scalar per source channel used
740 * to produce dest channels.
743 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
745 st_src_reg orig_src0
, st_src_reg orig_src1
)
748 int done_mask
= ~dst
.writemask
;
750 /* TGSI RCP is a scalar operation splatting results to all channels,
751 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
754 for (i
= 0; i
< 4; i
++) {
755 GLuint this_mask
= (1 << i
);
756 st_src_reg src0
= orig_src0
;
757 st_src_reg src1
= orig_src1
;
759 if (done_mask
& this_mask
)
762 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
763 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
764 for (j
= i
+ 1; j
< 4; j
++) {
765 /* If there is another enabled component in the destination that is
766 * derived from the same inputs, generate its value on this pass as
769 if (!(done_mask
& (1 << j
)) &&
770 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
771 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
772 this_mask
|= (1 << j
);
775 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
776 src0_swiz
, src0_swiz
);
777 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
778 src1_swiz
, src1_swiz
);
780 dst
.writemask
= this_mask
;
781 emit_asm(ir
, op
, dst
, src0
, src1
);
782 done_mask
|= this_mask
;
787 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
788 st_dst_reg dst
, st_src_reg src0
)
790 st_src_reg undef
= undef_src
;
792 undef
.swizzle
= SWIZZLE_XXXX
;
794 emit_scalar(ir
, op
, dst
, src0
, undef
);
798 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
799 st_dst_reg dst
, st_src_reg src0
)
801 int op
= TGSI_OPCODE_ARL
;
803 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
804 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
807 op
= TGSI_OPCODE_UARL
;
810 assert(dst
.file
== PROGRAM_ADDRESS
);
811 if (dst
.index
>= this->num_address_regs
)
812 this->num_address_regs
= dst
.index
+ 1;
814 emit_asm(NULL
, op
, dst
, src0
);
818 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
819 gl_constant_value values
[8], int size
, int datatype
,
820 uint16_t *swizzle_out
)
822 if (file
== PROGRAM_CONSTANT
) {
823 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
824 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
825 size
, datatype
, &swizzle
);
827 *swizzle_out
= swizzle
;
831 assert(file
== PROGRAM_IMMEDIATE
);
834 immediate_storage
*entry
;
835 int size32
= size
* ((datatype
== GL_DOUBLE
||
836 datatype
== GL_INT64_ARB
||
837 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
840 /* Search immediate storage to see if we already have an identical
841 * immediate that we can use instead of adding a duplicate entry.
843 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
844 immediate_storage
*tmp
= entry
;
846 for (i
= 0; i
* 4 < size32
; i
++) {
847 int slot_size
= MIN2(size32
- (i
* 4), 4);
848 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
850 if (memcmp(tmp
->values
, &values
[i
* 4],
851 slot_size
* sizeof(gl_constant_value
)))
854 /* Everything matches, keep going until the full size is matched */
855 tmp
= (immediate_storage
*)tmp
->next
;
858 /* The full value matched */
865 for (i
= 0; i
* 4 < size32
; i
++) {
866 int slot_size
= MIN2(size32
- (i
* 4), 4);
867 /* Add this immediate to the list. */
868 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
869 this->immediates
.push_tail(entry
);
870 this->num_immediates
++;
876 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
878 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
879 union gl_constant_value uval
;
882 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
888 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
890 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
891 union gl_constant_value uval
[2];
893 memcpy(uval
, &val
, sizeof(uval
));
894 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
895 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
900 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
902 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
903 union gl_constant_value uval
;
905 assert(native_integers
);
908 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
914 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
916 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
917 union gl_constant_value uval
[2];
919 memcpy(uval
, &val
, sizeof(uval
));
920 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
921 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
927 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
930 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
931 st_src_reg_for_int(val
);
933 return st_src_reg_for_float(val
);
937 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
939 return type
->count_attribute_slots(is_vs_input
);
943 type_size(const struct glsl_type
*type
)
945 return type
->count_attribute_slots(false);
949 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
950 exec_list
*instructions
, ir_constant
*access
)
953 * emit_asm() might have actually split the op into pieces, e.g. for
954 * double stores. We have to go back and fix up all the generated ops.
956 unsigned op
= inst
->op
;
958 inst
->resource
= *buf
;
960 inst
->buffer_access
= access
->value
.u
[0];
962 if (inst
== instructions
->get_head_raw())
964 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
966 if (inst
->op
== TGSI_OPCODE_UADD
) {
967 if (inst
== instructions
->get_head_raw())
969 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
971 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
975 * If the given GLSL type is an array or matrix or a structure containing
976 * an array/matrix member, return true. Else return false.
978 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
979 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
980 * we have an array that might be indexed with a variable, we need to use
981 * the later storage type.
984 type_has_array_or_matrix(const glsl_type
*type
)
986 if (type
->is_array() || type
->is_matrix())
989 if (type
->is_record()) {
990 for (unsigned i
= 0; i
< type
->length
; i
++) {
991 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1002 * In the initial pass of codegen, we assign temporary numbers to
1003 * intermediate results. (not SSA -- variable assignments will reuse
1007 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1011 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1016 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1017 if (next_array
>= max_num_arrays
) {
1018 max_num_arrays
+= 32;
1019 array_sizes
= (unsigned*)
1020 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1023 src
.file
= PROGRAM_ARRAY
;
1025 src
.array_id
= next_array
+ 1;
1026 array_sizes
[next_array
] = type_size(type
);
1030 src
.file
= PROGRAM_TEMPORARY
;
1031 src
.index
= next_temp
;
1032 next_temp
+= type_size(type
);
1035 if (type
->is_array() || type
->is_record()) {
1036 src
.swizzle
= SWIZZLE_NOOP
;
1038 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1045 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1047 struct hash_entry
*entry
;
1049 entry
= _mesa_hash_table_search(this->variables
, var
);
1053 return (variable_storage
*)entry
->data
;
1057 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1059 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1060 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1061 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1064 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1066 const ir_state_slot
*const slots
= ir
->get_state_slots();
1067 assert(slots
!= NULL
);
1069 /* Check if this statevar's setup in the STATE file exactly
1070 * matches how we'll want to reference it as a
1071 * struct/array/whatever. If not, then we need to move it into
1072 * temporary storage and hope that it'll get copy-propagated
1075 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1076 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1081 variable_storage
*storage
;
1083 if (i
== ir
->get_num_state_slots()) {
1084 /* We'll set the index later. */
1085 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1087 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1091 /* The variable_storage constructor allocates slots based on the size
1092 * of the type. However, this had better match the number of state
1093 * elements that we're going to copy into the new temporary.
1095 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1097 dst
= st_dst_reg(get_temp(ir
->type
));
1099 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1102 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1106 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1107 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1108 (gl_state_index
*)slots
[i
].tokens
);
1110 if (storage
->file
== PROGRAM_STATE_VAR
) {
1111 if (storage
->index
== -1) {
1112 storage
->index
= index
;
1114 assert(index
== storage
->index
+ (int)i
);
1117 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1118 * the data being moved since MOV does not care about the type of
1119 * data it is moving, and we don't want to declare registers with
1120 * array or struct types.
1122 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1123 src
.swizzle
= slots
[i
].swizzle
;
1124 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1125 /* even a float takes up a whole vec4 reg in a struct/array. */
1130 if (storage
->file
== PROGRAM_TEMPORARY
&&
1131 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1132 fail_link(this->shader_program
,
1133 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1134 ir
->name
, dst
.index
- storage
->index
,
1135 type_size(ir
->type
));
1141 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1143 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1145 visit_exec_list(&ir
->body_instructions
, this);
1147 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1151 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1154 case ir_loop_jump::jump_break
:
1155 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1157 case ir_loop_jump::jump_continue
:
1158 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1165 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1172 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1174 /* Ignore function bodies other than main() -- we shouldn't see calls to
1175 * them since they should all be inlined before we get to glsl_to_tgsi.
1177 if (strcmp(ir
->name
, "main") == 0) {
1178 const ir_function_signature
*sig
;
1181 sig
= ir
->matching_signature(NULL
, &empty
, false);
1185 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1192 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1194 int nonmul_operand
= 1 - mul_operand
;
1196 st_dst_reg result_dst
;
1198 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1199 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1202 expr
->operands
[0]->accept(this);
1204 expr
->operands
[1]->accept(this);
1206 ir
->operands
[nonmul_operand
]->accept(this);
1209 this->result
= get_temp(ir
->type
);
1210 result_dst
= st_dst_reg(this->result
);
1211 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1212 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1218 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1220 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1221 * implemented using multiplication, and logical-or is implemented using
1222 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1223 * As result, the logical expression (a & !b) can be rewritten as:
1227 * - (a * 1) - (a * b)
1231 * This final expression can be implemented as a single MAD(a, -b, a)
1235 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1237 const int other_operand
= 1 - try_operand
;
1240 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1241 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1244 ir
->operands
[other_operand
]->accept(this);
1246 expr
->operands
[0]->accept(this);
1249 b
.negate
= ~b
.negate
;
1251 this->result
= get_temp(ir
->type
);
1252 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1258 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1259 st_src_reg
*reg
, int *num_reladdr
)
1261 if (!reg
->reladdr
&& !reg
->reladdr2
)
1264 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1265 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1267 if (*num_reladdr
!= 1) {
1268 st_src_reg temp
= get_temp(glsl_type::get_instance(reg
->type
, 4, 1));
1270 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1278 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1280 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1282 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1284 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1285 if (try_emit_mad(ir
, 1))
1287 if (try_emit_mad(ir
, 0))
1291 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1293 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1294 if (try_emit_mad_for_and_not(ir
, 1))
1296 if (try_emit_mad_for_and_not(ir
, 0))
1300 if (ir
->operation
== ir_quadop_vector
)
1301 assert(!"ir_quadop_vector should have been lowered");
1303 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1304 this->result
.file
= PROGRAM_UNDEFINED
;
1305 ir
->operands
[operand
]->accept(this);
1306 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1307 printf("Failed to get tree for expression operand:\n");
1308 ir
->operands
[operand
]->print();
1312 op
[operand
] = this->result
;
1314 /* Matrix expression operands should have been broken down to vector
1315 * operations already.
1317 assert(!ir
->operands
[operand
]->type
->is_matrix());
1320 visit_expression(ir
, op
);
1323 /* The non-recursive part of the expression visitor lives in a separate
1324 * function and should be prevented from being inlined, to avoid a stack
1325 * explosion when deeply nested expressions are visited.
1328 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1330 st_src_reg result_src
;
1331 st_dst_reg result_dst
;
1333 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1334 if (ir
->operands
[1]) {
1335 vector_elements
= MAX2(vector_elements
,
1336 ir
->operands
[1]->type
->vector_elements
);
1339 this->result
.file
= PROGRAM_UNDEFINED
;
1341 /* Storage for our result. Ideally for an assignment we'd be using
1342 * the actual storage for the result here, instead.
1344 result_src
= get_temp(ir
->type
);
1345 /* convenience for the emit functions below. */
1346 result_dst
= st_dst_reg(result_src
);
1347 /* Limit writes to the channels that will be used by result_src later.
1348 * This does limit this temp's use as a temporary for multi-instruction
1351 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1353 switch (ir
->operation
) {
1354 case ir_unop_logic_not
:
1355 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1356 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1358 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1359 * older GPUs implement SEQ using multiple instructions (i915 uses two
1360 * SGE instructions and a MUL instruction). Since our logic values are
1361 * 0.0 and 1.0, 1-x also implements !x.
1363 op
[0].negate
= ~op
[0].negate
;
1364 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1368 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1369 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1370 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1371 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1372 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1373 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1375 op
[0].negate
= ~op
[0].negate
;
1379 case ir_unop_subroutine_to_int
:
1380 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1383 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1384 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1385 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1386 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1387 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1388 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1390 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1393 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1396 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1400 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1403 assert(!"not reached: should be handled by exp_to_exp2");
1406 assert(!"not reached: should be handled by log_to_log2");
1409 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1412 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1415 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1417 case ir_unop_saturate
: {
1418 glsl_to_tgsi_instruction
*inst
;
1419 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1420 inst
->saturate
= true;
1425 case ir_unop_dFdx_coarse
:
1426 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1428 case ir_unop_dFdx_fine
:
1429 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1432 case ir_unop_dFdy_coarse
:
1433 case ir_unop_dFdy_fine
:
1435 /* The X component contains 1 or -1 depending on whether the framebuffer
1436 * is a FBO or the window system buffer, respectively.
1437 * It is then multiplied with the source operand of DDY.
1439 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1440 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1442 unsigned transform_y_index
=
1443 _mesa_add_state_reference(this->prog
->Parameters
,
1446 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1448 glsl_type::vec4_type
);
1449 transform_y
.swizzle
= SWIZZLE_XXXX
;
1451 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1453 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1454 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1455 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1459 case ir_unop_frexp_sig
:
1460 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1463 case ir_unop_frexp_exp
:
1464 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1467 case ir_unop_noise
: {
1468 /* At some point, a motivated person could add a better
1469 * implementation of noise. Currently not even the nvidia
1470 * binary drivers do anything more than this. In any case, the
1471 * place to do this is in the GL state tracker, not the poor
1474 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1479 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1482 op
[1].negate
= ~op
[1].negate
;
1483 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1487 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1490 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1493 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1494 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1496 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1500 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1502 case ir_binop_greater
:
1503 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1505 case ir_binop_lequal
:
1506 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1508 case ir_binop_gequal
:
1509 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1511 case ir_binop_equal
:
1512 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1514 case ir_binop_nequal
:
1515 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1517 case ir_binop_all_equal
:
1518 /* "==" operator producing a scalar boolean. */
1519 if (ir
->operands
[0]->type
->is_vector() ||
1520 ir
->operands
[1]->type
->is_vector()) {
1521 st_src_reg temp
= get_temp(native_integers
?
1522 glsl_type::uvec4_type
:
1523 glsl_type::vec4_type
);
1525 if (native_integers
) {
1526 st_dst_reg temp_dst
= st_dst_reg(temp
);
1527 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1529 if (ir
->operands
[0]->type
->is_boolean() &&
1530 ir
->operands
[1]->as_constant() &&
1531 ir
->operands
[1]->as_constant()->is_one()) {
1532 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1534 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1537 /* Emit 1-3 AND operations to combine the SEQ results. */
1538 switch (ir
->operands
[0]->type
->vector_elements
) {
1542 temp_dst
.writemask
= WRITEMASK_Y
;
1543 temp1
.swizzle
= SWIZZLE_YYYY
;
1544 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1545 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1548 temp_dst
.writemask
= WRITEMASK_X
;
1549 temp1
.swizzle
= SWIZZLE_XXXX
;
1550 temp2
.swizzle
= SWIZZLE_YYYY
;
1551 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1552 temp_dst
.writemask
= WRITEMASK_Y
;
1553 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1554 temp2
.swizzle
= SWIZZLE_WWWW
;
1555 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1558 temp1
.swizzle
= SWIZZLE_XXXX
;
1559 temp2
.swizzle
= SWIZZLE_YYYY
;
1560 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1562 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1564 /* After the dot-product, the value will be an integer on the
1565 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1567 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1569 /* Negating the result of the dot-product gives values on the range
1570 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1571 * This is achieved using SGE.
1573 st_src_reg sge_src
= result_src
;
1574 sge_src
.negate
= ~sge_src
.negate
;
1575 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1578 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1581 case ir_binop_any_nequal
:
1582 /* "!=" operator producing a scalar boolean. */
1583 if (ir
->operands
[0]->type
->is_vector() ||
1584 ir
->operands
[1]->type
->is_vector()) {
1585 st_src_reg temp
= get_temp(native_integers
?
1586 glsl_type::uvec4_type
:
1587 glsl_type::vec4_type
);
1588 if (ir
->operands
[0]->type
->is_boolean() &&
1589 ir
->operands
[1]->as_constant() &&
1590 ir
->operands
[1]->as_constant()->is_zero()) {
1591 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1593 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1596 if (native_integers
) {
1597 st_dst_reg temp_dst
= st_dst_reg(temp
);
1598 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1600 /* Emit 1-3 OR operations to combine the SNE results. */
1601 switch (ir
->operands
[0]->type
->vector_elements
) {
1605 temp_dst
.writemask
= WRITEMASK_Y
;
1606 temp1
.swizzle
= SWIZZLE_YYYY
;
1607 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1608 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1611 temp_dst
.writemask
= WRITEMASK_X
;
1612 temp1
.swizzle
= SWIZZLE_XXXX
;
1613 temp2
.swizzle
= SWIZZLE_YYYY
;
1614 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1615 temp_dst
.writemask
= WRITEMASK_Y
;
1616 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1617 temp2
.swizzle
= SWIZZLE_WWWW
;
1618 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1621 temp1
.swizzle
= SWIZZLE_XXXX
;
1622 temp2
.swizzle
= SWIZZLE_YYYY
;
1623 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1625 /* After the dot-product, the value will be an integer on the
1626 * range [0,4]. Zero stays zero, and positive values become 1.0.
1628 glsl_to_tgsi_instruction
*const dp
=
1629 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1630 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1631 /* The clamping to [0,1] can be done for free in the fragment
1632 * shader with a saturate.
1634 dp
->saturate
= true;
1636 /* Negating the result of the dot-product gives values on the range
1637 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1638 * achieved using SLT.
1640 st_src_reg slt_src
= result_src
;
1641 slt_src
.negate
= ~slt_src
.negate
;
1642 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1646 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1650 case ir_binop_logic_xor
:
1651 if (native_integers
)
1652 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1654 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1657 case ir_binop_logic_or
: {
1658 if (native_integers
) {
1659 /* If integers are used as booleans, we can use an actual "or"
1662 assert(native_integers
);
1663 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1665 /* After the addition, the value will be an integer on the
1666 * range [0,2]. Zero stays zero, and positive values become 1.0.
1668 glsl_to_tgsi_instruction
*add
=
1669 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1670 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1671 /* The clamping to [0,1] can be done for free in the fragment
1672 * shader with a saturate if floats are being used as boolean values.
1674 add
->saturate
= true;
1676 /* Negating the result of the addition gives values on the range
1677 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1678 * is achieved using SLT.
1680 st_src_reg slt_src
= result_src
;
1681 slt_src
.negate
= ~slt_src
.negate
;
1682 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1688 case ir_binop_logic_and
:
1689 /* If native integers are disabled, the bool args are stored as float 0.0
1690 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1691 * actual AND opcode.
1693 if (native_integers
)
1694 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1696 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1700 assert(ir
->operands
[0]->type
->is_vector());
1701 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1702 emit_dp(ir
, result_dst
, op
[0], op
[1],
1703 ir
->operands
[0]->type
->vector_elements
);
1708 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1710 /* This is the only instruction sequence that makes the game "Risen"
1711 * render correctly. ABS is not required for the game, but since GLSL
1712 * declares negative values as "undefined", allowing us to do whatever
1713 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1716 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1717 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1721 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1724 if (native_integers
) {
1725 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1728 /* fallthrough to next case otherwise */
1730 if (native_integers
) {
1731 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1734 /* fallthrough to next case otherwise */
1737 case ir_unop_i642u64
:
1738 case ir_unop_u642i64
:
1739 /* Converting between signed and unsigned integers is a no-op. */
1741 result_src
.type
= result_dst
.type
;
1744 if (native_integers
) {
1745 /* Booleans are stored as integers using ~0 for true and 0 for false.
1746 * GLSL requires that int(bool) return 1 for true and 0 for false.
1747 * This conversion is done with AND, but it could be done with NEG.
1749 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1751 /* Booleans and integers are both stored as floats when native
1752 * integers are disabled.
1758 if (native_integers
)
1759 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1761 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1764 if (native_integers
)
1765 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1767 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1769 case ir_unop_bitcast_f2i
:
1770 case ir_unop_bitcast_f2u
:
1771 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1772 if (op
[0].negate
|| op
[0].abs
)
1773 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1776 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1779 case ir_unop_bitcast_i2f
:
1780 case ir_unop_bitcast_u2f
:
1782 result_src
.type
= GLSL_TYPE_FLOAT
;
1785 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1788 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1791 if (native_integers
)
1792 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1794 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1796 case ir_unop_bitcast_u642d
:
1797 case ir_unop_bitcast_i642d
:
1799 result_src
.type
= GLSL_TYPE_DOUBLE
;
1801 case ir_unop_bitcast_d2i64
:
1803 result_src
.type
= GLSL_TYPE_INT64
;
1805 case ir_unop_bitcast_d2u64
:
1807 result_src
.type
= GLSL_TYPE_UINT64
;
1810 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1813 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1816 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1818 case ir_unop_round_even
:
1819 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1822 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1826 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1829 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1832 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1835 case ir_unop_bit_not
:
1836 if (native_integers
) {
1837 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1841 if (native_integers
) {
1842 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1845 case ir_binop_lshift
:
1846 case ir_binop_rshift
:
1847 if (native_integers
) {
1848 unsigned opcode
= ir
->operation
== ir_binop_lshift
? TGSI_OPCODE_SHL
1852 if (glsl_base_type_is_64bit(op
[0].type
)) {
1853 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1856 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]->type
->components()));
1857 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1862 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1865 case ir_binop_bit_and
:
1866 if (native_integers
) {
1867 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1870 case ir_binop_bit_xor
:
1871 if (native_integers
) {
1872 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1875 case ir_binop_bit_or
:
1876 if (native_integers
) {
1877 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1881 assert(!"GLSL 1.30 features unsupported");
1884 case ir_binop_ubo_load
: {
1885 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1886 ir_rvalue
*block
= ir
->operands
[0];
1887 ir_rvalue
*offset
= ir
->operands
[1];
1888 ir_constant
*const_block
= block
->as_constant();
1890 st_src_reg
cbuf(PROGRAM_CONSTANT
,
1891 (const_block
? const_block
->value
.u
[0] + 1 : 1),
1892 ir
->type
->base_type
);
1894 cbuf
.has_index2
= true;
1897 block
->accept(this);
1898 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1899 *cbuf
.reladdr
= this->result
;
1900 emit_arl(ir
, sampler_reladdr
, this->result
);
1903 /* Calculate the surface offset */
1904 offset
->accept(this);
1905 st_src_reg off
= this->result
;
1907 glsl_to_tgsi_instruction
*inst
=
1908 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
1910 if (result_dst
.type
== GLSL_TYPE_BOOL
)
1911 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
1912 st_src_reg_for_int(0));
1914 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
1917 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1918 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1919 unsigned const_offset
= const_offset_ir
?
1920 const_offset_ir
->value
.u
[0] : 0;
1921 unsigned const_block
= const_uniform_block
?
1922 const_uniform_block
->value
.u
[0] + 1 : 1;
1923 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
1926 cbuf
.type
= ir
->type
->base_type
;
1927 cbuf
.file
= PROGRAM_CONSTANT
;
1929 cbuf
.reladdr
= NULL
;
1932 cbuf
.index2D
= const_block
;
1934 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1936 if (const_offset_ir
) {
1937 /* Constant index into constant buffer */
1938 cbuf
.reladdr
= NULL
;
1939 cbuf
.index
= const_offset
/ 16;
1941 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
1942 st_src_reg offset
= op
[1];
1944 /* The OpenGL spec is written in such a way that accesses with
1945 * non-constant offset are almost always vec4-aligned. The only
1946 * exception to this are members of structs in arrays of structs:
1947 * each struct in an array of structs is at least vec4-aligned,
1948 * but single-element and [ui]vec2 members of the struct may be at
1949 * an offset that is not a multiple of 16 bytes.
1951 * Here, we extract that offset, relying on previous passes to
1952 * always generate offset expressions of the form
1953 * (+ expr constant_offset).
1955 * Note that the std430 layout, which allows more cases of
1956 * alignment less than vec4 in arrays, is not supported for
1957 * uniform blocks, so we do not have to deal with it here.
1959 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
1960 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
1961 if (const_offset_ir
) {
1962 const_offset
= const_offset_ir
->value
.u
[0];
1963 cbuf
.index
= const_offset
/ 16;
1964 offset_expr
->operands
[0]->accept(this);
1965 offset
= this->result
;
1969 /* Relative/variable index into constant buffer */
1970 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
1971 st_src_reg_for_int(4));
1972 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1973 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
1976 if (const_uniform_block
) {
1977 /* Constant constant buffer */
1978 cbuf
.reladdr2
= NULL
;
1980 /* Relative/variable constant buffer */
1981 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
1982 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
1984 cbuf
.has_index2
= true;
1986 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1987 if (glsl_base_type_is_64bit(cbuf
.type
))
1988 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
1989 const_offset
% 16 / 8,
1990 const_offset
% 16 / 8,
1991 const_offset
% 16 / 8);
1993 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
1994 const_offset
% 16 / 4,
1995 const_offset
% 16 / 4,
1996 const_offset
% 16 / 4);
1998 if (ir
->type
->is_boolean()) {
1999 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2000 st_src_reg_for_int(0));
2002 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2008 /* note: we have to reorder the three args here */
2009 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2012 if (this->ctx
->Const
.NativeIntegers
)
2013 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2015 op
[0].negate
= ~op
[0].negate
;
2016 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2019 case ir_triop_bitfield_extract
:
2020 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2022 case ir_quadop_bitfield_insert
:
2023 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2025 case ir_unop_bitfield_reverse
:
2026 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2028 case ir_unop_bit_count
:
2029 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2031 case ir_unop_find_msb
:
2032 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2034 case ir_unop_find_lsb
:
2035 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2037 case ir_binop_imul_high
:
2038 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2041 /* In theory, MAD is incorrect here. */
2043 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2045 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2047 case ir_unop_interpolate_at_centroid
:
2048 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2050 case ir_binop_interpolate_at_offset
: {
2051 /* The y coordinate needs to be flipped for the default fb */
2052 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2053 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2055 unsigned transform_y_index
=
2056 _mesa_add_state_reference(this->prog
->Parameters
,
2059 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2061 glsl_type::vec4_type
);
2062 transform_y
.swizzle
= SWIZZLE_XXXX
;
2064 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2065 st_dst_reg temp_dst
= st_dst_reg(temp
);
2067 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2068 temp_dst
.writemask
= WRITEMASK_Y
;
2069 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2070 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2073 case ir_binop_interpolate_at_sample
:
2074 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2078 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2081 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2084 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2087 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2090 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2093 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2095 case ir_unop_unpack_double_2x32
:
2096 case ir_unop_pack_double_2x32
:
2097 case ir_unop_unpack_int_2x32
:
2098 case ir_unop_pack_int_2x32
:
2099 case ir_unop_unpack_uint_2x32
:
2100 case ir_unop_pack_uint_2x32
:
2101 case ir_unop_unpack_sampler_2x32
:
2102 case ir_unop_pack_sampler_2x32
:
2103 case ir_unop_unpack_image_2x32
:
2104 case ir_unop_pack_image_2x32
:
2105 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2108 case ir_binop_ldexp
:
2109 if (ir
->operands
[0]->type
->is_double()) {
2110 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2111 } else if (ir
->operands
[0]->type
->is_float()) {
2112 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2114 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2118 case ir_unop_pack_half_2x16
:
2119 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2121 case ir_unop_unpack_half_2x16
:
2122 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2125 case ir_unop_get_buffer_size
: {
2126 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2129 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2130 (const_offset
? const_offset
->value
.u
[0] : 0),
2132 if (!const_offset
) {
2133 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2134 *buffer
.reladdr
= op
[0];
2135 emit_arl(ir
, sampler_reladdr
, op
[0]);
2137 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2143 case ir_unop_b2i64
: {
2144 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2145 st_dst_reg temp_dst
= st_dst_reg(temp
);
2146 unsigned orig_swz
= op
[0].swizzle
;
2148 * To convert unsigned to 64-bit:
2149 * zero Y channel, copy X channel.
2151 temp_dst
.writemask
= WRITEMASK_Y
;
2152 if (vector_elements
> 1)
2153 temp_dst
.writemask
|= WRITEMASK_W
;
2154 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2155 temp_dst
.writemask
= WRITEMASK_X
;
2156 if (vector_elements
> 1)
2157 temp_dst
.writemask
|= WRITEMASK_Z
;
2158 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2159 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2160 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2161 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2163 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2165 result_src
.type
= GLSL_TYPE_UINT64
;
2166 if (vector_elements
> 2) {
2167 /* Subtle: We rely on the fact that get_temp here returns the next
2168 * TGSI temporary register directly after the temp register used for
2169 * the first two components, so that the result gets picked up
2172 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2173 st_dst_reg temp_dst
= st_dst_reg(temp
);
2174 temp_dst
.writemask
= WRITEMASK_Y
;
2175 if (vector_elements
> 3)
2176 temp_dst
.writemask
|= WRITEMASK_W
;
2177 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2179 temp_dst
.writemask
= WRITEMASK_X
;
2180 if (vector_elements
> 3)
2181 temp_dst
.writemask
|= WRITEMASK_Z
;
2182 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2183 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2184 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2185 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2187 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2194 case ir_unop_i642u
: {
2195 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2196 st_dst_reg temp_dst
= st_dst_reg(temp
);
2197 unsigned orig_swz
= op
[0].swizzle
;
2198 unsigned orig_idx
= op
[0].index
;
2200 temp_dst
.writemask
= WRITEMASK_X
;
2202 for (el
= 0; el
< vector_elements
; el
++) {
2203 unsigned swz
= GET_SWZ(orig_swz
, el
);
2205 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2207 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2209 op
[0].index
= orig_idx
+ 1;
2210 op
[0].type
= GLSL_TYPE_UINT
;
2211 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2212 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2215 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2216 result_src
.type
= GLSL_TYPE_UINT
;
2218 result_src
.type
= GLSL_TYPE_INT
;
2222 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int64(0));
2225 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2228 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2231 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2234 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2237 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2240 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2243 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2246 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2249 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2252 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2254 /* these might be needed */
2255 case ir_unop_pack_snorm_2x16
:
2256 case ir_unop_pack_unorm_2x16
:
2257 case ir_unop_pack_snorm_4x8
:
2258 case ir_unop_pack_unorm_4x8
:
2260 case ir_unop_unpack_snorm_2x16
:
2261 case ir_unop_unpack_unorm_2x16
:
2262 case ir_unop_unpack_snorm_4x8
:
2263 case ir_unop_unpack_unorm_4x8
:
2265 case ir_quadop_vector
:
2266 case ir_binop_vector_extract
:
2267 case ir_triop_vector_insert
:
2268 case ir_binop_carry
:
2269 case ir_binop_borrow
:
2270 case ir_unop_ssbo_unsized_array_length
:
2271 /* This operation is not supported, or should have already been handled.
2273 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2277 this->result
= result_src
;
2282 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2288 /* Note that this is only swizzles in expressions, not those on the left
2289 * hand side of an assignment, which do write masking. See ir_assignment
2293 ir
->val
->accept(this);
2295 assert(src
.file
!= PROGRAM_UNDEFINED
);
2296 assert(ir
->type
->vector_elements
> 0);
2298 for (i
= 0; i
< 4; i
++) {
2299 if (i
< ir
->type
->vector_elements
) {
2302 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2305 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2308 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2311 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2315 /* If the type is smaller than a vec4, replicate the last
2318 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2322 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2327 /* Test if the variable is an array. Note that geometry and
2328 * tessellation shader inputs are outputs are always arrays (except
2329 * for patch inputs), so only the array element type is considered.
2332 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2334 const glsl_type
*type
= var
->type
;
2336 *remove_array
= false;
2338 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2339 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2342 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2343 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2344 stage
== MESA_SHADER_TESS_CTRL
) &&
2346 if (!var
->type
->is_array())
2347 return false; /* a system value probably */
2349 type
= var
->type
->fields
.array
;
2350 *remove_array
= true;
2353 return type
->is_array() || type
->is_matrix();
2357 st_translate_interp_loc(ir_variable
*var
)
2359 if (var
->data
.centroid
)
2360 return TGSI_INTERPOLATE_LOC_CENTROID
;
2361 else if (var
->data
.sample
)
2362 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2364 return TGSI_INTERPOLATE_LOC_CENTER
;
2368 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2370 variable_storage
*entry
= find_variable_storage(ir
->var
);
2371 ir_variable
*var
= ir
->var
;
2375 switch (var
->data
.mode
) {
2376 case ir_var_uniform
:
2377 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2378 var
->data
.param_index
);
2379 _mesa_hash_table_insert(this->variables
, var
, entry
);
2381 case ir_var_shader_in
: {
2382 /* The linker assigns locations for varyings and attributes,
2383 * including deprecated builtins (like gl_Color), user-assign
2384 * generic attributes (glBindVertexLocation), and
2385 * user-defined varyings.
2387 assert(var
->data
.location
!= -1);
2389 const glsl_type
*type_without_array
= var
->type
->without_array();
2390 struct inout_decl
*decl
= &inputs
[num_inputs
];
2391 unsigned component
= var
->data
.location_frac
;
2392 unsigned num_components
;
2395 if (type_without_array
->is_64bit())
2396 component
= component
/ 2;
2397 if (type_without_array
->vector_elements
)
2398 num_components
= type_without_array
->vector_elements
;
2402 decl
->mesa_index
= var
->data
.location
;
2403 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2404 decl
->interp_loc
= st_translate_interp_loc(var
);
2405 decl
->base_type
= type_without_array
->base_type
;
2406 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2408 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2409 decl
->array_id
= num_input_arrays
+ 1;
2416 decl
->size
= type_size(var
->type
->fields
.array
);
2418 decl
->size
= type_size(var
->type
);
2420 entry
= new(mem_ctx
) variable_storage(var
,
2424 entry
->component
= component
;
2426 _mesa_hash_table_insert(this->variables
, var
, entry
);
2430 case ir_var_shader_out
: {
2431 assert(var
->data
.location
!= -1);
2433 const glsl_type
*type_without_array
= var
->type
->without_array();
2434 struct inout_decl
*decl
= &outputs
[num_outputs
];
2435 unsigned component
= var
->data
.location_frac
;
2436 unsigned num_components
;
2439 if (type_without_array
->is_64bit())
2440 component
= component
/ 2;
2441 if (type_without_array
->vector_elements
)
2442 num_components
= type_without_array
->vector_elements
;
2446 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2447 decl
->base_type
= type_without_array
->base_type
;
2448 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2449 if (var
->data
.stream
& (1u << 31)) {
2450 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2452 assert(var
->data
.stream
< 4);
2453 decl
->gs_out_streams
= 0;
2454 for (unsigned i
= 0; i
< num_components
; ++i
)
2455 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2458 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2459 decl
->array_id
= num_output_arrays
+ 1;
2460 num_output_arrays
++;
2466 decl
->size
= type_size(var
->type
->fields
.array
);
2468 decl
->size
= type_size(var
->type
);
2470 if (var
->data
.fb_fetch_output
) {
2471 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2472 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2473 var
->type
, component
, decl
->array_id
);
2474 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2475 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2478 entry
= new(mem_ctx
) variable_storage(var
,
2483 entry
->component
= component
;
2485 _mesa_hash_table_insert(this->variables
, var
, entry
);
2489 case ir_var_system_value
:
2490 entry
= new(mem_ctx
) variable_storage(var
,
2491 PROGRAM_SYSTEM_VALUE
,
2492 var
->data
.location
);
2495 case ir_var_temporary
:
2496 st_src_reg src
= get_temp(var
->type
);
2498 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2500 _mesa_hash_table_insert(this->variables
, var
, entry
);
2506 printf("Failed to make storage for %s\n", var
->name
);
2511 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2512 entry
->component
, entry
->array_id
);
2513 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2514 var
->data
.mode
== ir_var_shader_in
&&
2515 var
->type
->without_array()->is_double())
2516 this->result
.is_double_vertex_input
= true;
2517 if (!native_integers
)
2518 this->result
.type
= GLSL_TYPE_FLOAT
;
2522 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2523 GLbitfield64
* usage_mask
,
2524 GLbitfield64 double_usage_mask
,
2525 GLbitfield
* patch_usage_mask
)
2530 /* Fix array declarations by removing unused array elements at both ends
2531 * of the arrays. For example, mat4[3] where only mat[1] is used.
2533 for (i
= 0; i
< count
; i
++) {
2534 struct inout_decl
*decl
= &decls
[i
];
2535 if (!decl
->array_id
)
2538 /* Shrink the beginning. */
2539 for (j
= 0; j
< (int)decl
->size
; j
++) {
2540 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2541 if (*patch_usage_mask
&
2542 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2546 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2548 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2557 /* Shrink the end. */
2558 for (j
= decl
->size
-1; j
>= 0; j
--) {
2559 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2560 if (*patch_usage_mask
&
2561 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2565 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2567 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2574 /* When not all entries of an array are accessed, we mark them as used
2575 * here anyway, to ensure that the input/output mapping logic doesn't get
2578 * TODO This happens when an array isn't used via indirect access, which
2579 * some game ports do (at least eON-based). There is an optimization
2580 * opportunity here by replacing the array declaration with non-array
2581 * declarations of those slots that are actually used.
2583 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2584 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2585 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2587 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2593 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2598 ir_variable
*var
= ir
->variable_referenced();
2600 /* We only need the logic provided by st_glsl_storage_type_size()
2601 * for arrays of structs. Indirect sampler and image indexing is handled
2604 int element_size
= ir
->type
->without_array()->is_record() ?
2605 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2606 type_size(ir
->type
);
2608 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2610 ir
->array
->accept(this);
2613 if (!src
.has_index2
) {
2614 switch (this->prog
->Target
) {
2615 case GL_TESS_CONTROL_PROGRAM_NV
:
2616 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2617 !ir
->variable_referenced()->data
.patch
;
2619 case GL_TESS_EVALUATION_PROGRAM_NV
:
2620 is_2D
= src
.file
== PROGRAM_INPUT
&&
2621 !ir
->variable_referenced()->data
.patch
;
2623 case GL_GEOMETRY_PROGRAM_NV
:
2624 is_2D
= src
.file
== PROGRAM_INPUT
;
2634 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2635 src
.file
== PROGRAM_INPUT
)
2636 element_size
= attrib_type_size(ir
->type
, true);
2638 src
.index2D
= index
->value
.i
[0];
2639 src
.has_index2
= true;
2641 src
.index
+= index
->value
.i
[0] * element_size
;
2643 /* Variable index array dereference. It eats the "vec4" of the
2644 * base of the array and an index that offsets the TGSI register
2647 ir
->array_index
->accept(this);
2649 st_src_reg index_reg
;
2651 if (element_size
== 1) {
2652 index_reg
= this->result
;
2654 index_reg
= get_temp(native_integers
?
2655 glsl_type::int_type
: glsl_type::float_type
);
2657 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2658 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2661 /* If there was already a relative address register involved, add the
2662 * new and the old together to get the new offset.
2664 if (!is_2D
&& src
.reladdr
!= NULL
) {
2665 st_src_reg accum_reg
= get_temp(native_integers
?
2666 glsl_type::int_type
: glsl_type::float_type
);
2668 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2669 index_reg
, *src
.reladdr
);
2671 index_reg
= accum_reg
;
2675 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2676 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2678 src
.has_index2
= true;
2680 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2681 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2685 /* Change the register type to the element type of the array. */
2686 src
.type
= ir
->type
->base_type
;
2692 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2695 const glsl_type
*struct_type
= ir
->record
->type
;
2696 ir_variable
*var
= ir
->record
->variable_referenced();
2699 ir
->record
->accept(this);
2701 assert(ir
->field_idx
>= 0);
2703 for (i
= 0; i
< struct_type
->length
; i
++) {
2704 if (i
== (unsigned) ir
->field_idx
)
2706 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2707 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2710 /* If the type is smaller than a vec4, replicate the last channel out. */
2711 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2712 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2714 this->result
.swizzle
= SWIZZLE_NOOP
;
2716 this->result
.index
+= offset
;
2717 this->result
.type
= ir
->type
->base_type
;
2721 * We want to be careful in assignment setup to hit the actual storage
2722 * instead of potentially using a temporary like we might with the
2723 * ir_dereference handler.
2726 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2728 /* The LHS must be a dereference. If the LHS is a variable indexed array
2729 * access of a vector, it must be separated into a series conditional moves
2730 * before reaching this point (see ir_vec_index_to_cond_assign).
2732 assert(ir
->as_dereference());
2733 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2735 assert(!deref_array
->array
->type
->is_vector());
2738 /* Use the rvalue deref handler for the most part. We write swizzles using
2739 * the writemask, but we do extract the base component for enhanced layouts
2740 * from the source swizzle.
2743 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2744 return st_dst_reg(v
->result
);
2748 * Process the condition of a conditional assignment
2750 * Examines the condition of a conditional assignment to generate the optimal
2751 * first operand of a \c CMP instruction. If the condition is a relational
2752 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2753 * used as the source for the \c CMP instruction. Otherwise the comparison
2754 * is processed to a boolean result, and the boolean result is used as the
2755 * operand to the CMP instruction.
2758 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2760 ir_rvalue
*src_ir
= ir
;
2762 bool switch_order
= false;
2764 ir_expression
*const expr
= ir
->as_expression();
2766 if (native_integers
) {
2767 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2768 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2769 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2770 type
== GLSL_TYPE_BOOL
) {
2771 if (expr
->operation
== ir_binop_equal
) {
2772 if (expr
->operands
[0]->is_zero()) {
2773 src_ir
= expr
->operands
[1];
2774 switch_order
= true;
2776 else if (expr
->operands
[1]->is_zero()) {
2777 src_ir
= expr
->operands
[0];
2778 switch_order
= true;
2781 else if (expr
->operation
== ir_binop_nequal
) {
2782 if (expr
->operands
[0]->is_zero()) {
2783 src_ir
= expr
->operands
[1];
2785 else if (expr
->operands
[1]->is_zero()) {
2786 src_ir
= expr
->operands
[0];
2792 src_ir
->accept(this);
2793 return switch_order
;
2796 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2797 bool zero_on_left
= false;
2799 if (expr
->operands
[0]->is_zero()) {
2800 src_ir
= expr
->operands
[1];
2801 zero_on_left
= true;
2802 } else if (expr
->operands
[1]->is_zero()) {
2803 src_ir
= expr
->operands
[0];
2804 zero_on_left
= false;
2808 * (a < 0) T F F ( a < 0) T F F
2809 * (0 < a) F F T (-a < 0) F F T
2810 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2811 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2812 * (a > 0) F F T (-a < 0) F F T
2813 * (0 > a) T F F ( a < 0) T F F
2814 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2815 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2817 * Note that exchanging the order of 0 and 'a' in the comparison simply
2818 * means that the value of 'a' should be negated.
2821 switch (expr
->operation
) {
2823 switch_order
= false;
2824 negate
= zero_on_left
;
2827 case ir_binop_greater
:
2828 switch_order
= false;
2829 negate
= !zero_on_left
;
2832 case ir_binop_lequal
:
2833 switch_order
= true;
2834 negate
= !zero_on_left
;
2837 case ir_binop_gequal
:
2838 switch_order
= true;
2839 negate
= zero_on_left
;
2843 /* This isn't the right kind of comparison afterall, so make sure
2844 * the whole condition is visited.
2852 src_ir
->accept(this);
2854 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2855 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2856 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2857 * computing the condition.
2860 this->result
.negate
= ~this->result
.negate
;
2862 return switch_order
;
2866 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2867 st_dst_reg
*l
, st_src_reg
*r
,
2868 st_src_reg
*cond
, bool cond_swap
)
2870 if (type
->is_record()) {
2871 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2872 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2878 if (type
->is_array()) {
2879 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2880 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2885 if (type
->is_matrix()) {
2886 const struct glsl_type
*vec_type
;
2888 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2889 type
->vector_elements
, 1);
2891 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2892 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2897 assert(type
->is_scalar() || type
->is_vector());
2899 l
->type
= type
->base_type
;
2900 r
->type
= type
->base_type
;
2902 st_src_reg l_src
= st_src_reg(*l
);
2904 if (l_src
.file
== PROGRAM_OUTPUT
&&
2905 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
2906 (l_src
.index
== FRAG_RESULT_DEPTH
|| l_src
.index
== FRAG_RESULT_STENCIL
)) {
2907 /* This is a special case because the source swizzles will be shifted
2908 * later to account for the difference between GLSL (where they're
2909 * plain floats) and TGSI (where they're Z and Y components). */
2910 l_src
.swizzle
= SWIZZLE_XXXX
;
2913 if (native_integers
) {
2914 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2915 cond_swap
? l_src
: *r
,
2916 cond_swap
? *r
: l_src
);
2918 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2919 cond_swap
? l_src
: *r
,
2920 cond_swap
? *r
: l_src
);
2923 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2927 if (type
->is_dual_slot()) {
2929 if (r
->is_double_vertex_input
== false)
2935 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2941 /* all generated instructions need to be flaged as precise */
2942 this->precise
= is_precise(ir
->lhs
->variable_referenced());
2943 ir
->rhs
->accept(this);
2946 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2950 int first_enabled_chan
= 0;
2952 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2954 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2955 variable
->data
.mode
== ir_var_shader_out
&&
2956 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2957 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2958 assert(ir
->lhs
->type
->is_scalar());
2959 assert(ir
->write_mask
== WRITEMASK_X
);
2961 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2962 l
.writemask
= WRITEMASK_Z
;
2964 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2965 l
.writemask
= WRITEMASK_Y
;
2967 } else if (ir
->write_mask
== 0) {
2968 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2970 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2973 l
.writemask
= u_bit_consecutive(0, num_elements
);
2975 /* The type is a struct or an array of (array of) structs. */
2976 l
.writemask
= WRITEMASK_XYZW
;
2979 l
.writemask
= ir
->write_mask
;
2982 for (int i
= 0; i
< 4; i
++) {
2983 if (l
.writemask
& (1 << i
)) {
2984 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2989 l
.writemask
= l
.writemask
<< dst_component
;
2991 /* Swizzle a small RHS vector into the channels being written.
2993 * glsl ir treats write_mask as dictating how many channels are
2994 * present on the RHS while TGSI treats write_mask as just
2995 * showing which channels of the vec4 RHS get written.
2997 for (int i
= 0; i
< 4; i
++) {
2998 if (l
.writemask
& (1 << i
))
2999 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3001 swizzles
[i
] = first_enabled_chan
;
3003 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3004 swizzles
[2], swizzles
[3]);
3007 assert(l
.file
!= PROGRAM_UNDEFINED
);
3008 assert(r
.file
!= PROGRAM_UNDEFINED
);
3010 if (ir
->condition
) {
3011 const bool switch_order
= this->process_move_condition(ir
->condition
);
3012 st_src_reg condition
= this->result
;
3014 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3015 } else if (ir
->rhs
->as_expression() &&
3016 this->instructions
.get_tail() &&
3017 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3018 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3019 type_size(ir
->lhs
->type
) == 1 &&
3020 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3021 /* To avoid emitting an extra MOV when assigning an expression to a
3022 * variable, emit the last instruction of the expression again, but
3023 * replace the destination register with the target of the assignment.
3024 * Dead code elimination will remove the original instruction.
3026 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3027 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3028 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3029 new_inst
->saturate
= inst
->saturate
;
3030 new_inst
->resource
= inst
->resource
;
3031 inst
->dead_mask
= inst
->dst
[0].writemask
;
3033 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3040 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3043 GLdouble stack_vals
[4] = { 0 };
3044 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3045 GLenum gl_type
= GL_NONE
;
3047 static int in_array
= 0;
3048 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3050 /* Unfortunately, 4 floats is all we can get into
3051 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3052 * aggregate constant and move each constant value into it. If we
3053 * get lucky, copy propagation will eliminate the extra moves.
3055 if (ir
->type
->is_record()) {
3056 st_src_reg temp_base
= get_temp(ir
->type
);
3057 st_dst_reg temp
= st_dst_reg(temp_base
);
3059 for (i
= 0; i
< ir
->type
->length
; i
++) {
3060 ir_constant
*const field_value
= ir
->get_record_field(i
);
3061 int size
= type_size(field_value
->type
);
3065 field_value
->accept(this);
3068 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3069 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3075 this->result
= temp_base
;
3079 if (ir
->type
->is_array()) {
3080 st_src_reg temp_base
= get_temp(ir
->type
);
3081 st_dst_reg temp
= st_dst_reg(temp_base
);
3082 int size
= type_size(ir
->type
->fields
.array
);
3087 for (i
= 0; i
< ir
->type
->length
; i
++) {
3088 ir
->const_elements
[i
]->accept(this);
3090 for (int j
= 0; j
< size
; j
++) {
3091 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3097 this->result
= temp_base
;
3102 if (ir
->type
->is_matrix()) {
3103 st_src_reg mat
= get_temp(ir
->type
);
3104 st_dst_reg mat_column
= st_dst_reg(mat
);
3106 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3107 switch (ir
->type
->base_type
) {
3108 case GLSL_TYPE_FLOAT
:
3109 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3111 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3112 src
.index
= add_constant(file
,
3114 ir
->type
->vector_elements
,
3117 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3119 case GLSL_TYPE_DOUBLE
:
3120 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3121 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3122 src
.index
= add_constant(file
,
3124 ir
->type
->vector_elements
,
3127 if (ir
->type
->vector_elements
>= 2) {
3128 mat_column
.writemask
= WRITEMASK_XY
;
3129 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3130 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3132 mat_column
.writemask
= WRITEMASK_X
;
3133 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3134 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3137 if (ir
->type
->vector_elements
> 2) {
3138 if (ir
->type
->vector_elements
== 4) {
3139 mat_column
.writemask
= WRITEMASK_ZW
;
3140 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3141 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3143 mat_column
.writemask
= WRITEMASK_Z
;
3144 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3145 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3146 mat_column
.writemask
= WRITEMASK_XYZW
;
3147 src
.swizzle
= SWIZZLE_XYZW
;
3153 unreachable("Illegal matrix constant type.\n");
3162 switch (ir
->type
->base_type
) {
3163 case GLSL_TYPE_FLOAT
:
3165 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3166 values
[i
].f
= ir
->value
.f
[i
];
3169 case GLSL_TYPE_DOUBLE
:
3170 gl_type
= GL_DOUBLE
;
3171 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3172 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3175 case GLSL_TYPE_INT64
:
3176 gl_type
= GL_INT64_ARB
;
3177 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3178 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3181 case GLSL_TYPE_UINT64
:
3182 gl_type
= GL_UNSIGNED_INT64_ARB
;
3183 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3184 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3187 case GLSL_TYPE_UINT
:
3188 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3189 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3190 if (native_integers
)
3191 values
[i
].u
= ir
->value
.u
[i
];
3193 values
[i
].f
= ir
->value
.u
[i
];
3197 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3198 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3199 if (native_integers
)
3200 values
[i
].i
= ir
->value
.i
[i
];
3202 values
[i
].f
= ir
->value
.i
[i
];
3205 case GLSL_TYPE_BOOL
:
3206 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3207 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3208 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3212 assert(!"Non-float/uint/int/bool constant");
3215 this->result
= st_src_reg(file
, -1, ir
->type
);
3216 this->result
.index
= add_constant(file
,
3218 ir
->type
->vector_elements
,
3220 &this->result
.swizzle
);
3224 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3226 exec_node
*param
= ir
->actual_parameters
.get_head();
3227 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3228 ir_variable
*location
= deref
->variable_referenced();
3231 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3233 /* Calculate the surface offset */
3235 unsigned array_size
= 0, base
= 0;
3238 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3240 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3241 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3242 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3243 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3244 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3246 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3249 ir
->return_deref
->accept(this);
3250 st_dst_reg
dst(this->result
);
3251 dst
.writemask
= WRITEMASK_X
;
3253 glsl_to_tgsi_instruction
*inst
;
3255 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3256 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3257 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3258 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3259 st_src_reg_for_int(1));
3260 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3261 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3262 st_src_reg_for_int(-1));
3263 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3265 param
= param
->get_next();
3266 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3269 st_src_reg data
= this->result
, data2
= undef_src
;
3271 switch (ir
->callee
->intrinsic_id
) {
3272 case ir_intrinsic_atomic_counter_add
:
3273 opcode
= TGSI_OPCODE_ATOMUADD
;
3275 case ir_intrinsic_atomic_counter_min
:
3276 opcode
= TGSI_OPCODE_ATOMIMIN
;
3278 case ir_intrinsic_atomic_counter_max
:
3279 opcode
= TGSI_OPCODE_ATOMIMAX
;
3281 case ir_intrinsic_atomic_counter_and
:
3282 opcode
= TGSI_OPCODE_ATOMAND
;
3284 case ir_intrinsic_atomic_counter_or
:
3285 opcode
= TGSI_OPCODE_ATOMOR
;
3287 case ir_intrinsic_atomic_counter_xor
:
3288 opcode
= TGSI_OPCODE_ATOMXOR
;
3290 case ir_intrinsic_atomic_counter_exchange
:
3291 opcode
= TGSI_OPCODE_ATOMXCHG
;
3293 case ir_intrinsic_atomic_counter_comp_swap
: {
3294 opcode
= TGSI_OPCODE_ATOMCAS
;
3295 param
= param
->get_next();
3296 val
= ((ir_instruction
*)param
)->as_rvalue();
3298 data2
= this->result
;
3302 assert(!"Unexpected intrinsic");
3306 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3309 inst
->resource
= buffer
;
3313 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3315 exec_node
*param
= ir
->actual_parameters
.get_head();
3317 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3319 param
= param
->get_next();
3320 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3322 ir_constant
*const_block
= block
->as_constant();
3326 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3327 (const_block
? const_block
->value
.u
[0] : 0),
3331 block
->accept(this);
3332 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3333 *buffer
.reladdr
= this->result
;
3334 emit_arl(ir
, sampler_reladdr
, this->result
);
3337 /* Calculate the surface offset */
3338 offset
->accept(this);
3339 st_src_reg off
= this->result
;
3341 st_dst_reg dst
= undef_dst
;
3342 if (ir
->return_deref
) {
3343 ir
->return_deref
->accept(this);
3344 dst
= st_dst_reg(this->result
);
3345 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3348 glsl_to_tgsi_instruction
*inst
;
3350 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3351 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3352 if (dst
.type
== GLSL_TYPE_BOOL
)
3353 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3354 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3355 param
= param
->get_next();
3356 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3359 param
= param
->get_next();
3360 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3362 dst
.writemask
= write_mask
->value
.u
[0];
3364 dst
.type
= this->result
.type
;
3365 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3367 param
= param
->get_next();
3368 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3371 st_src_reg data
= this->result
, data2
= undef_src
;
3373 switch (ir
->callee
->intrinsic_id
) {
3374 case ir_intrinsic_ssbo_atomic_add
:
3375 opcode
= TGSI_OPCODE_ATOMUADD
;
3377 case ir_intrinsic_ssbo_atomic_min
:
3378 opcode
= TGSI_OPCODE_ATOMIMIN
;
3380 case ir_intrinsic_ssbo_atomic_max
:
3381 opcode
= TGSI_OPCODE_ATOMIMAX
;
3383 case ir_intrinsic_ssbo_atomic_and
:
3384 opcode
= TGSI_OPCODE_ATOMAND
;
3386 case ir_intrinsic_ssbo_atomic_or
:
3387 opcode
= TGSI_OPCODE_ATOMOR
;
3389 case ir_intrinsic_ssbo_atomic_xor
:
3390 opcode
= TGSI_OPCODE_ATOMXOR
;
3392 case ir_intrinsic_ssbo_atomic_exchange
:
3393 opcode
= TGSI_OPCODE_ATOMXCHG
;
3395 case ir_intrinsic_ssbo_atomic_comp_swap
:
3396 opcode
= TGSI_OPCODE_ATOMCAS
;
3397 param
= param
->get_next();
3398 val
= ((ir_instruction
*)param
)->as_rvalue();
3400 data2
= this->result
;
3403 assert(!"Unexpected intrinsic");
3407 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3410 param
= param
->get_next();
3411 ir_constant
*access
= NULL
;
3412 if (!param
->is_tail_sentinel()) {
3413 access
= ((ir_instruction
*)param
)->as_constant();
3417 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3421 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3423 switch (ir
->callee
->intrinsic_id
) {
3424 case ir_intrinsic_memory_barrier
:
3425 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3426 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3427 TGSI_MEMBAR_ATOMIC_BUFFER
|
3428 TGSI_MEMBAR_SHADER_IMAGE
|
3429 TGSI_MEMBAR_SHARED
));
3431 case ir_intrinsic_memory_barrier_atomic_counter
:
3432 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3433 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3435 case ir_intrinsic_memory_barrier_buffer
:
3436 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3437 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3439 case ir_intrinsic_memory_barrier_image
:
3440 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3441 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3443 case ir_intrinsic_memory_barrier_shared
:
3444 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3445 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3447 case ir_intrinsic_group_memory_barrier
:
3448 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3449 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3450 TGSI_MEMBAR_ATOMIC_BUFFER
|
3451 TGSI_MEMBAR_SHADER_IMAGE
|
3452 TGSI_MEMBAR_SHARED
|
3453 TGSI_MEMBAR_THREAD_GROUP
));
3456 assert(!"Unexpected memory barrier intrinsic");
3461 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3463 exec_node
*param
= ir
->actual_parameters
.get_head();
3465 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3467 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3469 /* Calculate the surface offset */
3470 offset
->accept(this);
3471 st_src_reg off
= this->result
;
3473 st_dst_reg dst
= undef_dst
;
3474 if (ir
->return_deref
) {
3475 ir
->return_deref
->accept(this);
3476 dst
= st_dst_reg(this->result
);
3477 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3480 glsl_to_tgsi_instruction
*inst
;
3482 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3483 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3484 inst
->resource
= buffer
;
3485 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3486 param
= param
->get_next();
3487 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3490 param
= param
->get_next();
3491 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3493 dst
.writemask
= write_mask
->value
.u
[0];
3495 dst
.type
= this->result
.type
;
3496 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3497 inst
->resource
= buffer
;
3499 param
= param
->get_next();
3500 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3503 st_src_reg data
= this->result
, data2
= undef_src
;
3505 switch (ir
->callee
->intrinsic_id
) {
3506 case ir_intrinsic_shared_atomic_add
:
3507 opcode
= TGSI_OPCODE_ATOMUADD
;
3509 case ir_intrinsic_shared_atomic_min
:
3510 opcode
= TGSI_OPCODE_ATOMIMIN
;
3512 case ir_intrinsic_shared_atomic_max
:
3513 opcode
= TGSI_OPCODE_ATOMIMAX
;
3515 case ir_intrinsic_shared_atomic_and
:
3516 opcode
= TGSI_OPCODE_ATOMAND
;
3518 case ir_intrinsic_shared_atomic_or
:
3519 opcode
= TGSI_OPCODE_ATOMOR
;
3521 case ir_intrinsic_shared_atomic_xor
:
3522 opcode
= TGSI_OPCODE_ATOMXOR
;
3524 case ir_intrinsic_shared_atomic_exchange
:
3525 opcode
= TGSI_OPCODE_ATOMXCHG
;
3527 case ir_intrinsic_shared_atomic_comp_swap
:
3528 opcode
= TGSI_OPCODE_ATOMCAS
;
3529 param
= param
->get_next();
3530 val
= ((ir_instruction
*)param
)->as_rvalue();
3532 data2
= this->result
;
3535 assert(!"Unexpected intrinsic");
3539 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3540 inst
->resource
= buffer
;
3545 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3546 bool *memory_coherent
, bool *memory_volatile
,
3547 bool *memory_restrict
, unsigned *image_format
)
3550 switch (ir
->ir_type
) {
3551 case ir_type_dereference_record
: {
3552 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3553 const glsl_type
*struct_type
= deref_record
->record
->type
;
3554 int fild_idx
= deref_record
->field_idx
;
3556 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3558 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3560 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3562 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3564 struct_type
->fields
.structure
[fild_idx
].image_format
;
3568 case ir_type_dereference_array
: {
3569 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3570 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3571 memory_coherent
, memory_volatile
, memory_restrict
,
3576 case ir_type_dereference_variable
: {
3577 ir_variable
*var
= ir
->variable_referenced();
3579 *type
= var
->type
->without_array();
3580 *memory_coherent
= var
->data
.memory_coherent
;
3581 *memory_volatile
= var
->data
.memory_volatile
;
3582 *memory_restrict
= var
->data
.memory_restrict
;
3583 *image_format
= var
->data
.image_format
;
3593 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3595 exec_node
*param
= ir
->actual_parameters
.get_head();
3597 ir_dereference
*img
= (ir_dereference
*)param
;
3598 const ir_variable
*imgvar
= img
->variable_referenced();
3599 unsigned sampler_array_size
= 1, sampler_base
= 0;
3600 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3601 unsigned image_format
= 0;
3602 const glsl_type
*type
= NULL
;
3604 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3605 &memory_restrict
, &image_format
);
3608 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3610 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3611 &index
, &reladdr
, !imgvar
->contains_bindless());
3613 image
.index
= index
;
3614 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3615 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3616 *image
.reladdr
= reladdr
;
3617 emit_arl(ir
, sampler_reladdr
, reladdr
);
3620 st_dst_reg dst
= undef_dst
;
3621 if (ir
->return_deref
) {
3622 ir
->return_deref
->accept(this);
3623 dst
= st_dst_reg(this->result
);
3624 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3627 glsl_to_tgsi_instruction
*inst
;
3629 st_src_reg bindless
;
3630 if (imgvar
->contains_bindless()) {
3632 bindless
= this->result
;
3635 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3636 dst
.writemask
= WRITEMASK_XYZ
;
3637 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3638 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3639 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3640 st_dst_reg dstres
= st_dst_reg(res
);
3641 dstres
.writemask
= WRITEMASK_W
;
3642 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3643 res
.swizzle
= SWIZZLE_WWWW
;
3644 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3646 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3648 st_dst_reg coord_dst
;
3649 coord
= get_temp(glsl_type::ivec4_type
);
3650 coord_dst
= st_dst_reg(coord
);
3651 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3652 param
= param
->get_next();
3653 ((ir_dereference
*)param
)->accept(this);
3654 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3655 coord
.swizzle
= SWIZZLE_XXXX
;
3656 switch (type
->coordinate_components()) {
3657 case 4: assert(!"unexpected coord count");
3659 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3661 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3664 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3665 param
= param
->get_next();
3666 ((ir_dereference
*)param
)->accept(this);
3667 st_src_reg sample
= this->result
;
3668 sample
.swizzle
= SWIZZLE_XXXX
;
3669 coord_dst
.writemask
= WRITEMASK_W
;
3670 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3671 coord
.swizzle
|= SWIZZLE_W
<< 9;
3674 param
= param
->get_next();
3675 if (!param
->is_tail_sentinel()) {
3676 ((ir_dereference
*)param
)->accept(this);
3677 arg1
= this->result
;
3678 param
= param
->get_next();
3681 if (!param
->is_tail_sentinel()) {
3682 ((ir_dereference
*)param
)->accept(this);
3683 arg2
= this->result
;
3684 param
= param
->get_next();
3687 assert(param
->is_tail_sentinel());
3690 switch (ir
->callee
->intrinsic_id
) {
3691 case ir_intrinsic_image_load
:
3692 opcode
= TGSI_OPCODE_LOAD
;
3694 case ir_intrinsic_image_store
:
3695 opcode
= TGSI_OPCODE_STORE
;
3697 case ir_intrinsic_image_atomic_add
:
3698 opcode
= TGSI_OPCODE_ATOMUADD
;
3700 case ir_intrinsic_image_atomic_min
:
3701 opcode
= TGSI_OPCODE_ATOMIMIN
;
3703 case ir_intrinsic_image_atomic_max
:
3704 opcode
= TGSI_OPCODE_ATOMIMAX
;
3706 case ir_intrinsic_image_atomic_and
:
3707 opcode
= TGSI_OPCODE_ATOMAND
;
3709 case ir_intrinsic_image_atomic_or
:
3710 opcode
= TGSI_OPCODE_ATOMOR
;
3712 case ir_intrinsic_image_atomic_xor
:
3713 opcode
= TGSI_OPCODE_ATOMXOR
;
3715 case ir_intrinsic_image_atomic_exchange
:
3716 opcode
= TGSI_OPCODE_ATOMXCHG
;
3718 case ir_intrinsic_image_atomic_comp_swap
:
3719 opcode
= TGSI_OPCODE_ATOMCAS
;
3722 assert(!"Unexpected intrinsic");
3726 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3727 if (opcode
== TGSI_OPCODE_STORE
)
3728 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3731 if (imgvar
->contains_bindless()) {
3732 inst
->resource
= bindless
;
3733 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3734 SWIZZLE_X
, SWIZZLE_Y
);
3736 inst
->resource
= image
;
3737 inst
->sampler_array_size
= sampler_array_size
;
3738 inst
->sampler_base
= sampler_base
;
3741 inst
->tex_target
= type
->sampler_index();
3742 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3743 _mesa_get_shader_image_format(image_format
));
3745 if (memory_coherent
)
3746 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3747 if (memory_restrict
)
3748 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3749 if (memory_volatile
)
3750 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3754 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, unsigned op
)
3756 ir
->return_deref
->accept(this);
3757 st_dst_reg dst
= st_dst_reg(this->result
);
3759 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3761 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3762 unsigned num_src
= 0;
3763 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3764 assert(num_src
< ARRAY_SIZE(src
));
3766 this->result
.file
= PROGRAM_UNDEFINED
;
3767 param
->accept(this);
3768 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3770 src
[num_src
] = this->result
;
3774 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3778 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3780 ir_function_signature
*sig
= ir
->callee
;
3782 /* Filter out intrinsics */
3783 switch (sig
->intrinsic_id
) {
3784 case ir_intrinsic_atomic_counter_read
:
3785 case ir_intrinsic_atomic_counter_increment
:
3786 case ir_intrinsic_atomic_counter_predecrement
:
3787 case ir_intrinsic_atomic_counter_add
:
3788 case ir_intrinsic_atomic_counter_min
:
3789 case ir_intrinsic_atomic_counter_max
:
3790 case ir_intrinsic_atomic_counter_and
:
3791 case ir_intrinsic_atomic_counter_or
:
3792 case ir_intrinsic_atomic_counter_xor
:
3793 case ir_intrinsic_atomic_counter_exchange
:
3794 case ir_intrinsic_atomic_counter_comp_swap
:
3795 visit_atomic_counter_intrinsic(ir
);
3798 case ir_intrinsic_ssbo_load
:
3799 case ir_intrinsic_ssbo_store
:
3800 case ir_intrinsic_ssbo_atomic_add
:
3801 case ir_intrinsic_ssbo_atomic_min
:
3802 case ir_intrinsic_ssbo_atomic_max
:
3803 case ir_intrinsic_ssbo_atomic_and
:
3804 case ir_intrinsic_ssbo_atomic_or
:
3805 case ir_intrinsic_ssbo_atomic_xor
:
3806 case ir_intrinsic_ssbo_atomic_exchange
:
3807 case ir_intrinsic_ssbo_atomic_comp_swap
:
3808 visit_ssbo_intrinsic(ir
);
3811 case ir_intrinsic_memory_barrier
:
3812 case ir_intrinsic_memory_barrier_atomic_counter
:
3813 case ir_intrinsic_memory_barrier_buffer
:
3814 case ir_intrinsic_memory_barrier_image
:
3815 case ir_intrinsic_memory_barrier_shared
:
3816 case ir_intrinsic_group_memory_barrier
:
3817 visit_membar_intrinsic(ir
);
3820 case ir_intrinsic_shared_load
:
3821 case ir_intrinsic_shared_store
:
3822 case ir_intrinsic_shared_atomic_add
:
3823 case ir_intrinsic_shared_atomic_min
:
3824 case ir_intrinsic_shared_atomic_max
:
3825 case ir_intrinsic_shared_atomic_and
:
3826 case ir_intrinsic_shared_atomic_or
:
3827 case ir_intrinsic_shared_atomic_xor
:
3828 case ir_intrinsic_shared_atomic_exchange
:
3829 case ir_intrinsic_shared_atomic_comp_swap
:
3830 visit_shared_intrinsic(ir
);
3833 case ir_intrinsic_image_load
:
3834 case ir_intrinsic_image_store
:
3835 case ir_intrinsic_image_atomic_add
:
3836 case ir_intrinsic_image_atomic_min
:
3837 case ir_intrinsic_image_atomic_max
:
3838 case ir_intrinsic_image_atomic_and
:
3839 case ir_intrinsic_image_atomic_or
:
3840 case ir_intrinsic_image_atomic_xor
:
3841 case ir_intrinsic_image_atomic_exchange
:
3842 case ir_intrinsic_image_atomic_comp_swap
:
3843 case ir_intrinsic_image_size
:
3844 case ir_intrinsic_image_samples
:
3845 visit_image_intrinsic(ir
);
3848 case ir_intrinsic_shader_clock
:
3849 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
3852 case ir_intrinsic_vote_all
:
3853 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
3855 case ir_intrinsic_vote_any
:
3856 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
3858 case ir_intrinsic_vote_eq
:
3859 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
3861 case ir_intrinsic_ballot
:
3862 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
3864 case ir_intrinsic_read_first_invocation
:
3865 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
3867 case ir_intrinsic_read_invocation
:
3868 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
3871 case ir_intrinsic_invalid
:
3872 case ir_intrinsic_generic_load
:
3873 case ir_intrinsic_generic_store
:
3874 case ir_intrinsic_generic_atomic_add
:
3875 case ir_intrinsic_generic_atomic_and
:
3876 case ir_intrinsic_generic_atomic_or
:
3877 case ir_intrinsic_generic_atomic_xor
:
3878 case ir_intrinsic_generic_atomic_min
:
3879 case ir_intrinsic_generic_atomic_max
:
3880 case ir_intrinsic_generic_atomic_exchange
:
3881 case ir_intrinsic_generic_atomic_comp_swap
:
3882 unreachable("Invalid intrinsic");
3887 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3888 unsigned *array_elements
,
3890 st_src_reg
*indirect
,
3893 switch (tail
->ir_type
) {
3894 case ir_type_dereference_record
: {
3895 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3896 const glsl_type
*struct_type
= deref_record
->record
->type
;
3897 int field_index
= deref_record
->field_idx
;
3899 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3901 assert(field_index
>= 0);
3902 *location
+= struct_type
->record_location_offset(field_index
);
3906 case ir_type_dereference_array
: {
3907 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3909 void *mem_ctx
= ralloc_parent(deref_arr
);
3910 ir_constant
*array_index
=
3911 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
3914 st_src_reg temp_reg
;
3915 st_dst_reg temp_dst
;
3917 temp_reg
= get_temp(glsl_type::uint_type
);
3918 temp_dst
= st_dst_reg(temp_reg
);
3919 temp_dst
.writemask
= 1;
3921 deref_arr
->array_index
->accept(this);
3922 if (*array_elements
!= 1)
3923 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3925 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3927 if (indirect
->file
== PROGRAM_UNDEFINED
)
3928 *indirect
= temp_reg
;
3930 temp_dst
= st_dst_reg(*indirect
);
3931 temp_dst
.writemask
= 1;
3932 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3935 *index
+= array_index
->value
.u
[0] * *array_elements
;
3937 *array_elements
*= deref_arr
->array
->type
->length
;
3939 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3948 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3949 unsigned *array_size
,
3952 st_src_reg
*reladdr
,
3955 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3956 unsigned location
= 0;
3957 ir_variable
*var
= ir
->variable_referenced();
3959 memset(reladdr
, 0, sizeof(*reladdr
));
3960 reladdr
->file
= PROGRAM_UNDEFINED
;
3966 location
= var
->data
.location
;
3967 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
3970 * If we end up with no indirect then adjust the base to the index,
3971 * and set the array size to 1.
3973 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3979 assert(location
!= 0xffffffff);
3980 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3981 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3986 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
3988 if (offset
.reladdr
|| offset
.reladdr2
) {
3989 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
3990 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
3991 tmp_dst
.writemask
= WRITEMASK_XY
;
3992 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4000 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4002 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4003 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4004 st_src_reg levels_src
, reladdr
;
4005 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4006 glsl_to_tgsi_instruction
*inst
= NULL
;
4007 unsigned opcode
= TGSI_OPCODE_NOP
;
4008 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4009 unsigned sampler_array_size
= 1, sampler_base
= 0;
4010 bool is_cube_array
= false, is_cube_shadow
= false;
4011 ir_variable
*var
= ir
->sampler
->variable_referenced();
4014 /* if we are a cube array sampler or a cube shadow */
4015 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4016 is_cube_array
= sampler_type
->sampler_array
;
4017 is_cube_shadow
= sampler_type
->sampler_shadow
;
4020 if (ir
->coordinate
) {
4021 ir
->coordinate
->accept(this);
4023 /* Put our coords in a temp. We'll need to modify them for shadow,
4024 * projection, or LOD, so the only case we'd use it as-is is if
4025 * we're doing plain old texturing. The optimization passes on
4026 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4028 coord
= get_temp(glsl_type::vec4_type
);
4029 coord_dst
= st_dst_reg(coord
);
4030 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4031 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4034 if (ir
->projector
) {
4035 ir
->projector
->accept(this);
4036 projector
= this->result
;
4039 /* Storage for our result. Ideally for an assignment we'd be using
4040 * the actual storage for the result here, instead.
4042 result_src
= get_temp(ir
->type
);
4043 result_dst
= st_dst_reg(result_src
);
4044 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4048 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4050 ir
->offset
->accept(this);
4051 offset
[0] = this->result
;
4055 if (is_cube_array
|| is_cube_shadow
) {
4056 opcode
= TGSI_OPCODE_TXB2
;
4059 opcode
= TGSI_OPCODE_TXB
;
4061 ir
->lod_info
.bias
->accept(this);
4062 lod_info
= this->result
;
4064 ir
->offset
->accept(this);
4065 offset
[0] = this->result
;
4069 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4070 opcode
= TGSI_OPCODE_TEX_LZ
;
4072 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4073 ir
->lod_info
.lod
->accept(this);
4074 lod_info
= this->result
;
4077 ir
->offset
->accept(this);
4078 offset
[0] = this->result
;
4082 opcode
= TGSI_OPCODE_TXD
;
4083 ir
->lod_info
.grad
.dPdx
->accept(this);
4085 ir
->lod_info
.grad
.dPdy
->accept(this);
4088 ir
->offset
->accept(this);
4089 offset
[0] = this->result
;
4093 opcode
= TGSI_OPCODE_TXQ
;
4094 ir
->lod_info
.lod
->accept(this);
4095 lod_info
= this->result
;
4097 case ir_query_levels
:
4098 opcode
= TGSI_OPCODE_TXQ
;
4099 lod_info
= undef_src
;
4100 levels_src
= get_temp(ir
->type
);
4103 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4104 opcode
= TGSI_OPCODE_TXF_LZ
;
4106 opcode
= TGSI_OPCODE_TXF
;
4107 ir
->lod_info
.lod
->accept(this);
4108 lod_info
= this->result
;
4111 ir
->offset
->accept(this);
4112 offset
[0] = this->result
;
4116 opcode
= TGSI_OPCODE_TXF
;
4117 ir
->lod_info
.sample_index
->accept(this);
4118 sample_index
= this->result
;
4121 opcode
= TGSI_OPCODE_TG4
;
4122 ir
->lod_info
.component
->accept(this);
4123 component
= this->result
;
4125 ir
->offset
->accept(this);
4126 if (ir
->offset
->type
->is_array()) {
4127 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4128 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4129 offset
[i
] = this->result
;
4130 offset
[i
].index
+= i
* type_size(elt_type
);
4131 offset
[i
].type
= elt_type
->base_type
;
4132 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4133 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4136 offset
[0] = canonicalize_gather_offset(this->result
);
4141 opcode
= TGSI_OPCODE_LODQ
;
4143 case ir_texture_samples
:
4144 opcode
= TGSI_OPCODE_TXQS
;
4146 case ir_samples_identical
:
4147 unreachable("Unexpected ir_samples_identical opcode");
4150 if (ir
->projector
) {
4151 if (opcode
== TGSI_OPCODE_TEX
) {
4152 /* Slot the projector in as the last component of the coord. */
4153 coord_dst
.writemask
= WRITEMASK_W
;
4154 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4155 coord_dst
.writemask
= WRITEMASK_XYZW
;
4156 opcode
= TGSI_OPCODE_TXP
;
4158 st_src_reg coord_w
= coord
;
4159 coord_w
.swizzle
= SWIZZLE_WWWW
;
4161 /* For the other TEX opcodes there's no projective version
4162 * since the last slot is taken up by LOD info. Do the
4163 * projective divide now.
4165 coord_dst
.writemask
= WRITEMASK_W
;
4166 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4168 /* In the case where we have to project the coordinates "by hand,"
4169 * the shadow comparator value must also be projected.
4171 st_src_reg tmp_src
= coord
;
4172 if (ir
->shadow_comparator
) {
4173 /* Slot the shadow value in as the second to last component of the
4176 ir
->shadow_comparator
->accept(this);
4178 tmp_src
= get_temp(glsl_type::vec4_type
);
4179 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4181 /* Projective division not allowed for array samplers. */
4182 assert(!sampler_type
->sampler_array
);
4184 tmp_dst
.writemask
= WRITEMASK_Z
;
4185 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4187 tmp_dst
.writemask
= WRITEMASK_XY
;
4188 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4191 coord_dst
.writemask
= WRITEMASK_XYZ
;
4192 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4194 coord_dst
.writemask
= WRITEMASK_XYZW
;
4195 coord
.swizzle
= SWIZZLE_XYZW
;
4199 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4200 * comparator was put in the correct place (and projected) by the code,
4201 * above, that handles by-hand projection.
4203 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4204 /* Slot the shadow value in as the second to last component of the
4207 ir
->shadow_comparator
->accept(this);
4209 if (is_cube_array
) {
4210 cube_sc
= get_temp(glsl_type::float_type
);
4211 cube_sc_dst
= st_dst_reg(cube_sc
);
4212 cube_sc_dst
.writemask
= WRITEMASK_X
;
4213 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4214 cube_sc_dst
.writemask
= WRITEMASK_X
;
4217 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4218 sampler_type
->sampler_array
) ||
4219 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4220 coord_dst
.writemask
= WRITEMASK_W
;
4222 coord_dst
.writemask
= WRITEMASK_Z
;
4224 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4225 coord_dst
.writemask
= WRITEMASK_XYZW
;
4229 if (ir
->op
== ir_txf_ms
) {
4230 coord_dst
.writemask
= WRITEMASK_W
;
4231 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4232 coord_dst
.writemask
= WRITEMASK_XYZW
;
4233 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4234 opcode
== TGSI_OPCODE_TXF
) {
4235 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4236 coord_dst
.writemask
= WRITEMASK_W
;
4237 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4238 coord_dst
.writemask
= WRITEMASK_XYZW
;
4241 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4244 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4245 &index
, &reladdr
, !var
->contains_bindless());
4247 sampler
.index
= index
;
4248 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4249 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4250 *sampler
.reladdr
= reladdr
;
4251 emit_arl(ir
, sampler_reladdr
, reladdr
);
4254 st_src_reg bindless
;
4255 if (var
->contains_bindless()) {
4256 ir
->sampler
->accept(this);
4257 bindless
= this->result
;
4260 if (opcode
== TGSI_OPCODE_TXD
)
4261 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4262 else if (opcode
== TGSI_OPCODE_TXQ
) {
4263 if (ir
->op
== ir_query_levels
) {
4264 /* the level is stored in W */
4265 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4266 result_dst
.writemask
= WRITEMASK_X
;
4267 levels_src
.swizzle
= SWIZZLE_WWWW
;
4268 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4270 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4271 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4272 inst
= emit_asm(ir
, opcode
, result_dst
);
4273 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4274 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4275 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4276 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4277 } else if (opcode
== TGSI_OPCODE_TG4
) {
4278 if (is_cube_array
&& ir
->shadow_comparator
) {
4279 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4281 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4284 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4286 if (ir
->shadow_comparator
)
4287 inst
->tex_shadow
= GL_TRUE
;
4289 if (var
->contains_bindless()) {
4290 inst
->resource
= bindless
;
4291 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4292 SWIZZLE_X
, SWIZZLE_Y
);
4294 inst
->resource
= sampler
;
4295 inst
->sampler_array_size
= sampler_array_size
;
4296 inst
->sampler_base
= sampler_base
;
4300 if (!inst
->tex_offsets
)
4301 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4303 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4304 inst
->tex_offsets
[i
] = offset
[i
];
4305 inst
->tex_offset_num_offset
= i
;
4308 inst
->tex_target
= sampler_type
->sampler_index();
4309 inst
->tex_type
= ir
->type
->base_type
;
4311 this->result
= result_src
;
4315 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4317 assert(!ir
->get_value());
4319 emit_asm(ir
, TGSI_OPCODE_RET
);
4323 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4325 if (ir
->condition
) {
4326 ir
->condition
->accept(this);
4327 st_src_reg condition
= this->result
;
4329 /* Convert the bool condition to a float so we can negate. */
4330 if (native_integers
) {
4331 st_src_reg temp
= get_temp(ir
->condition
->type
);
4332 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4333 condition
, st_src_reg_for_float(1.0));
4337 condition
.negate
= ~condition
.negate
;
4338 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4340 /* unconditional kil */
4341 emit_asm(ir
, TGSI_OPCODE_KILL
);
4346 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4349 glsl_to_tgsi_instruction
*if_inst
;
4351 ir
->condition
->accept(this);
4352 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4354 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4356 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4358 this->instructions
.push_tail(if_inst
);
4360 visit_exec_list(&ir
->then_instructions
, this);
4362 if (!ir
->else_instructions
.is_empty()) {
4363 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4364 visit_exec_list(&ir
->else_instructions
, this);
4367 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4372 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4374 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4376 ir
->stream
->accept(this);
4377 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4381 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4383 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4385 ir
->stream
->accept(this);
4386 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4390 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4392 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4393 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4395 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4398 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4400 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4402 result
.file
= PROGRAM_UNDEFINED
;
4409 num_input_arrays
= 0;
4410 num_output_arrays
= 0;
4412 num_address_regs
= 0;
4415 indirect_addr_consts
= false;
4416 wpos_transform_const
= -1;
4417 native_integers
= false;
4418 mem_ctx
= ralloc_context(NULL
);
4422 shader_program
= NULL
;
4427 use_shared_memory
= false;
4428 has_tex_txf_lz
= false;
4432 static void var_destroy(struct hash_entry
*entry
)
4434 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4439 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4441 _mesa_hash_table_destroy(variables
, var_destroy
);
4443 ralloc_free(mem_ctx
);
4446 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4453 * Count resources used by the given gpu program (number of texture
4457 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4459 v
->samplers_used
= 0;
4461 prog
->info
.textures_used_by_txf
= 0;
4463 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4464 if (inst
->info
->is_tex
) {
4465 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4466 unsigned idx
= inst
->sampler_base
+ i
;
4467 v
->samplers_used
|= 1u << idx
;
4469 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4470 v
->sampler_types
[idx
] = inst
->tex_type
;
4471 v
->sampler_targets
[idx
] =
4472 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4474 if (inst
->op
== TGSI_OPCODE_TXF
|| inst
->op
== TGSI_OPCODE_TXF_LZ
) {
4475 prog
->info
.textures_used_by_txf
|= 1u << idx
;
4480 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4481 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4483 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4484 is_resource_instruction(inst
->op
) ||
4485 inst
->op
== TGSI_OPCODE_STORE
)) {
4486 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4487 v
->use_shared_memory
= true;
4488 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4489 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4490 unsigned idx
= inst
->sampler_base
+ i
;
4491 v
->images_used
|= 1 << idx
;
4492 v
->image_targets
[idx
] =
4493 st_translate_texture_target(inst
->tex_target
, false);
4494 v
->image_formats
[idx
] = inst
->image_format
;
4499 prog
->SamplersUsed
= v
->samplers_used
;
4501 if (v
->shader_program
!= NULL
)
4502 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4506 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4507 * are read from the given src in this instruction
4510 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4512 int read_mask
= 0, comp
;
4514 /* Now, given the src swizzle and the written channels, find which
4515 * components are actually read
4517 for (comp
= 0; comp
< 4; ++comp
) {
4518 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4520 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4521 read_mask
|= 1 << coord
;
4528 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4529 * instruction is the first instruction to write to register T0. There are
4530 * several lowering passes done in GLSL IR (e.g. branches and
4531 * relative addressing) that create a large number of conditional assignments
4532 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4534 * Here is why this conversion is safe:
4535 * CMP T0, T1 T2 T0 can be expanded to:
4541 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4542 * as the original program. If (T1 < 0.0) evaluates to false, executing
4543 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4544 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4545 * because any instruction that was going to read from T0 after this was going
4546 * to read a garbage value anyway.
4549 glsl_to_tgsi_visitor::simplify_cmp(void)
4551 int tempWritesSize
= 0;
4552 unsigned *tempWrites
= NULL
;
4553 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4555 memset(outputWrites
, 0, sizeof(outputWrites
));
4557 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4558 unsigned prevWriteMask
= 0;
4560 /* Give up if we encounter relative addressing or flow control. */
4561 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4562 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4563 inst
->info
->is_branch
||
4564 inst
->op
== TGSI_OPCODE_CONT
||
4565 inst
->op
== TGSI_OPCODE_END
||
4566 inst
->op
== TGSI_OPCODE_RET
) {
4570 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4571 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4572 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4573 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4574 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4575 if (inst
->dst
[0].index
>= tempWritesSize
) {
4576 const int inc
= 4096;
4578 tempWrites
= (unsigned*)
4580 (tempWritesSize
+ inc
) * sizeof(unsigned));
4584 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4585 tempWritesSize
+= inc
;
4588 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4589 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4593 /* For a CMP to be considered a conditional write, the destination
4594 * register and source register two must be the same. */
4595 if (inst
->op
== TGSI_OPCODE_CMP
4596 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4597 && inst
->src
[2].file
== inst
->dst
[0].file
4598 && inst
->src
[2].index
== inst
->dst
[0].index
4599 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4601 inst
->op
= TGSI_OPCODE_MOV
;
4602 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4603 inst
->src
[0] = inst
->src
[1];
4611 rename_temp_handle_src(struct rename_reg_pair
*renames
,
4612 struct st_src_reg
*src
)
4614 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4615 int old_idx
= src
->index
;
4616 if (renames
[old_idx
].valid
)
4617 src
->index
= renames
[old_idx
].new_reg
;
4621 /* Replaces all references to a temporary register index with another index. */
4623 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4625 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4627 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4628 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4629 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4630 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4633 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4634 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4635 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4636 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4639 rename_temp_handle_src(renames
, &inst
->resource
);
4640 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4641 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4643 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4644 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4645 int old_idx
= inst
->dst
[j
].index
;
4646 if (renames
[old_idx
].valid
)
4647 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4649 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4650 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4656 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4658 int depth
= 0; /* loop depth */
4659 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4662 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4663 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4664 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4665 if (first_writes
[inst
->dst
[j
].index
] == -1)
4666 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4670 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4673 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4683 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4685 int depth
= 0; /* loop depth */
4686 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4689 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4690 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4691 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4692 if (first_reads
[inst
->src
[j
].index
] == -1)
4693 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4696 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4697 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4698 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4699 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4702 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4705 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4715 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4717 int depth
= 0; /* loop depth */
4718 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4721 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4722 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4723 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4724 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4726 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4727 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4728 if (first_writes
[inst
->dst
[j
].index
] == -1)
4729 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4730 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4733 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4734 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4735 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4737 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4740 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4743 for (k
= 0; k
< this->next_temp
; k
++) {
4744 if (last_reads
[k
] == -2) {
4756 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4758 int depth
= 0; /* loop depth */
4762 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4763 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4764 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4765 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4768 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4770 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4772 for (k
= 0; k
< this->next_temp
; k
++) {
4773 if (last_writes
[k
] == -2) {
4784 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4785 * channels for copy propagation and updates following instructions to
4786 * use the original versions.
4788 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4789 * will occur. As an example, a TXP production before this pass:
4791 * 0: MOV TEMP[1], INPUT[4].xyyy;
4792 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4793 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4797 * 0: MOV TEMP[1], INPUT[4].xyyy;
4798 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4799 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4801 * which allows for dead code elimination on TEMP[1]'s writes.
4804 glsl_to_tgsi_visitor::copy_propagate(void)
4806 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4807 glsl_to_tgsi_instruction
*,
4808 this->next_temp
* 4);
4809 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4812 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4813 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4814 || inst
->dst
[0].index
< this->next_temp
);
4816 /* First, do any copy propagation possible into the src regs. */
4817 for (int r
= 0; r
< 3; r
++) {
4818 glsl_to_tgsi_instruction
*first
= NULL
;
4820 int acp_base
= inst
->src
[r
].index
* 4;
4822 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4823 inst
->src
[r
].reladdr
||
4824 inst
->src
[r
].reladdr2
)
4827 /* See if we can find entries in the ACP consisting of MOVs
4828 * from the same src register for all the swizzled channels
4829 * of this src register reference.
4831 for (int i
= 0; i
< 4; i
++) {
4832 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4833 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4840 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4845 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4846 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4847 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4848 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4856 /* We've now validated that we can copy-propagate to
4857 * replace this src register reference. Do it.
4859 inst
->src
[r
].file
= first
->src
[0].file
;
4860 inst
->src
[r
].index
= first
->src
[0].index
;
4861 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4862 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4863 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4864 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4867 for (int i
= 0; i
< 4; i
++) {
4868 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4869 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4870 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4872 inst
->src
[r
].swizzle
= swizzle
;
4877 case TGSI_OPCODE_BGNLOOP
:
4878 case TGSI_OPCODE_ENDLOOP
:
4879 /* End of a basic block, clear the ACP entirely. */
4880 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4883 case TGSI_OPCODE_IF
:
4884 case TGSI_OPCODE_UIF
:
4888 case TGSI_OPCODE_ENDIF
:
4889 case TGSI_OPCODE_ELSE
:
4890 /* Clear all channels written inside the block from the ACP, but
4891 * leaving those that were not touched.
4893 for (int r
= 0; r
< this->next_temp
; r
++) {
4894 for (int c
= 0; c
< 4; c
++) {
4895 if (!acp
[4 * r
+ c
])
4898 if (acp_level
[4 * r
+ c
] >= level
)
4899 acp
[4 * r
+ c
] = NULL
;
4902 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4907 /* Continuing the block, clear any written channels from
4910 for (int d
= 0; d
< 2; d
++) {
4911 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4912 /* Any temporary might be written, so no copy propagation
4913 * across this instruction.
4915 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4916 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4917 inst
->dst
[d
].reladdr
) {
4918 /* Any output might be written, so no copy propagation
4919 * from outputs across this instruction.
4921 for (int r
= 0; r
< this->next_temp
; r
++) {
4922 for (int c
= 0; c
< 4; c
++) {
4923 if (!acp
[4 * r
+ c
])
4926 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4927 acp
[4 * r
+ c
] = NULL
;
4930 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4931 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4932 /* Clear where it's used as dst. */
4933 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4934 for (int c
= 0; c
< 4; c
++) {
4935 if (inst
->dst
[d
].writemask
& (1 << c
))
4936 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4940 /* Clear where it's used as src. */
4941 for (int r
= 0; r
< this->next_temp
; r
++) {
4942 for (int c
= 0; c
< 4; c
++) {
4943 if (!acp
[4 * r
+ c
])
4946 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4948 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4949 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4950 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4951 acp
[4 * r
+ c
] = NULL
;
4960 /* If this is a copy, add it to the ACP. */
4961 if (inst
->op
== TGSI_OPCODE_MOV
&&
4962 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4963 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4964 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4965 !inst
->dst
[0].reladdr
&&
4966 !inst
->dst
[0].reladdr2
&&
4968 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4969 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
4970 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
4971 !inst
->src
[0].reladdr
&&
4972 !inst
->src
[0].reladdr2
&&
4973 !inst
->src
[0].negate
&&
4974 !inst
->src
[0].abs
) {
4975 for (int i
= 0; i
< 4; i
++) {
4976 if (inst
->dst
[0].writemask
& (1 << i
)) {
4977 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4978 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4984 ralloc_free(acp_level
);
4989 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
4991 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
4992 /* Clear where it's used as src. */
4993 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
4994 writes
[4 * reladdr
->index
+ swz
] = NULL
;
4999 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5002 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5003 * will occur. As an example, a TXP production after copy propagation but
5006 * 0: MOV TEMP[1], INPUT[4].xyyy;
5007 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5008 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5010 * and after this pass:
5012 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5015 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5017 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5018 glsl_to_tgsi_instruction
*,
5019 this->next_temp
* 4);
5020 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5024 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5025 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5026 || inst
->dst
[0].index
< this->next_temp
);
5029 case TGSI_OPCODE_BGNLOOP
:
5030 case TGSI_OPCODE_ENDLOOP
:
5031 case TGSI_OPCODE_CONT
:
5032 case TGSI_OPCODE_BRK
:
5033 /* End of a basic block, clear the write array entirely.
5035 * This keeps us from killing dead code when the writes are
5036 * on either side of a loop, even when the register isn't touched
5037 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5038 * dead code of this type, so it shouldn't make a difference as long as
5039 * the dead code elimination pass in the GLSL compiler does its job.
5041 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5044 case TGSI_OPCODE_ENDIF
:
5045 case TGSI_OPCODE_ELSE
:
5046 /* Promote the recorded level of all channels written inside the
5047 * preceding if or else block to the level above the if/else block.
5049 for (int r
= 0; r
< this->next_temp
; r
++) {
5050 for (int c
= 0; c
< 4; c
++) {
5051 if (!writes
[4 * r
+ c
])
5054 if (write_level
[4 * r
+ c
] == level
)
5055 write_level
[4 * r
+ c
] = level
-1;
5058 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5062 case TGSI_OPCODE_IF
:
5063 case TGSI_OPCODE_UIF
:
5065 /* fallthrough to default case to mark the condition as read */
5067 /* Continuing the block, clear any channels from the write array that
5068 * are read by this instruction.
5070 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5071 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5072 /* Any temporary might be read, so no dead code elimination
5073 * across this instruction.
5075 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5076 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5077 /* Clear where it's used as src. */
5078 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5079 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5080 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5081 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5083 for (int c
= 0; c
< 4; c
++) {
5084 if (src_chans
& (1 << c
))
5085 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5088 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5089 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5091 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5092 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5093 /* Any temporary might be read, so no dead code elimination
5094 * across this instruction.
5096 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5097 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5098 /* Clear where it's used as src. */
5099 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5100 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5101 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5102 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5104 for (int c
= 0; c
< 4; c
++) {
5105 if (src_chans
& (1 << c
))
5106 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5109 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5110 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5113 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5116 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5117 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5118 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5119 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5121 for (int c
= 0; c
< 4; c
++) {
5122 if (src_chans
& (1 << c
))
5123 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5126 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5127 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5129 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5130 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5131 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5136 /* If this instruction writes to a temporary, add it to the write array.
5137 * If there is already an instruction in the write array for one or more
5138 * of the channels, flag that channel write as dead.
5140 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5141 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5142 !inst
->dst
[i
].reladdr
) {
5143 for (int c
= 0; c
< 4; c
++) {
5144 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5145 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5146 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5149 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5151 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5152 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5159 /* Anything still in the write array at this point is dead code. */
5160 for (int r
= 0; r
< this->next_temp
; r
++) {
5161 for (int c
= 0; c
< 4; c
++) {
5162 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5164 inst
->dead_mask
|= (1 << c
);
5168 /* Now actually remove the instructions that are completely dead and update
5169 * the writemask of other instructions with dead channels.
5171 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5172 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5174 /* No amount of dead masks should remove memory stores */
5175 if (inst
->info
->is_store
)
5178 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5183 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5184 if (inst
->dead_mask
== WRITEMASK_XY
||
5185 inst
->dead_mask
== WRITEMASK_ZW
)
5186 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5188 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5192 ralloc_free(write_level
);
5193 ralloc_free(writes
);
5198 /* merge DFRACEXP instructions into one. */
5200 glsl_to_tgsi_visitor::merge_two_dsts(void)
5202 /* We never delete inst, but we may delete its successor. */
5203 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5204 glsl_to_tgsi_instruction
*inst2
;
5207 if (num_inst_dst_regs(inst
) != 2)
5210 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5211 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5214 assert(inst
->dst
[0].file
!= PROGRAM_UNDEFINED
||
5215 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
);
5217 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
)
5222 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5224 if (inst
->op
== inst2
->op
&&
5225 inst2
->dst
[defined
].file
== PROGRAM_UNDEFINED
&&
5226 inst
->src
[0].file
== inst2
->src
[0].file
&&
5227 inst
->src
[0].index
== inst2
->src
[0].index
&&
5228 inst
->src
[0].type
== inst2
->src
[0].type
&&
5229 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5231 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5235 /* Undefined destinations are not allowed, substitute with an unused
5236 * temporary register.
5238 st_src_reg tmp
= get_temp(glsl_type::vec4_type
);
5239 inst
->dst
[defined
^ 1] = st_dst_reg(tmp
);
5240 inst
->dst
[defined
^ 1].writemask
= 0;
5244 inst
->dst
[defined
^ 1] = inst2
->dst
[defined
^ 1];
5250 /* Merges temporary registers together where possible to reduce the number of
5251 * registers needed to run a program.
5253 * Produces optimal code only after copy propagation and dead code elimination
5256 glsl_to_tgsi_visitor::merge_registers(void)
5259 struct lifetime
*lifetimes
=
5260 rzalloc_array(mem_ctx
, struct lifetime
, this->next_temp
);
5262 if (get_temp_registers_required_lifetimes(mem_ctx
, &this->instructions
,
5263 this->next_temp
, lifetimes
)) {
5264 struct rename_reg_pair
*renames
=
5265 rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5266 get_temp_registers_remapping(mem_ctx
, this->next_temp
, lifetimes
, renames
);
5267 rename_temp_registers(renames
);
5268 ralloc_free(renames
);
5271 ralloc_free(lifetimes
);
5274 /* Reassign indices to temporary registers by reusing unused indices created
5275 * by optimization passes. */
5277 glsl_to_tgsi_visitor::renumber_registers(void)
5281 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5282 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5284 for (i
= 0; i
< this->next_temp
; i
++) {
5285 first_writes
[i
] = -1;
5287 get_first_temp_write(first_writes
);
5289 for (i
= 0; i
< this->next_temp
; i
++) {
5290 if (first_writes
[i
] < 0) continue;
5291 if (i
!= new_index
) {
5292 renames
[i
].new_reg
= new_index
;
5293 renames
[i
].valid
= true;
5298 rename_temp_registers(renames
);
5299 this->next_temp
= new_index
;
5300 ralloc_free(renames
);
5301 ralloc_free(first_writes
);
5304 /* ------------------------- TGSI conversion stuff -------------------------- */
5307 * Intermediate state used during shader translation.
5309 struct st_translate
{
5310 struct ureg_program
*ureg
;
5312 unsigned temps_size
;
5313 struct ureg_dst
*temps
;
5315 struct ureg_dst
*arrays
;
5316 unsigned num_temp_arrays
;
5317 struct ureg_src
*constants
;
5319 struct ureg_src
*immediates
;
5321 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5322 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5323 struct ureg_dst address
[3];
5324 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5325 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5326 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5327 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5328 struct ureg_src shared_memory
;
5329 unsigned *array_sizes
;
5330 struct inout_decl
*input_decls
;
5331 unsigned num_input_decls
;
5332 struct inout_decl
*output_decls
;
5333 unsigned num_output_decls
;
5335 const ubyte
*inputMapping
;
5336 const ubyte
*outputMapping
;
5338 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5342 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5344 _mesa_sysval_to_semantic(unsigned sysval
)
5348 case SYSTEM_VALUE_VERTEX_ID
:
5349 return TGSI_SEMANTIC_VERTEXID
;
5350 case SYSTEM_VALUE_INSTANCE_ID
:
5351 return TGSI_SEMANTIC_INSTANCEID
;
5352 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5353 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5354 case SYSTEM_VALUE_BASE_VERTEX
:
5355 return TGSI_SEMANTIC_BASEVERTEX
;
5356 case SYSTEM_VALUE_BASE_INSTANCE
:
5357 return TGSI_SEMANTIC_BASEINSTANCE
;
5358 case SYSTEM_VALUE_DRAW_ID
:
5359 return TGSI_SEMANTIC_DRAWID
;
5361 /* Geometry shader */
5362 case SYSTEM_VALUE_INVOCATION_ID
:
5363 return TGSI_SEMANTIC_INVOCATIONID
;
5365 /* Fragment shader */
5366 case SYSTEM_VALUE_FRAG_COORD
:
5367 return TGSI_SEMANTIC_POSITION
;
5368 case SYSTEM_VALUE_FRONT_FACE
:
5369 return TGSI_SEMANTIC_FACE
;
5370 case SYSTEM_VALUE_SAMPLE_ID
:
5371 return TGSI_SEMANTIC_SAMPLEID
;
5372 case SYSTEM_VALUE_SAMPLE_POS
:
5373 return TGSI_SEMANTIC_SAMPLEPOS
;
5374 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5375 return TGSI_SEMANTIC_SAMPLEMASK
;
5376 case SYSTEM_VALUE_HELPER_INVOCATION
:
5377 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5379 /* Tessellation shader */
5380 case SYSTEM_VALUE_TESS_COORD
:
5381 return TGSI_SEMANTIC_TESSCOORD
;
5382 case SYSTEM_VALUE_VERTICES_IN
:
5383 return TGSI_SEMANTIC_VERTICESIN
;
5384 case SYSTEM_VALUE_PRIMITIVE_ID
:
5385 return TGSI_SEMANTIC_PRIMID
;
5386 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5387 return TGSI_SEMANTIC_TESSOUTER
;
5388 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5389 return TGSI_SEMANTIC_TESSINNER
;
5391 /* Compute shader */
5392 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5393 return TGSI_SEMANTIC_THREAD_ID
;
5394 case SYSTEM_VALUE_WORK_GROUP_ID
:
5395 return TGSI_SEMANTIC_BLOCK_ID
;
5396 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5397 return TGSI_SEMANTIC_GRID_SIZE
;
5398 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5399 return TGSI_SEMANTIC_BLOCK_SIZE
;
5401 /* ARB_shader_ballot */
5402 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5403 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5404 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5405 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5406 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5407 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5408 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5409 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5410 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5411 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5412 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5413 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5414 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5415 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5418 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5419 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5420 case SYSTEM_VALUE_VERTEX_CNT
:
5422 assert(!"Unexpected SYSTEM_VALUE_ enum");
5423 return TGSI_SEMANTIC_COUNT
;
5428 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5430 static struct ureg_src
5431 emit_immediate(struct st_translate
*t
,
5432 gl_constant_value values
[4],
5435 struct ureg_program
*ureg
= t
->ureg
;
5440 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5442 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5444 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5445 case GL_UNSIGNED_INT64_ARB
:
5446 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5448 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5449 case GL_UNSIGNED_INT
:
5451 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5453 assert(!"should not get here - type must be float, int, uint, or bool");
5454 return ureg_src_undef();
5459 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5461 static struct ureg_dst
5462 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5468 case PROGRAM_UNDEFINED
:
5469 return ureg_dst_undef();
5471 case PROGRAM_TEMPORARY
:
5472 /* Allocate space for temporaries on demand. */
5473 if (index
>= t
->temps_size
) {
5474 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5476 t
->temps
= (struct ureg_dst
*)
5478 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5480 return ureg_dst_undef();
5482 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5483 t
->temps_size
+= inc
;
5486 if (ureg_dst_is_undef(t
->temps
[index
]))
5487 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5489 return t
->temps
[index
];
5492 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5493 array
= array_id
- 1;
5495 if (ureg_dst_is_undef(t
->arrays
[array
]))
5496 t
->arrays
[array
] = ureg_DECL_array_temporary(
5497 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5499 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5501 case PROGRAM_OUTPUT
:
5503 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5504 assert(index
< 2 * FRAG_RESULT_MAX
);
5505 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5506 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5507 assert(index
< VARYING_SLOT_TESS_MAX
);
5509 assert(index
< VARYING_SLOT_MAX
);
5511 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5512 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5513 return t
->outputs
[t
->outputMapping
[index
]];
5516 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5517 unsigned mesa_index
= decl
->mesa_index
;
5518 int slot
= t
->outputMapping
[mesa_index
];
5520 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5522 struct ureg_dst dst
= t
->outputs
[slot
];
5523 dst
.ArrayID
= array_id
;
5524 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5527 case PROGRAM_ADDRESS
:
5528 return t
->address
[index
];
5531 assert(!"unknown dst register file");
5532 return ureg_dst_undef();
5536 static struct ureg_src
5537 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
5539 static struct ureg_src
5540 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
5541 unsigned addr_index
)
5543 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
5544 return ureg_src(t
->address
[addr_index
]);
5546 return translate_src(t
, reladdr
);
5550 * Create a TGSI ureg_dst register from an st_dst_reg.
5552 static struct ureg_dst
5553 translate_dst(struct st_translate
*t
,
5554 const st_dst_reg
*dst_reg
,
5557 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5560 if (dst
.File
== TGSI_FILE_NULL
)
5563 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5566 dst
= ureg_saturate(dst
);
5568 if (dst_reg
->reladdr
!= NULL
) {
5569 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5570 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
5573 if (dst_reg
->has_index2
) {
5574 if (dst_reg
->reladdr2
)
5575 dst
= ureg_dst_dimension_indirect(dst
,
5576 translate_addr(t
, dst_reg
->reladdr2
, 1),
5579 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5586 * Create a TGSI ureg_src register from an st_src_reg.
5588 static struct ureg_src
5589 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5591 struct ureg_src src
;
5592 int index
= src_reg
->index
;
5593 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
5595 switch(src_reg
->file
) {
5596 case PROGRAM_UNDEFINED
:
5597 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5600 case PROGRAM_TEMPORARY
:
5602 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
));
5605 case PROGRAM_OUTPUT
: {
5606 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
);
5607 assert(dst
.WriteMask
!= 0);
5608 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5609 src
= ureg_swizzle(ureg_src(dst
),
5613 MIN2(shift
+ 3, 3));
5617 case PROGRAM_UNIFORM
:
5618 assert(src_reg
->index
>= 0);
5619 src
= src_reg
->index
< t
->num_constants
?
5620 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5622 case PROGRAM_STATE_VAR
:
5623 case PROGRAM_CONSTANT
: /* ie, immediate */
5624 if (src_reg
->has_index2
)
5625 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
5627 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
5628 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5631 case PROGRAM_IMMEDIATE
:
5632 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
5633 src
= t
->immediates
[src_reg
->index
];
5637 /* GLSL inputs are 64-bit containers, so we have to
5638 * map back to the original index and add the offset after
5640 index
-= double_reg2
;
5641 if (!src_reg
->array_id
) {
5642 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5643 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5644 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5647 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
,
5649 unsigned mesa_index
= decl
->mesa_index
;
5650 int slot
= t
->inputMapping
[mesa_index
];
5652 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5654 src
= t
->inputs
[slot
];
5655 src
.ArrayID
= src_reg
->array_id
;
5656 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5660 case PROGRAM_ADDRESS
:
5661 src
= ureg_src(t
->address
[src_reg
->index
]);
5664 case PROGRAM_SYSTEM_VALUE
:
5665 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5666 src
= t
->systemValues
[src_reg
->index
];
5670 assert(!"unknown src register file");
5671 return ureg_src_undef();
5674 if (src_reg
->has_index2
) {
5675 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5676 * and UBO constant buffers (buffer, position).
5678 if (src_reg
->reladdr2
)
5679 src
= ureg_src_dimension_indirect(src
,
5680 translate_addr(t
, src_reg
->reladdr2
, 1),
5683 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5686 src
= ureg_swizzle(src
,
5687 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5688 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5689 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5690 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5693 src
= ureg_abs(src
);
5695 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5696 src
= ureg_negate(src
);
5698 if (src_reg
->reladdr
!= NULL
) {
5699 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5700 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
5706 static struct tgsi_texture_offset
5707 translate_tex_offset(struct st_translate
*t
,
5708 const st_src_reg
*in_offset
)
5710 struct tgsi_texture_offset offset
;
5711 struct ureg_src src
= translate_src(t
, in_offset
);
5713 offset
.File
= src
.File
;
5714 offset
.Index
= src
.Index
;
5715 offset
.SwizzleX
= src
.SwizzleX
;
5716 offset
.SwizzleY
= src
.SwizzleY
;
5717 offset
.SwizzleZ
= src
.SwizzleZ
;
5720 assert(!src
.Indirect
);
5721 assert(!src
.DimIndirect
);
5722 assert(!src
.Dimension
);
5723 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5724 assert(!src
.Negate
);
5730 compile_tgsi_instruction(struct st_translate
*t
,
5731 const glsl_to_tgsi_instruction
*inst
)
5733 struct ureg_program
*ureg
= t
->ureg
;
5735 struct ureg_dst dst
[2];
5736 struct ureg_src src
[4];
5737 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5741 unsigned tex_target
= 0;
5743 num_dst
= num_inst_dst_regs(inst
);
5744 num_src
= num_inst_src_regs(inst
);
5746 for (i
= 0; i
< num_dst
; i
++)
5747 dst
[i
] = translate_dst(t
,
5751 for (i
= 0; i
< num_src
; i
++)
5752 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5755 case TGSI_OPCODE_BGNLOOP
:
5756 case TGSI_OPCODE_ELSE
:
5757 case TGSI_OPCODE_ENDLOOP
:
5758 case TGSI_OPCODE_IF
:
5759 case TGSI_OPCODE_UIF
:
5760 assert(num_dst
== 0);
5761 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
5764 case TGSI_OPCODE_TEX
:
5765 case TGSI_OPCODE_TEX_LZ
:
5766 case TGSI_OPCODE_TXB
:
5767 case TGSI_OPCODE_TXD
:
5768 case TGSI_OPCODE_TXL
:
5769 case TGSI_OPCODE_TXP
:
5770 case TGSI_OPCODE_TXQ
:
5771 case TGSI_OPCODE_TXQS
:
5772 case TGSI_OPCODE_TXF
:
5773 case TGSI_OPCODE_TXF_LZ
:
5774 case TGSI_OPCODE_TEX2
:
5775 case TGSI_OPCODE_TXB2
:
5776 case TGSI_OPCODE_TXL2
:
5777 case TGSI_OPCODE_TG4
:
5778 case TGSI_OPCODE_LODQ
:
5779 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5780 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5782 /* Bindless samplers. */
5783 src
[num_src
] = translate_src(t
, &inst
->resource
);
5785 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5786 if (inst
->resource
.reladdr
)
5788 ureg_src_indirect(src
[num_src
],
5789 translate_addr(t
, inst
->resource
.reladdr
, 2));
5791 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5792 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5794 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5800 st_translate_texture_type(inst
->tex_type
),
5801 texoffsets
, inst
->tex_offset_num_offset
,
5805 case TGSI_OPCODE_RESQ
:
5806 case TGSI_OPCODE_LOAD
:
5807 case TGSI_OPCODE_ATOMUADD
:
5808 case TGSI_OPCODE_ATOMXCHG
:
5809 case TGSI_OPCODE_ATOMCAS
:
5810 case TGSI_OPCODE_ATOMAND
:
5811 case TGSI_OPCODE_ATOMOR
:
5812 case TGSI_OPCODE_ATOMXOR
:
5813 case TGSI_OPCODE_ATOMUMIN
:
5814 case TGSI_OPCODE_ATOMUMAX
:
5815 case TGSI_OPCODE_ATOMIMIN
:
5816 case TGSI_OPCODE_ATOMIMAX
:
5817 for (i
= num_src
- 1; i
>= 0; i
--)
5818 src
[i
+ 1] = src
[i
];
5820 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5821 src
[0] = t
->shared_memory
;
5822 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5823 src
[0] = t
->buffers
[inst
->resource
.index
];
5824 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
5825 assert(inst
->resource
.has_index2
);
5826 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
5828 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
5829 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5830 src
[0] = t
->images
[inst
->resource
.index
];
5832 /* Bindless images. */
5833 src
[0] = translate_src(t
, &inst
->resource
);
5835 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5837 if (inst
->resource
.reladdr
)
5838 src
[0] = ureg_src_indirect(src
[0],
5839 translate_addr(t
, inst
->resource
.reladdr
, 2));
5840 assert(src
[0].File
!= TGSI_FILE_NULL
);
5841 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5842 inst
->buffer_access
,
5843 tex_target
, inst
->image_format
);
5846 case TGSI_OPCODE_STORE
:
5847 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5848 dst
[0] = ureg_dst(t
->shared_memory
);
5849 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5850 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5852 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5853 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5855 /* Bindless images. */
5856 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
5858 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5860 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5861 if (inst
->resource
.reladdr
)
5862 dst
[0] = ureg_dst_indirect(dst
[0],
5863 translate_addr(t
, inst
->resource
.reladdr
, 2));
5864 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5865 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5866 inst
->buffer_access
,
5867 tex_target
, inst
->image_format
);
5874 src
, num_src
, inst
->precise
);
5880 * Emit the TGSI instructions for inverting and adjusting WPOS.
5881 * This code is unavoidable because it also depends on whether
5882 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5885 emit_wpos_adjustment(struct gl_context
*ctx
,
5886 struct st_translate
*t
,
5887 int wpos_transform_const
,
5889 GLfloat adjX
, GLfloat adjY
[2])
5891 struct ureg_program
*ureg
= t
->ureg
;
5893 assert(wpos_transform_const
>= 0);
5895 /* Fragment program uses fragment position input.
5896 * Need to replace instances of INPUT[WPOS] with temp T
5897 * where T = INPUT[WPOS] is inverted by Y.
5899 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5900 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5901 struct ureg_src
*wpos
=
5902 ctx
->Const
.GLSLFragCoordIsSysVal
?
5903 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5904 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5905 struct ureg_src wpos_input
= *wpos
;
5907 /* First, apply the coordinate shift: */
5908 if (adjX
|| adjY
[0] || adjY
[1]) {
5909 if (adjY
[0] != adjY
[1]) {
5910 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5911 * depending on whether inversion is actually going to be applied
5912 * or not, which is determined by testing against the inversion
5913 * state variable used below, which will be either +1 or -1.
5915 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5917 ureg_CMP(ureg
, adj_temp
,
5918 ureg_scalar(wpostrans
, invert
? 2 : 0),
5919 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5920 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5921 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5923 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5924 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5926 wpos_input
= ureg_src(wpos_temp
);
5928 /* MOV wpos_temp, input[wpos]
5930 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5933 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5934 * inversion/identity, or the other way around if we're drawing to an FBO.
5937 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5940 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5942 ureg_scalar(wpostrans
, 0),
5943 ureg_scalar(wpostrans
, 1));
5945 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5948 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5950 ureg_scalar(wpostrans
, 2),
5951 ureg_scalar(wpostrans
, 3));
5954 /* Use wpos_temp as position input from here on:
5956 *wpos
= ureg_src(wpos_temp
);
5961 * Emit fragment position/ooordinate code.
5964 emit_wpos(struct st_context
*st
,
5965 struct st_translate
*t
,
5966 const struct gl_program
*program
,
5967 struct ureg_program
*ureg
,
5968 int wpos_transform_const
)
5970 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5971 GLfloat adjX
= 0.0f
;
5972 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5973 boolean invert
= FALSE
;
5975 /* Query the pixel center conventions supported by the pipe driver and set
5976 * adjX, adjY to help out if it cannot handle the requested one internally.
5978 * The bias of the y-coordinate depends on whether y-inversion takes place
5979 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5980 * drawing to an FBO (causes additional inversion), and whether the pipe
5981 * driver origin and the requested origin differ (the latter condition is
5982 * stored in the 'invert' variable).
5984 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5986 * center shift only:
5991 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5992 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5993 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5994 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5996 * inversion and center shift:
5997 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5998 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5999 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6000 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6002 if (program
->OriginUpperLeft
) {
6003 /* Fragment shader wants origin in upper-left */
6004 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6005 /* the driver supports upper-left origin */
6007 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6008 /* the driver supports lower-left origin, need to invert Y */
6009 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6010 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6017 /* Fragment shader wants origin in lower-left */
6018 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6019 /* the driver supports lower-left origin */
6020 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6021 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6022 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6023 /* the driver supports upper-left origin, need to invert Y */
6029 if (program
->PixelCenterInteger
) {
6030 /* Fragment shader wants pixel center integer */
6031 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6032 /* the driver supports pixel center integer */
6034 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6035 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6037 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6038 /* the driver supports pixel center half integer, need to bias X,Y */
6047 /* Fragment shader wants pixel center half integer */
6048 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6049 /* the driver supports pixel center half integer */
6051 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6052 /* the driver supports pixel center integer, need to bias X,Y */
6053 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6054 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6055 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6061 /* we invert after adjustment so that we avoid the MOV to temporary,
6062 * and reuse the adjustment ADD instead */
6063 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6067 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6068 * TGSI uses +1 for front, -1 for back.
6069 * This function converts the TGSI value to the GL value. Simply clamping/
6070 * saturating the value to [0,1] does the job.
6073 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6075 struct ureg_program
*ureg
= t
->ureg
;
6076 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6077 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6079 if (ctx
->Const
.NativeIntegers
) {
6080 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6083 /* MOV_SAT face_temp, input[face] */
6084 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6087 /* Use face_temp as face input from here on: */
6088 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6092 emit_compute_block_size(const struct gl_program
*prog
,
6093 struct ureg_program
*ureg
) {
6094 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6095 prog
->info
.cs
.local_size
[0]);
6096 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6097 prog
->info
.cs
.local_size
[1]);
6098 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6099 prog
->info
.cs
.local_size
[2]);
6102 struct sort_inout_decls
{
6103 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6104 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6107 const ubyte
*mapping
;
6110 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6112 * This is for the benefit of older drivers which are broken when the
6113 * declarations aren't sorted in this way.
6116 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6118 const ubyte mapping
[])
6120 sort_inout_decls sorter
;
6121 sorter
.mapping
= mapping
;
6122 std::sort(decls
, decls
+ count
, sorter
);
6126 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6128 switch (glsl_qual
) {
6129 case INTERP_MODE_NONE
:
6130 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6131 return TGSI_INTERPOLATE_COLOR
;
6132 return TGSI_INTERPOLATE_PERSPECTIVE
;
6133 case INTERP_MODE_SMOOTH
:
6134 return TGSI_INTERPOLATE_PERSPECTIVE
;
6135 case INTERP_MODE_FLAT
:
6136 return TGSI_INTERPOLATE_CONSTANT
;
6137 case INTERP_MODE_NOPERSPECTIVE
:
6138 return TGSI_INTERPOLATE_LINEAR
;
6140 assert(0 && "unexpected interp mode in st_translate_interp()");
6141 return TGSI_INTERPOLATE_PERSPECTIVE
;
6146 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6147 * \param program the program to translate
6148 * \param numInputs number of input registers used
6149 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6151 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6152 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6154 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6155 * \param numOutputs number of output registers used
6156 * \param outputMapping maps Mesa fragment program outputs to TGSI
6158 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6159 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6162 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6164 extern "C" enum pipe_error
6165 st_translate_program(
6166 struct gl_context
*ctx
,
6168 struct ureg_program
*ureg
,
6169 glsl_to_tgsi_visitor
*program
,
6170 const struct gl_program
*proginfo
,
6172 const ubyte inputMapping
[],
6173 const ubyte inputSlotToAttr
[],
6174 const ubyte inputSemanticName
[],
6175 const ubyte inputSemanticIndex
[],
6176 const ubyte interpMode
[],
6178 const ubyte outputMapping
[],
6179 const ubyte outputSemanticName
[],
6180 const ubyte outputSemanticIndex
[])
6182 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6183 struct st_translate
*t
;
6185 struct gl_program_constants
*frag_const
=
6186 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6187 enum pipe_error ret
= PIPE_OK
;
6189 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6190 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6192 t
= CALLOC_STRUCT(st_translate
);
6194 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6198 t
->procType
= procType
;
6199 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6200 t
->inputMapping
= inputMapping
;
6201 t
->outputMapping
= outputMapping
;
6203 t
->num_temp_arrays
= program
->next_array
;
6204 if (t
->num_temp_arrays
)
6205 t
->arrays
= (struct ureg_dst
*)
6206 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6209 * Declare input attributes.
6212 case PIPE_SHADER_FRAGMENT
:
6213 case PIPE_SHADER_GEOMETRY
:
6214 case PIPE_SHADER_TESS_EVAL
:
6215 case PIPE_SHADER_TESS_CTRL
:
6216 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6218 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6219 struct inout_decl
*decl
= &program
->inputs
[i
];
6220 unsigned slot
= inputMapping
[decl
->mesa_index
];
6221 struct ureg_src src
;
6222 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6224 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6225 if (tgsi_usage_mask
== 1)
6226 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6227 else if (tgsi_usage_mask
== 2)
6228 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6230 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6233 unsigned interp_mode
= 0;
6234 unsigned interp_location
= 0;
6235 if (procType
== PIPE_SHADER_FRAGMENT
) {
6237 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6239 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6241 interp_location
= decl
->interp_loc
;
6244 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6245 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6246 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6247 decl
->array_id
, decl
->size
);
6249 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6250 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6251 /* The ArrayID is set up in dst_register */
6252 t
->inputs
[slot
+ j
] = src
;
6253 t
->inputs
[slot
+ j
].ArrayID
= 0;
6254 t
->inputs
[slot
+ j
].Index
+= j
;
6259 case PIPE_SHADER_VERTEX
:
6260 for (i
= 0; i
< numInputs
; i
++) {
6261 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6264 case PIPE_SHADER_COMPUTE
:
6271 * Declare output attributes.
6274 case PIPE_SHADER_FRAGMENT
:
6275 case PIPE_SHADER_COMPUTE
:
6277 case PIPE_SHADER_GEOMETRY
:
6278 case PIPE_SHADER_TESS_EVAL
:
6279 case PIPE_SHADER_TESS_CTRL
:
6280 case PIPE_SHADER_VERTEX
:
6281 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6283 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6284 struct inout_decl
*decl
= &program
->outputs
[i
];
6285 unsigned slot
= outputMapping
[decl
->mesa_index
];
6286 struct ureg_dst dst
;
6287 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6289 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6290 if (tgsi_usage_mask
== 1)
6291 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6292 else if (tgsi_usage_mask
== 2)
6293 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6295 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6298 dst
= ureg_DECL_output_layout(ureg
,
6299 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6300 decl
->gs_out_streams
,
6301 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6303 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6304 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6305 /* The ArrayID is set up in dst_register */
6306 t
->outputs
[slot
+ j
] = dst
;
6307 t
->outputs
[slot
+ j
].ArrayID
= 0;
6308 t
->outputs
[slot
+ j
].Index
+= j
;
6317 if (procType
== PIPE_SHADER_FRAGMENT
) {
6318 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6319 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6320 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6322 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6323 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6326 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6327 /* Must do this after setting up t->inputs. */
6328 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6329 program
->wpos_transform_const
);
6332 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6333 emit_face_var(ctx
, t
);
6335 for (i
= 0; i
< numOutputs
; i
++) {
6336 switch (outputSemanticName
[i
]) {
6337 case TGSI_SEMANTIC_POSITION
:
6338 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6339 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6340 outputSemanticIndex
[i
]);
6341 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6343 case TGSI_SEMANTIC_STENCIL
:
6344 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6345 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6346 outputSemanticIndex
[i
]);
6347 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6349 case TGSI_SEMANTIC_COLOR
:
6350 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6351 TGSI_SEMANTIC_COLOR
,
6352 outputSemanticIndex
[i
]);
6354 case TGSI_SEMANTIC_SAMPLEMASK
:
6355 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6356 TGSI_SEMANTIC_SAMPLEMASK
,
6357 outputSemanticIndex
[i
]);
6358 /* TODO: If we ever support more than 32 samples, this will have
6359 * to become an array.
6361 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6364 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6365 ret
= PIPE_ERROR_BAD_INPUT
;
6370 else if (procType
== PIPE_SHADER_VERTEX
) {
6371 for (i
= 0; i
< numOutputs
; i
++) {
6372 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6373 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6375 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6376 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6377 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6382 if (procType
== PIPE_SHADER_COMPUTE
) {
6383 emit_compute_block_size(proginfo
, ureg
);
6386 /* Declare address register.
6388 if (program
->num_address_regs
> 0) {
6389 assert(program
->num_address_regs
<= 3);
6390 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6391 t
->address
[i
] = ureg_DECL_address(ureg
);
6394 /* Declare misc input registers
6397 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6399 for (i
= 0; sysInputs
; i
++) {
6400 if (sysInputs
& (1 << i
)) {
6401 unsigned semName
= _mesa_sysval_to_semantic(i
);
6403 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6405 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6406 semName
== TGSI_SEMANTIC_VERTEXID
) {
6407 /* From Gallium perspective, these system values are always
6408 * integer, and require native integer support. However, if
6409 * native integer is supported on the vertex stage but not the
6410 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6411 * assumes these system values are floats. To resolve the
6412 * inconsistency, we insert a U2F.
6414 struct st_context
*st
= st_context(ctx
);
6415 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6416 assert(procType
== PIPE_SHADER_VERTEX
);
6417 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6419 if (!ctx
->Const
.NativeIntegers
) {
6420 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6421 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6422 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6426 if (procType
== PIPE_SHADER_FRAGMENT
&&
6427 semName
== TGSI_SEMANTIC_POSITION
)
6428 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6429 program
->wpos_transform_const
);
6431 sysInputs
&= ~(1 << i
);
6436 t
->array_sizes
= program
->array_sizes
;
6437 t
->input_decls
= program
->inputs
;
6438 t
->num_input_decls
= program
->num_inputs
;
6439 t
->output_decls
= program
->outputs
;
6440 t
->num_output_decls
= program
->num_outputs
;
6442 /* Emit constants and uniforms. TGSI uses a single index space for these,
6443 * so we put all the translated regs in t->constants.
6445 if (proginfo
->Parameters
) {
6446 t
->constants
= (struct ureg_src
*)
6447 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6448 if (t
->constants
== NULL
) {
6449 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6452 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6454 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6455 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6456 case PROGRAM_STATE_VAR
:
6457 case PROGRAM_UNIFORM
:
6458 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6461 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6462 * addressing of the const buffer.
6463 * FIXME: Be smarter and recognize param arrays:
6464 * indirect addressing is only valid within the referenced
6467 case PROGRAM_CONSTANT
:
6468 if (program
->indirect_addr_consts
)
6469 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6471 t
->constants
[i
] = emit_immediate(t
,
6472 proginfo
->Parameters
->ParameterValues
[i
],
6473 proginfo
->Parameters
->Parameters
[i
].DataType
,
6482 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6483 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6484 unsigned num_const_vecs
= (size
+ 15) / 16;
6485 unsigned first
, last
;
6486 assert(num_const_vecs
> 0);
6488 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6489 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6492 /* Emit immediate values.
6494 t
->immediates
= (struct ureg_src
*)
6495 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6496 if (t
->immediates
== NULL
) {
6497 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6500 t
->num_immediates
= program
->num_immediates
;
6503 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6504 assert(i
< program
->num_immediates
);
6505 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6507 assert(i
== program
->num_immediates
);
6509 /* texture samplers */
6510 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6511 if (program
->samplers_used
& (1u << i
)) {
6512 unsigned type
= st_translate_texture_type(program
->sampler_types
[i
]);
6514 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6516 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6517 type
, type
, type
, type
);
6521 /* Declare atomic and shader storage buffers. */
6523 struct gl_program
*prog
= program
->prog
;
6525 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6526 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6527 assert(index
< frag_const
->MaxAtomicBuffers
);
6528 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6531 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6532 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6533 unsigned index
= frag_const
->MaxAtomicBuffers
+ i
;
6534 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6538 if (program
->use_shared_memory
)
6539 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6541 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6542 if (program
->images_used
& (1 << i
)) {
6543 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6544 program
->image_targets
[i
],
6545 program
->image_formats
[i
],
6550 /* Emit each instruction in turn:
6552 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6553 compile_tgsi_instruction(t
, inst
);
6555 /* Set the next shader stage hint for VS and TES. */
6557 case PIPE_SHADER_VERTEX
:
6558 case PIPE_SHADER_TESS_EVAL
:
6559 if (program
->shader_program
->SeparateShader
)
6562 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6563 if (program
->shader_program
->_LinkedShaders
[i
]) {
6564 ureg_set_next_shader_processor(
6565 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6577 t
->num_constants
= 0;
6578 free(t
->immediates
);
6579 t
->num_immediates
= 0;
6585 /* ----------------------------- End TGSI code ------------------------------ */
6589 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6590 * generating Mesa IR.
6592 static struct gl_program
*
6593 get_mesa_program_tgsi(struct gl_context
*ctx
,
6594 struct gl_shader_program
*shader_program
,
6595 struct gl_linked_shader
*shader
)
6597 glsl_to_tgsi_visitor
* v
;
6598 struct gl_program
*prog
;
6599 struct gl_shader_compiler_options
*options
=
6600 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6601 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6602 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
6603 unsigned skip_merge_registers
;
6605 validate_ir_tree(shader
->ir
);
6607 prog
= shader
->Program
;
6609 prog
->Parameters
= _mesa_new_parameter_list();
6610 v
= new glsl_to_tgsi_visitor();
6613 v
->shader_program
= shader_program
;
6615 v
->options
= options
;
6616 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6618 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6619 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6620 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6621 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6622 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6623 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6624 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6626 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6627 _mesa_key_pointer_equal
);
6628 skip_merge_registers
=
6629 pscreen
->get_shader_param(pscreen
, ptarget
,
6630 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6632 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
6635 /* Remove reads from output registers. */
6636 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6637 lower_output_reads(shader
->Stage
, shader
->ir
);
6639 /* Emit intermediate IR for main(). */
6640 visit_exec_list(shader
->ir
, v
);
6643 /* Print out some information (for debugging purposes) used by the
6644 * optimization passes. */
6647 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6648 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6649 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6650 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6652 for (i
= 0; i
< v
->next_temp
; i
++) {
6653 first_writes
[i
] = -1;
6654 first_reads
[i
] = -1;
6655 last_writes
[i
] = -1;
6658 v
->get_first_temp_read(first_reads
);
6659 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6660 v
->get_last_temp_write(last_writes
);
6661 for (i
= 0; i
< v
->next_temp
; i
++)
6662 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6666 ralloc_free(first_writes
);
6667 ralloc_free(first_reads
);
6668 ralloc_free(last_writes
);
6669 ralloc_free(last_reads
);
6673 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6675 v
->copy_propagate();
6677 while (v
->eliminate_dead_code());
6679 v
->merge_two_dsts();
6680 if (!skip_merge_registers
)
6681 v
->merge_registers();
6682 v
->renumber_registers();
6684 /* Write the END instruction. */
6685 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6687 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6689 _mesa_log("GLSL IR for linked %s program %d:\n",
6690 _mesa_shader_stage_to_string(shader
->Stage
),
6691 shader_program
->Name
);
6692 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6696 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6697 _mesa_copy_linked_program_data(shader_program
, shader
);
6698 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6699 &prog
->info
.inputs_read
,
6700 prog
->info
.double_inputs_read
,
6701 &prog
->info
.patch_inputs_read
);
6702 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6703 &prog
->info
.outputs_written
, 0ULL,
6704 &prog
->info
.patch_outputs_written
);
6705 count_resources(v
, prog
);
6707 /* The GLSL IR won't be needed anymore. */
6708 ralloc_free(shader
->ir
);
6711 /* This must be done before the uniform storage is associated. */
6712 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6713 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6714 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6715 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6716 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6719 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6720 wposTransformState
);
6723 /* Avoid reallocation of the program parameter list, because the uniform
6724 * storage is only associated with the original parameter list.
6725 * This should be enough for Bitmap and DrawPixels constants.
6727 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6729 /* This has to be done last. Any operation the can cause
6730 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6731 * program constant) has to happen before creating this linkage.
6733 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6734 if (!shader_program
->data
->LinkStatus
) {
6735 free_glsl_to_tgsi_visitor(v
);
6736 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6740 struct st_vertex_program
*stvp
;
6741 struct st_fragment_program
*stfp
;
6742 struct st_common_program
*stp
;
6743 struct st_compute_program
*stcp
;
6745 switch (shader
->Stage
) {
6746 case MESA_SHADER_VERTEX
:
6747 stvp
= (struct st_vertex_program
*)prog
;
6748 stvp
->glsl_to_tgsi
= v
;
6750 case MESA_SHADER_FRAGMENT
:
6751 stfp
= (struct st_fragment_program
*)prog
;
6752 stfp
->glsl_to_tgsi
= v
;
6754 case MESA_SHADER_TESS_CTRL
:
6755 case MESA_SHADER_TESS_EVAL
:
6756 case MESA_SHADER_GEOMETRY
:
6757 stp
= st_common_program(prog
);
6758 stp
->glsl_to_tgsi
= v
;
6760 case MESA_SHADER_COMPUTE
:
6761 stcp
= (struct st_compute_program
*)prog
;
6762 stcp
->glsl_to_tgsi
= v
;
6765 assert(!"should not be reached");
6772 /* See if there are unsupported control flow statements. */
6773 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6775 const struct gl_shader_compiler_options
*options
;
6777 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6783 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6785 /* Other functions are skipped (same as glsl_to_tgsi). */
6786 if (strcmp(ir
->name
, "main") == 0)
6787 return visit_continue
;
6789 return visit_continue_with_parent
;
6792 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6794 if (!ir
->callee
->is_intrinsic()) {
6795 unsupported
= true; /* it's a function call */
6798 return visit_continue
;
6801 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6803 if (options
->EmitNoMainReturn
) {
6807 return visit_continue
;
6814 has_unsupported_control_flow(exec_list
*ir
,
6815 const struct gl_shader_compiler_options
*options
)
6817 ir_control_flow_info_visitor
visitor(options
);
6818 visit_list_elements(&visitor
, ir
);
6819 return visitor
.unsupported
;
6826 * Called via ctx->Driver.LinkShader()
6827 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6828 * with code lowering and other optimizations.
6831 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6833 /* Return early if we are loading the shader from on-disk cache */
6834 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
6838 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6839 assert(prog
->data
->LinkStatus
);
6841 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6842 if (prog
->_LinkedShaders
[i
] == NULL
)
6845 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6846 exec_list
*ir
= shader
->ir
;
6847 gl_shader_stage stage
= shader
->Stage
;
6848 const struct gl_shader_compiler_options
*options
=
6849 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6850 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
6851 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6852 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6853 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6854 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6855 bool have_ldexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6856 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
);
6857 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6858 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6860 /* If there are forms of indirect addressing that the driver
6861 * cannot handle, perform the lowering pass.
6863 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6864 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6865 lower_variable_index_to_cond_assign(stage
, ir
,
6866 options
->EmitNoIndirectInput
,
6867 options
->EmitNoIndirectOutput
,
6868 options
->EmitNoIndirectTemp
,
6869 options
->EmitNoIndirectUniform
);
6872 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
6873 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
6875 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6876 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6877 LOWER_UNPACK_SNORM_2x16
|
6878 LOWER_PACK_UNORM_2x16
|
6879 LOWER_UNPACK_UNORM_2x16
|
6880 LOWER_PACK_SNORM_4x8
|
6881 LOWER_UNPACK_SNORM_4x8
|
6882 LOWER_UNPACK_UNORM_4x8
|
6883 LOWER_PACK_UNORM_4x8
;
6885 if (ctx
->Extensions
.ARB_gpu_shader5
)
6886 lower_inst
|= LOWER_PACK_USE_BFI
|
6888 if (!ctx
->st
->has_half_float_packing
)
6889 lower_inst
|= LOWER_PACK_HALF_2x16
|
6890 LOWER_UNPACK_HALF_2x16
;
6892 lower_packing_builtins(ir
, lower_inst
);
6895 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6896 lower_offset_arrays(ir
);
6897 do_mat_op_to_vec(ir
);
6899 if (stage
== MESA_SHADER_FRAGMENT
)
6900 lower_blend_equation_advanced(shader
);
6902 lower_instructions(ir
,
6907 (have_ldexp
? 0 : LDEXP_TO_ARITH
) |
6908 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6911 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6912 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6913 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6914 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6915 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
6916 /* Assume that if ARB_gpu_shader5 is not supported
6917 * then all of the extended integer functions need
6918 * lowering. It may be necessary to add some caps
6919 * for individual instructions.
6921 (!ctx
->Extensions
.ARB_gpu_shader5
6922 ? BIT_COUNT_TO_MATH
|
6926 FIND_LSB_TO_FLOAT_CAST
|
6927 FIND_MSB_TO_FLOAT_CAST
|
6931 do_vec_index_to_cond_assign(ir
);
6932 lower_vector_insert(ir
, true);
6933 lower_quadop_vector(ir
, false);
6935 if (options
->MaxIfDepth
== 0) {
6939 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6940 /* Do it once and repeat only if there's unsupported control flow. */
6942 do_common_optimization(ir
, true, true, options
,
6943 ctx
->Const
.NativeIntegers
);
6944 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6945 options
->MaxIfDepth
, if_threshold
);
6946 } while (has_unsupported_control_flow(ir
, options
));
6948 /* Repeat it until it stops making changes. */
6951 progress
= do_common_optimization(ir
, true, true, options
,
6952 ctx
->Const
.NativeIntegers
);
6953 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6954 options
->MaxIfDepth
, if_threshold
);
6958 validate_ir_tree(ir
);
6961 build_program_resource_list(ctx
, prog
);
6963 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6964 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6968 enum pipe_shader_type ptarget
=
6969 pipe_shader_type_from_mesa(shader
->Stage
);
6970 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6971 pscreen
->get_shader_param(pscreen
, ptarget
,
6972 PIPE_SHADER_CAP_PREFERRED_IR
);
6974 struct gl_program
*linked_prog
= NULL
;
6975 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6976 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
6978 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
6982 st_set_prog_affected_state_flags(linked_prog
);
6983 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6984 _mesa_shader_stage_to_program(i
),
6986 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6996 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6997 const ubyte outputMapping
[],
6998 struct pipe_stream_output_info
*so
)
7000 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7003 struct gl_transform_feedback_info
*info
=
7004 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7005 st_translate_stream_output_info2(info
, outputMapping
, so
);
7009 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7010 const ubyte outputMapping
[],
7011 struct pipe_stream_output_info
*so
)
7015 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7016 so
->output
[i
].register_index
=
7017 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7018 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7019 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7020 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7021 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7022 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7025 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7026 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7028 so
->num_outputs
= info
->NumOutputs
;