2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_glsl_types.h"
53 #include "st_program.h"
54 #include "st_mesa_to_tgsi.h"
55 #include "st_format.h"
57 #include "st_shader_cache.h"
58 #include "st_glsl_to_tgsi_temprename.h"
60 #include "util/hash_table.h"
63 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
64 (1 << PROGRAM_CONSTANT) | \
65 (1 << PROGRAM_UNIFORM))
67 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static unsigned is_precise(const ir_variable
*ir
)
73 return ir
->data
.precise
|| ir
->data
.invariant
;
76 class variable_storage
{
77 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
80 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
81 unsigned array_id
= 0)
82 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
84 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
87 gl_register_file file
;
90 /* Explicit component location. This is given in terms of the GLSL-style
91 * swizzles where each double is a single component, i.e. for 64-bit types
92 * it can only be 0 or 1.
95 ir_variable
*var
; /* variable that maps to this, if any */
99 class immediate_storage
: public exec_node
{
101 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
103 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
104 this->size32
= size32
;
108 /* doubles are stored across 2 gl_constant_values */
109 gl_constant_value values
[4];
110 int size32
; /**< Number of 32-bit components (1-4) */
111 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
114 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
115 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
119 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
122 unsigned gs_out_streams
;
123 enum glsl_interp_mode interp
;
124 enum glsl_base_type base_type
;
125 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
128 static struct inout_decl
*
129 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
131 assert(array_id
!= 0);
133 for (unsigned i
= 0; i
< count
; i
++) {
134 struct inout_decl
*decl
= &decls
[i
];
136 if (array_id
== decl
->array_id
) {
144 static enum glsl_base_type
145 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
148 return GLSL_TYPE_ERROR
;
149 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
151 return decl
->base_type
;
152 return GLSL_TYPE_ERROR
;
155 struct glsl_to_tgsi_visitor
: public ir_visitor
{
157 glsl_to_tgsi_visitor();
158 ~glsl_to_tgsi_visitor();
160 struct gl_context
*ctx
;
161 struct gl_program
*prog
;
162 struct gl_shader_program
*shader_program
;
163 struct gl_linked_shader
*shader
;
164 struct gl_shader_compiler_options
*options
;
168 unsigned *array_sizes
;
169 unsigned max_num_arrays
;
172 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
174 unsigned num_input_arrays
;
175 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
176 unsigned num_outputs
;
177 unsigned num_output_arrays
;
179 int num_address_regs
;
180 uint32_t samplers_used
;
181 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
182 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
184 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
185 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
186 bool indirect_addr_consts
;
187 int wpos_transform_const
;
190 bool native_integers
;
193 bool use_shared_memory
;
198 variable_storage
*find_variable_storage(ir_variable
*var
);
200 int add_constant(gl_register_file file
, gl_constant_value values
[8],
201 int size
, int datatype
, uint16_t *swizzle_out
);
203 st_src_reg
get_temp(const glsl_type
*type
);
204 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
206 st_src_reg
st_src_reg_for_double(double val
);
207 st_src_reg
st_src_reg_for_float(float val
);
208 st_src_reg
st_src_reg_for_int(int val
);
209 st_src_reg
st_src_reg_for_int64(int64_t val
);
210 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
213 * \name Visit methods
215 * As typical for the visitor pattern, there must be one \c visit method for
216 * each concrete subclass of \c ir_instruction. Virtual base classes within
217 * the hierarchy should not have \c visit methods.
220 virtual void visit(ir_variable
*);
221 virtual void visit(ir_loop
*);
222 virtual void visit(ir_loop_jump
*);
223 virtual void visit(ir_function_signature
*);
224 virtual void visit(ir_function
*);
225 virtual void visit(ir_expression
*);
226 virtual void visit(ir_swizzle
*);
227 virtual void visit(ir_dereference_variable
*);
228 virtual void visit(ir_dereference_array
*);
229 virtual void visit(ir_dereference_record
*);
230 virtual void visit(ir_assignment
*);
231 virtual void visit(ir_constant
*);
232 virtual void visit(ir_call
*);
233 virtual void visit(ir_return
*);
234 virtual void visit(ir_discard
*);
235 virtual void visit(ir_texture
*);
236 virtual void visit(ir_if
*);
237 virtual void visit(ir_emit_vertex
*);
238 virtual void visit(ir_end_primitive
*);
239 virtual void visit(ir_barrier
*);
242 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
244 void visit_atomic_counter_intrinsic(ir_call
*);
245 void visit_ssbo_intrinsic(ir_call
*);
246 void visit_membar_intrinsic(ir_call
*);
247 void visit_shared_intrinsic(ir_call
*);
248 void visit_image_intrinsic(ir_call
*);
249 void visit_generic_intrinsic(ir_call
*, unsigned op
);
253 /** List of variable_storage */
254 struct hash_table
*variables
;
256 /** List of immediate_storage */
257 exec_list immediates
;
258 unsigned num_immediates
;
260 /** List of glsl_to_tgsi_instruction */
261 exec_list instructions
;
263 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
264 st_dst_reg dst
= undef_dst
,
265 st_src_reg src0
= undef_src
,
266 st_src_reg src1
= undef_src
,
267 st_src_reg src2
= undef_src
,
268 st_src_reg src3
= undef_src
);
270 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
271 st_dst_reg dst
, st_dst_reg dst1
,
272 st_src_reg src0
= undef_src
,
273 st_src_reg src1
= undef_src
,
274 st_src_reg src2
= undef_src
,
275 st_src_reg src3
= undef_src
);
277 unsigned get_opcode(unsigned op
,
279 st_src_reg src0
, st_src_reg src1
);
282 * Emit the correct dot-product instruction for the type of arguments
284 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
290 void emit_scalar(ir_instruction
*ir
, unsigned op
,
291 st_dst_reg dst
, st_src_reg src0
);
293 void emit_scalar(ir_instruction
*ir
, unsigned op
,
294 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
296 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
298 void get_deref_offsets(ir_dereference
*ir
,
299 unsigned *array_size
,
304 void calc_deref_offsets(ir_dereference
*tail
,
305 unsigned *array_elements
,
307 st_src_reg
*indirect
,
309 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
311 bool try_emit_mad(ir_expression
*ir
,
313 bool try_emit_mad_for_and_not(ir_expression
*ir
,
316 void emit_swz(ir_expression
*ir
);
318 bool process_move_condition(ir_rvalue
*ir
);
320 void simplify_cmp(void);
322 void rename_temp_registers(struct rename_reg_pair
*renames
);
323 void get_first_temp_read(int *first_reads
);
324 void get_first_temp_write(int *first_writes
);
325 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
326 void get_last_temp_write(int *last_writes
);
328 void copy_propagate(void);
329 int eliminate_dead_code(void);
331 void merge_two_dsts(void);
332 void merge_registers(void);
333 void renumber_registers(void);
335 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
336 st_dst_reg
*l
, st_src_reg
*r
,
337 st_src_reg
*cond
, bool cond_swap
);
342 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
343 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
344 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
347 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
350 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
354 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
357 prog
->data
->LinkStatus
= linking_failure
;
361 swizzle_for_size(int size
)
363 static const int size_swizzles
[4] = {
364 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
365 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
366 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
367 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
370 assert((size
>= 1) && (size
<= 4));
371 return size_swizzles
[size
- 1];
375 glsl_to_tgsi_instruction
*
376 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
377 st_dst_reg dst
, st_dst_reg dst1
,
378 st_src_reg src0
, st_src_reg src1
,
379 st_src_reg src2
, st_src_reg src3
)
381 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
382 int num_reladdr
= 0, i
, j
;
383 bool dst_is_64bit
[2];
385 op
= get_opcode(op
, dst
, src0
, src1
);
387 /* If we have to do relative addressing, we want to load the ARL
388 * reg directly for one of the regs, and preload the other reladdr
389 * sources into temps.
391 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
392 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
393 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
394 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
395 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
396 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
398 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
399 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
400 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
401 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
403 if (dst
.reladdr
|| dst
.reladdr2
) {
405 emit_arl(ir
, address_reg
, *dst
.reladdr
);
407 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
411 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
414 assert(num_reladdr
== 0);
416 /* inst->op has only 8 bits. */
417 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
420 inst
->precise
= this->precise
;
421 inst
->info
= tgsi_get_opcode_info(op
);
428 inst
->is_64bit_expanded
= false;
431 inst
->tex_offsets
= NULL
;
432 inst
->tex_offset_num_offset
= 0;
434 inst
->tex_shadow
= 0;
435 /* default to float, for paths where this is not initialized
436 * (since 0==UINT which is likely wrong):
438 inst
->tex_type
= GLSL_TYPE_FLOAT
;
440 /* Update indirect addressing status used by TGSI */
441 if (dst
.reladdr
|| dst
.reladdr2
) {
443 case PROGRAM_STATE_VAR
:
444 case PROGRAM_CONSTANT
:
445 case PROGRAM_UNIFORM
:
446 this->indirect_addr_consts
= true;
448 case PROGRAM_IMMEDIATE
:
449 assert(!"immediates should not have indirect addressing");
456 for (i
= 0; i
< 4; i
++) {
457 if(inst
->src
[i
].reladdr
) {
458 switch(inst
->src
[i
].file
) {
459 case PROGRAM_STATE_VAR
:
460 case PROGRAM_CONSTANT
:
461 case PROGRAM_UNIFORM
:
462 this->indirect_addr_consts
= true;
464 case PROGRAM_IMMEDIATE
:
465 assert(!"immediates should not have indirect addressing");
475 * This section contains the double processing.
476 * GLSL just represents doubles as single channel values,
477 * however most HW and TGSI represent doubles as pairs of register channels.
479 * so we have to fixup destination writemask/index and src swizzle/indexes.
480 * dest writemasks need to translate from single channel write mask
481 * to a dual-channel writemask, but also need to modify the index,
482 * if we are touching the Z,W fields in the pre-translated writemask.
484 * src channels have similiar index modifications along with swizzle
485 * changes to we pick the XY, ZW pairs from the correct index.
487 * GLSL [0].x -> TGSI [0].xy
488 * GLSL [0].y -> TGSI [0].zw
489 * GLSL [0].z -> TGSI [1].xy
490 * GLSL [0].w -> TGSI [1].zw
492 for (j
= 0; j
< 2; j
++) {
493 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
494 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
495 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
496 if (glsl_base_type_is_64bit(type
))
497 dst_is_64bit
[j
] = true;
501 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
502 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
503 glsl_to_tgsi_instruction
*dinst
= NULL
;
504 int initial_src_swz
[4], initial_src_idx
[4];
505 int initial_dst_idx
[2], initial_dst_writemask
[2];
506 /* select the writemask for dst0 or dst1 */
507 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
509 /* copy out the writemask, index and swizzles for all src/dsts. */
510 for (j
= 0; j
< 2; j
++) {
511 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
512 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
515 for (j
= 0; j
< 4; j
++) {
516 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
517 initial_src_idx
[j
] = inst
->src
[j
].index
;
521 * scan all the components in the dst writemask
522 * generate an instruction for each of them if required.
527 int i
= u_bit_scan(&writemask
);
529 /* before emitting the instruction, see if we have to adjust load / store
531 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
532 addr
.file
== PROGRAM_UNDEFINED
) {
533 /* We have to advance the buffer address by 16 */
534 addr
= get_temp(glsl_type::uint_type
);
535 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
536 inst
->src
[0], st_src_reg_for_int(16));
539 /* first time use previous instruction */
543 /* create a new instructions for subsequent attempts */
544 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
549 this->instructions
.push_tail(dinst
);
550 dinst
->is_64bit_expanded
= true;
552 /* modify the destination if we are splitting */
553 for (j
= 0; j
< 2; j
++) {
554 if (dst_is_64bit
[j
]) {
555 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
556 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
558 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
559 dinst
->src
[0] = addr
;
560 if (dinst
->op
!= TGSI_OPCODE_STORE
)
561 dinst
->dst
[j
].index
++;
564 /* if we aren't writing to a double, just get the bit of the initial writemask
566 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
570 /* modify the src registers */
571 for (j
= 0; j
< 4; j
++) {
572 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
574 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
575 dinst
->src
[j
].index
= initial_src_idx
[j
];
577 dinst
->src
[j
].double_reg2
= true;
578 dinst
->src
[j
].index
++;
582 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
584 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
587 /* some opcodes are special case in what they use as sources
588 - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is integer src1 */
589 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
590 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
591 op
== TGSI_OPCODE_DLDEXP
|| op
== TGSI_OPCODE_LDEXP
||
592 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
593 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
600 this->instructions
.push_tail(inst
);
607 glsl_to_tgsi_instruction
*
608 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
610 st_src_reg src0
, st_src_reg src1
,
611 st_src_reg src2
, st_src_reg src3
)
613 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
617 * Determines whether to use an integer, unsigned integer, or float opcode
618 * based on the operands and input opcode, then emits the result.
621 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
623 st_src_reg src0
, st_src_reg src1
)
625 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
627 if (op
== TGSI_OPCODE_MOV
)
630 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
631 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
632 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
633 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
635 if (is_resource_instruction(op
))
637 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
638 type
= GLSL_TYPE_INT64
;
639 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
640 type
= GLSL_TYPE_UINT64
;
641 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
642 type
= GLSL_TYPE_DOUBLE
;
643 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
644 type
= GLSL_TYPE_FLOAT
;
645 else if (native_integers
)
646 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
648 #define case7(c, f, i, u, d, i64, ui64) \
649 case TGSI_OPCODE_##c: \
650 if (type == GLSL_TYPE_UINT64) \
651 op = TGSI_OPCODE_##ui64; \
652 else if (type == GLSL_TYPE_INT64) \
653 op = TGSI_OPCODE_##i64; \
654 else if (type == GLSL_TYPE_DOUBLE) \
655 op = TGSI_OPCODE_##d; \
656 else if (type == GLSL_TYPE_INT) \
657 op = TGSI_OPCODE_##i; \
658 else if (type == GLSL_TYPE_UINT) \
659 op = TGSI_OPCODE_##u; \
661 op = TGSI_OPCODE_##f; \
664 #define casecomp(c, f, i, u, d, i64, ui64) \
665 case TGSI_OPCODE_##c: \
666 if (type == GLSL_TYPE_INT64) \
667 op = TGSI_OPCODE_##i64; \
668 else if (type == GLSL_TYPE_UINT64) \
669 op = TGSI_OPCODE_##ui64; \
670 else if (type == GLSL_TYPE_DOUBLE) \
671 op = TGSI_OPCODE_##d; \
672 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
673 op = TGSI_OPCODE_##i; \
674 else if (type == GLSL_TYPE_UINT) \
675 op = TGSI_OPCODE_##u; \
676 else if (native_integers) \
677 op = TGSI_OPCODE_##f; \
679 op = TGSI_OPCODE_##c; \
683 /* Some instructions are initially selected without considering the type.
684 * This fixes the type:
686 * INIT FLOAT SINT UINT DOUBLE SINT64 UINT64
688 case7(ADD
, ADD
, UADD
, UADD
, DADD
, U64ADD
, U64ADD
);
689 case7(CEIL
, CEIL
, LAST
, LAST
, DCEIL
, LAST
, LAST
);
690 case7(DIV
, DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
691 case7(FMA
, FMA
, UMAD
, UMAD
, DFMA
, LAST
, LAST
);
692 case7(FLR
, FLR
, LAST
, LAST
, DFLR
, LAST
, LAST
);
693 case7(FRC
, FRC
, LAST
, LAST
, DFRAC
, LAST
, LAST
);
694 case7(MUL
, MUL
, UMUL
, UMUL
, DMUL
, U64MUL
, U64MUL
);
695 case7(MAD
, MAD
, UMAD
, UMAD
, DMAD
, LAST
, LAST
);
696 case7(MAX
, MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
697 case7(MIN
, MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
698 case7(RCP
, RCP
, LAST
, LAST
, DRCP
, LAST
, LAST
);
699 case7(ROUND
, ROUND
,LAST
, LAST
, DROUND
, LAST
, LAST
);
700 case7(RSQ
, RSQ
, LAST
, LAST
, DRSQ
, LAST
, LAST
);
701 case7(SQRT
, SQRT
, LAST
, LAST
, DSQRT
, LAST
, LAST
);
702 case7(SSG
, SSG
, ISSG
, ISSG
, DSSG
, I64SSG
, I64SSG
);
703 case7(TRUNC
, TRUNC
,LAST
, LAST
, DTRUNC
, LAST
, LAST
);
705 case7(MOD
, LAST
, MOD
, UMOD
, LAST
, I64MOD
, U64MOD
);
706 case7(SHL
, LAST
, SHL
, SHL
, LAST
, U64SHL
, U64SHL
);
707 case7(IBFE
, LAST
, IBFE
, UBFE
, LAST
, LAST
, LAST
);
708 case7(IMSB
, LAST
, IMSB
, UMSB
, LAST
, LAST
, LAST
);
709 case7(IMUL_HI
, LAST
, IMUL_HI
, UMUL_HI
, LAST
, LAST
, LAST
);
710 case7(ISHR
, LAST
, ISHR
, USHR
, LAST
, I64SHR
, U64SHR
);
711 case7(ATOMIMAX
,LAST
, ATOMIMAX
,ATOMUMAX
,LAST
, LAST
, LAST
);
712 case7(ATOMIMIN
,LAST
, ATOMIMIN
,ATOMUMIN
,LAST
, LAST
, LAST
);
714 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
715 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
716 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
717 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
722 assert(op
!= TGSI_OPCODE_LAST
);
726 glsl_to_tgsi_instruction
*
727 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
728 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
731 static const unsigned dot_opcodes
[] = {
732 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
735 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
739 * Emits TGSI scalar opcodes to produce unique answers across channels.
741 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
742 * channel determines the result across all channels. So to do a vec4
743 * of this operation, we want to emit a scalar per source channel used
744 * to produce dest channels.
747 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
749 st_src_reg orig_src0
, st_src_reg orig_src1
)
752 int done_mask
= ~dst
.writemask
;
754 /* TGSI RCP is a scalar operation splatting results to all channels,
755 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
758 for (i
= 0; i
< 4; i
++) {
759 GLuint this_mask
= (1 << i
);
760 st_src_reg src0
= orig_src0
;
761 st_src_reg src1
= orig_src1
;
763 if (done_mask
& this_mask
)
766 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
767 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
768 for (j
= i
+ 1; j
< 4; j
++) {
769 /* If there is another enabled component in the destination that is
770 * derived from the same inputs, generate its value on this pass as
773 if (!(done_mask
& (1 << j
)) &&
774 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
775 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
776 this_mask
|= (1 << j
);
779 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
780 src0_swiz
, src0_swiz
);
781 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
782 src1_swiz
, src1_swiz
);
784 dst
.writemask
= this_mask
;
785 emit_asm(ir
, op
, dst
, src0
, src1
);
786 done_mask
|= this_mask
;
791 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
792 st_dst_reg dst
, st_src_reg src0
)
794 st_src_reg undef
= undef_src
;
796 undef
.swizzle
= SWIZZLE_XXXX
;
798 emit_scalar(ir
, op
, dst
, src0
, undef
);
802 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
803 st_dst_reg dst
, st_src_reg src0
)
805 int op
= TGSI_OPCODE_ARL
;
807 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
) {
808 if (!this->need_uarl
&& src0
.is_legal_tgsi_address_operand())
811 op
= TGSI_OPCODE_UARL
;
814 assert(dst
.file
== PROGRAM_ADDRESS
);
815 if (dst
.index
>= this->num_address_regs
)
816 this->num_address_regs
= dst
.index
+ 1;
818 emit_asm(NULL
, op
, dst
, src0
);
822 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
823 gl_constant_value values
[8], int size
, int datatype
,
824 uint16_t *swizzle_out
)
826 if (file
== PROGRAM_CONSTANT
) {
827 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
828 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
829 size
, datatype
, &swizzle
);
831 *swizzle_out
= swizzle
;
835 assert(file
== PROGRAM_IMMEDIATE
);
838 immediate_storage
*entry
;
839 int size32
= size
* ((datatype
== GL_DOUBLE
||
840 datatype
== GL_INT64_ARB
||
841 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
844 /* Search immediate storage to see if we already have an identical
845 * immediate that we can use instead of adding a duplicate entry.
847 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
848 immediate_storage
*tmp
= entry
;
850 for (i
= 0; i
* 4 < size32
; i
++) {
851 int slot_size
= MIN2(size32
- (i
* 4), 4);
852 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
854 if (memcmp(tmp
->values
, &values
[i
* 4],
855 slot_size
* sizeof(gl_constant_value
)))
858 /* Everything matches, keep going until the full size is matched */
859 tmp
= (immediate_storage
*)tmp
->next
;
862 /* The full value matched */
869 for (i
= 0; i
* 4 < size32
; i
++) {
870 int slot_size
= MIN2(size32
- (i
* 4), 4);
871 /* Add this immediate to the list. */
872 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
873 this->immediates
.push_tail(entry
);
874 this->num_immediates
++;
880 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
882 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
883 union gl_constant_value uval
;
886 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
892 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
894 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
895 union gl_constant_value uval
[2];
897 memcpy(uval
, &val
, sizeof(uval
));
898 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
899 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
904 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
906 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
907 union gl_constant_value uval
;
909 assert(native_integers
);
912 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
918 glsl_to_tgsi_visitor::st_src_reg_for_int64(int64_t val
)
920 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT64
);
921 union gl_constant_value uval
[2];
923 memcpy(uval
, &val
, sizeof(uval
));
924 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
925 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
931 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
934 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
935 st_src_reg_for_int(val
);
937 return st_src_reg_for_float(val
);
941 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
943 return type
->count_attribute_slots(is_vs_input
);
947 type_size(const struct glsl_type
*type
)
949 return type
->count_attribute_slots(false);
953 add_buffer_to_load_and_stores(glsl_to_tgsi_instruction
*inst
, st_src_reg
*buf
,
954 exec_list
*instructions
, ir_constant
*access
)
957 * emit_asm() might have actually split the op into pieces, e.g. for
958 * double stores. We have to go back and fix up all the generated ops.
960 unsigned op
= inst
->op
;
962 inst
->resource
= *buf
;
964 inst
->buffer_access
= access
->value
.u
[0];
966 if (inst
== instructions
->get_head_raw())
968 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
970 if (inst
->op
== TGSI_OPCODE_UADD
) {
971 if (inst
== instructions
->get_head_raw())
973 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
975 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
979 * If the given GLSL type is an array or matrix or a structure containing
980 * an array/matrix member, return true. Else return false.
982 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
983 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
984 * we have an array that might be indexed with a variable, we need to use
985 * the later storage type.
988 type_has_array_or_matrix(const glsl_type
*type
)
990 if (type
->is_array() || type
->is_matrix())
993 if (type
->is_record()) {
994 for (unsigned i
= 0; i
< type
->length
; i
++) {
995 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1006 * In the initial pass of codegen, we assign temporary numbers to
1007 * intermediate results. (not SSA -- variable assignments will reuse
1011 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1015 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1020 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1021 if (next_array
>= max_num_arrays
) {
1022 max_num_arrays
+= 32;
1023 array_sizes
= (unsigned*)
1024 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1027 src
.file
= PROGRAM_ARRAY
;
1029 src
.array_id
= next_array
+ 1;
1030 array_sizes
[next_array
] = type_size(type
);
1034 src
.file
= PROGRAM_TEMPORARY
;
1035 src
.index
= next_temp
;
1036 next_temp
+= type_size(type
);
1039 if (type
->is_array() || type
->is_record()) {
1040 src
.swizzle
= SWIZZLE_NOOP
;
1042 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1049 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1051 struct hash_entry
*entry
;
1053 entry
= _mesa_hash_table_search(this->variables
, var
);
1057 return (variable_storage
*)entry
->data
;
1061 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1063 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1064 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1065 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1068 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1070 const ir_state_slot
*const slots
= ir
->get_state_slots();
1071 assert(slots
!= NULL
);
1073 /* Check if this statevar's setup in the STATE file exactly
1074 * matches how we'll want to reference it as a
1075 * struct/array/whatever. If not, then we need to move it into
1076 * temporary storage and hope that it'll get copy-propagated
1079 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1080 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1085 variable_storage
*storage
;
1087 if (i
== ir
->get_num_state_slots()) {
1088 /* We'll set the index later. */
1089 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1091 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1095 /* The variable_storage constructor allocates slots based on the size
1096 * of the type. However, this had better match the number of state
1097 * elements that we're going to copy into the new temporary.
1099 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1101 dst
= st_dst_reg(get_temp(ir
->type
));
1103 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1106 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1110 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1111 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1112 (gl_state_index
*)slots
[i
].tokens
);
1114 if (storage
->file
== PROGRAM_STATE_VAR
) {
1115 if (storage
->index
== -1) {
1116 storage
->index
= index
;
1118 assert(index
== storage
->index
+ (int)i
);
1121 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1122 * the data being moved since MOV does not care about the type of
1123 * data it is moving, and we don't want to declare registers with
1124 * array or struct types.
1126 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1127 src
.swizzle
= slots
[i
].swizzle
;
1128 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1129 /* even a float takes up a whole vec4 reg in a struct/array. */
1134 if (storage
->file
== PROGRAM_TEMPORARY
&&
1135 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1136 fail_link(this->shader_program
,
1137 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1138 ir
->name
, dst
.index
- storage
->index
,
1139 type_size(ir
->type
));
1145 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1147 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1149 visit_exec_list(&ir
->body_instructions
, this);
1151 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1155 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1158 case ir_loop_jump::jump_break
:
1159 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1161 case ir_loop_jump::jump_continue
:
1162 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1169 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1176 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1178 /* Ignore function bodies other than main() -- we shouldn't see calls to
1179 * them since they should all be inlined before we get to glsl_to_tgsi.
1181 if (strcmp(ir
->name
, "main") == 0) {
1182 const ir_function_signature
*sig
;
1185 sig
= ir
->matching_signature(NULL
, &empty
, false);
1189 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1196 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1198 int nonmul_operand
= 1 - mul_operand
;
1200 st_dst_reg result_dst
;
1202 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1203 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1206 expr
->operands
[0]->accept(this);
1208 expr
->operands
[1]->accept(this);
1210 ir
->operands
[nonmul_operand
]->accept(this);
1213 this->result
= get_temp(ir
->type
);
1214 result_dst
= st_dst_reg(this->result
);
1215 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1216 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1222 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1224 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1225 * implemented using multiplication, and logical-or is implemented using
1226 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1227 * As result, the logical expression (a & !b) can be rewritten as:
1231 * - (a * 1) - (a * b)
1235 * This final expression can be implemented as a single MAD(a, -b, a)
1239 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1241 const int other_operand
= 1 - try_operand
;
1244 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1245 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1248 ir
->operands
[other_operand
]->accept(this);
1250 expr
->operands
[0]->accept(this);
1253 b
.negate
= ~b
.negate
;
1255 this->result
= get_temp(ir
->type
);
1256 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1262 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1263 st_src_reg
*reg
, int *num_reladdr
)
1265 if (!reg
->reladdr
&& !reg
->reladdr2
)
1268 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1269 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1271 if (*num_reladdr
!= 1) {
1272 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1274 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1282 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1284 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1286 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1288 if (!this->precise
&& ir
->operation
== ir_binop_add
) {
1289 if (try_emit_mad(ir
, 1))
1291 if (try_emit_mad(ir
, 0))
1295 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1297 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1298 if (try_emit_mad_for_and_not(ir
, 1))
1300 if (try_emit_mad_for_and_not(ir
, 0))
1304 if (ir
->operation
== ir_quadop_vector
)
1305 assert(!"ir_quadop_vector should have been lowered");
1307 for (unsigned int operand
= 0; operand
< ir
->num_operands
; operand
++) {
1308 this->result
.file
= PROGRAM_UNDEFINED
;
1309 ir
->operands
[operand
]->accept(this);
1310 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1311 printf("Failed to get tree for expression operand:\n");
1312 ir
->operands
[operand
]->print();
1316 op
[operand
] = this->result
;
1318 /* Matrix expression operands should have been broken down to vector
1319 * operations already.
1321 assert(!ir
->operands
[operand
]->type
->is_matrix());
1324 visit_expression(ir
, op
);
1327 /* The non-recursive part of the expression visitor lives in a separate
1328 * function and should be prevented from being inlined, to avoid a stack
1329 * explosion when deeply nested expressions are visited.
1332 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1334 st_src_reg result_src
;
1335 st_dst_reg result_dst
;
1337 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1338 if (ir
->operands
[1]) {
1339 vector_elements
= MAX2(vector_elements
,
1340 ir
->operands
[1]->type
->vector_elements
);
1343 this->result
.file
= PROGRAM_UNDEFINED
;
1345 /* Storage for our result. Ideally for an assignment we'd be using
1346 * the actual storage for the result here, instead.
1348 result_src
= get_temp(ir
->type
);
1349 /* convenience for the emit functions below. */
1350 result_dst
= st_dst_reg(result_src
);
1351 /* Limit writes to the channels that will be used by result_src later.
1352 * This does limit this temp's use as a temporary for multi-instruction
1355 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1357 switch (ir
->operation
) {
1358 case ir_unop_logic_not
:
1359 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1360 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1362 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1363 * older GPUs implement SEQ using multiple instructions (i915 uses two
1364 * SGE instructions and a MUL instruction). Since our logic values are
1365 * 0.0 and 1.0, 1-x also implements !x.
1367 op
[0].negate
= ~op
[0].negate
;
1368 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1372 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1373 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1374 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1375 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1376 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1377 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1379 op
[0].negate
= ~op
[0].negate
;
1383 case ir_unop_subroutine_to_int
:
1384 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1387 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1388 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1389 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1390 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1391 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1392 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1394 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1397 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1400 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1404 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1407 assert(!"not reached: should be handled by exp_to_exp2");
1410 assert(!"not reached: should be handled by log_to_log2");
1413 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1416 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1419 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1421 case ir_unop_saturate
: {
1422 glsl_to_tgsi_instruction
*inst
;
1423 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1424 inst
->saturate
= true;
1429 case ir_unop_dFdx_coarse
:
1430 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1432 case ir_unop_dFdx_fine
:
1433 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1436 case ir_unop_dFdy_coarse
:
1437 case ir_unop_dFdy_fine
:
1439 /* The X component contains 1 or -1 depending on whether the framebuffer
1440 * is a FBO or the window system buffer, respectively.
1441 * It is then multiplied with the source operand of DDY.
1443 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1444 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1446 unsigned transform_y_index
=
1447 _mesa_add_state_reference(this->prog
->Parameters
,
1450 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1452 glsl_type::vec4_type
);
1453 transform_y
.swizzle
= SWIZZLE_XXXX
;
1455 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1457 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1458 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1459 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1463 case ir_unop_frexp_sig
:
1464 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1467 case ir_unop_frexp_exp
:
1468 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1471 case ir_unop_noise
: {
1472 /* At some point, a motivated person could add a better
1473 * implementation of noise. Currently not even the nvidia
1474 * binary drivers do anything more than this. In any case, the
1475 * place to do this is in the GL state tracker, not the poor
1478 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1483 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1486 op
[1].negate
= ~op
[1].negate
;
1487 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1491 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1494 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1497 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1498 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1500 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1504 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1506 case ir_binop_greater
:
1507 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1509 case ir_binop_lequal
:
1510 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1512 case ir_binop_gequal
:
1513 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1515 case ir_binop_equal
:
1516 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1518 case ir_binop_nequal
:
1519 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1521 case ir_binop_all_equal
:
1522 /* "==" operator producing a scalar boolean. */
1523 if (ir
->operands
[0]->type
->is_vector() ||
1524 ir
->operands
[1]->type
->is_vector()) {
1525 st_src_reg temp
= get_temp(native_integers
?
1526 glsl_type::uvec4_type
:
1527 glsl_type::vec4_type
);
1529 if (native_integers
) {
1530 st_dst_reg temp_dst
= st_dst_reg(temp
);
1531 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1533 if (ir
->operands
[0]->type
->is_boolean() &&
1534 ir
->operands
[1]->as_constant() &&
1535 ir
->operands
[1]->as_constant()->is_one()) {
1536 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1538 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1541 /* Emit 1-3 AND operations to combine the SEQ results. */
1542 switch (ir
->operands
[0]->type
->vector_elements
) {
1546 temp_dst
.writemask
= WRITEMASK_Y
;
1547 temp1
.swizzle
= SWIZZLE_YYYY
;
1548 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1549 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1552 temp_dst
.writemask
= WRITEMASK_X
;
1553 temp1
.swizzle
= SWIZZLE_XXXX
;
1554 temp2
.swizzle
= SWIZZLE_YYYY
;
1555 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1556 temp_dst
.writemask
= WRITEMASK_Y
;
1557 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1558 temp2
.swizzle
= SWIZZLE_WWWW
;
1559 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1562 temp1
.swizzle
= SWIZZLE_XXXX
;
1563 temp2
.swizzle
= SWIZZLE_YYYY
;
1564 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1566 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1568 /* After the dot-product, the value will be an integer on the
1569 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1571 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1573 /* Negating the result of the dot-product gives values on the range
1574 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1575 * This is achieved using SGE.
1577 st_src_reg sge_src
= result_src
;
1578 sge_src
.negate
= ~sge_src
.negate
;
1579 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1582 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1585 case ir_binop_any_nequal
:
1586 /* "!=" operator producing a scalar boolean. */
1587 if (ir
->operands
[0]->type
->is_vector() ||
1588 ir
->operands
[1]->type
->is_vector()) {
1589 st_src_reg temp
= get_temp(native_integers
?
1590 glsl_type::uvec4_type
:
1591 glsl_type::vec4_type
);
1592 if (ir
->operands
[0]->type
->is_boolean() &&
1593 ir
->operands
[1]->as_constant() &&
1594 ir
->operands
[1]->as_constant()->is_zero()) {
1595 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1597 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1600 if (native_integers
) {
1601 st_dst_reg temp_dst
= st_dst_reg(temp
);
1602 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1604 /* Emit 1-3 OR operations to combine the SNE results. */
1605 switch (ir
->operands
[0]->type
->vector_elements
) {
1609 temp_dst
.writemask
= WRITEMASK_Y
;
1610 temp1
.swizzle
= SWIZZLE_YYYY
;
1611 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1612 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1615 temp_dst
.writemask
= WRITEMASK_X
;
1616 temp1
.swizzle
= SWIZZLE_XXXX
;
1617 temp2
.swizzle
= SWIZZLE_YYYY
;
1618 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1619 temp_dst
.writemask
= WRITEMASK_Y
;
1620 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1621 temp2
.swizzle
= SWIZZLE_WWWW
;
1622 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1625 temp1
.swizzle
= SWIZZLE_XXXX
;
1626 temp2
.swizzle
= SWIZZLE_YYYY
;
1627 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1629 /* After the dot-product, the value will be an integer on the
1630 * range [0,4]. Zero stays zero, and positive values become 1.0.
1632 glsl_to_tgsi_instruction
*const dp
=
1633 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1634 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1635 /* The clamping to [0,1] can be done for free in the fragment
1636 * shader with a saturate.
1638 dp
->saturate
= true;
1640 /* Negating the result of the dot-product gives values on the range
1641 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1642 * achieved using SLT.
1644 st_src_reg slt_src
= result_src
;
1645 slt_src
.negate
= ~slt_src
.negate
;
1646 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1650 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1654 case ir_binop_logic_xor
:
1655 if (native_integers
)
1656 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1658 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1661 case ir_binop_logic_or
: {
1662 if (native_integers
) {
1663 /* If integers are used as booleans, we can use an actual "or"
1666 assert(native_integers
);
1667 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1669 /* After the addition, the value will be an integer on the
1670 * range [0,2]. Zero stays zero, and positive values become 1.0.
1672 glsl_to_tgsi_instruction
*add
=
1673 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1674 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1675 /* The clamping to [0,1] can be done for free in the fragment
1676 * shader with a saturate if floats are being used as boolean values.
1678 add
->saturate
= true;
1680 /* Negating the result of the addition gives values on the range
1681 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1682 * is achieved using SLT.
1684 st_src_reg slt_src
= result_src
;
1685 slt_src
.negate
= ~slt_src
.negate
;
1686 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1692 case ir_binop_logic_and
:
1693 /* If native integers are disabled, the bool args are stored as float 0.0
1694 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1695 * actual AND opcode.
1697 if (native_integers
)
1698 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1700 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1704 assert(ir
->operands
[0]->type
->is_vector());
1705 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1706 emit_dp(ir
, result_dst
, op
[0], op
[1],
1707 ir
->operands
[0]->type
->vector_elements
);
1712 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1714 /* This is the only instruction sequence that makes the game "Risen"
1715 * render correctly. ABS is not required for the game, but since GLSL
1716 * declares negative values as "undefined", allowing us to do whatever
1717 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1720 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1721 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1725 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1728 if (native_integers
) {
1729 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1732 /* fallthrough to next case otherwise */
1734 if (native_integers
) {
1735 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1738 /* fallthrough to next case otherwise */
1741 case ir_unop_i642u64
:
1742 case ir_unop_u642i64
:
1743 /* Converting between signed and unsigned integers is a no-op. */
1745 result_src
.type
= result_dst
.type
;
1748 if (native_integers
) {
1749 /* Booleans are stored as integers using ~0 for true and 0 for false.
1750 * GLSL requires that int(bool) return 1 for true and 0 for false.
1751 * This conversion is done with AND, but it could be done with NEG.
1753 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1755 /* Booleans and integers are both stored as floats when native
1756 * integers are disabled.
1762 if (native_integers
)
1763 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1765 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1768 if (native_integers
)
1769 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1771 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1773 case ir_unop_bitcast_f2i
:
1774 case ir_unop_bitcast_f2u
:
1775 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1776 if (op
[0].negate
|| op
[0].abs
)
1777 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1780 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
1783 case ir_unop_bitcast_i2f
:
1784 case ir_unop_bitcast_u2f
:
1786 result_src
.type
= GLSL_TYPE_FLOAT
;
1789 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1792 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1795 if (native_integers
)
1796 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1798 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1800 case ir_unop_bitcast_u642d
:
1801 case ir_unop_bitcast_i642d
:
1803 result_src
.type
= GLSL_TYPE_DOUBLE
;
1805 case ir_unop_bitcast_d2i64
:
1807 result_src
.type
= GLSL_TYPE_INT64
;
1809 case ir_unop_bitcast_d2u64
:
1811 result_src
.type
= GLSL_TYPE_UINT64
;
1814 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1817 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1820 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1822 case ir_unop_round_even
:
1823 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1826 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1830 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1833 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1836 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1839 case ir_unop_bit_not
:
1840 if (native_integers
) {
1841 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1845 if (native_integers
) {
1846 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
1849 case ir_binop_lshift
:
1850 case ir_binop_rshift
:
1851 if (native_integers
) {
1852 unsigned opcode
= ir
->operation
== ir_binop_lshift
? TGSI_OPCODE_SHL
1856 if (glsl_base_type_is_64bit(op
[0].type
)) {
1857 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
1860 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]->type
->components()));
1861 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
1866 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
1869 case ir_binop_bit_and
:
1870 if (native_integers
) {
1871 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1874 case ir_binop_bit_xor
:
1875 if (native_integers
) {
1876 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1879 case ir_binop_bit_or
:
1880 if (native_integers
) {
1881 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1885 assert(!"GLSL 1.30 features unsupported");
1888 case ir_binop_ubo_load
: {
1889 if (ctx
->Const
.UseSTD430AsDefaultPacking
) {
1890 ir_rvalue
*block
= ir
->operands
[0];
1891 ir_rvalue
*offset
= ir
->operands
[1];
1892 ir_constant
*const_block
= block
->as_constant();
1894 st_src_reg
cbuf(PROGRAM_CONSTANT
,
1895 (const_block
? const_block
->value
.u
[0] + 1 : 1),
1896 ir
->type
->base_type
);
1898 cbuf
.has_index2
= true;
1901 block
->accept(this);
1902 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1903 *cbuf
.reladdr
= this->result
;
1904 emit_arl(ir
, sampler_reladdr
, this->result
);
1907 /* Calculate the surface offset */
1908 offset
->accept(this);
1909 st_src_reg off
= this->result
;
1911 glsl_to_tgsi_instruction
*inst
=
1912 emit_asm(ir
, TGSI_OPCODE_LOAD
, result_dst
, off
);
1914 if (result_dst
.type
== GLSL_TYPE_BOOL
)
1915 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, st_src_reg(result_dst
),
1916 st_src_reg_for_int(0));
1918 add_buffer_to_load_and_stores(inst
, &cbuf
, &this->instructions
,
1921 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
1922 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
1923 unsigned const_offset
= const_offset_ir
?
1924 const_offset_ir
->value
.u
[0] : 0;
1925 unsigned const_block
= const_uniform_block
?
1926 const_uniform_block
->value
.u
[0] + 1 : 1;
1927 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
1930 cbuf
.type
= ir
->type
->base_type
;
1931 cbuf
.file
= PROGRAM_CONSTANT
;
1933 cbuf
.reladdr
= NULL
;
1936 cbuf
.index2D
= const_block
;
1938 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
1940 if (const_offset_ir
) {
1941 /* Constant index into constant buffer */
1942 cbuf
.reladdr
= NULL
;
1943 cbuf
.index
= const_offset
/ 16;
1945 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
1946 st_src_reg offset
= op
[1];
1948 /* The OpenGL spec is written in such a way that accesses with
1949 * non-constant offset are almost always vec4-aligned. The only
1950 * exception to this are members of structs in arrays of structs:
1951 * each struct in an array of structs is at least vec4-aligned,
1952 * but single-element and [ui]vec2 members of the struct may be at
1953 * an offset that is not a multiple of 16 bytes.
1955 * Here, we extract that offset, relying on previous passes to
1956 * always generate offset expressions of the form
1957 * (+ expr constant_offset).
1959 * Note that the std430 layout, which allows more cases of
1960 * alignment less than vec4 in arrays, is not supported for
1961 * uniform blocks, so we do not have to deal with it here.
1963 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
1964 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
1965 if (const_offset_ir
) {
1966 const_offset
= const_offset_ir
->value
.u
[0];
1967 cbuf
.index
= const_offset
/ 16;
1968 offset_expr
->operands
[0]->accept(this);
1969 offset
= this->result
;
1973 /* Relative/variable index into constant buffer */
1974 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
1975 st_src_reg_for_int(4));
1976 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
1977 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
1980 if (const_uniform_block
) {
1981 /* Constant constant buffer */
1982 cbuf
.reladdr2
= NULL
;
1984 /* Relative/variable constant buffer */
1985 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
1986 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
1988 cbuf
.has_index2
= true;
1990 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
1991 if (glsl_base_type_is_64bit(cbuf
.type
))
1992 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
1993 const_offset
% 16 / 8,
1994 const_offset
% 16 / 8,
1995 const_offset
% 16 / 8);
1997 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
1998 const_offset
% 16 / 4,
1999 const_offset
% 16 / 4,
2000 const_offset
% 16 / 4);
2002 if (ir
->type
->is_boolean()) {
2003 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
,
2004 st_src_reg_for_int(0));
2006 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2012 /* note: we have to reorder the three args here */
2013 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2016 if (this->ctx
->Const
.NativeIntegers
)
2017 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2019 op
[0].negate
= ~op
[0].negate
;
2020 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2023 case ir_triop_bitfield_extract
:
2024 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2026 case ir_quadop_bitfield_insert
:
2027 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2029 case ir_unop_bitfield_reverse
:
2030 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2032 case ir_unop_bit_count
:
2033 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2035 case ir_unop_find_msb
:
2036 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2038 case ir_unop_find_lsb
:
2039 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2041 case ir_binop_imul_high
:
2042 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2045 /* In theory, MAD is incorrect here. */
2047 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2049 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2051 case ir_unop_interpolate_at_centroid
:
2052 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2054 case ir_binop_interpolate_at_offset
: {
2055 /* The y coordinate needs to be flipped for the default fb */
2056 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2057 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2059 unsigned transform_y_index
=
2060 _mesa_add_state_reference(this->prog
->Parameters
,
2063 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2065 glsl_type::vec4_type
);
2066 transform_y
.swizzle
= SWIZZLE_XXXX
;
2068 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2069 st_dst_reg temp_dst
= st_dst_reg(temp
);
2071 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2072 temp_dst
.writemask
= WRITEMASK_Y
;
2073 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2074 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2077 case ir_binop_interpolate_at_sample
:
2078 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2082 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2085 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2088 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2091 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2094 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2097 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2099 case ir_unop_unpack_double_2x32
:
2100 case ir_unop_pack_double_2x32
:
2101 case ir_unop_unpack_int_2x32
:
2102 case ir_unop_pack_int_2x32
:
2103 case ir_unop_unpack_uint_2x32
:
2104 case ir_unop_pack_uint_2x32
:
2105 case ir_unop_unpack_sampler_2x32
:
2106 case ir_unop_pack_sampler_2x32
:
2107 case ir_unop_unpack_image_2x32
:
2108 case ir_unop_pack_image_2x32
:
2109 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2112 case ir_binop_ldexp
:
2113 if (ir
->operands
[0]->type
->is_double()) {
2114 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2115 } else if (ir
->operands
[0]->type
->is_float()) {
2116 emit_asm(ir
, TGSI_OPCODE_LDEXP
, result_dst
, op
[0], op
[1]);
2118 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2122 case ir_unop_pack_half_2x16
:
2123 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2125 case ir_unop_unpack_half_2x16
:
2126 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2129 case ir_unop_get_buffer_size
: {
2130 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2133 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2134 (const_offset
? const_offset
->value
.u
[0] : 0),
2136 if (!const_offset
) {
2137 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2138 *buffer
.reladdr
= op
[0];
2139 emit_arl(ir
, sampler_reladdr
, op
[0]);
2141 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2147 case ir_unop_b2i64
: {
2148 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2149 st_dst_reg temp_dst
= st_dst_reg(temp
);
2150 unsigned orig_swz
= op
[0].swizzle
;
2152 * To convert unsigned to 64-bit:
2153 * zero Y channel, copy X channel.
2155 temp_dst
.writemask
= WRITEMASK_Y
;
2156 if (vector_elements
> 1)
2157 temp_dst
.writemask
|= WRITEMASK_W
;
2158 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2159 temp_dst
.writemask
= WRITEMASK_X
;
2160 if (vector_elements
> 1)
2161 temp_dst
.writemask
|= WRITEMASK_Z
;
2162 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2163 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2164 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2165 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2167 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2169 result_src
.type
= GLSL_TYPE_UINT64
;
2170 if (vector_elements
> 2) {
2171 /* Subtle: We rely on the fact that get_temp here returns the next
2172 * TGSI temporary register directly after the temp register used for
2173 * the first two components, so that the result gets picked up
2176 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2177 st_dst_reg temp_dst
= st_dst_reg(temp
);
2178 temp_dst
.writemask
= WRITEMASK_Y
;
2179 if (vector_elements
> 3)
2180 temp_dst
.writemask
|= WRITEMASK_W
;
2181 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2183 temp_dst
.writemask
= WRITEMASK_X
;
2184 if (vector_elements
> 3)
2185 temp_dst
.writemask
|= WRITEMASK_Z
;
2186 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2187 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2188 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2189 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2191 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2198 case ir_unop_i642u
: {
2199 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2200 st_dst_reg temp_dst
= st_dst_reg(temp
);
2201 unsigned orig_swz
= op
[0].swizzle
;
2202 unsigned orig_idx
= op
[0].index
;
2204 temp_dst
.writemask
= WRITEMASK_X
;
2206 for (el
= 0; el
< vector_elements
; el
++) {
2207 unsigned swz
= GET_SWZ(orig_swz
, el
);
2209 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2211 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2213 op
[0].index
= orig_idx
+ 1;
2214 op
[0].type
= GLSL_TYPE_UINT
;
2215 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2216 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2219 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2220 result_src
.type
= GLSL_TYPE_UINT
;
2222 result_src
.type
= GLSL_TYPE_INT
;
2226 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int64(0));
2229 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2232 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2235 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2238 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2241 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2244 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2247 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2250 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2253 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2256 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2258 /* these might be needed */
2259 case ir_unop_pack_snorm_2x16
:
2260 case ir_unop_pack_unorm_2x16
:
2261 case ir_unop_pack_snorm_4x8
:
2262 case ir_unop_pack_unorm_4x8
:
2264 case ir_unop_unpack_snorm_2x16
:
2265 case ir_unop_unpack_unorm_2x16
:
2266 case ir_unop_unpack_snorm_4x8
:
2267 case ir_unop_unpack_unorm_4x8
:
2269 case ir_quadop_vector
:
2270 case ir_binop_vector_extract
:
2271 case ir_triop_vector_insert
:
2272 case ir_binop_carry
:
2273 case ir_binop_borrow
:
2274 case ir_unop_ssbo_unsized_array_length
:
2275 /* This operation is not supported, or should have already been handled.
2277 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2281 this->result
= result_src
;
2286 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2292 /* Note that this is only swizzles in expressions, not those on the left
2293 * hand side of an assignment, which do write masking. See ir_assignment
2297 ir
->val
->accept(this);
2299 assert(src
.file
!= PROGRAM_UNDEFINED
);
2300 assert(ir
->type
->vector_elements
> 0);
2302 for (i
= 0; i
< 4; i
++) {
2303 if (i
< ir
->type
->vector_elements
) {
2306 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2309 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2312 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2315 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2319 /* If the type is smaller than a vec4, replicate the last
2322 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2326 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2331 /* Test if the variable is an array. Note that geometry and
2332 * tessellation shader inputs are outputs are always arrays (except
2333 * for patch inputs), so only the array element type is considered.
2336 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2338 const glsl_type
*type
= var
->type
;
2340 *remove_array
= false;
2342 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2343 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2346 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2347 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2348 stage
== MESA_SHADER_TESS_CTRL
) &&
2350 if (!var
->type
->is_array())
2351 return false; /* a system value probably */
2353 type
= var
->type
->fields
.array
;
2354 *remove_array
= true;
2357 return type
->is_array() || type
->is_matrix();
2361 st_translate_interp_loc(ir_variable
*var
)
2363 if (var
->data
.centroid
)
2364 return TGSI_INTERPOLATE_LOC_CENTROID
;
2365 else if (var
->data
.sample
)
2366 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2368 return TGSI_INTERPOLATE_LOC_CENTER
;
2372 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2374 variable_storage
*entry
= find_variable_storage(ir
->var
);
2375 ir_variable
*var
= ir
->var
;
2379 switch (var
->data
.mode
) {
2380 case ir_var_uniform
:
2381 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2382 var
->data
.param_index
);
2383 _mesa_hash_table_insert(this->variables
, var
, entry
);
2385 case ir_var_shader_in
: {
2386 /* The linker assigns locations for varyings and attributes,
2387 * including deprecated builtins (like gl_Color), user-assign
2388 * generic attributes (glBindVertexLocation), and
2389 * user-defined varyings.
2391 assert(var
->data
.location
!= -1);
2393 const glsl_type
*type_without_array
= var
->type
->without_array();
2394 struct inout_decl
*decl
= &inputs
[num_inputs
];
2395 unsigned component
= var
->data
.location_frac
;
2396 unsigned num_components
;
2399 if (type_without_array
->is_64bit())
2400 component
= component
/ 2;
2401 if (type_without_array
->vector_elements
)
2402 num_components
= type_without_array
->vector_elements
;
2406 decl
->mesa_index
= var
->data
.location
;
2407 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2408 decl
->interp_loc
= st_translate_interp_loc(var
);
2409 decl
->base_type
= type_without_array
->base_type
;
2410 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2412 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2413 decl
->array_id
= num_input_arrays
+ 1;
2420 decl
->size
= type_size(var
->type
->fields
.array
);
2422 decl
->size
= type_size(var
->type
);
2424 entry
= new(mem_ctx
) variable_storage(var
,
2428 entry
->component
= component
;
2430 _mesa_hash_table_insert(this->variables
, var
, entry
);
2434 case ir_var_shader_out
: {
2435 assert(var
->data
.location
!= -1);
2437 const glsl_type
*type_without_array
= var
->type
->without_array();
2438 struct inout_decl
*decl
= &outputs
[num_outputs
];
2439 unsigned component
= var
->data
.location_frac
;
2440 unsigned num_components
;
2443 if (type_without_array
->is_64bit())
2444 component
= component
/ 2;
2445 if (type_without_array
->vector_elements
)
2446 num_components
= type_without_array
->vector_elements
;
2450 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2451 decl
->base_type
= type_without_array
->base_type
;
2452 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2453 if (var
->data
.stream
& (1u << 31)) {
2454 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2456 assert(var
->data
.stream
< 4);
2457 decl
->gs_out_streams
= 0;
2458 for (unsigned i
= 0; i
< num_components
; ++i
)
2459 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2462 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2463 decl
->array_id
= num_output_arrays
+ 1;
2464 num_output_arrays
++;
2470 decl
->size
= type_size(var
->type
->fields
.array
);
2472 decl
->size
= type_size(var
->type
);
2474 if (var
->data
.fb_fetch_output
) {
2475 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2476 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2477 var
->type
, component
, decl
->array_id
);
2478 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2479 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2482 entry
= new(mem_ctx
) variable_storage(var
,
2487 entry
->component
= component
;
2489 _mesa_hash_table_insert(this->variables
, var
, entry
);
2493 case ir_var_system_value
:
2494 entry
= new(mem_ctx
) variable_storage(var
,
2495 PROGRAM_SYSTEM_VALUE
,
2496 var
->data
.location
);
2499 case ir_var_temporary
:
2500 st_src_reg src
= get_temp(var
->type
);
2502 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2504 _mesa_hash_table_insert(this->variables
, var
, entry
);
2510 printf("Failed to make storage for %s\n", var
->name
);
2515 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2516 entry
->component
, entry
->array_id
);
2517 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&&
2518 var
->data
.mode
== ir_var_shader_in
&&
2519 var
->type
->without_array()->is_double())
2520 this->result
.is_double_vertex_input
= true;
2521 if (!native_integers
)
2522 this->result
.type
= GLSL_TYPE_FLOAT
;
2526 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2527 GLbitfield64
* usage_mask
,
2528 GLbitfield64 double_usage_mask
,
2529 GLbitfield
* patch_usage_mask
)
2534 /* Fix array declarations by removing unused array elements at both ends
2535 * of the arrays. For example, mat4[3] where only mat[1] is used.
2537 for (i
= 0; i
< count
; i
++) {
2538 struct inout_decl
*decl
= &decls
[i
];
2539 if (!decl
->array_id
)
2542 /* Shrink the beginning. */
2543 for (j
= 0; j
< (int)decl
->size
; j
++) {
2544 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2545 if (*patch_usage_mask
&
2546 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2550 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2552 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2561 /* Shrink the end. */
2562 for (j
= decl
->size
-1; j
>= 0; j
--) {
2563 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2564 if (*patch_usage_mask
&
2565 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2569 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2571 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2578 /* When not all entries of an array are accessed, we mark them as used
2579 * here anyway, to ensure that the input/output mapping logic doesn't get
2582 * TODO This happens when an array isn't used via indirect access, which
2583 * some game ports do (at least eON-based). There is an optimization
2584 * opportunity here by replacing the array declaration with non-array
2585 * declarations of those slots that are actually used.
2587 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2588 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2589 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2591 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2597 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2602 ir_variable
*var
= ir
->variable_referenced();
2604 /* We only need the logic provided by st_glsl_storage_type_size()
2605 * for arrays of structs. Indirect sampler and image indexing is handled
2608 int element_size
= ir
->type
->without_array()->is_record() ?
2609 st_glsl_storage_type_size(ir
->type
, var
->data
.bindless
) :
2610 type_size(ir
->type
);
2612 index
= ir
->array_index
->constant_expression_value(ralloc_parent(ir
));
2614 ir
->array
->accept(this);
2617 if (!src
.has_index2
) {
2618 switch (this->prog
->Target
) {
2619 case GL_TESS_CONTROL_PROGRAM_NV
:
2620 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2621 !ir
->variable_referenced()->data
.patch
;
2623 case GL_TESS_EVALUATION_PROGRAM_NV
:
2624 is_2D
= src
.file
== PROGRAM_INPUT
&&
2625 !ir
->variable_referenced()->data
.patch
;
2627 case GL_GEOMETRY_PROGRAM_NV
:
2628 is_2D
= src
.file
== PROGRAM_INPUT
;
2638 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2639 src
.file
== PROGRAM_INPUT
)
2640 element_size
= attrib_type_size(ir
->type
, true);
2642 src
.index2D
= index
->value
.i
[0];
2643 src
.has_index2
= true;
2645 src
.index
+= index
->value
.i
[0] * element_size
;
2647 /* Variable index array dereference. It eats the "vec4" of the
2648 * base of the array and an index that offsets the TGSI register
2651 ir
->array_index
->accept(this);
2653 st_src_reg index_reg
;
2655 if (element_size
== 1) {
2656 index_reg
= this->result
;
2658 index_reg
= get_temp(native_integers
?
2659 glsl_type::int_type
: glsl_type::float_type
);
2661 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2662 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2665 /* If there was already a relative address register involved, add the
2666 * new and the old together to get the new offset.
2668 if (!is_2D
&& src
.reladdr
!= NULL
) {
2669 st_src_reg accum_reg
= get_temp(native_integers
?
2670 glsl_type::int_type
: glsl_type::float_type
);
2672 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2673 index_reg
, *src
.reladdr
);
2675 index_reg
= accum_reg
;
2679 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2680 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2682 src
.has_index2
= true;
2684 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2685 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2689 /* Change the register type to the element type of the array. */
2690 src
.type
= ir
->type
->base_type
;
2696 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2699 const glsl_type
*struct_type
= ir
->record
->type
;
2700 ir_variable
*var
= ir
->record
->variable_referenced();
2703 ir
->record
->accept(this);
2705 assert(ir
->field_idx
>= 0);
2707 for (i
= 0; i
< struct_type
->length
; i
++) {
2708 if (i
== (unsigned) ir
->field_idx
)
2710 const glsl_type
*member_type
= struct_type
->fields
.structure
[i
].type
;
2711 offset
+= st_glsl_storage_type_size(member_type
, var
->data
.bindless
);
2714 /* If the type is smaller than a vec4, replicate the last channel out. */
2715 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2716 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2718 this->result
.swizzle
= SWIZZLE_NOOP
;
2720 this->result
.index
+= offset
;
2721 this->result
.type
= ir
->type
->base_type
;
2725 * We want to be careful in assignment setup to hit the actual storage
2726 * instead of potentially using a temporary like we might with the
2727 * ir_dereference handler.
2730 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2732 /* The LHS must be a dereference. If the LHS is a variable indexed array
2733 * access of a vector, it must be separated into a series conditional moves
2734 * before reaching this point (see ir_vec_index_to_cond_assign).
2736 assert(ir
->as_dereference());
2737 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2739 assert(!deref_array
->array
->type
->is_vector());
2742 /* Use the rvalue deref handler for the most part. We write swizzles using
2743 * the writemask, but we do extract the base component for enhanced layouts
2744 * from the source swizzle.
2747 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2748 return st_dst_reg(v
->result
);
2752 * Process the condition of a conditional assignment
2754 * Examines the condition of a conditional assignment to generate the optimal
2755 * first operand of a \c CMP instruction. If the condition is a relational
2756 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2757 * used as the source for the \c CMP instruction. Otherwise the comparison
2758 * is processed to a boolean result, and the boolean result is used as the
2759 * operand to the CMP instruction.
2762 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2764 ir_rvalue
*src_ir
= ir
;
2766 bool switch_order
= false;
2768 ir_expression
*const expr
= ir
->as_expression();
2770 if (native_integers
) {
2771 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2772 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2773 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2774 type
== GLSL_TYPE_BOOL
) {
2775 if (expr
->operation
== ir_binop_equal
) {
2776 if (expr
->operands
[0]->is_zero()) {
2777 src_ir
= expr
->operands
[1];
2778 switch_order
= true;
2780 else if (expr
->operands
[1]->is_zero()) {
2781 src_ir
= expr
->operands
[0];
2782 switch_order
= true;
2785 else if (expr
->operation
== ir_binop_nequal
) {
2786 if (expr
->operands
[0]->is_zero()) {
2787 src_ir
= expr
->operands
[1];
2789 else if (expr
->operands
[1]->is_zero()) {
2790 src_ir
= expr
->operands
[0];
2796 src_ir
->accept(this);
2797 return switch_order
;
2800 if ((expr
!= NULL
) && (expr
->num_operands
== 2)) {
2801 bool zero_on_left
= false;
2803 if (expr
->operands
[0]->is_zero()) {
2804 src_ir
= expr
->operands
[1];
2805 zero_on_left
= true;
2806 } else if (expr
->operands
[1]->is_zero()) {
2807 src_ir
= expr
->operands
[0];
2808 zero_on_left
= false;
2812 * (a < 0) T F F ( a < 0) T F F
2813 * (0 < a) F F T (-a < 0) F F T
2814 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2815 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2816 * (a > 0) F F T (-a < 0) F F T
2817 * (0 > a) T F F ( a < 0) T F F
2818 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2819 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2821 * Note that exchanging the order of 0 and 'a' in the comparison simply
2822 * means that the value of 'a' should be negated.
2825 switch (expr
->operation
) {
2827 switch_order
= false;
2828 negate
= zero_on_left
;
2831 case ir_binop_greater
:
2832 switch_order
= false;
2833 negate
= !zero_on_left
;
2836 case ir_binop_lequal
:
2837 switch_order
= true;
2838 negate
= !zero_on_left
;
2841 case ir_binop_gequal
:
2842 switch_order
= true;
2843 negate
= zero_on_left
;
2847 /* This isn't the right kind of comparison afterall, so make sure
2848 * the whole condition is visited.
2856 src_ir
->accept(this);
2858 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2859 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2860 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2861 * computing the condition.
2864 this->result
.negate
= ~this->result
.negate
;
2866 return switch_order
;
2870 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2871 st_dst_reg
*l
, st_src_reg
*r
,
2872 st_src_reg
*cond
, bool cond_swap
)
2874 if (type
->is_record()) {
2875 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2876 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2882 if (type
->is_array()) {
2883 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2884 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2889 if (type
->is_matrix()) {
2890 const struct glsl_type
*vec_type
;
2892 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2893 type
->vector_elements
, 1);
2895 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2896 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2901 assert(type
->is_scalar() || type
->is_vector());
2903 l
->type
= type
->base_type
;
2904 r
->type
= type
->base_type
;
2906 st_src_reg l_src
= st_src_reg(*l
);
2908 if (l_src
.file
== PROGRAM_OUTPUT
&&
2909 this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
2910 (l_src
.index
== FRAG_RESULT_DEPTH
|| l_src
.index
== FRAG_RESULT_STENCIL
)) {
2911 /* This is a special case because the source swizzles will be shifted
2912 * later to account for the difference between GLSL (where they're
2913 * plain floats) and TGSI (where they're Z and Y components). */
2914 l_src
.swizzle
= SWIZZLE_XXXX
;
2917 if (native_integers
) {
2918 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2919 cond_swap
? l_src
: *r
,
2920 cond_swap
? *r
: l_src
);
2922 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2923 cond_swap
? l_src
: *r
,
2924 cond_swap
? *r
: l_src
);
2927 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2931 if (type
->is_dual_slot()) {
2933 if (r
->is_double_vertex_input
== false)
2939 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2945 /* all generated instructions need to be flaged as precise */
2946 this->precise
= is_precise(ir
->lhs
->variable_referenced());
2947 ir
->rhs
->accept(this);
2950 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2954 int first_enabled_chan
= 0;
2956 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2958 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2959 variable
->data
.mode
== ir_var_shader_out
&&
2960 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2961 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2962 assert(ir
->lhs
->type
->is_scalar());
2963 assert(ir
->write_mask
== WRITEMASK_X
);
2965 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2966 l
.writemask
= WRITEMASK_Z
;
2968 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2969 l
.writemask
= WRITEMASK_Y
;
2971 } else if (ir
->write_mask
== 0) {
2972 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2974 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2977 l
.writemask
= u_bit_consecutive(0, num_elements
);
2979 /* The type is a struct or an array of (array of) structs. */
2980 l
.writemask
= WRITEMASK_XYZW
;
2983 l
.writemask
= ir
->write_mask
;
2986 for (int i
= 0; i
< 4; i
++) {
2987 if (l
.writemask
& (1 << i
)) {
2988 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2993 l
.writemask
= l
.writemask
<< dst_component
;
2995 /* Swizzle a small RHS vector into the channels being written.
2997 * glsl ir treats write_mask as dictating how many channels are
2998 * present on the RHS while TGSI treats write_mask as just
2999 * showing which channels of the vec4 RHS get written.
3001 for (int i
= 0; i
< 4; i
++) {
3002 if (l
.writemask
& (1 << i
))
3003 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3005 swizzles
[i
] = first_enabled_chan
;
3007 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3008 swizzles
[2], swizzles
[3]);
3011 assert(l
.file
!= PROGRAM_UNDEFINED
);
3012 assert(r
.file
!= PROGRAM_UNDEFINED
);
3014 if (ir
->condition
) {
3015 const bool switch_order
= this->process_move_condition(ir
->condition
);
3016 st_src_reg condition
= this->result
;
3018 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3019 } else if (ir
->rhs
->as_expression() &&
3020 this->instructions
.get_tail() &&
3021 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3022 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3023 type_size(ir
->lhs
->type
) == 1 &&
3024 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3025 /* To avoid emitting an extra MOV when assigning an expression to a
3026 * variable, emit the last instruction of the expression again, but
3027 * replace the destination register with the target of the assignment.
3028 * Dead code elimination will remove the original instruction.
3030 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3031 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3032 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3033 new_inst
->saturate
= inst
->saturate
;
3034 new_inst
->resource
= inst
->resource
;
3035 inst
->dead_mask
= inst
->dst
[0].writemask
;
3037 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3044 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3047 GLdouble stack_vals
[4] = { 0 };
3048 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3049 GLenum gl_type
= GL_NONE
;
3051 static int in_array
= 0;
3052 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3054 /* Unfortunately, 4 floats is all we can get into
3055 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3056 * aggregate constant and move each constant value into it. If we
3057 * get lucky, copy propagation will eliminate the extra moves.
3059 if (ir
->type
->is_record()) {
3060 st_src_reg temp_base
= get_temp(ir
->type
);
3061 st_dst_reg temp
= st_dst_reg(temp_base
);
3063 for (i
= 0; i
< ir
->type
->length
; i
++) {
3064 ir_constant
*const field_value
= ir
->get_record_field(i
);
3065 int size
= type_size(field_value
->type
);
3069 field_value
->accept(this);
3072 for (unsigned j
= 0; j
< (unsigned int)size
; j
++) {
3073 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3079 this->result
= temp_base
;
3083 if (ir
->type
->is_array()) {
3084 st_src_reg temp_base
= get_temp(ir
->type
);
3085 st_dst_reg temp
= st_dst_reg(temp_base
);
3086 int size
= type_size(ir
->type
->fields
.array
);
3091 for (i
= 0; i
< ir
->type
->length
; i
++) {
3092 ir
->const_elements
[i
]->accept(this);
3094 for (int j
= 0; j
< size
; j
++) {
3095 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3101 this->result
= temp_base
;
3106 if (ir
->type
->is_matrix()) {
3107 st_src_reg mat
= get_temp(ir
->type
);
3108 st_dst_reg mat_column
= st_dst_reg(mat
);
3110 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3111 switch (ir
->type
->base_type
) {
3112 case GLSL_TYPE_FLOAT
:
3113 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3115 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3116 src
.index
= add_constant(file
,
3118 ir
->type
->vector_elements
,
3121 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3123 case GLSL_TYPE_DOUBLE
:
3124 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3125 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3126 src
.index
= add_constant(file
,
3128 ir
->type
->vector_elements
,
3131 if (ir
->type
->vector_elements
>= 2) {
3132 mat_column
.writemask
= WRITEMASK_XY
;
3133 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3134 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3136 mat_column
.writemask
= WRITEMASK_X
;
3137 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3138 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3141 if (ir
->type
->vector_elements
> 2) {
3142 if (ir
->type
->vector_elements
== 4) {
3143 mat_column
.writemask
= WRITEMASK_ZW
;
3144 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3145 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3147 mat_column
.writemask
= WRITEMASK_Z
;
3148 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3149 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3150 mat_column
.writemask
= WRITEMASK_XYZW
;
3151 src
.swizzle
= SWIZZLE_XYZW
;
3157 unreachable("Illegal matrix constant type.\n");
3166 switch (ir
->type
->base_type
) {
3167 case GLSL_TYPE_FLOAT
:
3169 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3170 values
[i
].f
= ir
->value
.f
[i
];
3173 case GLSL_TYPE_DOUBLE
:
3174 gl_type
= GL_DOUBLE
;
3175 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3176 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3179 case GLSL_TYPE_INT64
:
3180 gl_type
= GL_INT64_ARB
;
3181 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3182 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3185 case GLSL_TYPE_UINT64
:
3186 gl_type
= GL_UNSIGNED_INT64_ARB
;
3187 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3188 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3191 case GLSL_TYPE_UINT
:
3192 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3193 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3194 if (native_integers
)
3195 values
[i
].u
= ir
->value
.u
[i
];
3197 values
[i
].f
= ir
->value
.u
[i
];
3201 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3202 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3203 if (native_integers
)
3204 values
[i
].i
= ir
->value
.i
[i
];
3206 values
[i
].f
= ir
->value
.i
[i
];
3209 case GLSL_TYPE_BOOL
:
3210 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3211 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3212 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3216 assert(!"Non-float/uint/int/bool constant");
3219 this->result
= st_src_reg(file
, -1, ir
->type
);
3220 this->result
.index
= add_constant(file
,
3222 ir
->type
->vector_elements
,
3224 &this->result
.swizzle
);
3228 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3230 exec_node
*param
= ir
->actual_parameters
.get_head();
3231 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3232 ir_variable
*location
= deref
->variable_referenced();
3235 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3237 /* Calculate the surface offset */
3239 unsigned array_size
= 0, base
= 0;
3242 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3244 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3245 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3246 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3247 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3248 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3250 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3253 ir
->return_deref
->accept(this);
3254 st_dst_reg
dst(this->result
);
3255 dst
.writemask
= WRITEMASK_X
;
3257 glsl_to_tgsi_instruction
*inst
;
3259 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3260 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3261 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3262 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3263 st_src_reg_for_int(1));
3264 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3265 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3266 st_src_reg_for_int(-1));
3267 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3269 param
= param
->get_next();
3270 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3273 st_src_reg data
= this->result
, data2
= undef_src
;
3275 switch (ir
->callee
->intrinsic_id
) {
3276 case ir_intrinsic_atomic_counter_add
:
3277 opcode
= TGSI_OPCODE_ATOMUADD
;
3279 case ir_intrinsic_atomic_counter_min
:
3280 opcode
= TGSI_OPCODE_ATOMIMIN
;
3282 case ir_intrinsic_atomic_counter_max
:
3283 opcode
= TGSI_OPCODE_ATOMIMAX
;
3285 case ir_intrinsic_atomic_counter_and
:
3286 opcode
= TGSI_OPCODE_ATOMAND
;
3288 case ir_intrinsic_atomic_counter_or
:
3289 opcode
= TGSI_OPCODE_ATOMOR
;
3291 case ir_intrinsic_atomic_counter_xor
:
3292 opcode
= TGSI_OPCODE_ATOMXOR
;
3294 case ir_intrinsic_atomic_counter_exchange
:
3295 opcode
= TGSI_OPCODE_ATOMXCHG
;
3297 case ir_intrinsic_atomic_counter_comp_swap
: {
3298 opcode
= TGSI_OPCODE_ATOMCAS
;
3299 param
= param
->get_next();
3300 val
= ((ir_instruction
*)param
)->as_rvalue();
3302 data2
= this->result
;
3306 assert(!"Unexpected intrinsic");
3310 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3313 inst
->resource
= buffer
;
3317 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3319 exec_node
*param
= ir
->actual_parameters
.get_head();
3321 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3323 param
= param
->get_next();
3324 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3326 ir_constant
*const_block
= block
->as_constant();
3330 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3331 (const_block
? const_block
->value
.u
[0] : 0),
3335 block
->accept(this);
3336 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3337 *buffer
.reladdr
= this->result
;
3338 emit_arl(ir
, sampler_reladdr
, this->result
);
3341 /* Calculate the surface offset */
3342 offset
->accept(this);
3343 st_src_reg off
= this->result
;
3345 st_dst_reg dst
= undef_dst
;
3346 if (ir
->return_deref
) {
3347 ir
->return_deref
->accept(this);
3348 dst
= st_dst_reg(this->result
);
3349 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3352 glsl_to_tgsi_instruction
*inst
;
3354 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3355 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3356 if (dst
.type
== GLSL_TYPE_BOOL
)
3357 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3358 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3359 param
= param
->get_next();
3360 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3363 param
= param
->get_next();
3364 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3366 dst
.writemask
= write_mask
->value
.u
[0];
3368 dst
.type
= this->result
.type
;
3369 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3371 param
= param
->get_next();
3372 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3375 st_src_reg data
= this->result
, data2
= undef_src
;
3377 switch (ir
->callee
->intrinsic_id
) {
3378 case ir_intrinsic_ssbo_atomic_add
:
3379 opcode
= TGSI_OPCODE_ATOMUADD
;
3381 case ir_intrinsic_ssbo_atomic_min
:
3382 opcode
= TGSI_OPCODE_ATOMIMIN
;
3384 case ir_intrinsic_ssbo_atomic_max
:
3385 opcode
= TGSI_OPCODE_ATOMIMAX
;
3387 case ir_intrinsic_ssbo_atomic_and
:
3388 opcode
= TGSI_OPCODE_ATOMAND
;
3390 case ir_intrinsic_ssbo_atomic_or
:
3391 opcode
= TGSI_OPCODE_ATOMOR
;
3393 case ir_intrinsic_ssbo_atomic_xor
:
3394 opcode
= TGSI_OPCODE_ATOMXOR
;
3396 case ir_intrinsic_ssbo_atomic_exchange
:
3397 opcode
= TGSI_OPCODE_ATOMXCHG
;
3399 case ir_intrinsic_ssbo_atomic_comp_swap
:
3400 opcode
= TGSI_OPCODE_ATOMCAS
;
3401 param
= param
->get_next();
3402 val
= ((ir_instruction
*)param
)->as_rvalue();
3404 data2
= this->result
;
3407 assert(!"Unexpected intrinsic");
3411 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3414 param
= param
->get_next();
3415 ir_constant
*access
= NULL
;
3416 if (!param
->is_tail_sentinel()) {
3417 access
= ((ir_instruction
*)param
)->as_constant();
3421 add_buffer_to_load_and_stores(inst
, &buffer
, &this->instructions
, access
);
3425 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3427 switch (ir
->callee
->intrinsic_id
) {
3428 case ir_intrinsic_memory_barrier
:
3429 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3430 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3431 TGSI_MEMBAR_ATOMIC_BUFFER
|
3432 TGSI_MEMBAR_SHADER_IMAGE
|
3433 TGSI_MEMBAR_SHARED
));
3435 case ir_intrinsic_memory_barrier_atomic_counter
:
3436 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3437 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3439 case ir_intrinsic_memory_barrier_buffer
:
3440 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3441 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3443 case ir_intrinsic_memory_barrier_image
:
3444 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3445 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3447 case ir_intrinsic_memory_barrier_shared
:
3448 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3449 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3451 case ir_intrinsic_group_memory_barrier
:
3452 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3453 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3454 TGSI_MEMBAR_ATOMIC_BUFFER
|
3455 TGSI_MEMBAR_SHADER_IMAGE
|
3456 TGSI_MEMBAR_SHARED
|
3457 TGSI_MEMBAR_THREAD_GROUP
));
3460 assert(!"Unexpected memory barrier intrinsic");
3465 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3467 exec_node
*param
= ir
->actual_parameters
.get_head();
3469 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3471 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3473 /* Calculate the surface offset */
3474 offset
->accept(this);
3475 st_src_reg off
= this->result
;
3477 st_dst_reg dst
= undef_dst
;
3478 if (ir
->return_deref
) {
3479 ir
->return_deref
->accept(this);
3480 dst
= st_dst_reg(this->result
);
3481 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3484 glsl_to_tgsi_instruction
*inst
;
3486 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3487 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3488 inst
->resource
= buffer
;
3489 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3490 param
= param
->get_next();
3491 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3494 param
= param
->get_next();
3495 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3497 dst
.writemask
= write_mask
->value
.u
[0];
3499 dst
.type
= this->result
.type
;
3500 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3501 inst
->resource
= buffer
;
3503 param
= param
->get_next();
3504 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3507 st_src_reg data
= this->result
, data2
= undef_src
;
3509 switch (ir
->callee
->intrinsic_id
) {
3510 case ir_intrinsic_shared_atomic_add
:
3511 opcode
= TGSI_OPCODE_ATOMUADD
;
3513 case ir_intrinsic_shared_atomic_min
:
3514 opcode
= TGSI_OPCODE_ATOMIMIN
;
3516 case ir_intrinsic_shared_atomic_max
:
3517 opcode
= TGSI_OPCODE_ATOMIMAX
;
3519 case ir_intrinsic_shared_atomic_and
:
3520 opcode
= TGSI_OPCODE_ATOMAND
;
3522 case ir_intrinsic_shared_atomic_or
:
3523 opcode
= TGSI_OPCODE_ATOMOR
;
3525 case ir_intrinsic_shared_atomic_xor
:
3526 opcode
= TGSI_OPCODE_ATOMXOR
;
3528 case ir_intrinsic_shared_atomic_exchange
:
3529 opcode
= TGSI_OPCODE_ATOMXCHG
;
3531 case ir_intrinsic_shared_atomic_comp_swap
:
3532 opcode
= TGSI_OPCODE_ATOMCAS
;
3533 param
= param
->get_next();
3534 val
= ((ir_instruction
*)param
)->as_rvalue();
3536 data2
= this->result
;
3539 assert(!"Unexpected intrinsic");
3543 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3544 inst
->resource
= buffer
;
3549 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3550 bool *memory_coherent
, bool *memory_volatile
,
3551 bool *memory_restrict
, unsigned *image_format
)
3554 switch (ir
->ir_type
) {
3555 case ir_type_dereference_record
: {
3556 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3557 const glsl_type
*struct_type
= deref_record
->record
->type
;
3558 int fild_idx
= deref_record
->field_idx
;
3560 *type
= struct_type
->fields
.structure
[fild_idx
].type
->without_array();
3562 struct_type
->fields
.structure
[fild_idx
].memory_coherent
;
3564 struct_type
->fields
.structure
[fild_idx
].memory_volatile
;
3566 struct_type
->fields
.structure
[fild_idx
].memory_restrict
;
3568 struct_type
->fields
.structure
[fild_idx
].image_format
;
3572 case ir_type_dereference_array
: {
3573 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3574 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3575 memory_coherent
, memory_volatile
, memory_restrict
,
3580 case ir_type_dereference_variable
: {
3581 ir_variable
*var
= ir
->variable_referenced();
3583 *type
= var
->type
->without_array();
3584 *memory_coherent
= var
->data
.memory_coherent
;
3585 *memory_volatile
= var
->data
.memory_volatile
;
3586 *memory_restrict
= var
->data
.memory_restrict
;
3587 *image_format
= var
->data
.image_format
;
3597 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3599 exec_node
*param
= ir
->actual_parameters
.get_head();
3601 ir_dereference
*img
= (ir_dereference
*)param
;
3602 const ir_variable
*imgvar
= img
->variable_referenced();
3603 unsigned sampler_array_size
= 1, sampler_base
= 0;
3604 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3605 unsigned image_format
= 0;
3606 const glsl_type
*type
= NULL
;
3608 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3609 &memory_restrict
, &image_format
);
3612 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3614 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3615 &index
, &reladdr
, !imgvar
->contains_bindless());
3617 image
.index
= index
;
3618 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3619 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3620 *image
.reladdr
= reladdr
;
3621 emit_arl(ir
, sampler_reladdr
, reladdr
);
3624 st_dst_reg dst
= undef_dst
;
3625 if (ir
->return_deref
) {
3626 ir
->return_deref
->accept(this);
3627 dst
= st_dst_reg(this->result
);
3628 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3631 glsl_to_tgsi_instruction
*inst
;
3633 st_src_reg bindless
;
3634 if (imgvar
->contains_bindless()) {
3636 bindless
= this->result
;
3639 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3640 dst
.writemask
= WRITEMASK_XYZ
;
3641 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3642 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3643 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3644 st_dst_reg dstres
= st_dst_reg(res
);
3645 dstres
.writemask
= WRITEMASK_W
;
3646 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3647 res
.swizzle
= SWIZZLE_WWWW
;
3648 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3650 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3652 st_dst_reg coord_dst
;
3653 coord
= get_temp(glsl_type::ivec4_type
);
3654 coord_dst
= st_dst_reg(coord
);
3655 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3656 param
= param
->get_next();
3657 ((ir_dereference
*)param
)->accept(this);
3658 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3659 coord
.swizzle
= SWIZZLE_XXXX
;
3660 switch (type
->coordinate_components()) {
3661 case 4: assert(!"unexpected coord count");
3663 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3665 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3668 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3669 param
= param
->get_next();
3670 ((ir_dereference
*)param
)->accept(this);
3671 st_src_reg sample
= this->result
;
3672 sample
.swizzle
= SWIZZLE_XXXX
;
3673 coord_dst
.writemask
= WRITEMASK_W
;
3674 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3675 coord
.swizzle
|= SWIZZLE_W
<< 9;
3678 param
= param
->get_next();
3679 if (!param
->is_tail_sentinel()) {
3680 ((ir_dereference
*)param
)->accept(this);
3681 arg1
= this->result
;
3682 param
= param
->get_next();
3685 if (!param
->is_tail_sentinel()) {
3686 ((ir_dereference
*)param
)->accept(this);
3687 arg2
= this->result
;
3688 param
= param
->get_next();
3691 assert(param
->is_tail_sentinel());
3694 switch (ir
->callee
->intrinsic_id
) {
3695 case ir_intrinsic_image_load
:
3696 opcode
= TGSI_OPCODE_LOAD
;
3698 case ir_intrinsic_image_store
:
3699 opcode
= TGSI_OPCODE_STORE
;
3701 case ir_intrinsic_image_atomic_add
:
3702 opcode
= TGSI_OPCODE_ATOMUADD
;
3704 case ir_intrinsic_image_atomic_min
:
3705 opcode
= TGSI_OPCODE_ATOMIMIN
;
3707 case ir_intrinsic_image_atomic_max
:
3708 opcode
= TGSI_OPCODE_ATOMIMAX
;
3710 case ir_intrinsic_image_atomic_and
:
3711 opcode
= TGSI_OPCODE_ATOMAND
;
3713 case ir_intrinsic_image_atomic_or
:
3714 opcode
= TGSI_OPCODE_ATOMOR
;
3716 case ir_intrinsic_image_atomic_xor
:
3717 opcode
= TGSI_OPCODE_ATOMXOR
;
3719 case ir_intrinsic_image_atomic_exchange
:
3720 opcode
= TGSI_OPCODE_ATOMXCHG
;
3722 case ir_intrinsic_image_atomic_comp_swap
:
3723 opcode
= TGSI_OPCODE_ATOMCAS
;
3726 assert(!"Unexpected intrinsic");
3730 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3731 if (opcode
== TGSI_OPCODE_STORE
)
3732 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3735 if (imgvar
->contains_bindless()) {
3736 inst
->resource
= bindless
;
3737 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3738 SWIZZLE_X
, SWIZZLE_Y
);
3740 inst
->resource
= image
;
3741 inst
->sampler_array_size
= sampler_array_size
;
3742 inst
->sampler_base
= sampler_base
;
3745 inst
->tex_target
= type
->sampler_index();
3746 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3747 _mesa_get_shader_image_format(image_format
));
3749 if (memory_coherent
)
3750 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3751 if (memory_restrict
)
3752 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3753 if (memory_volatile
)
3754 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3758 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, unsigned op
)
3760 ir
->return_deref
->accept(this);
3761 st_dst_reg dst
= st_dst_reg(this->result
);
3763 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3765 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3766 unsigned num_src
= 0;
3767 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3768 assert(num_src
< ARRAY_SIZE(src
));
3770 this->result
.file
= PROGRAM_UNDEFINED
;
3771 param
->accept(this);
3772 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3774 src
[num_src
] = this->result
;
3778 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
3782 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3784 ir_function_signature
*sig
= ir
->callee
;
3786 /* Filter out intrinsics */
3787 switch (sig
->intrinsic_id
) {
3788 case ir_intrinsic_atomic_counter_read
:
3789 case ir_intrinsic_atomic_counter_increment
:
3790 case ir_intrinsic_atomic_counter_predecrement
:
3791 case ir_intrinsic_atomic_counter_add
:
3792 case ir_intrinsic_atomic_counter_min
:
3793 case ir_intrinsic_atomic_counter_max
:
3794 case ir_intrinsic_atomic_counter_and
:
3795 case ir_intrinsic_atomic_counter_or
:
3796 case ir_intrinsic_atomic_counter_xor
:
3797 case ir_intrinsic_atomic_counter_exchange
:
3798 case ir_intrinsic_atomic_counter_comp_swap
:
3799 visit_atomic_counter_intrinsic(ir
);
3802 case ir_intrinsic_ssbo_load
:
3803 case ir_intrinsic_ssbo_store
:
3804 case ir_intrinsic_ssbo_atomic_add
:
3805 case ir_intrinsic_ssbo_atomic_min
:
3806 case ir_intrinsic_ssbo_atomic_max
:
3807 case ir_intrinsic_ssbo_atomic_and
:
3808 case ir_intrinsic_ssbo_atomic_or
:
3809 case ir_intrinsic_ssbo_atomic_xor
:
3810 case ir_intrinsic_ssbo_atomic_exchange
:
3811 case ir_intrinsic_ssbo_atomic_comp_swap
:
3812 visit_ssbo_intrinsic(ir
);
3815 case ir_intrinsic_memory_barrier
:
3816 case ir_intrinsic_memory_barrier_atomic_counter
:
3817 case ir_intrinsic_memory_barrier_buffer
:
3818 case ir_intrinsic_memory_barrier_image
:
3819 case ir_intrinsic_memory_barrier_shared
:
3820 case ir_intrinsic_group_memory_barrier
:
3821 visit_membar_intrinsic(ir
);
3824 case ir_intrinsic_shared_load
:
3825 case ir_intrinsic_shared_store
:
3826 case ir_intrinsic_shared_atomic_add
:
3827 case ir_intrinsic_shared_atomic_min
:
3828 case ir_intrinsic_shared_atomic_max
:
3829 case ir_intrinsic_shared_atomic_and
:
3830 case ir_intrinsic_shared_atomic_or
:
3831 case ir_intrinsic_shared_atomic_xor
:
3832 case ir_intrinsic_shared_atomic_exchange
:
3833 case ir_intrinsic_shared_atomic_comp_swap
:
3834 visit_shared_intrinsic(ir
);
3837 case ir_intrinsic_image_load
:
3838 case ir_intrinsic_image_store
:
3839 case ir_intrinsic_image_atomic_add
:
3840 case ir_intrinsic_image_atomic_min
:
3841 case ir_intrinsic_image_atomic_max
:
3842 case ir_intrinsic_image_atomic_and
:
3843 case ir_intrinsic_image_atomic_or
:
3844 case ir_intrinsic_image_atomic_xor
:
3845 case ir_intrinsic_image_atomic_exchange
:
3846 case ir_intrinsic_image_atomic_comp_swap
:
3847 case ir_intrinsic_image_size
:
3848 case ir_intrinsic_image_samples
:
3849 visit_image_intrinsic(ir
);
3852 case ir_intrinsic_shader_clock
:
3853 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
3856 case ir_intrinsic_vote_all
:
3857 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
3859 case ir_intrinsic_vote_any
:
3860 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
3862 case ir_intrinsic_vote_eq
:
3863 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
3865 case ir_intrinsic_ballot
:
3866 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
3868 case ir_intrinsic_read_first_invocation
:
3869 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
3871 case ir_intrinsic_read_invocation
:
3872 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
3875 case ir_intrinsic_invalid
:
3876 case ir_intrinsic_generic_load
:
3877 case ir_intrinsic_generic_store
:
3878 case ir_intrinsic_generic_atomic_add
:
3879 case ir_intrinsic_generic_atomic_and
:
3880 case ir_intrinsic_generic_atomic_or
:
3881 case ir_intrinsic_generic_atomic_xor
:
3882 case ir_intrinsic_generic_atomic_min
:
3883 case ir_intrinsic_generic_atomic_max
:
3884 case ir_intrinsic_generic_atomic_exchange
:
3885 case ir_intrinsic_generic_atomic_comp_swap
:
3886 unreachable("Invalid intrinsic");
3891 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3892 unsigned *array_elements
,
3894 st_src_reg
*indirect
,
3897 switch (tail
->ir_type
) {
3898 case ir_type_dereference_record
: {
3899 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3900 const glsl_type
*struct_type
= deref_record
->record
->type
;
3901 int field_index
= deref_record
->field_idx
;
3903 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3905 assert(field_index
>= 0);
3906 *location
+= struct_type
->record_location_offset(field_index
);
3910 case ir_type_dereference_array
: {
3911 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3913 void *mem_ctx
= ralloc_parent(deref_arr
);
3914 ir_constant
*array_index
=
3915 deref_arr
->array_index
->constant_expression_value(mem_ctx
);
3918 st_src_reg temp_reg
;
3919 st_dst_reg temp_dst
;
3921 temp_reg
= get_temp(glsl_type::uint_type
);
3922 temp_dst
= st_dst_reg(temp_reg
);
3923 temp_dst
.writemask
= 1;
3925 deref_arr
->array_index
->accept(this);
3926 if (*array_elements
!= 1)
3927 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3929 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3931 if (indirect
->file
== PROGRAM_UNDEFINED
)
3932 *indirect
= temp_reg
;
3934 temp_dst
= st_dst_reg(*indirect
);
3935 temp_dst
.writemask
= 1;
3936 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3939 *index
+= array_index
->value
.u
[0] * *array_elements
;
3941 *array_elements
*= deref_arr
->array
->type
->length
;
3943 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3952 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3953 unsigned *array_size
,
3956 st_src_reg
*reladdr
,
3959 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3960 unsigned location
= 0;
3961 ir_variable
*var
= ir
->variable_referenced();
3963 memset(reladdr
, 0, sizeof(*reladdr
));
3964 reladdr
->file
= PROGRAM_UNDEFINED
;
3970 location
= var
->data
.location
;
3971 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
3974 * If we end up with no indirect then adjust the base to the index,
3975 * and set the array size to 1.
3977 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3983 assert(location
!= 0xffffffff);
3984 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3985 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3990 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
3992 if (offset
.reladdr
|| offset
.reladdr2
) {
3993 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
3994 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
3995 tmp_dst
.writemask
= WRITEMASK_XY
;
3996 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4004 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4006 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4007 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4008 st_src_reg levels_src
, reladdr
;
4009 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4010 glsl_to_tgsi_instruction
*inst
= NULL
;
4011 unsigned opcode
= TGSI_OPCODE_NOP
;
4012 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4013 unsigned sampler_array_size
= 1, sampler_base
= 0;
4014 bool is_cube_array
= false, is_cube_shadow
= false;
4015 ir_variable
*var
= ir
->sampler
->variable_referenced();
4018 /* if we are a cube array sampler or a cube shadow */
4019 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4020 is_cube_array
= sampler_type
->sampler_array
;
4021 is_cube_shadow
= sampler_type
->sampler_shadow
;
4024 if (ir
->coordinate
) {
4025 ir
->coordinate
->accept(this);
4027 /* Put our coords in a temp. We'll need to modify them for shadow,
4028 * projection, or LOD, so the only case we'd use it as-is is if
4029 * we're doing plain old texturing. The optimization passes on
4030 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4032 coord
= get_temp(glsl_type::vec4_type
);
4033 coord_dst
= st_dst_reg(coord
);
4034 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4035 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4038 if (ir
->projector
) {
4039 ir
->projector
->accept(this);
4040 projector
= this->result
;
4043 /* Storage for our result. Ideally for an assignment we'd be using
4044 * the actual storage for the result here, instead.
4046 result_src
= get_temp(ir
->type
);
4047 result_dst
= st_dst_reg(result_src
);
4048 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4052 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4054 ir
->offset
->accept(this);
4055 offset
[0] = this->result
;
4059 if (is_cube_array
|| is_cube_shadow
) {
4060 opcode
= TGSI_OPCODE_TXB2
;
4063 opcode
= TGSI_OPCODE_TXB
;
4065 ir
->lod_info
.bias
->accept(this);
4066 lod_info
= this->result
;
4068 ir
->offset
->accept(this);
4069 offset
[0] = this->result
;
4073 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4074 opcode
= TGSI_OPCODE_TEX_LZ
;
4076 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4077 ir
->lod_info
.lod
->accept(this);
4078 lod_info
= this->result
;
4081 ir
->offset
->accept(this);
4082 offset
[0] = this->result
;
4086 opcode
= TGSI_OPCODE_TXD
;
4087 ir
->lod_info
.grad
.dPdx
->accept(this);
4089 ir
->lod_info
.grad
.dPdy
->accept(this);
4092 ir
->offset
->accept(this);
4093 offset
[0] = this->result
;
4097 opcode
= TGSI_OPCODE_TXQ
;
4098 ir
->lod_info
.lod
->accept(this);
4099 lod_info
= this->result
;
4101 case ir_query_levels
:
4102 opcode
= TGSI_OPCODE_TXQ
;
4103 lod_info
= undef_src
;
4104 levels_src
= get_temp(ir
->type
);
4107 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4108 opcode
= TGSI_OPCODE_TXF_LZ
;
4110 opcode
= TGSI_OPCODE_TXF
;
4111 ir
->lod_info
.lod
->accept(this);
4112 lod_info
= this->result
;
4115 ir
->offset
->accept(this);
4116 offset
[0] = this->result
;
4120 opcode
= TGSI_OPCODE_TXF
;
4121 ir
->lod_info
.sample_index
->accept(this);
4122 sample_index
= this->result
;
4125 opcode
= TGSI_OPCODE_TG4
;
4126 ir
->lod_info
.component
->accept(this);
4127 component
= this->result
;
4129 ir
->offset
->accept(this);
4130 if (ir
->offset
->type
->is_array()) {
4131 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4132 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4133 offset
[i
] = this->result
;
4134 offset
[i
].index
+= i
* type_size(elt_type
);
4135 offset
[i
].type
= elt_type
->base_type
;
4136 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4137 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4140 offset
[0] = canonicalize_gather_offset(this->result
);
4145 opcode
= TGSI_OPCODE_LODQ
;
4147 case ir_texture_samples
:
4148 opcode
= TGSI_OPCODE_TXQS
;
4150 case ir_samples_identical
:
4151 unreachable("Unexpected ir_samples_identical opcode");
4154 if (ir
->projector
) {
4155 if (opcode
== TGSI_OPCODE_TEX
) {
4156 /* Slot the projector in as the last component of the coord. */
4157 coord_dst
.writemask
= WRITEMASK_W
;
4158 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4159 coord_dst
.writemask
= WRITEMASK_XYZW
;
4160 opcode
= TGSI_OPCODE_TXP
;
4162 st_src_reg coord_w
= coord
;
4163 coord_w
.swizzle
= SWIZZLE_WWWW
;
4165 /* For the other TEX opcodes there's no projective version
4166 * since the last slot is taken up by LOD info. Do the
4167 * projective divide now.
4169 coord_dst
.writemask
= WRITEMASK_W
;
4170 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4172 /* In the case where we have to project the coordinates "by hand,"
4173 * the shadow comparator value must also be projected.
4175 st_src_reg tmp_src
= coord
;
4176 if (ir
->shadow_comparator
) {
4177 /* Slot the shadow value in as the second to last component of the
4180 ir
->shadow_comparator
->accept(this);
4182 tmp_src
= get_temp(glsl_type::vec4_type
);
4183 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4185 /* Projective division not allowed for array samplers. */
4186 assert(!sampler_type
->sampler_array
);
4188 tmp_dst
.writemask
= WRITEMASK_Z
;
4189 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4191 tmp_dst
.writemask
= WRITEMASK_XY
;
4192 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4195 coord_dst
.writemask
= WRITEMASK_XYZ
;
4196 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4198 coord_dst
.writemask
= WRITEMASK_XYZW
;
4199 coord
.swizzle
= SWIZZLE_XYZW
;
4203 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4204 * comparator was put in the correct place (and projected) by the code,
4205 * above, that handles by-hand projection.
4207 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4208 /* Slot the shadow value in as the second to last component of the
4211 ir
->shadow_comparator
->accept(this);
4213 if (is_cube_array
) {
4214 cube_sc
= get_temp(glsl_type::float_type
);
4215 cube_sc_dst
= st_dst_reg(cube_sc
);
4216 cube_sc_dst
.writemask
= WRITEMASK_X
;
4217 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4218 cube_sc_dst
.writemask
= WRITEMASK_X
;
4221 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4222 sampler_type
->sampler_array
) ||
4223 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4224 coord_dst
.writemask
= WRITEMASK_W
;
4226 coord_dst
.writemask
= WRITEMASK_Z
;
4228 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4229 coord_dst
.writemask
= WRITEMASK_XYZW
;
4233 if (ir
->op
== ir_txf_ms
) {
4234 coord_dst
.writemask
= WRITEMASK_W
;
4235 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4236 coord_dst
.writemask
= WRITEMASK_XYZW
;
4237 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4238 opcode
== TGSI_OPCODE_TXF
) {
4239 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4240 coord_dst
.writemask
= WRITEMASK_W
;
4241 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4242 coord_dst
.writemask
= WRITEMASK_XYZW
;
4245 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4248 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4249 &index
, &reladdr
, !var
->contains_bindless());
4251 sampler
.index
= index
;
4252 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4253 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4254 *sampler
.reladdr
= reladdr
;
4255 emit_arl(ir
, sampler_reladdr
, reladdr
);
4258 st_src_reg bindless
;
4259 if (var
->contains_bindless()) {
4260 ir
->sampler
->accept(this);
4261 bindless
= this->result
;
4264 if (opcode
== TGSI_OPCODE_TXD
)
4265 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4266 else if (opcode
== TGSI_OPCODE_TXQ
) {
4267 if (ir
->op
== ir_query_levels
) {
4268 /* the level is stored in W */
4269 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4270 result_dst
.writemask
= WRITEMASK_X
;
4271 levels_src
.swizzle
= SWIZZLE_WWWW
;
4272 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4274 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4275 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4276 inst
= emit_asm(ir
, opcode
, result_dst
);
4277 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4278 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4279 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4280 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4281 } else if (opcode
== TGSI_OPCODE_TG4
) {
4282 if (is_cube_array
&& ir
->shadow_comparator
) {
4283 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4285 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4288 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4290 if (ir
->shadow_comparator
)
4291 inst
->tex_shadow
= GL_TRUE
;
4293 if (var
->contains_bindless()) {
4294 inst
->resource
= bindless
;
4295 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4296 SWIZZLE_X
, SWIZZLE_Y
);
4298 inst
->resource
= sampler
;
4299 inst
->sampler_array_size
= sampler_array_size
;
4300 inst
->sampler_base
= sampler_base
;
4304 if (!inst
->tex_offsets
)
4305 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4307 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4308 inst
->tex_offsets
[i
] = offset
[i
];
4309 inst
->tex_offset_num_offset
= i
;
4312 inst
->tex_target
= sampler_type
->sampler_index();
4313 inst
->tex_type
= ir
->type
->base_type
;
4315 this->result
= result_src
;
4319 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4321 assert(!ir
->get_value());
4323 emit_asm(ir
, TGSI_OPCODE_RET
);
4327 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4329 if (ir
->condition
) {
4330 ir
->condition
->accept(this);
4331 st_src_reg condition
= this->result
;
4333 /* Convert the bool condition to a float so we can negate. */
4334 if (native_integers
) {
4335 st_src_reg temp
= get_temp(ir
->condition
->type
);
4336 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4337 condition
, st_src_reg_for_float(1.0));
4341 condition
.negate
= ~condition
.negate
;
4342 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4344 /* unconditional kil */
4345 emit_asm(ir
, TGSI_OPCODE_KILL
);
4350 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4353 glsl_to_tgsi_instruction
*if_inst
;
4355 ir
->condition
->accept(this);
4356 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4358 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4360 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4362 this->instructions
.push_tail(if_inst
);
4364 visit_exec_list(&ir
->then_instructions
, this);
4366 if (!ir
->else_instructions
.is_empty()) {
4367 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4368 visit_exec_list(&ir
->else_instructions
, this);
4371 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4376 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4378 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4380 ir
->stream
->accept(this);
4381 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4385 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4387 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4389 ir
->stream
->accept(this);
4390 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4394 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4396 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4397 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4399 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4402 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4404 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4406 result
.file
= PROGRAM_UNDEFINED
;
4413 num_input_arrays
= 0;
4414 num_output_arrays
= 0;
4416 num_address_regs
= 0;
4419 indirect_addr_consts
= false;
4420 wpos_transform_const
= -1;
4422 native_integers
= false;
4423 mem_ctx
= ralloc_context(NULL
);
4427 shader_program
= NULL
;
4432 use_shared_memory
= false;
4433 has_tex_txf_lz
= false;
4437 static void var_destroy(struct hash_entry
*entry
)
4439 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4444 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4446 _mesa_hash_table_destroy(variables
, var_destroy
);
4448 ralloc_free(mem_ctx
);
4451 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4458 * Count resources used by the given gpu program (number of texture
4462 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4464 v
->samplers_used
= 0;
4467 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4468 if (inst
->info
->is_tex
) {
4469 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4470 unsigned idx
= inst
->sampler_base
+ i
;
4471 v
->samplers_used
|= 1u << idx
;
4473 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4474 v
->sampler_types
[idx
] = inst
->tex_type
;
4475 v
->sampler_targets
[idx
] =
4476 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4478 if (inst
->tex_shadow
) {
4479 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4484 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4485 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4487 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4488 is_resource_instruction(inst
->op
) ||
4489 inst
->op
== TGSI_OPCODE_STORE
)) {
4490 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4491 v
->use_shared_memory
= true;
4492 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4493 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4494 unsigned idx
= inst
->sampler_base
+ i
;
4495 v
->images_used
|= 1 << idx
;
4496 v
->image_targets
[idx
] =
4497 st_translate_texture_target(inst
->tex_target
, false);
4498 v
->image_formats
[idx
] = inst
->image_format
;
4503 prog
->SamplersUsed
= v
->samplers_used
;
4505 if (v
->shader_program
!= NULL
)
4506 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4510 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4511 * are read from the given src in this instruction
4514 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4516 int read_mask
= 0, comp
;
4518 /* Now, given the src swizzle and the written channels, find which
4519 * components are actually read
4521 for (comp
= 0; comp
< 4; ++comp
) {
4522 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4524 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4525 read_mask
|= 1 << coord
;
4532 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4533 * instruction is the first instruction to write to register T0. There are
4534 * several lowering passes done in GLSL IR (e.g. branches and
4535 * relative addressing) that create a large number of conditional assignments
4536 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4538 * Here is why this conversion is safe:
4539 * CMP T0, T1 T2 T0 can be expanded to:
4545 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4546 * as the original program. If (T1 < 0.0) evaluates to false, executing
4547 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4548 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4549 * because any instruction that was going to read from T0 after this was going
4550 * to read a garbage value anyway.
4553 glsl_to_tgsi_visitor::simplify_cmp(void)
4555 int tempWritesSize
= 0;
4556 unsigned *tempWrites
= NULL
;
4557 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4559 memset(outputWrites
, 0, sizeof(outputWrites
));
4561 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4562 unsigned prevWriteMask
= 0;
4564 /* Give up if we encounter relative addressing or flow control. */
4565 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4566 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4567 inst
->info
->is_branch
||
4568 inst
->op
== TGSI_OPCODE_CONT
||
4569 inst
->op
== TGSI_OPCODE_END
||
4570 inst
->op
== TGSI_OPCODE_RET
) {
4574 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4575 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4576 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4577 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4578 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4579 if (inst
->dst
[0].index
>= tempWritesSize
) {
4580 const int inc
= 4096;
4582 tempWrites
= (unsigned*)
4584 (tempWritesSize
+ inc
) * sizeof(unsigned));
4588 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4589 tempWritesSize
+= inc
;
4592 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4593 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4597 /* For a CMP to be considered a conditional write, the destination
4598 * register and source register two must be the same. */
4599 if (inst
->op
== TGSI_OPCODE_CMP
4600 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4601 && inst
->src
[2].file
== inst
->dst
[0].file
4602 && inst
->src
[2].index
== inst
->dst
[0].index
4603 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4605 inst
->op
= TGSI_OPCODE_MOV
;
4606 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4607 inst
->src
[0] = inst
->src
[1];
4615 rename_temp_handle_src(struct rename_reg_pair
*renames
,
4616 struct st_src_reg
*src
)
4618 if (src
&& src
->file
== PROGRAM_TEMPORARY
) {
4619 int old_idx
= src
->index
;
4620 if (renames
[old_idx
].valid
)
4621 src
->index
= renames
[old_idx
].new_reg
;
4625 /* Replaces all references to a temporary register index with another index. */
4627 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4629 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4631 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4632 rename_temp_handle_src(renames
, &inst
->src
[j
]);
4633 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr
);
4634 rename_temp_handle_src(renames
, inst
->src
[j
].reladdr2
);
4637 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4638 rename_temp_handle_src(renames
, &inst
->tex_offsets
[j
]);
4639 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr
);
4640 rename_temp_handle_src(renames
, inst
->tex_offsets
[j
].reladdr2
);
4643 rename_temp_handle_src(renames
, &inst
->resource
);
4644 rename_temp_handle_src(renames
, inst
->resource
.reladdr
);
4645 rename_temp_handle_src(renames
, inst
->resource
.reladdr2
);
4647 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4648 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4649 int old_idx
= inst
->dst
[j
].index
;
4650 if (renames
[old_idx
].valid
)
4651 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;
4653 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr
);
4654 rename_temp_handle_src(renames
, inst
->dst
[j
].reladdr2
);
4660 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4662 int depth
= 0; /* loop depth */
4663 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4666 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4667 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4668 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4669 if (first_writes
[inst
->dst
[j
].index
] == -1)
4670 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4674 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4677 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4687 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4689 int depth
= 0; /* loop depth */
4690 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4693 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4694 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4695 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4696 if (first_reads
[inst
->src
[j
].index
] == -1)
4697 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4700 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4701 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4702 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4703 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4706 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4709 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4719 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4721 int depth
= 0; /* loop depth */
4722 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4725 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4726 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4727 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4728 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4730 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4731 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4732 if (first_writes
[inst
->dst
[j
].index
] == -1)
4733 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4734 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4737 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4738 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4739 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4741 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4744 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4747 for (k
= 0; k
< this->next_temp
; k
++) {
4748 if (last_reads
[k
] == -2) {
4760 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4762 int depth
= 0; /* loop depth */
4766 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4767 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4768 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4769 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4772 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4774 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4776 for (k
= 0; k
< this->next_temp
; k
++) {
4777 if (last_writes
[k
] == -2) {
4788 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4789 * channels for copy propagation and updates following instructions to
4790 * use the original versions.
4792 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4793 * will occur. As an example, a TXP production before this pass:
4795 * 0: MOV TEMP[1], INPUT[4].xyyy;
4796 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4797 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4801 * 0: MOV TEMP[1], INPUT[4].xyyy;
4802 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4803 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4805 * which allows for dead code elimination on TEMP[1]'s writes.
4808 glsl_to_tgsi_visitor::copy_propagate(void)
4810 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4811 glsl_to_tgsi_instruction
*,
4812 this->next_temp
* 4);
4813 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4816 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4817 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4818 || inst
->dst
[0].index
< this->next_temp
);
4820 /* First, do any copy propagation possible into the src regs. */
4821 for (int r
= 0; r
< 3; r
++) {
4822 glsl_to_tgsi_instruction
*first
= NULL
;
4824 int acp_base
= inst
->src
[r
].index
* 4;
4826 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4827 inst
->src
[r
].reladdr
||
4828 inst
->src
[r
].reladdr2
)
4831 /* See if we can find entries in the ACP consisting of MOVs
4832 * from the same src register for all the swizzled channels
4833 * of this src register reference.
4835 for (int i
= 0; i
< 4; i
++) {
4836 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4837 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4844 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4849 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4850 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4851 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4852 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4860 /* We've now validated that we can copy-propagate to
4861 * replace this src register reference. Do it.
4863 inst
->src
[r
].file
= first
->src
[0].file
;
4864 inst
->src
[r
].index
= first
->src
[0].index
;
4865 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4866 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4867 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4868 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4871 for (int i
= 0; i
< 4; i
++) {
4872 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4873 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4874 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4876 inst
->src
[r
].swizzle
= swizzle
;
4881 case TGSI_OPCODE_BGNLOOP
:
4882 case TGSI_OPCODE_ENDLOOP
:
4883 /* End of a basic block, clear the ACP entirely. */
4884 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4887 case TGSI_OPCODE_IF
:
4888 case TGSI_OPCODE_UIF
:
4892 case TGSI_OPCODE_ENDIF
:
4893 case TGSI_OPCODE_ELSE
:
4894 /* Clear all channels written inside the block from the ACP, but
4895 * leaving those that were not touched.
4897 for (int r
= 0; r
< this->next_temp
; r
++) {
4898 for (int c
= 0; c
< 4; c
++) {
4899 if (!acp
[4 * r
+ c
])
4902 if (acp_level
[4 * r
+ c
] >= level
)
4903 acp
[4 * r
+ c
] = NULL
;
4906 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4911 /* Continuing the block, clear any written channels from
4914 for (int d
= 0; d
< 2; d
++) {
4915 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4916 /* Any temporary might be written, so no copy propagation
4917 * across this instruction.
4919 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4920 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4921 inst
->dst
[d
].reladdr
) {
4922 /* Any output might be written, so no copy propagation
4923 * from outputs across this instruction.
4925 for (int r
= 0; r
< this->next_temp
; r
++) {
4926 for (int c
= 0; c
< 4; c
++) {
4927 if (!acp
[4 * r
+ c
])
4930 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4931 acp
[4 * r
+ c
] = NULL
;
4934 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4935 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4936 /* Clear where it's used as dst. */
4937 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4938 for (int c
= 0; c
< 4; c
++) {
4939 if (inst
->dst
[d
].writemask
& (1 << c
))
4940 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4944 /* Clear where it's used as src. */
4945 for (int r
= 0; r
< this->next_temp
; r
++) {
4946 for (int c
= 0; c
< 4; c
++) {
4947 if (!acp
[4 * r
+ c
])
4950 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4952 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4953 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4954 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4955 acp
[4 * r
+ c
] = NULL
;
4964 /* If this is a copy, add it to the ACP. */
4965 if (inst
->op
== TGSI_OPCODE_MOV
&&
4966 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4967 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4968 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4969 !inst
->dst
[0].reladdr
&&
4970 !inst
->dst
[0].reladdr2
&&
4972 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4973 (inst
->src
[0].file
!= PROGRAM_OUTPUT
||
4974 this->shader
->Stage
!= MESA_SHADER_TESS_CTRL
) &&
4975 !inst
->src
[0].reladdr
&&
4976 !inst
->src
[0].reladdr2
&&
4977 !inst
->src
[0].negate
&&
4978 !inst
->src
[0].abs
) {
4979 for (int i
= 0; i
< 4; i
++) {
4980 if (inst
->dst
[0].writemask
& (1 << i
)) {
4981 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4982 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4988 ralloc_free(acp_level
);
4993 dead_code_handle_reladdr(glsl_to_tgsi_instruction
**writes
, st_src_reg
*reladdr
)
4995 if (reladdr
&& reladdr
->file
== PROGRAM_TEMPORARY
) {
4996 /* Clear where it's used as src. */
4997 int swz
= GET_SWZ(reladdr
->swizzle
, 0);
4998 writes
[4 * reladdr
->index
+ swz
] = NULL
;
5003 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5006 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5007 * will occur. As an example, a TXP production after copy propagation but
5010 * 0: MOV TEMP[1], INPUT[4].xyyy;
5011 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5012 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5014 * and after this pass:
5016 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5019 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5021 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5022 glsl_to_tgsi_instruction
*,
5023 this->next_temp
* 4);
5024 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5028 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5029 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5030 || inst
->dst
[0].index
< this->next_temp
);
5033 case TGSI_OPCODE_BGNLOOP
:
5034 case TGSI_OPCODE_ENDLOOP
:
5035 case TGSI_OPCODE_CONT
:
5036 case TGSI_OPCODE_BRK
:
5037 /* End of a basic block, clear the write array entirely.
5039 * This keeps us from killing dead code when the writes are
5040 * on either side of a loop, even when the register isn't touched
5041 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5042 * dead code of this type, so it shouldn't make a difference as long as
5043 * the dead code elimination pass in the GLSL compiler does its job.
5045 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5048 case TGSI_OPCODE_ENDIF
:
5049 case TGSI_OPCODE_ELSE
:
5050 /* Promote the recorded level of all channels written inside the
5051 * preceding if or else block to the level above the if/else block.
5053 for (int r
= 0; r
< this->next_temp
; r
++) {
5054 for (int c
= 0; c
< 4; c
++) {
5055 if (!writes
[4 * r
+ c
])
5058 if (write_level
[4 * r
+ c
] == level
)
5059 write_level
[4 * r
+ c
] = level
-1;
5062 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5066 case TGSI_OPCODE_IF
:
5067 case TGSI_OPCODE_UIF
:
5069 /* fallthrough to default case to mark the condition as read */
5071 /* Continuing the block, clear any channels from the write array that
5072 * are read by this instruction.
5074 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5075 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5076 /* Any temporary might be read, so no dead code elimination
5077 * across this instruction.
5079 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5080 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5081 /* Clear where it's used as src. */
5082 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5083 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5084 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5085 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5087 for (int c
= 0; c
< 4; c
++) {
5088 if (src_chans
& (1 << c
))
5089 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5092 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr
);
5093 dead_code_handle_reladdr(writes
, inst
->src
[i
].reladdr2
);
5095 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5096 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5097 /* Any temporary might be read, so no dead code elimination
5098 * across this instruction.
5100 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5101 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5102 /* Clear where it's used as src. */
5103 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5104 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5105 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5106 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5108 for (int c
= 0; c
< 4; c
++) {
5109 if (src_chans
& (1 << c
))
5110 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5113 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr
);
5114 dead_code_handle_reladdr(writes
, inst
->tex_offsets
[i
].reladdr2
);
5117 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5120 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5121 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5122 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5123 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5125 for (int c
= 0; c
< 4; c
++) {
5126 if (src_chans
& (1 << c
))
5127 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5130 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr
);
5131 dead_code_handle_reladdr(writes
, inst
->resource
.reladdr2
);
5133 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5134 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr
);
5135 dead_code_handle_reladdr(writes
, inst
->dst
[i
].reladdr2
);
5140 /* If this instruction writes to a temporary, add it to the write array.
5141 * If there is already an instruction in the write array for one or more
5142 * of the channels, flag that channel write as dead.
5144 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5145 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5146 !inst
->dst
[i
].reladdr
) {
5147 for (int c
= 0; c
< 4; c
++) {
5148 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5149 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5150 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5153 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5155 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5156 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5163 /* Anything still in the write array at this point is dead code. */
5164 for (int r
= 0; r
< this->next_temp
; r
++) {
5165 for (int c
= 0; c
< 4; c
++) {
5166 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5168 inst
->dead_mask
|= (1 << c
);
5172 /* Now actually remove the instructions that are completely dead and update
5173 * the writemask of other instructions with dead channels.
5175 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5176 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5178 /* No amount of dead masks should remove memory stores */
5179 if (inst
->info
->is_store
)
5182 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5187 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5188 if (inst
->dead_mask
== WRITEMASK_XY
||
5189 inst
->dead_mask
== WRITEMASK_ZW
)
5190 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5192 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5196 ralloc_free(write_level
);
5197 ralloc_free(writes
);
5202 /* merge DFRACEXP instructions into one. */
5204 glsl_to_tgsi_visitor::merge_two_dsts(void)
5206 /* We never delete inst, but we may delete its successor. */
5207 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5208 glsl_to_tgsi_instruction
*inst2
;
5210 if (num_inst_dst_regs(inst
) != 2)
5213 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5214 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5217 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5220 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5221 inst
->src
[0].index
== inst2
->src
[0].index
&&
5222 inst
->src
[0].type
== inst2
->src
[0].type
&&
5223 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5225 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5231 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5233 inst
->dst
[0] = inst2
->dst
[0];
5234 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5235 inst
->dst
[1] = inst2
->dst
[1];
5246 /* Merges temporary registers together where possible to reduce the number of
5247 * registers needed to run a program.
5249 * Produces optimal code only after copy propagation and dead code elimination
5252 glsl_to_tgsi_visitor::merge_registers(void)
5255 struct lifetime
*lifetimes
=
5256 rzalloc_array(mem_ctx
, struct lifetime
, this->next_temp
);
5258 if (get_temp_registers_required_lifetimes(mem_ctx
, &this->instructions
,
5259 this->next_temp
, lifetimes
)) {
5260 struct rename_reg_pair
*renames
=
5261 rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5262 get_temp_registers_remapping(mem_ctx
, this->next_temp
, lifetimes
, renames
);
5263 rename_temp_registers(renames
);
5264 ralloc_free(renames
);
5267 ralloc_free(lifetimes
);
5270 /* Reassign indices to temporary registers by reusing unused indices created
5271 * by optimization passes. */
5273 glsl_to_tgsi_visitor::renumber_registers(void)
5277 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5278 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5280 for (i
= 0; i
< this->next_temp
; i
++) {
5281 first_writes
[i
] = -1;
5283 get_first_temp_write(first_writes
);
5285 for (i
= 0; i
< this->next_temp
; i
++) {
5286 if (first_writes
[i
] < 0) continue;
5287 if (i
!= new_index
) {
5288 renames
[i
].new_reg
= new_index
;
5289 renames
[i
].valid
= true;
5294 rename_temp_registers(renames
);
5295 this->next_temp
= new_index
;
5296 ralloc_free(renames
);
5297 ralloc_free(first_writes
);
5300 /* ------------------------- TGSI conversion stuff -------------------------- */
5303 * Intermediate state used during shader translation.
5305 struct st_translate
{
5306 struct ureg_program
*ureg
;
5308 unsigned temps_size
;
5309 struct ureg_dst
*temps
;
5311 struct ureg_dst
*arrays
;
5312 unsigned num_temp_arrays
;
5313 struct ureg_src
*constants
;
5315 struct ureg_src
*immediates
;
5317 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5318 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5319 struct ureg_dst address
[3];
5320 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5321 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5322 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5323 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5324 struct ureg_src shared_memory
;
5325 unsigned *array_sizes
;
5326 struct inout_decl
*input_decls
;
5327 unsigned num_input_decls
;
5328 struct inout_decl
*output_decls
;
5329 unsigned num_output_decls
;
5331 const ubyte
*inputMapping
;
5332 const ubyte
*outputMapping
;
5334 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5338 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5340 _mesa_sysval_to_semantic(unsigned sysval
)
5344 case SYSTEM_VALUE_VERTEX_ID
:
5345 return TGSI_SEMANTIC_VERTEXID
;
5346 case SYSTEM_VALUE_INSTANCE_ID
:
5347 return TGSI_SEMANTIC_INSTANCEID
;
5348 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5349 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5350 case SYSTEM_VALUE_BASE_VERTEX
:
5351 return TGSI_SEMANTIC_BASEVERTEX
;
5352 case SYSTEM_VALUE_BASE_INSTANCE
:
5353 return TGSI_SEMANTIC_BASEINSTANCE
;
5354 case SYSTEM_VALUE_DRAW_ID
:
5355 return TGSI_SEMANTIC_DRAWID
;
5357 /* Geometry shader */
5358 case SYSTEM_VALUE_INVOCATION_ID
:
5359 return TGSI_SEMANTIC_INVOCATIONID
;
5361 /* Fragment shader */
5362 case SYSTEM_VALUE_FRAG_COORD
:
5363 return TGSI_SEMANTIC_POSITION
;
5364 case SYSTEM_VALUE_FRONT_FACE
:
5365 return TGSI_SEMANTIC_FACE
;
5366 case SYSTEM_VALUE_SAMPLE_ID
:
5367 return TGSI_SEMANTIC_SAMPLEID
;
5368 case SYSTEM_VALUE_SAMPLE_POS
:
5369 return TGSI_SEMANTIC_SAMPLEPOS
;
5370 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5371 return TGSI_SEMANTIC_SAMPLEMASK
;
5372 case SYSTEM_VALUE_HELPER_INVOCATION
:
5373 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5375 /* Tessellation shader */
5376 case SYSTEM_VALUE_TESS_COORD
:
5377 return TGSI_SEMANTIC_TESSCOORD
;
5378 case SYSTEM_VALUE_VERTICES_IN
:
5379 return TGSI_SEMANTIC_VERTICESIN
;
5380 case SYSTEM_VALUE_PRIMITIVE_ID
:
5381 return TGSI_SEMANTIC_PRIMID
;
5382 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5383 return TGSI_SEMANTIC_TESSOUTER
;
5384 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5385 return TGSI_SEMANTIC_TESSINNER
;
5387 /* Compute shader */
5388 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5389 return TGSI_SEMANTIC_THREAD_ID
;
5390 case SYSTEM_VALUE_WORK_GROUP_ID
:
5391 return TGSI_SEMANTIC_BLOCK_ID
;
5392 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5393 return TGSI_SEMANTIC_GRID_SIZE
;
5394 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5395 return TGSI_SEMANTIC_BLOCK_SIZE
;
5397 /* ARB_shader_ballot */
5398 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5399 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5400 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5401 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5402 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5403 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5404 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5405 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5406 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5407 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5408 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5409 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5410 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5411 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5414 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5415 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5416 case SYSTEM_VALUE_VERTEX_CNT
:
5418 assert(!"Unexpected SYSTEM_VALUE_ enum");
5419 return TGSI_SEMANTIC_COUNT
;
5424 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5426 static struct ureg_src
5427 emit_immediate(struct st_translate
*t
,
5428 gl_constant_value values
[4],
5431 struct ureg_program
*ureg
= t
->ureg
;
5436 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5438 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5440 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5441 case GL_UNSIGNED_INT64_ARB
:
5442 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5444 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5445 case GL_UNSIGNED_INT
:
5447 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5449 assert(!"should not get here - type must be float, int, uint, or bool");
5450 return ureg_src_undef();
5455 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5457 static struct ureg_dst
5458 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5464 case PROGRAM_UNDEFINED
:
5465 return ureg_dst_undef();
5467 case PROGRAM_TEMPORARY
:
5468 /* Allocate space for temporaries on demand. */
5469 if (index
>= t
->temps_size
) {
5470 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5472 t
->temps
= (struct ureg_dst
*)
5474 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5476 return ureg_dst_undef();
5478 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5479 t
->temps_size
+= inc
;
5482 if (ureg_dst_is_undef(t
->temps
[index
]))
5483 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5485 return t
->temps
[index
];
5488 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5489 array
= array_id
- 1;
5491 if (ureg_dst_is_undef(t
->arrays
[array
]))
5492 t
->arrays
[array
] = ureg_DECL_array_temporary(
5493 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5495 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5497 case PROGRAM_OUTPUT
:
5499 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5500 assert(index
< 2 * FRAG_RESULT_MAX
);
5501 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5502 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5503 assert(index
< VARYING_SLOT_TESS_MAX
);
5505 assert(index
< VARYING_SLOT_MAX
);
5507 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5508 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5509 return t
->outputs
[t
->outputMapping
[index
]];
5512 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5513 unsigned mesa_index
= decl
->mesa_index
;
5514 int slot
= t
->outputMapping
[mesa_index
];
5516 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5518 struct ureg_dst dst
= t
->outputs
[slot
];
5519 dst
.ArrayID
= array_id
;
5520 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5523 case PROGRAM_ADDRESS
:
5524 return t
->address
[index
];
5527 assert(!"unknown dst register file");
5528 return ureg_dst_undef();
5532 static struct ureg_src
5533 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
);
5535 static struct ureg_src
5536 translate_addr(struct st_translate
*t
, const st_src_reg
*reladdr
,
5537 unsigned addr_index
)
5539 if (t
->need_uarl
|| !reladdr
->is_legal_tgsi_address_operand())
5540 return ureg_src(t
->address
[addr_index
]);
5542 return translate_src(t
, reladdr
);
5546 * Create a TGSI ureg_dst register from an st_dst_reg.
5548 static struct ureg_dst
5549 translate_dst(struct st_translate
*t
,
5550 const st_dst_reg
*dst_reg
,
5553 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5556 if (dst
.File
== TGSI_FILE_NULL
)
5559 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5562 dst
= ureg_saturate(dst
);
5564 if (dst_reg
->reladdr
!= NULL
) {
5565 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5566 dst
= ureg_dst_indirect(dst
, translate_addr(t
, dst_reg
->reladdr
, 0));
5569 if (dst_reg
->has_index2
) {
5570 if (dst_reg
->reladdr2
)
5571 dst
= ureg_dst_dimension_indirect(dst
,
5572 translate_addr(t
, dst_reg
->reladdr2
, 1),
5575 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5582 * Create a TGSI ureg_src register from an st_src_reg.
5584 static struct ureg_src
5585 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5587 struct ureg_src src
;
5588 int index
= src_reg
->index
;
5589 int double_reg2
= src_reg
->double_reg2
? 1 : 0;
5591 switch(src_reg
->file
) {
5592 case PROGRAM_UNDEFINED
:
5593 src
= ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5596 case PROGRAM_TEMPORARY
:
5598 src
= ureg_src(dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
));
5601 case PROGRAM_OUTPUT
: {
5602 struct ureg_dst dst
= dst_register(t
, src_reg
->file
, src_reg
->index
, src_reg
->array_id
);
5603 assert(dst
.WriteMask
!= 0);
5604 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5605 src
= ureg_swizzle(ureg_src(dst
),
5609 MIN2(shift
+ 3, 3));
5613 case PROGRAM_UNIFORM
:
5614 assert(src_reg
->index
>= 0);
5615 src
= src_reg
->index
< t
->num_constants
?
5616 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5618 case PROGRAM_STATE_VAR
:
5619 case PROGRAM_CONSTANT
: /* ie, immediate */
5620 if (src_reg
->has_index2
)
5621 src
= ureg_src_register(TGSI_FILE_CONSTANT
, src_reg
->index
);
5623 src
= src_reg
->index
>= 0 && src_reg
->index
< t
->num_constants
?
5624 t
->constants
[src_reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5627 case PROGRAM_IMMEDIATE
:
5628 assert(src_reg
->index
>= 0 && src_reg
->index
< t
->num_immediates
);
5629 src
= t
->immediates
[src_reg
->index
];
5633 /* GLSL inputs are 64-bit containers, so we have to
5634 * map back to the original index and add the offset after
5636 index
-= double_reg2
;
5637 if (!src_reg
->array_id
) {
5638 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5639 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5640 src
= t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5643 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
,
5645 unsigned mesa_index
= decl
->mesa_index
;
5646 int slot
= t
->inputMapping
[mesa_index
];
5648 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5650 src
= t
->inputs
[slot
];
5651 src
.ArrayID
= src_reg
->array_id
;
5652 src
= ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5656 case PROGRAM_ADDRESS
:
5657 src
= ureg_src(t
->address
[src_reg
->index
]);
5660 case PROGRAM_SYSTEM_VALUE
:
5661 assert(src_reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5662 src
= t
->systemValues
[src_reg
->index
];
5666 assert(!"unknown src register file");
5667 return ureg_src_undef();
5670 if (src_reg
->has_index2
) {
5671 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5672 * and UBO constant buffers (buffer, position).
5674 if (src_reg
->reladdr2
)
5675 src
= ureg_src_dimension_indirect(src
,
5676 translate_addr(t
, src_reg
->reladdr2
, 1),
5679 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5682 src
= ureg_swizzle(src
,
5683 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5684 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5685 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5686 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5689 src
= ureg_abs(src
);
5691 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5692 src
= ureg_negate(src
);
5694 if (src_reg
->reladdr
!= NULL
) {
5695 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5696 src
= ureg_src_indirect(src
, translate_addr(t
, src_reg
->reladdr
, 0));
5702 static struct tgsi_texture_offset
5703 translate_tex_offset(struct st_translate
*t
,
5704 const st_src_reg
*in_offset
)
5706 struct tgsi_texture_offset offset
;
5707 struct ureg_src src
= translate_src(t
, in_offset
);
5709 offset
.File
= src
.File
;
5710 offset
.Index
= src
.Index
;
5711 offset
.SwizzleX
= src
.SwizzleX
;
5712 offset
.SwizzleY
= src
.SwizzleY
;
5713 offset
.SwizzleZ
= src
.SwizzleZ
;
5716 assert(!src
.Indirect
);
5717 assert(!src
.DimIndirect
);
5718 assert(!src
.Dimension
);
5719 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5720 assert(!src
.Negate
);
5726 compile_tgsi_instruction(struct st_translate
*t
,
5727 const glsl_to_tgsi_instruction
*inst
)
5729 struct ureg_program
*ureg
= t
->ureg
;
5731 struct ureg_dst dst
[2];
5732 struct ureg_src src
[4];
5733 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5737 unsigned tex_target
= 0;
5739 num_dst
= num_inst_dst_regs(inst
);
5740 num_src
= num_inst_src_regs(inst
);
5742 for (i
= 0; i
< num_dst
; i
++)
5743 dst
[i
] = translate_dst(t
,
5747 for (i
= 0; i
< num_src
; i
++)
5748 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5751 case TGSI_OPCODE_BGNLOOP
:
5752 case TGSI_OPCODE_ELSE
:
5753 case TGSI_OPCODE_ENDLOOP
:
5754 case TGSI_OPCODE_IF
:
5755 case TGSI_OPCODE_UIF
:
5756 assert(num_dst
== 0);
5757 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
, inst
->precise
);
5760 case TGSI_OPCODE_TEX
:
5761 case TGSI_OPCODE_TEX_LZ
:
5762 case TGSI_OPCODE_TXB
:
5763 case TGSI_OPCODE_TXD
:
5764 case TGSI_OPCODE_TXL
:
5765 case TGSI_OPCODE_TXP
:
5766 case TGSI_OPCODE_TXQ
:
5767 case TGSI_OPCODE_TXQS
:
5768 case TGSI_OPCODE_TXF
:
5769 case TGSI_OPCODE_TXF_LZ
:
5770 case TGSI_OPCODE_TEX2
:
5771 case TGSI_OPCODE_TXB2
:
5772 case TGSI_OPCODE_TXL2
:
5773 case TGSI_OPCODE_TG4
:
5774 case TGSI_OPCODE_LODQ
:
5775 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5776 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5778 /* Bindless samplers. */
5779 src
[num_src
] = translate_src(t
, &inst
->resource
);
5781 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5782 if (inst
->resource
.reladdr
)
5784 ureg_src_indirect(src
[num_src
],
5785 translate_addr(t
, inst
->resource
.reladdr
, 2));
5787 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5788 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5790 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5796 st_translate_texture_type(inst
->tex_type
),
5797 texoffsets
, inst
->tex_offset_num_offset
,
5801 case TGSI_OPCODE_RESQ
:
5802 case TGSI_OPCODE_LOAD
:
5803 case TGSI_OPCODE_ATOMUADD
:
5804 case TGSI_OPCODE_ATOMXCHG
:
5805 case TGSI_OPCODE_ATOMCAS
:
5806 case TGSI_OPCODE_ATOMAND
:
5807 case TGSI_OPCODE_ATOMOR
:
5808 case TGSI_OPCODE_ATOMXOR
:
5809 case TGSI_OPCODE_ATOMUMIN
:
5810 case TGSI_OPCODE_ATOMUMAX
:
5811 case TGSI_OPCODE_ATOMIMIN
:
5812 case TGSI_OPCODE_ATOMIMAX
:
5813 for (i
= num_src
- 1; i
>= 0; i
--)
5814 src
[i
+ 1] = src
[i
];
5816 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5817 src
[0] = t
->shared_memory
;
5818 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5819 src
[0] = t
->buffers
[inst
->resource
.index
];
5820 } else if (inst
->resource
.file
== PROGRAM_CONSTANT
) {
5821 assert(inst
->resource
.has_index2
);
5822 src
[0] = ureg_src_register(TGSI_FILE_CONSTBUF
, inst
->resource
.index
);
5824 assert(inst
->resource
.file
!= PROGRAM_UNDEFINED
);
5825 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5826 src
[0] = t
->images
[inst
->resource
.index
];
5828 /* Bindless images. */
5829 src
[0] = translate_src(t
, &inst
->resource
);
5831 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5833 if (inst
->resource
.reladdr
)
5834 src
[0] = ureg_src_indirect(src
[0],
5835 translate_addr(t
, inst
->resource
.reladdr
, 2));
5836 assert(src
[0].File
!= TGSI_FILE_NULL
);
5837 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5838 inst
->buffer_access
,
5839 tex_target
, inst
->image_format
);
5842 case TGSI_OPCODE_STORE
:
5843 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5844 dst
[0] = ureg_dst(t
->shared_memory
);
5845 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5846 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5848 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
5849 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5851 /* Bindless images. */
5852 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
5854 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5856 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5857 if (inst
->resource
.reladdr
)
5858 dst
[0] = ureg_dst_indirect(dst
[0],
5859 translate_addr(t
, inst
->resource
.reladdr
, 2));
5860 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5861 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5862 inst
->buffer_access
,
5863 tex_target
, inst
->image_format
);
5870 src
, num_src
, inst
->precise
);
5876 * Emit the TGSI instructions for inverting and adjusting WPOS.
5877 * This code is unavoidable because it also depends on whether
5878 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5881 emit_wpos_adjustment(struct gl_context
*ctx
,
5882 struct st_translate
*t
,
5883 int wpos_transform_const
,
5885 GLfloat adjX
, GLfloat adjY
[2])
5887 struct ureg_program
*ureg
= t
->ureg
;
5889 assert(wpos_transform_const
>= 0);
5891 /* Fragment program uses fragment position input.
5892 * Need to replace instances of INPUT[WPOS] with temp T
5893 * where T = INPUT[WPOS] is inverted by Y.
5895 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5896 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5897 struct ureg_src
*wpos
=
5898 ctx
->Const
.GLSLFragCoordIsSysVal
?
5899 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5900 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5901 struct ureg_src wpos_input
= *wpos
;
5903 /* First, apply the coordinate shift: */
5904 if (adjX
|| adjY
[0] || adjY
[1]) {
5905 if (adjY
[0] != adjY
[1]) {
5906 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5907 * depending on whether inversion is actually going to be applied
5908 * or not, which is determined by testing against the inversion
5909 * state variable used below, which will be either +1 or -1.
5911 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5913 ureg_CMP(ureg
, adj_temp
,
5914 ureg_scalar(wpostrans
, invert
? 2 : 0),
5915 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5916 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5917 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5919 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5920 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5922 wpos_input
= ureg_src(wpos_temp
);
5924 /* MOV wpos_temp, input[wpos]
5926 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5929 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5930 * inversion/identity, or the other way around if we're drawing to an FBO.
5933 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5936 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5938 ureg_scalar(wpostrans
, 0),
5939 ureg_scalar(wpostrans
, 1));
5941 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5944 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5946 ureg_scalar(wpostrans
, 2),
5947 ureg_scalar(wpostrans
, 3));
5950 /* Use wpos_temp as position input from here on:
5952 *wpos
= ureg_src(wpos_temp
);
5957 * Emit fragment position/ooordinate code.
5960 emit_wpos(struct st_context
*st
,
5961 struct st_translate
*t
,
5962 const struct gl_program
*program
,
5963 struct ureg_program
*ureg
,
5964 int wpos_transform_const
)
5966 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5967 GLfloat adjX
= 0.0f
;
5968 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5969 boolean invert
= FALSE
;
5971 /* Query the pixel center conventions supported by the pipe driver and set
5972 * adjX, adjY to help out if it cannot handle the requested one internally.
5974 * The bias of the y-coordinate depends on whether y-inversion takes place
5975 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5976 * drawing to an FBO (causes additional inversion), and whether the pipe
5977 * driver origin and the requested origin differ (the latter condition is
5978 * stored in the 'invert' variable).
5980 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5982 * center shift only:
5987 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5988 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5989 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5990 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5992 * inversion and center shift:
5993 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5994 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5995 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5996 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5998 if (program
->OriginUpperLeft
) {
5999 /* Fragment shader wants origin in upper-left */
6000 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6001 /* the driver supports upper-left origin */
6003 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6004 /* the driver supports lower-left origin, need to invert Y */
6005 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6006 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6013 /* Fragment shader wants origin in lower-left */
6014 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6015 /* the driver supports lower-left origin */
6016 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6017 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6018 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6019 /* the driver supports upper-left origin, need to invert Y */
6025 if (program
->PixelCenterInteger
) {
6026 /* Fragment shader wants pixel center integer */
6027 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6028 /* the driver supports pixel center integer */
6030 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6031 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6033 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6034 /* the driver supports pixel center half integer, need to bias X,Y */
6043 /* Fragment shader wants pixel center half integer */
6044 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6045 /* the driver supports pixel center half integer */
6047 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6048 /* the driver supports pixel center integer, need to bias X,Y */
6049 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6050 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6051 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6057 /* we invert after adjustment so that we avoid the MOV to temporary,
6058 * and reuse the adjustment ADD instead */
6059 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6063 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6064 * TGSI uses +1 for front, -1 for back.
6065 * This function converts the TGSI value to the GL value. Simply clamping/
6066 * saturating the value to [0,1] does the job.
6069 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6071 struct ureg_program
*ureg
= t
->ureg
;
6072 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6073 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6075 if (ctx
->Const
.NativeIntegers
) {
6076 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6079 /* MOV_SAT face_temp, input[face] */
6080 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6083 /* Use face_temp as face input from here on: */
6084 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6088 emit_compute_block_size(const struct gl_program
*prog
,
6089 struct ureg_program
*ureg
) {
6090 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6091 prog
->info
.cs
.local_size
[0]);
6092 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6093 prog
->info
.cs
.local_size
[1]);
6094 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6095 prog
->info
.cs
.local_size
[2]);
6098 struct sort_inout_decls
{
6099 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6100 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6103 const ubyte
*mapping
;
6106 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6108 * This is for the benefit of older drivers which are broken when the
6109 * declarations aren't sorted in this way.
6112 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6114 const ubyte mapping
[])
6116 sort_inout_decls sorter
;
6117 sorter
.mapping
= mapping
;
6118 std::sort(decls
, decls
+ count
, sorter
);
6122 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6124 switch (glsl_qual
) {
6125 case INTERP_MODE_NONE
:
6126 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6127 return TGSI_INTERPOLATE_COLOR
;
6128 return TGSI_INTERPOLATE_PERSPECTIVE
;
6129 case INTERP_MODE_SMOOTH
:
6130 return TGSI_INTERPOLATE_PERSPECTIVE
;
6131 case INTERP_MODE_FLAT
:
6132 return TGSI_INTERPOLATE_CONSTANT
;
6133 case INTERP_MODE_NOPERSPECTIVE
:
6134 return TGSI_INTERPOLATE_LINEAR
;
6136 assert(0 && "unexpected interp mode in st_translate_interp()");
6137 return TGSI_INTERPOLATE_PERSPECTIVE
;
6142 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6143 * \param program the program to translate
6144 * \param numInputs number of input registers used
6145 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6147 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6148 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6150 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6151 * \param numOutputs number of output registers used
6152 * \param outputMapping maps Mesa fragment program outputs to TGSI
6154 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6155 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6158 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6160 extern "C" enum pipe_error
6161 st_translate_program(
6162 struct gl_context
*ctx
,
6164 struct ureg_program
*ureg
,
6165 glsl_to_tgsi_visitor
*program
,
6166 const struct gl_program
*proginfo
,
6168 const ubyte inputMapping
[],
6169 const ubyte inputSlotToAttr
[],
6170 const ubyte inputSemanticName
[],
6171 const ubyte inputSemanticIndex
[],
6172 const ubyte interpMode
[],
6174 const ubyte outputMapping
[],
6175 const ubyte outputSemanticName
[],
6176 const ubyte outputSemanticIndex
[])
6178 struct pipe_screen
*screen
= st_context(ctx
)->pipe
->screen
;
6179 struct st_translate
*t
;
6181 struct gl_program_constants
*frag_const
=
6182 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6183 enum pipe_error ret
= PIPE_OK
;
6185 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6186 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6188 t
= CALLOC_STRUCT(st_translate
);
6190 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6194 t
->procType
= procType
;
6195 t
->need_uarl
= !screen
->get_param(screen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6196 t
->inputMapping
= inputMapping
;
6197 t
->outputMapping
= outputMapping
;
6199 t
->num_temp_arrays
= program
->next_array
;
6200 if (t
->num_temp_arrays
)
6201 t
->arrays
= (struct ureg_dst
*)
6202 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6205 * Declare input attributes.
6208 case PIPE_SHADER_FRAGMENT
:
6209 case PIPE_SHADER_GEOMETRY
:
6210 case PIPE_SHADER_TESS_EVAL
:
6211 case PIPE_SHADER_TESS_CTRL
:
6212 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6214 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6215 struct inout_decl
*decl
= &program
->inputs
[i
];
6216 unsigned slot
= inputMapping
[decl
->mesa_index
];
6217 struct ureg_src src
;
6218 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6220 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6221 if (tgsi_usage_mask
== 1)
6222 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6223 else if (tgsi_usage_mask
== 2)
6224 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6226 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6229 unsigned interp_mode
= 0;
6230 unsigned interp_location
= 0;
6231 if (procType
== PIPE_SHADER_FRAGMENT
) {
6233 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6235 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6237 interp_location
= decl
->interp_loc
;
6240 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6241 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6242 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6243 decl
->array_id
, decl
->size
);
6245 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6246 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6247 /* The ArrayID is set up in dst_register */
6248 t
->inputs
[slot
+ j
] = src
;
6249 t
->inputs
[slot
+ j
].ArrayID
= 0;
6250 t
->inputs
[slot
+ j
].Index
+= j
;
6255 case PIPE_SHADER_VERTEX
:
6256 for (i
= 0; i
< numInputs
; i
++) {
6257 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6260 case PIPE_SHADER_COMPUTE
:
6267 * Declare output attributes.
6270 case PIPE_SHADER_FRAGMENT
:
6271 case PIPE_SHADER_COMPUTE
:
6273 case PIPE_SHADER_GEOMETRY
:
6274 case PIPE_SHADER_TESS_EVAL
:
6275 case PIPE_SHADER_TESS_CTRL
:
6276 case PIPE_SHADER_VERTEX
:
6277 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6279 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6280 struct inout_decl
*decl
= &program
->outputs
[i
];
6281 unsigned slot
= outputMapping
[decl
->mesa_index
];
6282 struct ureg_dst dst
;
6283 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6285 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6286 if (tgsi_usage_mask
== 1)
6287 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6288 else if (tgsi_usage_mask
== 2)
6289 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6291 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6294 dst
= ureg_DECL_output_layout(ureg
,
6295 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6296 decl
->gs_out_streams
,
6297 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6299 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6300 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6301 /* The ArrayID is set up in dst_register */
6302 t
->outputs
[slot
+ j
] = dst
;
6303 t
->outputs
[slot
+ j
].ArrayID
= 0;
6304 t
->outputs
[slot
+ j
].Index
+= j
;
6313 if (procType
== PIPE_SHADER_FRAGMENT
) {
6314 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6315 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6316 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6318 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6319 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6322 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6323 /* Must do this after setting up t->inputs. */
6324 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6325 program
->wpos_transform_const
);
6328 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6329 emit_face_var(ctx
, t
);
6331 for (i
= 0; i
< numOutputs
; i
++) {
6332 switch (outputSemanticName
[i
]) {
6333 case TGSI_SEMANTIC_POSITION
:
6334 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6335 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6336 outputSemanticIndex
[i
]);
6337 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6339 case TGSI_SEMANTIC_STENCIL
:
6340 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6341 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6342 outputSemanticIndex
[i
]);
6343 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6345 case TGSI_SEMANTIC_COLOR
:
6346 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6347 TGSI_SEMANTIC_COLOR
,
6348 outputSemanticIndex
[i
]);
6350 case TGSI_SEMANTIC_SAMPLEMASK
:
6351 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6352 TGSI_SEMANTIC_SAMPLEMASK
,
6353 outputSemanticIndex
[i
]);
6354 /* TODO: If we ever support more than 32 samples, this will have
6355 * to become an array.
6357 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6360 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6361 ret
= PIPE_ERROR_BAD_INPUT
;
6366 else if (procType
== PIPE_SHADER_VERTEX
) {
6367 for (i
= 0; i
< numOutputs
; i
++) {
6368 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6369 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6371 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6372 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6373 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6378 if (procType
== PIPE_SHADER_COMPUTE
) {
6379 emit_compute_block_size(proginfo
, ureg
);
6382 /* Declare address register.
6384 if (program
->num_address_regs
> 0) {
6385 assert(program
->num_address_regs
<= 3);
6386 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6387 t
->address
[i
] = ureg_DECL_address(ureg
);
6390 /* Declare misc input registers
6393 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6395 for (i
= 0; sysInputs
; i
++) {
6396 if (sysInputs
& (1 << i
)) {
6397 unsigned semName
= _mesa_sysval_to_semantic(i
);
6399 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6401 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6402 semName
== TGSI_SEMANTIC_VERTEXID
) {
6403 /* From Gallium perspective, these system values are always
6404 * integer, and require native integer support. However, if
6405 * native integer is supported on the vertex stage but not the
6406 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6407 * assumes these system values are floats. To resolve the
6408 * inconsistency, we insert a U2F.
6410 struct st_context
*st
= st_context(ctx
);
6411 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6412 assert(procType
== PIPE_SHADER_VERTEX
);
6413 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6415 if (!ctx
->Const
.NativeIntegers
) {
6416 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6417 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6418 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6422 if (procType
== PIPE_SHADER_FRAGMENT
&&
6423 semName
== TGSI_SEMANTIC_POSITION
)
6424 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6425 program
->wpos_transform_const
);
6427 sysInputs
&= ~(1 << i
);
6432 t
->array_sizes
= program
->array_sizes
;
6433 t
->input_decls
= program
->inputs
;
6434 t
->num_input_decls
= program
->num_inputs
;
6435 t
->output_decls
= program
->outputs
;
6436 t
->num_output_decls
= program
->num_outputs
;
6438 /* Emit constants and uniforms. TGSI uses a single index space for these,
6439 * so we put all the translated regs in t->constants.
6441 if (proginfo
->Parameters
) {
6442 t
->constants
= (struct ureg_src
*)
6443 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6444 if (t
->constants
== NULL
) {
6445 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6448 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6450 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6451 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6452 case PROGRAM_STATE_VAR
:
6453 case PROGRAM_UNIFORM
:
6454 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6457 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6458 * addressing of the const buffer.
6459 * FIXME: Be smarter and recognize param arrays:
6460 * indirect addressing is only valid within the referenced
6463 case PROGRAM_CONSTANT
:
6464 if (program
->indirect_addr_consts
)
6465 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6467 t
->constants
[i
] = emit_immediate(t
,
6468 proginfo
->Parameters
->ParameterValues
[i
],
6469 proginfo
->Parameters
->Parameters
[i
].DataType
,
6478 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6479 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6480 unsigned num_const_vecs
= (size
+ 15) / 16;
6481 unsigned first
, last
;
6482 assert(num_const_vecs
> 0);
6484 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6485 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6488 /* Emit immediate values.
6490 t
->immediates
= (struct ureg_src
*)
6491 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6492 if (t
->immediates
== NULL
) {
6493 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6496 t
->num_immediates
= program
->num_immediates
;
6499 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6500 assert(i
< program
->num_immediates
);
6501 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6503 assert(i
== program
->num_immediates
);
6505 /* texture samplers */
6506 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6507 if (program
->samplers_used
& (1u << i
)) {
6508 unsigned type
= st_translate_texture_type(program
->sampler_types
[i
]);
6510 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6512 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6513 type
, type
, type
, type
);
6517 /* Declare atomic and shader storage buffers. */
6519 struct gl_program
*prog
= program
->prog
;
6521 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6522 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6523 assert(index
< frag_const
->MaxAtomicBuffers
);
6524 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6527 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6528 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6529 unsigned index
= frag_const
->MaxAtomicBuffers
+ i
;
6530 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6534 if (program
->use_shared_memory
)
6535 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6537 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6538 if (program
->images_used
& (1 << i
)) {
6539 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6540 program
->image_targets
[i
],
6541 program
->image_formats
[i
],
6546 /* Emit each instruction in turn:
6548 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6549 compile_tgsi_instruction(t
, inst
);
6551 /* Set the next shader stage hint for VS and TES. */
6553 case PIPE_SHADER_VERTEX
:
6554 case PIPE_SHADER_TESS_EVAL
:
6555 if (program
->shader_program
->SeparateShader
)
6558 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6559 if (program
->shader_program
->_LinkedShaders
[i
]) {
6560 ureg_set_next_shader_processor(
6561 ureg
, pipe_shader_type_from_mesa((gl_shader_stage
)i
));
6573 t
->num_constants
= 0;
6574 free(t
->immediates
);
6575 t
->num_immediates
= 0;
6581 /* ----------------------------- End TGSI code ------------------------------ */
6585 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6586 * generating Mesa IR.
6588 static struct gl_program
*
6589 get_mesa_program_tgsi(struct gl_context
*ctx
,
6590 struct gl_shader_program
*shader_program
,
6591 struct gl_linked_shader
*shader
)
6593 glsl_to_tgsi_visitor
* v
;
6594 struct gl_program
*prog
;
6595 struct gl_shader_compiler_options
*options
=
6596 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6597 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6598 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(shader
->Stage
);
6599 unsigned skip_merge_registers
;
6601 validate_ir_tree(shader
->ir
);
6603 prog
= shader
->Program
;
6605 prog
->Parameters
= _mesa_new_parameter_list();
6606 v
= new glsl_to_tgsi_visitor();
6609 v
->shader_program
= shader_program
;
6611 v
->options
= options
;
6612 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6613 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6615 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6616 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6617 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6618 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6619 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6620 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6621 v
->need_uarl
= !pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
);
6623 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6624 _mesa_key_pointer_equal
);
6625 skip_merge_registers
=
6626 pscreen
->get_shader_param(pscreen
, ptarget
,
6627 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6629 _mesa_generate_parameters_list_for_uniforms(ctx
, shader_program
, shader
,
6632 /* Remove reads from output registers. */
6633 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6634 lower_output_reads(shader
->Stage
, shader
->ir
);
6636 /* Emit intermediate IR for main(). */
6637 visit_exec_list(shader
->ir
, v
);
6640 /* Print out some information (for debugging purposes) used by the
6641 * optimization passes. */
6644 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6645 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6646 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6647 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6649 for (i
= 0; i
< v
->next_temp
; i
++) {
6650 first_writes
[i
] = -1;
6651 first_reads
[i
] = -1;
6652 last_writes
[i
] = -1;
6655 v
->get_first_temp_read(first_reads
);
6656 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6657 v
->get_last_temp_write(last_writes
);
6658 for (i
= 0; i
< v
->next_temp
; i
++)
6659 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6663 ralloc_free(first_writes
);
6664 ralloc_free(first_reads
);
6665 ralloc_free(last_writes
);
6666 ralloc_free(last_reads
);
6670 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6672 v
->copy_propagate();
6674 while (v
->eliminate_dead_code());
6676 v
->merge_two_dsts();
6677 if (!skip_merge_registers
)
6678 v
->merge_registers();
6679 v
->renumber_registers();
6681 /* Write the END instruction. */
6682 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6684 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6686 _mesa_log("GLSL IR for linked %s program %d:\n",
6687 _mesa_shader_stage_to_string(shader
->Stage
),
6688 shader_program
->Name
);
6689 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6693 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6694 _mesa_copy_linked_program_data(shader_program
, shader
);
6695 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6696 &prog
->info
.inputs_read
,
6697 prog
->info
.double_inputs_read
,
6698 &prog
->info
.patch_inputs_read
);
6699 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6700 &prog
->info
.outputs_written
, 0ULL,
6701 &prog
->info
.patch_outputs_written
);
6702 count_resources(v
, prog
);
6704 /* The GLSL IR won't be needed anymore. */
6705 ralloc_free(shader
->ir
);
6708 /* This must be done before the uniform storage is associated. */
6709 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6710 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6711 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6712 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6713 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6716 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6717 wposTransformState
);
6720 /* Avoid reallocation of the program parameter list, because the uniform
6721 * storage is only associated with the original parameter list.
6722 * This should be enough for Bitmap and DrawPixels constants.
6724 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6726 /* This has to be done last. Any operation the can cause
6727 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6728 * program constant) has to happen before creating this linkage.
6730 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6731 if (!shader_program
->data
->LinkStatus
) {
6732 free_glsl_to_tgsi_visitor(v
);
6733 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6737 struct st_vertex_program
*stvp
;
6738 struct st_fragment_program
*stfp
;
6739 struct st_common_program
*stp
;
6740 struct st_compute_program
*stcp
;
6742 switch (shader
->Stage
) {
6743 case MESA_SHADER_VERTEX
:
6744 stvp
= (struct st_vertex_program
*)prog
;
6745 stvp
->glsl_to_tgsi
= v
;
6747 case MESA_SHADER_FRAGMENT
:
6748 stfp
= (struct st_fragment_program
*)prog
;
6749 stfp
->glsl_to_tgsi
= v
;
6751 case MESA_SHADER_TESS_CTRL
:
6752 case MESA_SHADER_TESS_EVAL
:
6753 case MESA_SHADER_GEOMETRY
:
6754 stp
= st_common_program(prog
);
6755 stp
->glsl_to_tgsi
= v
;
6757 case MESA_SHADER_COMPUTE
:
6758 stcp
= (struct st_compute_program
*)prog
;
6759 stcp
->glsl_to_tgsi
= v
;
6762 assert(!"should not be reached");
6769 /* See if there are unsupported control flow statements. */
6770 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6772 const struct gl_shader_compiler_options
*options
;
6774 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6780 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6782 /* Other functions are skipped (same as glsl_to_tgsi). */
6783 if (strcmp(ir
->name
, "main") == 0)
6784 return visit_continue
;
6786 return visit_continue_with_parent
;
6789 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6791 if (!ir
->callee
->is_intrinsic()) {
6792 unsupported
= true; /* it's a function call */
6795 return visit_continue
;
6798 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6800 if (options
->EmitNoMainReturn
) {
6804 return visit_continue
;
6811 has_unsupported_control_flow(exec_list
*ir
,
6812 const struct gl_shader_compiler_options
*options
)
6814 ir_control_flow_info_visitor
visitor(options
);
6815 visit_list_elements(&visitor
, ir
);
6816 return visitor
.unsupported
;
6823 * Called via ctx->Driver.LinkShader()
6824 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6825 * with code lowering and other optimizations.
6828 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6830 /* Return early if we are loading the shader from on-disk cache */
6831 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
6835 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6836 assert(prog
->data
->LinkStatus
);
6838 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6839 if (prog
->_LinkedShaders
[i
] == NULL
)
6842 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6843 exec_list
*ir
= shader
->ir
;
6844 gl_shader_stage stage
= shader
->Stage
;
6845 const struct gl_shader_compiler_options
*options
=
6846 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6847 enum pipe_shader_type ptarget
= pipe_shader_type_from_mesa(stage
);
6848 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6849 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6850 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6851 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6852 bool have_ldexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6853 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
);
6854 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6855 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6857 /* If there are forms of indirect addressing that the driver
6858 * cannot handle, perform the lowering pass.
6860 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6861 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6862 lower_variable_index_to_cond_assign(stage
, ir
,
6863 options
->EmitNoIndirectInput
,
6864 options
->EmitNoIndirectOutput
,
6865 options
->EmitNoIndirectTemp
,
6866 options
->EmitNoIndirectUniform
);
6869 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
6870 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
6872 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6873 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6874 LOWER_UNPACK_SNORM_2x16
|
6875 LOWER_PACK_UNORM_2x16
|
6876 LOWER_UNPACK_UNORM_2x16
|
6877 LOWER_PACK_SNORM_4x8
|
6878 LOWER_UNPACK_SNORM_4x8
|
6879 LOWER_UNPACK_UNORM_4x8
|
6880 LOWER_PACK_UNORM_4x8
;
6882 if (ctx
->Extensions
.ARB_gpu_shader5
)
6883 lower_inst
|= LOWER_PACK_USE_BFI
|
6885 if (!ctx
->st
->has_half_float_packing
)
6886 lower_inst
|= LOWER_PACK_HALF_2x16
|
6887 LOWER_UNPACK_HALF_2x16
;
6889 lower_packing_builtins(ir
, lower_inst
);
6892 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6893 lower_offset_arrays(ir
);
6894 do_mat_op_to_vec(ir
);
6896 if (stage
== MESA_SHADER_FRAGMENT
)
6897 lower_blend_equation_advanced(shader
);
6899 lower_instructions(ir
,
6904 (have_ldexp
? 0 : LDEXP_TO_ARITH
) |
6905 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6908 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6909 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6910 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6911 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6912 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
6913 /* Assume that if ARB_gpu_shader5 is not supported
6914 * then all of the extended integer functions need
6915 * lowering. It may be necessary to add some caps
6916 * for individual instructions.
6918 (!ctx
->Extensions
.ARB_gpu_shader5
6919 ? BIT_COUNT_TO_MATH
|
6923 FIND_LSB_TO_FLOAT_CAST
|
6924 FIND_MSB_TO_FLOAT_CAST
|
6928 do_vec_index_to_cond_assign(ir
);
6929 lower_vector_insert(ir
, true);
6930 lower_quadop_vector(ir
, false);
6932 if (options
->MaxIfDepth
== 0) {
6936 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6937 /* Do it once and repeat only if there's unsupported control flow. */
6939 do_common_optimization(ir
, true, true, options
,
6940 ctx
->Const
.NativeIntegers
);
6941 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6942 options
->MaxIfDepth
, if_threshold
);
6943 } while (has_unsupported_control_flow(ir
, options
));
6945 /* Repeat it until it stops making changes. */
6948 progress
= do_common_optimization(ir
, true, true, options
,
6949 ctx
->Const
.NativeIntegers
);
6950 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6951 options
->MaxIfDepth
, if_threshold
);
6955 validate_ir_tree(ir
);
6958 build_program_resource_list(ctx
, prog
);
6960 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6961 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
6965 enum pipe_shader_type ptarget
=
6966 pipe_shader_type_from_mesa(shader
->Stage
);
6967 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6968 pscreen
->get_shader_param(pscreen
, ptarget
,
6969 PIPE_SHADER_CAP_PREFERRED_IR
);
6971 struct gl_program
*linked_prog
= NULL
;
6972 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6973 /* TODO only for GLSL VS/FS/CS for now: */
6974 switch (shader
->Stage
) {
6975 case MESA_SHADER_VERTEX
:
6976 case MESA_SHADER_FRAGMENT
:
6977 case MESA_SHADER_COMPUTE
:
6978 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
6983 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
6987 st_set_prog_affected_state_flags(linked_prog
);
6988 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6989 _mesa_shader_stage_to_program(i
),
6991 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7001 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7002 const ubyte outputMapping
[],
7003 struct pipe_stream_output_info
*so
)
7005 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7008 struct gl_transform_feedback_info
*info
=
7009 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7010 st_translate_stream_output_info2(info
, outputMapping
, so
);
7014 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7015 const ubyte outputMapping
[],
7016 struct pipe_stream_output_info
*so
)
7020 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7021 so
->output
[i
].register_index
=
7022 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7023 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7024 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7025 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7026 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7027 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7030 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7031 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7033 so
->num_outputs
= info
->NumOutputs
;