2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
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8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
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12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
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19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "glsl_parser_extras.h"
36 #include "ir_optimization.h"
38 #include "main/errors.h"
39 #include "main/shaderobj.h"
40 #include "main/uniforms.h"
41 #include "main/shaderapi.h"
42 #include "program/prog_instruction.h"
43 #include "program/sampler.h"
45 #include "pipe/p_context.h"
46 #include "pipe/p_screen.h"
47 #include "tgsi/tgsi_ureg.h"
48 #include "tgsi/tgsi_info.h"
49 #include "util/u_math.h"
50 #include "util/u_memory.h"
51 #include "st_program.h"
52 #include "st_mesa_to_tgsi.h"
55 #define PROGRAM_IMMEDIATE PROGRAM_FILE_MAX
56 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
57 (1 << PROGRAM_CONSTANT) | \
58 (1 << PROGRAM_UNIFORM))
60 #define MAX_GLSL_TEXTURE_OFFSET 4
65 static int swizzle_for_size(int size
);
68 * This struct is a corresponding struct to TGSI ureg_src.
72 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
)
76 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
77 this->swizzle
= swizzle_for_size(type
->vector_elements
);
79 this->swizzle
= SWIZZLE_XYZW
;
82 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
84 this->reladdr2
= NULL
;
85 this->has_index2
= false;
86 this->double_reg2
= false;
90 st_src_reg(gl_register_file file
, int index
, int type
)
96 this->swizzle
= SWIZZLE_XYZW
;
99 this->reladdr2
= NULL
;
100 this->has_index2
= false;
101 this->double_reg2
= false;
105 st_src_reg(gl_register_file file
, int index
, int type
, int index2D
)
110 this->index2D
= index2D
;
111 this->swizzle
= SWIZZLE_XYZW
;
113 this->reladdr
= NULL
;
114 this->reladdr2
= NULL
;
115 this->has_index2
= false;
116 this->double_reg2
= false;
122 this->type
= GLSL_TYPE_ERROR
;
123 this->file
= PROGRAM_UNDEFINED
;
128 this->reladdr
= NULL
;
129 this->reladdr2
= NULL
;
130 this->has_index2
= false;
131 this->double_reg2
= false;
135 explicit st_src_reg(st_dst_reg reg
);
137 gl_register_file file
; /**< PROGRAM_* from Mesa */
138 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
140 GLuint swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
141 int negate
; /**< NEGATE_XYZW mask from mesa */
142 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
143 /** Register index should be offset by the integer in this reg. */
145 st_src_reg
*reladdr2
;
148 * Is this the second half of a double register pair?
149 * currently used for input mapping only.
157 st_dst_reg(gl_register_file file
, int writemask
, int type
, int index
)
162 this->writemask
= writemask
;
163 this->cond_mask
= COND_TR
;
164 this->reladdr
= NULL
;
165 this->reladdr2
= NULL
;
166 this->has_index2
= false;
171 st_dst_reg(gl_register_file file
, int writemask
, int type
)
176 this->writemask
= writemask
;
177 this->cond_mask
= COND_TR
;
178 this->reladdr
= NULL
;
179 this->reladdr2
= NULL
;
180 this->has_index2
= false;
187 this->type
= GLSL_TYPE_ERROR
;
188 this->file
= PROGRAM_UNDEFINED
;
192 this->cond_mask
= COND_TR
;
193 this->reladdr
= NULL
;
194 this->reladdr2
= NULL
;
195 this->has_index2
= false;
199 explicit st_dst_reg(st_src_reg reg
);
201 gl_register_file file
; /**< PROGRAM_* from Mesa */
202 int index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
204 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
206 int type
; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
207 /** Register index should be offset by the integer in this reg. */
209 st_src_reg
*reladdr2
;
214 st_src_reg::st_src_reg(st_dst_reg reg
)
216 this->type
= reg
.type
;
217 this->file
= reg
.file
;
218 this->index
= reg
.index
;
219 this->swizzle
= SWIZZLE_XYZW
;
221 this->reladdr
= reg
.reladdr
;
222 this->index2D
= reg
.index2D
;
223 this->reladdr2
= reg
.reladdr2
;
224 this->has_index2
= reg
.has_index2
;
225 this->double_reg2
= false;
226 this->array_id
= reg
.array_id
;
229 st_dst_reg::st_dst_reg(st_src_reg reg
)
231 this->type
= reg
.type
;
232 this->file
= reg
.file
;
233 this->index
= reg
.index
;
234 this->writemask
= WRITEMASK_XYZW
;
235 this->cond_mask
= COND_TR
;
236 this->reladdr
= reg
.reladdr
;
237 this->index2D
= reg
.index2D
;
238 this->reladdr2
= reg
.reladdr2
;
239 this->has_index2
= reg
.has_index2
;
240 this->array_id
= reg
.array_id
;
243 class glsl_to_tgsi_instruction
: public exec_node
{
245 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
250 /** Pointer to the ir source this tree came from for debugging */
252 GLboolean cond_update
;
254 st_src_reg sampler
; /**< sampler register */
255 int sampler_array_size
; /**< 1-based size of sampler array, 1 if not array */
256 int tex_target
; /**< One of TEXTURE_*_INDEX */
257 glsl_base_type tex_type
;
258 GLboolean tex_shadow
;
260 st_src_reg tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
261 unsigned tex_offset_num_offset
;
262 int dead_mask
; /**< Used in dead code elimination */
264 class function_entry
*function
; /* Set on TGSI_OPCODE_CAL or TGSI_OPCODE_BGNSUB */
267 class variable_storage
: public exec_node
{
269 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
270 unsigned array_id
= 0)
271 : file(file
), index(index
), var(var
), array_id(array_id
)
276 gl_register_file file
;
278 ir_variable
*var
; /* variable that maps to this, if any */
282 class immediate_storage
: public exec_node
{
284 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
286 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
287 this->size32
= size32
;
291 /* doubles are stored across 2 gl_constant_values */
292 gl_constant_value values
[4];
293 int size32
; /**< Number of 32-bit components (1-4) */
294 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
297 class function_entry
: public exec_node
{
299 ir_function_signature
*sig
;
302 * identifier of this function signature used by the program.
304 * At the point that TGSI instructions for function calls are
305 * generated, we don't know the address of the first instruction of
306 * the function body. So we make the BranchTarget that is called a
307 * small integer and rewrite them during set_branchtargets().
312 * Pointer to first instruction of the function body.
314 * Set during function body emits after main() is processed.
316 glsl_to_tgsi_instruction
*bgn_inst
;
319 * Index of the first instruction of the function body in actual TGSI.
321 * Set after conversion from glsl_to_tgsi_instruction to TGSI.
325 /** Storage for the return value. */
326 st_src_reg return_reg
;
329 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
330 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
338 struct glsl_to_tgsi_visitor
: public ir_visitor
{
340 glsl_to_tgsi_visitor();
341 ~glsl_to_tgsi_visitor();
343 function_entry
*current_function
;
345 struct gl_context
*ctx
;
346 struct gl_program
*prog
;
347 struct gl_shader_program
*shader_program
;
348 struct gl_shader
*shader
;
349 struct gl_shader_compiler_options
*options
;
353 unsigned *array_sizes
;
354 unsigned max_num_arrays
;
357 struct array_decl input_arrays
[PIPE_MAX_SHADER_INPUTS
];
358 unsigned num_input_arrays
;
359 struct array_decl output_arrays
[PIPE_MAX_SHADER_OUTPUTS
];
360 unsigned num_output_arrays
;
362 int num_address_regs
;
364 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
365 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
366 bool indirect_addr_consts
;
367 int wpos_transform_const
;
370 bool native_integers
;
374 variable_storage
*find_variable_storage(ir_variable
*var
);
376 int add_constant(gl_register_file file
, gl_constant_value values
[8],
377 int size
, int datatype
, GLuint
*swizzle_out
);
379 function_entry
*get_function_signature(ir_function_signature
*sig
);
381 st_src_reg
get_temp(const glsl_type
*type
);
382 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
384 st_src_reg
st_src_reg_for_double(double val
);
385 st_src_reg
st_src_reg_for_float(float val
);
386 st_src_reg
st_src_reg_for_int(int val
);
387 st_src_reg
st_src_reg_for_type(int type
, int val
);
390 * \name Visit methods
392 * As typical for the visitor pattern, there must be one \c visit method for
393 * each concrete subclass of \c ir_instruction. Virtual base classes within
394 * the hierarchy should not have \c visit methods.
397 virtual void visit(ir_variable
*);
398 virtual void visit(ir_loop
*);
399 virtual void visit(ir_loop_jump
*);
400 virtual void visit(ir_function_signature
*);
401 virtual void visit(ir_function
*);
402 virtual void visit(ir_expression
*);
403 virtual void visit(ir_swizzle
*);
404 virtual void visit(ir_dereference_variable
*);
405 virtual void visit(ir_dereference_array
*);
406 virtual void visit(ir_dereference_record
*);
407 virtual void visit(ir_assignment
*);
408 virtual void visit(ir_constant
*);
409 virtual void visit(ir_call
*);
410 virtual void visit(ir_return
*);
411 virtual void visit(ir_discard
*);
412 virtual void visit(ir_texture
*);
413 virtual void visit(ir_if
*);
414 virtual void visit(ir_emit_vertex
*);
415 virtual void visit(ir_end_primitive
*);
416 virtual void visit(ir_barrier
*);
421 /** List of variable_storage */
424 /** List of immediate_storage */
425 exec_list immediates
;
426 unsigned num_immediates
;
428 /** List of function_entry */
429 exec_list function_signatures
;
430 int next_signature_id
;
432 /** List of glsl_to_tgsi_instruction */
433 exec_list instructions
;
435 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
436 st_dst_reg dst
= undef_dst
,
437 st_src_reg src0
= undef_src
,
438 st_src_reg src1
= undef_src
,
439 st_src_reg src2
= undef_src
,
440 st_src_reg src3
= undef_src
);
442 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
443 st_dst_reg dst
, st_dst_reg dst1
,
444 st_src_reg src0
= undef_src
,
445 st_src_reg src1
= undef_src
,
446 st_src_reg src2
= undef_src
,
447 st_src_reg src3
= undef_src
);
449 unsigned get_opcode(ir_instruction
*ir
, unsigned op
,
451 st_src_reg src0
, st_src_reg src1
);
454 * Emit the correct dot-product instruction for the type of arguments
456 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
462 void emit_scalar(ir_instruction
*ir
, unsigned op
,
463 st_dst_reg dst
, st_src_reg src0
);
465 void emit_scalar(ir_instruction
*ir
, unsigned op
,
466 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
468 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
470 bool try_emit_mad(ir_expression
*ir
,
472 bool try_emit_mad_for_and_not(ir_expression
*ir
,
475 void emit_swz(ir_expression
*ir
);
477 bool process_move_condition(ir_rvalue
*ir
);
479 void simplify_cmp(void);
481 void rename_temp_register(int index
, int new_index
);
482 int get_first_temp_read(int index
);
483 int get_first_temp_write(int index
);
484 int get_last_temp_read(int index
);
485 int get_last_temp_write(int index
);
487 void copy_propagate(void);
488 int eliminate_dead_code(void);
490 void merge_two_dsts(void);
491 void merge_registers(void);
492 void renumber_registers(void);
494 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
495 st_dst_reg
*l
, st_src_reg
*r
,
496 st_src_reg
*cond
, bool cond_swap
);
501 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
502 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
503 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
506 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
509 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
513 ralloc_vasprintf_append(&prog
->InfoLog
, fmt
, args
);
516 prog
->LinkStatus
= GL_FALSE
;
520 swizzle_for_size(int size
)
522 static const int size_swizzles
[4] = {
523 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
524 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
525 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
526 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
529 assert((size
>= 1) && (size
<= 4));
530 return size_swizzles
[size
- 1];
534 is_tex_instruction(unsigned opcode
)
536 const tgsi_opcode_info
* info
= tgsi_get_opcode_info(opcode
);
541 num_inst_dst_regs(unsigned opcode
)
543 const tgsi_opcode_info
* info
= tgsi_get_opcode_info(opcode
);
544 return info
->num_dst
;
548 num_inst_src_regs(unsigned opcode
)
550 const tgsi_opcode_info
* info
= tgsi_get_opcode_info(opcode
);
551 return info
->is_tex
? info
->num_src
- 1 : info
->num_src
;
554 glsl_to_tgsi_instruction
*
555 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
556 st_dst_reg dst
, st_dst_reg dst1
,
557 st_src_reg src0
, st_src_reg src1
,
558 st_src_reg src2
, st_src_reg src3
)
560 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
561 int num_reladdr
= 0, i
, j
;
563 op
= get_opcode(ir
, op
, dst
, src0
, src1
);
565 /* If we have to do relative addressing, we want to load the ARL
566 * reg directly for one of the regs, and preload the other reladdr
567 * sources into temps.
569 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
570 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
571 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
572 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
573 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
574 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
576 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
577 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
578 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
579 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
581 if (dst
.reladdr
|| dst
.reladdr2
) {
583 emit_arl(ir
, address_reg
, *dst
.reladdr
);
585 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
589 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
592 assert(num_reladdr
== 0);
603 /* default to float, for paths where this is not initialized
604 * (since 0==UINT which is likely wrong):
606 inst
->tex_type
= GLSL_TYPE_FLOAT
;
608 inst
->function
= NULL
;
610 /* Update indirect addressing status used by TGSI */
611 if (dst
.reladdr
|| dst
.reladdr2
) {
613 case PROGRAM_STATE_VAR
:
614 case PROGRAM_CONSTANT
:
615 case PROGRAM_UNIFORM
:
616 this->indirect_addr_consts
= true;
618 case PROGRAM_IMMEDIATE
:
619 assert(!"immediates should not have indirect addressing");
626 for (i
= 0; i
< 4; i
++) {
627 if(inst
->src
[i
].reladdr
) {
628 switch(inst
->src
[i
].file
) {
629 case PROGRAM_STATE_VAR
:
630 case PROGRAM_CONSTANT
:
631 case PROGRAM_UNIFORM
:
632 this->indirect_addr_consts
= true;
634 case PROGRAM_IMMEDIATE
:
635 assert(!"immediates should not have indirect addressing");
644 this->instructions
.push_tail(inst
);
647 * This section contains the double processing.
648 * GLSL just represents doubles as single channel values,
649 * however most HW and TGSI represent doubles as pairs of register channels.
651 * so we have to fixup destination writemask/index and src swizzle/indexes.
652 * dest writemasks need to translate from single channel write mask
653 * to a dual-channel writemask, but also need to modify the index,
654 * if we are touching the Z,W fields in the pre-translated writemask.
656 * src channels have similiar index modifications along with swizzle
657 * changes to we pick the XY, ZW pairs from the correct index.
659 * GLSL [0].x -> TGSI [0].xy
660 * GLSL [0].y -> TGSI [0].zw
661 * GLSL [0].z -> TGSI [1].xy
662 * GLSL [0].w -> TGSI [1].zw
664 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
|| inst
->dst
[1].type
== GLSL_TYPE_DOUBLE
||
665 inst
->src
[0].type
== GLSL_TYPE_DOUBLE
) {
666 glsl_to_tgsi_instruction
*dinst
= NULL
;
667 int initial_src_swz
[4], initial_src_idx
[4];
668 int initial_dst_idx
[2], initial_dst_writemask
[2];
669 /* select the writemask for dst0 or dst1 */
670 unsigned writemask
= inst
->dst
[0].file
== PROGRAM_UNDEFINED
? inst
->dst
[1].writemask
: inst
->dst
[0].writemask
;
672 /* copy out the writemask, index and swizzles for all src/dsts. */
673 for (j
= 0; j
< 2; j
++) {
674 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
675 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
678 for (j
= 0; j
< 4; j
++) {
679 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
680 initial_src_idx
[j
] = inst
->src
[j
].index
;
684 * scan all the components in the dst writemask
685 * generate an instruction for each of them if required.
689 int i
= u_bit_scan(&writemask
);
691 /* first time use previous instruction */
695 /* create a new instructions for subsequent attempts */
696 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
700 this->instructions
.push_tail(dinst
);
703 /* modify the destination if we are splitting */
704 for (j
= 0; j
< 2; j
++) {
705 if (dinst
->dst
[j
].type
== GLSL_TYPE_DOUBLE
) {
706 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
707 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
709 dinst
->dst
[j
].index
++;
711 /* if we aren't writing to a double, just get the bit of the initial writemask
713 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
717 /* modify the src registers */
718 for (j
= 0; j
< 4; j
++) {
719 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
721 if (dinst
->src
[j
].type
== GLSL_TYPE_DOUBLE
) {
722 dinst
->src
[j
].index
= initial_src_idx
[j
];
724 dinst
->src
[j
].double_reg2
= true;
725 dinst
->src
[j
].index
++;
729 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
731 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
734 /* some opcodes are special case in what they use as sources
735 - F2D is a float src0, DLDEXP is integer src1 */
736 if (op
== TGSI_OPCODE_F2D
||
737 op
== TGSI_OPCODE_DLDEXP
||
738 (op
== TGSI_OPCODE_UCMP
&& dinst
->dst
[0].type
== GLSL_TYPE_DOUBLE
)) {
739 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
751 glsl_to_tgsi_instruction
*
752 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
754 st_src_reg src0
, st_src_reg src1
,
755 st_src_reg src2
, st_src_reg src3
)
757 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
761 * Determines whether to use an integer, unsigned integer, or float opcode
762 * based on the operands and input opcode, then emits the result.
765 glsl_to_tgsi_visitor::get_opcode(ir_instruction
*ir
, unsigned op
,
767 st_src_reg src0
, st_src_reg src1
)
769 int type
= GLSL_TYPE_FLOAT
;
771 if (op
== TGSI_OPCODE_MOV
)
774 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
775 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
776 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
777 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
779 if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
780 type
= GLSL_TYPE_DOUBLE
;
781 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
782 type
= GLSL_TYPE_FLOAT
;
783 else if (native_integers
)
784 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
786 #define case5(c, f, i, u, d) \
787 case TGSI_OPCODE_##c: \
788 if (type == GLSL_TYPE_DOUBLE) \
789 op = TGSI_OPCODE_##d; \
790 else if (type == GLSL_TYPE_INT) \
791 op = TGSI_OPCODE_##i; \
792 else if (type == GLSL_TYPE_UINT) \
793 op = TGSI_OPCODE_##u; \
795 op = TGSI_OPCODE_##f; \
798 #define case4(c, f, i, u) \
799 case TGSI_OPCODE_##c: \
800 if (type == GLSL_TYPE_INT) \
801 op = TGSI_OPCODE_##i; \
802 else if (type == GLSL_TYPE_UINT) \
803 op = TGSI_OPCODE_##u; \
805 op = TGSI_OPCODE_##f; \
808 #define case3(f, i, u) case4(f, f, i, u)
809 #define case4d(f, i, u, d) case5(f, f, i, u, d)
810 #define case3fid(f, i, d) case5(f, f, i, i, d)
811 #define case2fi(f, i) case4(f, f, i, i)
812 #define case2iu(i, u) case4(i, LAST, i, u)
814 #define casecomp(c, f, i, u, d) \
815 case TGSI_OPCODE_##c: \
816 if (type == GLSL_TYPE_DOUBLE) \
817 op = TGSI_OPCODE_##d; \
818 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
819 op = TGSI_OPCODE_##i; \
820 else if (type == GLSL_TYPE_UINT) \
821 op = TGSI_OPCODE_##u; \
822 else if (native_integers) \
823 op = TGSI_OPCODE_##f; \
825 op = TGSI_OPCODE_##c; \
829 case3fid(ADD
, UADD
, DADD
);
830 case3fid(MUL
, UMUL
, DMUL
);
831 case3fid(MAD
, UMAD
, DMAD
);
832 case3fid(FMA
, UMAD
, DFMA
);
833 case3(DIV
, IDIV
, UDIV
);
834 case4d(MAX
, IMAX
, UMAX
, DMAX
);
835 case4d(MIN
, IMIN
, UMIN
, DMIN
);
838 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
839 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
840 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
841 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
845 case3fid(SSG
, ISSG
, DSSG
);
846 case3fid(ABS
, IABS
, DABS
);
850 case2iu(IMUL_HI
, UMUL_HI
);
852 case3fid(SQRT
, SQRT
, DSQRT
);
854 case3fid(RCP
, RCP
, DRCP
);
855 case3fid(RSQ
, RSQ
, DRSQ
);
857 case3fid(FRC
, FRC
, DFRAC
);
858 case3fid(TRUNC
, TRUNC
, DTRUNC
);
859 case3fid(CEIL
, CEIL
, DCEIL
);
860 case3fid(FLR
, FLR
, DFLR
);
861 case3fid(ROUND
, ROUND
, DROUND
);
866 assert(op
!= TGSI_OPCODE_LAST
);
870 glsl_to_tgsi_instruction
*
871 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
872 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
875 static const unsigned dot_opcodes
[] = {
876 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
879 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
883 * Emits TGSI scalar opcodes to produce unique answers across channels.
885 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
886 * channel determines the result across all channels. So to do a vec4
887 * of this operation, we want to emit a scalar per source channel used
888 * to produce dest channels.
891 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
893 st_src_reg orig_src0
, st_src_reg orig_src1
)
896 int done_mask
= ~dst
.writemask
;
898 /* TGSI RCP is a scalar operation splatting results to all channels,
899 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
902 for (i
= 0; i
< 4; i
++) {
903 GLuint this_mask
= (1 << i
);
904 st_src_reg src0
= orig_src0
;
905 st_src_reg src1
= orig_src1
;
907 if (done_mask
& this_mask
)
910 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
911 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
912 for (j
= i
+ 1; j
< 4; j
++) {
913 /* If there is another enabled component in the destination that is
914 * derived from the same inputs, generate its value on this pass as
917 if (!(done_mask
& (1 << j
)) &&
918 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
919 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
920 this_mask
|= (1 << j
);
923 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
924 src0_swiz
, src0_swiz
);
925 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
926 src1_swiz
, src1_swiz
);
928 dst
.writemask
= this_mask
;
929 emit_asm(ir
, op
, dst
, src0
, src1
);
930 done_mask
|= this_mask
;
935 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
936 st_dst_reg dst
, st_src_reg src0
)
938 st_src_reg undef
= undef_src
;
940 undef
.swizzle
= SWIZZLE_XXXX
;
942 emit_scalar(ir
, op
, dst
, src0
, undef
);
946 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
947 st_dst_reg dst
, st_src_reg src0
)
949 int op
= TGSI_OPCODE_ARL
;
951 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
952 op
= TGSI_OPCODE_UARL
;
954 assert(dst
.file
== PROGRAM_ADDRESS
);
955 if (dst
.index
>= this->num_address_regs
)
956 this->num_address_regs
= dst
.index
+ 1;
958 emit_asm(NULL
, op
, dst
, src0
);
962 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
963 gl_constant_value values
[8], int size
, int datatype
,
966 if (file
== PROGRAM_CONSTANT
) {
967 return _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
968 size
, datatype
, swizzle_out
);
971 assert(file
== PROGRAM_IMMEDIATE
);
974 immediate_storage
*entry
;
975 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
978 /* Search immediate storage to see if we already have an identical
979 * immediate that we can use instead of adding a duplicate entry.
981 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
982 immediate_storage
*tmp
= entry
;
984 for (i
= 0; i
* 4 < size32
; i
++) {
985 int slot_size
= MIN2(size32
- (i
* 4), 4);
986 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
988 if (memcmp(tmp
->values
, &values
[i
* 4],
989 slot_size
* sizeof(gl_constant_value
)))
992 /* Everything matches, keep going until the full size is matched */
993 tmp
= (immediate_storage
*)tmp
->next
;
996 /* The full value matched */
1003 for (i
= 0; i
* 4 < size32
; i
++) {
1004 int slot_size
= MIN2(size32
- (i
* 4), 4);
1005 /* Add this immediate to the list. */
1006 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1007 this->immediates
.push_tail(entry
);
1008 this->num_immediates
++;
1014 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1016 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1017 union gl_constant_value uval
;
1020 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1026 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1028 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1029 union gl_constant_value uval
[2];
1031 uval
[0].u
= *(uint32_t *)&val
;
1032 uval
[1].u
= *(((uint32_t *)&val
) + 1);
1033 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1039 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1041 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1042 union gl_constant_value uval
;
1044 assert(native_integers
);
1047 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1053 glsl_to_tgsi_visitor::st_src_reg_for_type(int type
, int val
)
1055 if (native_integers
)
1056 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1057 st_src_reg_for_int(val
);
1059 return st_src_reg_for_float(val
);
1063 type_size(const struct glsl_type
*type
)
1068 switch (type
->base_type
) {
1069 case GLSL_TYPE_UINT
:
1071 case GLSL_TYPE_FLOAT
:
1072 case GLSL_TYPE_BOOL
:
1073 if (type
->is_matrix()) {
1074 return type
->matrix_columns
;
1076 /* Regardless of size of vector, it gets a vec4. This is bad
1077 * packing for things like floats, but otherwise arrays become a
1078 * mess. Hopefully a later pass over the code can pack scalars
1079 * down if appropriate.
1084 case GLSL_TYPE_DOUBLE
:
1085 if (type
->is_matrix()) {
1086 if (type
->vector_elements
<= 2)
1087 return type
->matrix_columns
;
1089 return type
->matrix_columns
* 2;
1091 /* For doubles if we have a double or dvec2 they fit in one
1092 * vec4, else they need 2 vec4s.
1094 if (type
->vector_elements
<= 2)
1100 case GLSL_TYPE_ARRAY
:
1101 assert(type
->length
> 0);
1102 return type_size(type
->fields
.array
) * type
->length
;
1103 case GLSL_TYPE_STRUCT
:
1105 for (i
= 0; i
< type
->length
; i
++) {
1106 size
+= type_size(type
->fields
.structure
[i
].type
);
1109 case GLSL_TYPE_SAMPLER
:
1110 case GLSL_TYPE_IMAGE
:
1111 case GLSL_TYPE_SUBROUTINE
:
1112 /* Samplers take up one slot in UNIFORMS[], but they're baked in
1116 case GLSL_TYPE_ATOMIC_UINT
:
1117 case GLSL_TYPE_INTERFACE
:
1118 case GLSL_TYPE_VOID
:
1119 case GLSL_TYPE_ERROR
:
1120 assert(!"Invalid type in type_size");
1127 * In the initial pass of codegen, we assign temporary numbers to
1128 * intermediate results. (not SSA -- variable assignments will reuse
1132 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1136 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1140 if (!options
->EmitNoIndirectTemp
&&
1141 (type
->is_array() || type
->is_matrix())) {
1143 if (next_array
>= max_num_arrays
) {
1144 max_num_arrays
+= 32;
1145 array_sizes
= (unsigned*)
1146 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1149 src
.file
= PROGRAM_ARRAY
;
1150 src
.index
= next_array
<< 16 | 0x8000;
1151 array_sizes
[next_array
] = type_size(type
);
1155 src
.file
= PROGRAM_TEMPORARY
;
1156 src
.index
= next_temp
;
1157 next_temp
+= type_size(type
);
1160 if (type
->is_array() || type
->is_record()) {
1161 src
.swizzle
= SWIZZLE_NOOP
;
1163 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1170 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1173 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1174 if (entry
->var
== var
)
1182 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1184 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1185 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*)this->prog
;
1187 fp
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1188 fp
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1191 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1193 const ir_state_slot
*const slots
= ir
->get_state_slots();
1194 assert(slots
!= NULL
);
1196 /* Check if this statevar's setup in the STATE file exactly
1197 * matches how we'll want to reference it as a
1198 * struct/array/whatever. If not, then we need to move it into
1199 * temporary storage and hope that it'll get copy-propagated
1202 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1203 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1208 variable_storage
*storage
;
1210 if (i
== ir
->get_num_state_slots()) {
1211 /* We'll set the index later. */
1212 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1213 this->variables
.push_tail(storage
);
1217 /* The variable_storage constructor allocates slots based on the size
1218 * of the type. However, this had better match the number of state
1219 * elements that we're going to copy into the new temporary.
1221 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1223 dst
= st_dst_reg(get_temp(ir
->type
));
1225 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
);
1227 this->variables
.push_tail(storage
);
1231 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1232 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1233 (gl_state_index
*)slots
[i
].tokens
);
1235 if (storage
->file
== PROGRAM_STATE_VAR
) {
1236 if (storage
->index
== -1) {
1237 storage
->index
= index
;
1239 assert(index
== storage
->index
+ (int)i
);
1242 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1243 * the data being moved since MOV does not care about the type of
1244 * data it is moving, and we don't want to declare registers with
1245 * array or struct types.
1247 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1248 src
.swizzle
= slots
[i
].swizzle
;
1249 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1250 /* even a float takes up a whole vec4 reg in a struct/array. */
1255 if (storage
->file
== PROGRAM_TEMPORARY
&&
1256 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1257 fail_link(this->shader_program
,
1258 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1259 ir
->name
, dst
.index
- storage
->index
,
1260 type_size(ir
->type
));
1266 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1268 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1270 visit_exec_list(&ir
->body_instructions
, this);
1272 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1276 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1279 case ir_loop_jump::jump_break
:
1280 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1282 case ir_loop_jump::jump_continue
:
1283 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1290 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1297 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1299 /* Ignore function bodies other than main() -- we shouldn't see calls to
1300 * them since they should all be inlined before we get to glsl_to_tgsi.
1302 if (strcmp(ir
->name
, "main") == 0) {
1303 const ir_function_signature
*sig
;
1306 sig
= ir
->matching_signature(NULL
, &empty
, false);
1310 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1317 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1319 int nonmul_operand
= 1 - mul_operand
;
1321 st_dst_reg result_dst
;
1323 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1324 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1327 expr
->operands
[0]->accept(this);
1329 expr
->operands
[1]->accept(this);
1331 ir
->operands
[nonmul_operand
]->accept(this);
1334 this->result
= get_temp(ir
->type
);
1335 result_dst
= st_dst_reg(this->result
);
1336 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1337 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1343 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1345 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1346 * implemented using multiplication, and logical-or is implemented using
1347 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1348 * As result, the logical expression (a & !b) can be rewritten as:
1352 * - (a * 1) - (a * b)
1356 * This final expression can be implemented as a single MAD(a, -b, a)
1360 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1362 const int other_operand
= 1 - try_operand
;
1365 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1366 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1369 ir
->operands
[other_operand
]->accept(this);
1371 expr
->operands
[0]->accept(this);
1374 b
.negate
= ~b
.negate
;
1376 this->result
= get_temp(ir
->type
);
1377 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1383 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1384 st_src_reg
*reg
, int *num_reladdr
)
1386 if (!reg
->reladdr
&& !reg
->reladdr2
)
1389 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1390 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1392 if (*num_reladdr
!= 1) {
1393 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1395 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1403 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1405 unsigned int operand
;
1406 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1407 st_src_reg result_src
;
1408 st_dst_reg result_dst
;
1410 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1412 if (ir
->operation
== ir_binop_add
) {
1413 if (try_emit_mad(ir
, 1))
1415 if (try_emit_mad(ir
, 0))
1419 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1421 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1422 if (try_emit_mad_for_and_not(ir
, 1))
1424 if (try_emit_mad_for_and_not(ir
, 0))
1428 if (ir
->operation
== ir_quadop_vector
)
1429 assert(!"ir_quadop_vector should have been lowered");
1431 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1432 this->result
.file
= PROGRAM_UNDEFINED
;
1433 ir
->operands
[operand
]->accept(this);
1434 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1435 printf("Failed to get tree for expression operand:\n");
1436 ir
->operands
[operand
]->print();
1440 op
[operand
] = this->result
;
1442 /* Matrix expression operands should have been broken down to vector
1443 * operations already.
1445 assert(!ir
->operands
[operand
]->type
->is_matrix());
1448 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1449 if (ir
->operands
[1]) {
1450 vector_elements
= MAX2(vector_elements
,
1451 ir
->operands
[1]->type
->vector_elements
);
1454 this->result
.file
= PROGRAM_UNDEFINED
;
1456 /* Storage for our result. Ideally for an assignment we'd be using
1457 * the actual storage for the result here, instead.
1459 result_src
= get_temp(ir
->type
);
1460 /* convenience for the emit functions below. */
1461 result_dst
= st_dst_reg(result_src
);
1462 /* Limit writes to the channels that will be used by result_src later.
1463 * This does limit this temp's use as a temporary for multi-instruction
1466 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1468 switch (ir
->operation
) {
1469 case ir_unop_logic_not
:
1470 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1471 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1473 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1474 * older GPUs implement SEQ using multiple instructions (i915 uses two
1475 * SGE instructions and a MUL instruction). Since our logic values are
1476 * 0.0 and 1.0, 1-x also implements !x.
1478 op
[0].negate
= ~op
[0].negate
;
1479 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1483 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1484 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1485 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1486 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1488 op
[0].negate
= ~op
[0].negate
;
1492 case ir_unop_subroutine_to_int
:
1493 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1496 emit_asm(ir
, TGSI_OPCODE_ABS
, result_dst
, op
[0]);
1499 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1502 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1506 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1510 assert(!"not reached: should be handled by ir_explog_to_explog2");
1513 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1516 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1519 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1521 case ir_unop_saturate
: {
1522 glsl_to_tgsi_instruction
*inst
;
1523 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1524 inst
->saturate
= true;
1529 case ir_unop_dFdx_coarse
:
1530 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1532 case ir_unop_dFdx_fine
:
1533 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1536 case ir_unop_dFdy_coarse
:
1537 case ir_unop_dFdy_fine
:
1539 /* The X component contains 1 or -1 depending on whether the framebuffer
1540 * is a FBO or the window system buffer, respectively.
1541 * It is then multiplied with the source operand of DDY.
1543 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1544 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1546 unsigned transform_y_index
=
1547 _mesa_add_state_reference(this->prog
->Parameters
,
1550 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1552 glsl_type::vec4_type
);
1553 transform_y
.swizzle
= SWIZZLE_XXXX
;
1555 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1557 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1558 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1559 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1563 case ir_unop_frexp_sig
:
1564 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1567 case ir_unop_frexp_exp
:
1568 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1571 case ir_unop_noise
: {
1572 /* At some point, a motivated person could add a better
1573 * implementation of noise. Currently not even the nvidia
1574 * binary drivers do anything more than this. In any case, the
1575 * place to do this is in the GL state tracker, not the poor
1578 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1583 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1586 emit_asm(ir
, TGSI_OPCODE_SUB
, result_dst
, op
[0], op
[1]);
1590 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1593 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1594 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1596 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1599 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1600 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1602 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1606 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1608 case ir_binop_greater
:
1609 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1611 case ir_binop_lequal
:
1612 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1614 case ir_binop_gequal
:
1615 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1617 case ir_binop_equal
:
1618 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1620 case ir_binop_nequal
:
1621 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1623 case ir_binop_all_equal
:
1624 /* "==" operator producing a scalar boolean. */
1625 if (ir
->operands
[0]->type
->is_vector() ||
1626 ir
->operands
[1]->type
->is_vector()) {
1627 st_src_reg temp
= get_temp(native_integers
?
1628 glsl_type::uvec4_type
:
1629 glsl_type::vec4_type
);
1631 if (native_integers
) {
1632 st_dst_reg temp_dst
= st_dst_reg(temp
);
1633 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1635 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1637 /* Emit 1-3 AND operations to combine the SEQ results. */
1638 switch (ir
->operands
[0]->type
->vector_elements
) {
1642 temp_dst
.writemask
= WRITEMASK_Y
;
1643 temp1
.swizzle
= SWIZZLE_YYYY
;
1644 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1645 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1648 temp_dst
.writemask
= WRITEMASK_X
;
1649 temp1
.swizzle
= SWIZZLE_XXXX
;
1650 temp2
.swizzle
= SWIZZLE_YYYY
;
1651 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1652 temp_dst
.writemask
= WRITEMASK_Y
;
1653 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1654 temp2
.swizzle
= SWIZZLE_WWWW
;
1655 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1658 temp1
.swizzle
= SWIZZLE_XXXX
;
1659 temp2
.swizzle
= SWIZZLE_YYYY
;
1660 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1662 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1664 /* After the dot-product, the value will be an integer on the
1665 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1667 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1669 /* Negating the result of the dot-product gives values on the range
1670 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1671 * This is achieved using SGE.
1673 st_src_reg sge_src
= result_src
;
1674 sge_src
.negate
= ~sge_src
.negate
;
1675 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1678 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1681 case ir_binop_any_nequal
:
1682 /* "!=" operator producing a scalar boolean. */
1683 if (ir
->operands
[0]->type
->is_vector() ||
1684 ir
->operands
[1]->type
->is_vector()) {
1685 st_src_reg temp
= get_temp(native_integers
?
1686 glsl_type::uvec4_type
:
1687 glsl_type::vec4_type
);
1688 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1690 if (native_integers
) {
1691 st_dst_reg temp_dst
= st_dst_reg(temp
);
1692 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1694 /* Emit 1-3 OR operations to combine the SNE results. */
1695 switch (ir
->operands
[0]->type
->vector_elements
) {
1699 temp_dst
.writemask
= WRITEMASK_Y
;
1700 temp1
.swizzle
= SWIZZLE_YYYY
;
1701 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1702 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1705 temp_dst
.writemask
= WRITEMASK_X
;
1706 temp1
.swizzle
= SWIZZLE_XXXX
;
1707 temp2
.swizzle
= SWIZZLE_YYYY
;
1708 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1709 temp_dst
.writemask
= WRITEMASK_Y
;
1710 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1711 temp2
.swizzle
= SWIZZLE_WWWW
;
1712 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1715 temp1
.swizzle
= SWIZZLE_XXXX
;
1716 temp2
.swizzle
= SWIZZLE_YYYY
;
1717 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1719 /* After the dot-product, the value will be an integer on the
1720 * range [0,4]. Zero stays zero, and positive values become 1.0.
1722 glsl_to_tgsi_instruction
*const dp
=
1723 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1724 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1725 /* The clamping to [0,1] can be done for free in the fragment
1726 * shader with a saturate.
1728 dp
->saturate
= true;
1730 /* Negating the result of the dot-product gives values on the range
1731 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1732 * achieved using SLT.
1734 st_src_reg slt_src
= result_src
;
1735 slt_src
.negate
= ~slt_src
.negate
;
1736 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1740 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1745 assert(ir
->operands
[0]->type
->is_vector());
1747 if (native_integers
) {
1748 int dst_swizzle
= 0, op0_swizzle
, i
;
1749 st_src_reg accum
= op
[0];
1751 op0_swizzle
= op
[0].swizzle
;
1752 accum
.swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 0),
1753 GET_SWZ(op0_swizzle
, 0),
1754 GET_SWZ(op0_swizzle
, 0),
1755 GET_SWZ(op0_swizzle
, 0));
1756 for (i
= 0; i
< 4; i
++) {
1757 if (result_dst
.writemask
& (1 << i
)) {
1758 dst_swizzle
= MAKE_SWIZZLE4(i
, i
, i
, i
);
1763 assert(ir
->operands
[0]->type
->is_boolean());
1765 /* OR all the components together, since they should be either 0 or ~0
1767 switch (ir
->operands
[0]->type
->vector_elements
) {
1769 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 3),
1770 GET_SWZ(op0_swizzle
, 3),
1771 GET_SWZ(op0_swizzle
, 3),
1772 GET_SWZ(op0_swizzle
, 3));
1773 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1774 accum
= st_src_reg(result_dst
);
1775 accum
.swizzle
= dst_swizzle
;
1778 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 2),
1779 GET_SWZ(op0_swizzle
, 2),
1780 GET_SWZ(op0_swizzle
, 2),
1781 GET_SWZ(op0_swizzle
, 2));
1782 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1783 accum
= st_src_reg(result_dst
);
1784 accum
.swizzle
= dst_swizzle
;
1787 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(op0_swizzle
, 1),
1788 GET_SWZ(op0_swizzle
, 1),
1789 GET_SWZ(op0_swizzle
, 1),
1790 GET_SWZ(op0_swizzle
, 1));
1791 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, accum
, op
[0]);
1794 assert(!"Unexpected vector size");
1798 /* After the dot-product, the value will be an integer on the
1799 * range [0,4]. Zero stays zero, and positive values become 1.0.
1801 glsl_to_tgsi_instruction
*const dp
=
1802 emit_dp(ir
, result_dst
, op
[0], op
[0],
1803 ir
->operands
[0]->type
->vector_elements
);
1804 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
&&
1805 result_dst
.type
== GLSL_TYPE_FLOAT
) {
1806 /* The clamping to [0,1] can be done for free in the fragment
1807 * shader with a saturate.
1809 dp
->saturate
= true;
1810 } else if (result_dst
.type
== GLSL_TYPE_FLOAT
) {
1811 /* Negating the result of the dot-product gives values on the range
1812 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1813 * is achieved using SLT.
1815 st_src_reg slt_src
= result_src
;
1816 slt_src
.negate
= ~slt_src
.negate
;
1817 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1820 /* Use SNE 0 if integers are being used as boolean values. */
1821 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, result_src
, st_src_reg_for_int(0));
1827 case ir_binop_logic_xor
:
1828 if (native_integers
)
1829 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1831 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1834 case ir_binop_logic_or
: {
1835 if (native_integers
) {
1836 /* If integers are used as booleans, we can use an actual "or"
1839 assert(native_integers
);
1840 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1842 /* After the addition, the value will be an integer on the
1843 * range [0,2]. Zero stays zero, and positive values become 1.0.
1845 glsl_to_tgsi_instruction
*add
=
1846 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1847 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1848 /* The clamping to [0,1] can be done for free in the fragment
1849 * shader with a saturate if floats are being used as boolean values.
1851 add
->saturate
= true;
1853 /* Negating the result of the addition gives values on the range
1854 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1855 * is achieved using SLT.
1857 st_src_reg slt_src
= result_src
;
1858 slt_src
.negate
= ~slt_src
.negate
;
1859 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1865 case ir_binop_logic_and
:
1866 /* If native integers are disabled, the bool args are stored as float 0.0
1867 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1868 * actual AND opcode.
1870 if (native_integers
)
1871 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1873 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1877 assert(ir
->operands
[0]->type
->is_vector());
1878 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1879 emit_dp(ir
, result_dst
, op
[0], op
[1],
1880 ir
->operands
[0]->type
->vector_elements
);
1885 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1887 /* sqrt(x) = x * rsq(x). */
1888 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1889 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, result_src
, op
[0]);
1890 /* For incoming channels <= 0, set the result to 0. */
1891 op
[0].negate
= ~op
[0].negate
;
1892 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
,
1893 op
[0], result_src
, st_src_reg_for_float(0.0));
1897 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1900 if (native_integers
) {
1901 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1904 /* fallthrough to next case otherwise */
1906 if (native_integers
) {
1907 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1910 /* fallthrough to next case otherwise */
1913 /* Converting between signed and unsigned integers is a no-op. */
1917 if (native_integers
) {
1918 /* Booleans are stored as integers using ~0 for true and 0 for false.
1919 * GLSL requires that int(bool) return 1 for true and 0 for false.
1920 * This conversion is done with AND, but it could be done with NEG.
1922 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1924 /* Booleans and integers are both stored as floats when native
1925 * integers are disabled.
1931 if (native_integers
)
1932 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1934 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1937 if (native_integers
)
1938 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1940 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1942 case ir_unop_bitcast_f2i
:
1944 result_src
.type
= GLSL_TYPE_INT
;
1946 case ir_unop_bitcast_f2u
:
1948 result_src
.type
= GLSL_TYPE_UINT
;
1950 case ir_unop_bitcast_i2f
:
1951 case ir_unop_bitcast_u2f
:
1953 result_src
.type
= GLSL_TYPE_FLOAT
;
1956 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1959 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
1962 if (native_integers
)
1963 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
1965 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
1968 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1971 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
1974 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
1976 case ir_unop_round_even
:
1977 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
1980 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
1984 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
1987 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
1990 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
1993 case ir_unop_bit_not
:
1994 if (native_integers
) {
1995 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1999 if (native_integers
) {
2000 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2003 case ir_binop_lshift
:
2004 if (native_integers
) {
2005 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2008 case ir_binop_rshift
:
2009 if (native_integers
) {
2010 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2013 case ir_binop_bit_and
:
2014 if (native_integers
) {
2015 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2018 case ir_binop_bit_xor
:
2019 if (native_integers
) {
2020 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2023 case ir_binop_bit_or
:
2024 if (native_integers
) {
2025 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2029 assert(!"GLSL 1.30 features unsupported");
2032 case ir_binop_ubo_load
: {
2033 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2034 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2035 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2036 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2037 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2040 cbuf
.type
= ir
->type
->base_type
;
2041 cbuf
.file
= PROGRAM_CONSTANT
;
2043 cbuf
.reladdr
= NULL
;
2046 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2048 if (const_offset_ir
) {
2049 /* Constant index into constant buffer */
2050 cbuf
.reladdr
= NULL
;
2051 cbuf
.index
= const_offset
/ 16;
2054 /* Relative/variable index into constant buffer */
2055 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), op
[1],
2056 st_src_reg_for_int(4));
2057 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2058 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2061 if (const_uniform_block
) {
2062 /* Constant constant buffer */
2063 cbuf
.reladdr2
= NULL
;
2064 cbuf
.index2D
= const_block
;
2065 cbuf
.has_index2
= true;
2068 /* Relative/variable constant buffer */
2069 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2071 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2072 cbuf
.has_index2
= true;
2075 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2076 if (cbuf
.type
== GLSL_TYPE_DOUBLE
)
2077 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2078 const_offset
% 16 / 8,
2079 const_offset
% 16 / 8,
2080 const_offset
% 16 / 8);
2082 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2083 const_offset
% 16 / 4,
2084 const_offset
% 16 / 4,
2085 const_offset
% 16 / 4);
2087 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2088 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2090 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2095 /* note: we have to reorder the three args here */
2096 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2099 if (this->ctx
->Const
.NativeIntegers
)
2100 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2102 op
[0].negate
= ~op
[0].negate
;
2103 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2106 case ir_triop_bitfield_extract
:
2107 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2109 case ir_quadop_bitfield_insert
:
2110 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2112 case ir_unop_bitfield_reverse
:
2113 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2115 case ir_unop_bit_count
:
2116 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2118 case ir_unop_find_msb
:
2119 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2121 case ir_unop_find_lsb
:
2122 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2124 case ir_binop_imul_high
:
2125 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2128 /* In theory, MAD is incorrect here. */
2130 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2132 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2134 case ir_unop_interpolate_at_centroid
:
2135 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2137 case ir_binop_interpolate_at_offset
:
2138 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], op
[1]);
2140 case ir_binop_interpolate_at_sample
:
2141 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2145 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2148 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2151 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2154 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2157 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2160 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2162 case ir_unop_unpack_double_2x32
:
2163 case ir_unop_pack_double_2x32
:
2164 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2167 case ir_binop_ldexp
:
2168 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2169 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2171 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2175 case ir_unop_pack_snorm_2x16
:
2176 case ir_unop_pack_unorm_2x16
:
2177 case ir_unop_pack_half_2x16
:
2178 case ir_unop_pack_snorm_4x8
:
2179 case ir_unop_pack_unorm_4x8
:
2181 case ir_unop_unpack_snorm_2x16
:
2182 case ir_unop_unpack_unorm_2x16
:
2183 case ir_unop_unpack_half_2x16
:
2184 case ir_unop_unpack_half_2x16_split_x
:
2185 case ir_unop_unpack_half_2x16_split_y
:
2186 case ir_unop_unpack_snorm_4x8
:
2187 case ir_unop_unpack_unorm_4x8
:
2189 case ir_binop_pack_half_2x16_split
:
2192 case ir_quadop_vector
:
2193 case ir_binop_vector_extract
:
2194 case ir_triop_vector_insert
:
2195 case ir_binop_carry
:
2196 case ir_binop_borrow
:
2197 /* This operation is not supported, or should have already been handled.
2199 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2203 this->result
= result_src
;
2208 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2214 /* Note that this is only swizzles in expressions, not those on the left
2215 * hand side of an assignment, which do write masking. See ir_assignment
2219 ir
->val
->accept(this);
2221 assert(src
.file
!= PROGRAM_UNDEFINED
);
2222 assert(ir
->type
->vector_elements
> 0);
2224 for (i
= 0; i
< 4; i
++) {
2225 if (i
< ir
->type
->vector_elements
) {
2228 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2231 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2234 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2237 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2241 /* If the type is smaller than a vec4, replicate the last
2244 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2248 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2253 /* Test if the variable is an array. Note that geometry and
2254 * tessellation shader inputs are outputs are always arrays (except
2255 * for patch inputs), so only the array element type is considered.
2258 is_inout_array(unsigned stage
, ir_variable
*var
, bool *is_2d
)
2260 const glsl_type
*type
= var
->type
;
2262 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2263 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2268 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2269 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2270 stage
== MESA_SHADER_TESS_CTRL
) &&
2272 if (!var
->type
->is_array())
2273 return false; /* a system value probably */
2275 type
= var
->type
->fields
.array
;
2279 return type
->is_array() || type
->is_matrix();
2283 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2285 variable_storage
*entry
= find_variable_storage(ir
->var
);
2286 ir_variable
*var
= ir
->var
;
2290 switch (var
->data
.mode
) {
2291 case ir_var_uniform
:
2292 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2293 var
->data
.location
);
2294 this->variables
.push_tail(entry
);
2296 case ir_var_shader_in
:
2297 /* The linker assigns locations for varyings and attributes,
2298 * including deprecated builtins (like gl_Color), user-assign
2299 * generic attributes (glBindVertexLocation), and
2300 * user-defined varyings.
2302 assert(var
->data
.location
!= -1);
2304 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2305 struct array_decl
*decl
= &input_arrays
[num_input_arrays
];
2307 decl
->mesa_index
= var
->data
.location
;
2308 decl
->array_id
= num_input_arrays
+ 1;
2310 decl
->array_size
= type_size(var
->type
->fields
.array
);
2312 decl
->array_size
= type_size(var
->type
);
2315 entry
= new(mem_ctx
) variable_storage(var
,
2321 entry
= new(mem_ctx
) variable_storage(var
,
2323 var
->data
.location
);
2325 this->variables
.push_tail(entry
);
2327 case ir_var_shader_out
:
2328 assert(var
->data
.location
!= -1);
2330 if (is_inout_array(shader
->Stage
, var
, &is_2d
)) {
2331 struct array_decl
*decl
= &output_arrays
[num_output_arrays
];
2333 decl
->mesa_index
= var
->data
.location
;
2334 decl
->array_id
= num_output_arrays
+ 1;
2336 decl
->array_size
= type_size(var
->type
->fields
.array
);
2338 decl
->array_size
= type_size(var
->type
);
2339 num_output_arrays
++;
2341 entry
= new(mem_ctx
) variable_storage(var
,
2347 entry
= new(mem_ctx
) variable_storage(var
,
2352 this->variables
.push_tail(entry
);
2354 case ir_var_system_value
:
2355 entry
= new(mem_ctx
) variable_storage(var
,
2356 PROGRAM_SYSTEM_VALUE
,
2357 var
->data
.location
);
2360 case ir_var_temporary
:
2361 st_src_reg src
= get_temp(var
->type
);
2363 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
);
2364 this->variables
.push_tail(entry
);
2370 printf("Failed to make storage for %s\n", var
->name
);
2375 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
);
2376 this->result
.array_id
= entry
->array_id
;
2377 if (!native_integers
)
2378 this->result
.type
= GLSL_TYPE_FLOAT
;
2382 shrink_array_declarations(struct array_decl
*arrays
, unsigned count
,
2383 GLbitfield64 usage_mask
,
2384 GLbitfield patch_usage_mask
)
2388 /* Fix array declarations by removing unused array elements at both ends
2389 * of the arrays. For example, mat4[3] where only mat[1] is used.
2391 for (i
= 0; i
< count
; i
++) {
2392 struct array_decl
*decl
= &arrays
[i
];
2394 /* Shrink the beginning. */
2395 for (j
= 0; j
< decl
->array_size
; j
++) {
2396 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2397 if (patch_usage_mask
&
2398 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2402 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2411 /* Shrink the end. */
2412 for (j
= decl
->array_size
-1; j
>= 0; j
--) {
2413 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2414 if (patch_usage_mask
&
2415 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2419 if (usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2429 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2433 int element_size
= type_size(ir
->type
);
2436 index
= ir
->array_index
->constant_expression_value();
2438 ir
->array
->accept(this);
2441 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2442 switch (this->prog
->Target
) {
2443 case GL_TESS_CONTROL_PROGRAM_NV
:
2444 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2445 !ir
->variable_referenced()->data
.patch
;
2447 case GL_TESS_EVALUATION_PROGRAM_NV
:
2448 is_2D
= src
.file
== PROGRAM_INPUT
&&
2449 !ir
->variable_referenced()->data
.patch
;
2451 case GL_GEOMETRY_PROGRAM_NV
:
2452 is_2D
= src
.file
== PROGRAM_INPUT
;
2462 src
.index2D
= index
->value
.i
[0];
2463 src
.has_index2
= true;
2465 src
.index
+= index
->value
.i
[0] * element_size
;
2467 /* Variable index array dereference. It eats the "vec4" of the
2468 * base of the array and an index that offsets the TGSI register
2471 ir
->array_index
->accept(this);
2473 st_src_reg index_reg
;
2475 if (element_size
== 1) {
2476 index_reg
= this->result
;
2478 index_reg
= get_temp(native_integers
?
2479 glsl_type::int_type
: glsl_type::float_type
);
2481 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2482 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2485 /* If there was already a relative address register involved, add the
2486 * new and the old together to get the new offset.
2488 if (!is_2D
&& src
.reladdr
!= NULL
) {
2489 st_src_reg accum_reg
= get_temp(native_integers
?
2490 glsl_type::int_type
: glsl_type::float_type
);
2492 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2493 index_reg
, *src
.reladdr
);
2495 index_reg
= accum_reg
;
2499 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2500 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2502 src
.has_index2
= true;
2504 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2505 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2509 /* If the type is smaller than a vec4, replicate the last channel out. */
2510 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2511 src
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2513 src
.swizzle
= SWIZZLE_NOOP
;
2515 /* Change the register type to the element type of the array. */
2516 src
.type
= ir
->type
->base_type
;
2522 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2525 const glsl_type
*struct_type
= ir
->record
->type
;
2528 ir
->record
->accept(this);
2530 for (i
= 0; i
< struct_type
->length
; i
++) {
2531 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2533 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2536 /* If the type is smaller than a vec4, replicate the last channel out. */
2537 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2538 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2540 this->result
.swizzle
= SWIZZLE_NOOP
;
2542 this->result
.index
+= offset
;
2543 this->result
.type
= ir
->type
->base_type
;
2547 * We want to be careful in assignment setup to hit the actual storage
2548 * instead of potentially using a temporary like we might with the
2549 * ir_dereference handler.
2552 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
)
2554 /* The LHS must be a dereference. If the LHS is a variable indexed array
2555 * access of a vector, it must be separated into a series conditional moves
2556 * before reaching this point (see ir_vec_index_to_cond_assign).
2558 assert(ir
->as_dereference());
2559 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2561 assert(!deref_array
->array
->type
->is_vector());
2564 /* Use the rvalue deref handler for the most part. We'll ignore
2565 * swizzles in it and write swizzles using writemask, though.
2568 return st_dst_reg(v
->result
);
2572 * Process the condition of a conditional assignment
2574 * Examines the condition of a conditional assignment to generate the optimal
2575 * first operand of a \c CMP instruction. If the condition is a relational
2576 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2577 * used as the source for the \c CMP instruction. Otherwise the comparison
2578 * is processed to a boolean result, and the boolean result is used as the
2579 * operand to the CMP instruction.
2582 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2584 ir_rvalue
*src_ir
= ir
;
2586 bool switch_order
= false;
2588 ir_expression
*const expr
= ir
->as_expression();
2590 if (native_integers
) {
2591 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2592 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2593 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2594 type
== GLSL_TYPE_BOOL
) {
2595 if (expr
->operation
== ir_binop_equal
) {
2596 if (expr
->operands
[0]->is_zero()) {
2597 src_ir
= expr
->operands
[1];
2598 switch_order
= true;
2600 else if (expr
->operands
[1]->is_zero()) {
2601 src_ir
= expr
->operands
[0];
2602 switch_order
= true;
2605 else if (expr
->operation
== ir_binop_nequal
) {
2606 if (expr
->operands
[0]->is_zero()) {
2607 src_ir
= expr
->operands
[1];
2609 else if (expr
->operands
[1]->is_zero()) {
2610 src_ir
= expr
->operands
[0];
2616 src_ir
->accept(this);
2617 return switch_order
;
2620 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2621 bool zero_on_left
= false;
2623 if (expr
->operands
[0]->is_zero()) {
2624 src_ir
= expr
->operands
[1];
2625 zero_on_left
= true;
2626 } else if (expr
->operands
[1]->is_zero()) {
2627 src_ir
= expr
->operands
[0];
2628 zero_on_left
= false;
2632 * (a < 0) T F F ( a < 0) T F F
2633 * (0 < a) F F T (-a < 0) F F T
2634 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2635 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2636 * (a > 0) F F T (-a < 0) F F T
2637 * (0 > a) T F F ( a < 0) T F F
2638 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2639 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2641 * Note that exchanging the order of 0 and 'a' in the comparison simply
2642 * means that the value of 'a' should be negated.
2645 switch (expr
->operation
) {
2647 switch_order
= false;
2648 negate
= zero_on_left
;
2651 case ir_binop_greater
:
2652 switch_order
= false;
2653 negate
= !zero_on_left
;
2656 case ir_binop_lequal
:
2657 switch_order
= true;
2658 negate
= !zero_on_left
;
2661 case ir_binop_gequal
:
2662 switch_order
= true;
2663 negate
= zero_on_left
;
2667 /* This isn't the right kind of comparison afterall, so make sure
2668 * the whole condition is visited.
2676 src_ir
->accept(this);
2678 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2679 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2680 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2681 * computing the condition.
2684 this->result
.negate
= ~this->result
.negate
;
2686 return switch_order
;
2690 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2691 st_dst_reg
*l
, st_src_reg
*r
,
2692 st_src_reg
*cond
, bool cond_swap
)
2694 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2695 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2696 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2702 if (type
->is_array()) {
2703 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2704 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2709 if (type
->is_matrix()) {
2710 const struct glsl_type
*vec_type
;
2712 vec_type
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
2713 type
->vector_elements
, 1);
2715 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2716 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2721 assert(type
->is_scalar() || type
->is_vector());
2723 r
->type
= type
->base_type
;
2725 st_src_reg l_src
= st_src_reg(*l
);
2726 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2728 if (native_integers
) {
2729 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2730 cond_swap
? l_src
: *r
,
2731 cond_swap
? *r
: l_src
);
2733 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2734 cond_swap
? l_src
: *r
,
2735 cond_swap
? *r
: l_src
);
2738 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2745 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2750 ir
->rhs
->accept(this);
2753 l
= get_assignment_lhs(ir
->lhs
, this);
2755 /* FINISHME: This should really set to the correct maximal writemask for each
2756 * FINISHME: component written (in the loops below). This case can only
2757 * FINISHME: occur for matrices, arrays, and structures.
2759 if (ir
->write_mask
== 0) {
2760 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2761 l
.writemask
= WRITEMASK_XYZW
;
2762 } else if (ir
->lhs
->type
->is_scalar() &&
2763 !ir
->lhs
->type
->is_double() &&
2764 ir
->lhs
->variable_referenced()->data
.mode
== ir_var_shader_out
) {
2765 /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
2766 * FINISHME: W component of fragment shader output zero, work correctly.
2768 l
.writemask
= WRITEMASK_XYZW
;
2771 int first_enabled_chan
= 0;
2774 l
.writemask
= ir
->write_mask
;
2776 for (int i
= 0; i
< 4; i
++) {
2777 if (l
.writemask
& (1 << i
)) {
2778 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
2783 /* Swizzle a small RHS vector into the channels being written.
2785 * glsl ir treats write_mask as dictating how many channels are
2786 * present on the RHS while TGSI treats write_mask as just
2787 * showing which channels of the vec4 RHS get written.
2789 for (int i
= 0; i
< 4; i
++) {
2790 if (l
.writemask
& (1 << i
))
2791 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
2793 swizzles
[i
] = first_enabled_chan
;
2795 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
2796 swizzles
[2], swizzles
[3]);
2799 assert(l
.file
!= PROGRAM_UNDEFINED
);
2800 assert(r
.file
!= PROGRAM_UNDEFINED
);
2802 if (ir
->condition
) {
2803 const bool switch_order
= this->process_move_condition(ir
->condition
);
2804 st_src_reg condition
= this->result
;
2806 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
2807 } else if (ir
->rhs
->as_expression() &&
2808 this->instructions
.get_tail() &&
2809 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
2810 type_size(ir
->lhs
->type
) == 1 &&
2811 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
2812 /* To avoid emitting an extra MOV when assigning an expression to a
2813 * variable, emit the last instruction of the expression again, but
2814 * replace the destination register with the target of the assignment.
2815 * Dead code elimination will remove the original instruction.
2817 glsl_to_tgsi_instruction
*inst
, *new_inst
;
2818 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
2819 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2]);
2820 new_inst
->saturate
= inst
->saturate
;
2821 inst
->dead_mask
= inst
->dst
[0].writemask
;
2823 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
2829 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
2832 GLdouble stack_vals
[4] = { 0 };
2833 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
2834 GLenum gl_type
= GL_NONE
;
2836 static int in_array
= 0;
2837 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
2839 /* Unfortunately, 4 floats is all we can get into
2840 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
2841 * aggregate constant and move each constant value into it. If we
2842 * get lucky, copy propagation will eliminate the extra moves.
2844 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
2845 st_src_reg temp_base
= get_temp(ir
->type
);
2846 st_dst_reg temp
= st_dst_reg(temp_base
);
2848 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
2849 int size
= type_size(field_value
->type
);
2853 field_value
->accept(this);
2856 for (i
= 0; i
< (unsigned int)size
; i
++) {
2857 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2863 this->result
= temp_base
;
2867 if (ir
->type
->is_array()) {
2868 st_src_reg temp_base
= get_temp(ir
->type
);
2869 st_dst_reg temp
= st_dst_reg(temp_base
);
2870 int size
= type_size(ir
->type
->fields
.array
);
2875 for (i
= 0; i
< ir
->type
->length
; i
++) {
2876 ir
->array_elements
[i
]->accept(this);
2878 for (int j
= 0; j
< size
; j
++) {
2879 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
2885 this->result
= temp_base
;
2890 if (ir
->type
->is_matrix()) {
2891 st_src_reg mat
= get_temp(ir
->type
);
2892 st_dst_reg mat_column
= st_dst_reg(mat
);
2894 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
2895 assert(ir
->type
->base_type
== GLSL_TYPE_FLOAT
);
2896 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
2898 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
2899 src
.index
= add_constant(file
,
2901 ir
->type
->vector_elements
,
2904 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
2913 switch (ir
->type
->base_type
) {
2914 case GLSL_TYPE_FLOAT
:
2916 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2917 values
[i
].f
= ir
->value
.f
[i
];
2920 case GLSL_TYPE_DOUBLE
:
2921 gl_type
= GL_DOUBLE
;
2922 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2923 values
[i
* 2].i
= *(uint32_t *)&ir
->value
.d
[i
];
2924 values
[i
* 2 + 1].i
= *(((uint32_t *)&ir
->value
.d
[i
]) + 1);
2927 case GLSL_TYPE_UINT
:
2928 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
2929 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2930 if (native_integers
)
2931 values
[i
].u
= ir
->value
.u
[i
];
2933 values
[i
].f
= ir
->value
.u
[i
];
2937 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
2938 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2939 if (native_integers
)
2940 values
[i
].i
= ir
->value
.i
[i
];
2942 values
[i
].f
= ir
->value
.i
[i
];
2945 case GLSL_TYPE_BOOL
:
2946 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
2947 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2948 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
2952 assert(!"Non-float/uint/int/bool constant");
2955 this->result
= st_src_reg(file
, -1, ir
->type
);
2956 this->result
.index
= add_constant(file
,
2958 ir
->type
->vector_elements
,
2960 &this->result
.swizzle
);
2964 glsl_to_tgsi_visitor::get_function_signature(ir_function_signature
*sig
)
2966 foreach_in_list_use_after(function_entry
, entry
, &this->function_signatures
) {
2967 if (entry
->sig
== sig
)
2971 entry
= ralloc(mem_ctx
, function_entry
);
2973 entry
->sig_id
= this->next_signature_id
++;
2974 entry
->bgn_inst
= NULL
;
2976 /* Allocate storage for all the parameters. */
2977 foreach_in_list(ir_variable
, param
, &sig
->parameters
) {
2978 variable_storage
*storage
;
2980 storage
= find_variable_storage(param
);
2983 st_src_reg src
= get_temp(param
->type
);
2985 storage
= new(mem_ctx
) variable_storage(param
, src
.file
, src
.index
);
2986 this->variables
.push_tail(storage
);
2989 if (!sig
->return_type
->is_void()) {
2990 entry
->return_reg
= get_temp(sig
->return_type
);
2992 entry
->return_reg
= undef_src
;
2995 this->function_signatures
.push_tail(entry
);
3000 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3002 glsl_to_tgsi_instruction
*call_inst
;
3003 ir_function_signature
*sig
= ir
->callee
;
3004 function_entry
*entry
= get_function_signature(sig
);
3007 /* Process in parameters. */
3008 foreach_two_lists(formal_node
, &sig
->parameters
,
3009 actual_node
, &ir
->actual_parameters
) {
3010 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3011 ir_variable
*param
= (ir_variable
*) formal_node
;
3013 if (param
->data
.mode
== ir_var_function_in
||
3014 param
->data
.mode
== ir_var_function_inout
) {
3015 variable_storage
*storage
= find_variable_storage(param
);
3018 param_rval
->accept(this);
3019 st_src_reg r
= this->result
;
3022 l
.file
= storage
->file
;
3023 l
.index
= storage
->index
;
3025 l
.writemask
= WRITEMASK_XYZW
;
3026 l
.cond_mask
= COND_TR
;
3028 for (i
= 0; i
< type_size(param
->type
); i
++) {
3029 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3036 /* Emit call instruction */
3037 call_inst
= emit_asm(ir
, TGSI_OPCODE_CAL
);
3038 call_inst
->function
= entry
;
3040 /* Process out parameters. */
3041 foreach_two_lists(formal_node
, &sig
->parameters
,
3042 actual_node
, &ir
->actual_parameters
) {
3043 ir_rvalue
*param_rval
= (ir_rvalue
*) actual_node
;
3044 ir_variable
*param
= (ir_variable
*) formal_node
;
3046 if (param
->data
.mode
== ir_var_function_out
||
3047 param
->data
.mode
== ir_var_function_inout
) {
3048 variable_storage
*storage
= find_variable_storage(param
);
3052 r
.file
= storage
->file
;
3053 r
.index
= storage
->index
;
3055 r
.swizzle
= SWIZZLE_NOOP
;
3058 param_rval
->accept(this);
3059 st_dst_reg l
= st_dst_reg(this->result
);
3061 for (i
= 0; i
< type_size(param
->type
); i
++) {
3062 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3069 /* Process return value. */
3070 this->result
= entry
->return_reg
;
3074 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3076 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3077 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3078 st_src_reg levels_src
;
3079 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3080 glsl_to_tgsi_instruction
*inst
= NULL
;
3081 unsigned opcode
= TGSI_OPCODE_NOP
;
3082 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3083 ir_rvalue
*sampler_index
=
3084 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
3085 bool is_cube_array
= false;
3088 /* if we are a cube array sampler */
3089 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3090 sampler_type
->sampler_array
)) {
3091 is_cube_array
= true;
3094 if (ir
->coordinate
) {
3095 ir
->coordinate
->accept(this);
3097 /* Put our coords in a temp. We'll need to modify them for shadow,
3098 * projection, or LOD, so the only case we'd use it as is is if
3099 * we're doing plain old texturing. The optimization passes on
3100 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3102 coord
= get_temp(glsl_type::vec4_type
);
3103 coord_dst
= st_dst_reg(coord
);
3104 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3105 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3108 if (ir
->projector
) {
3109 ir
->projector
->accept(this);
3110 projector
= this->result
;
3113 /* Storage for our result. Ideally for an assignment we'd be using
3114 * the actual storage for the result here, instead.
3116 result_src
= get_temp(ir
->type
);
3117 result_dst
= st_dst_reg(result_src
);
3121 opcode
= (is_cube_array
&& ir
->shadow_comparitor
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3123 ir
->offset
->accept(this);
3124 offset
[0] = this->result
;
3128 if (is_cube_array
||
3129 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3130 opcode
= TGSI_OPCODE_TXB2
;
3133 opcode
= TGSI_OPCODE_TXB
;
3135 ir
->lod_info
.bias
->accept(this);
3136 lod_info
= this->result
;
3138 ir
->offset
->accept(this);
3139 offset
[0] = this->result
;
3143 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
3144 ir
->lod_info
.lod
->accept(this);
3145 lod_info
= this->result
;
3147 ir
->offset
->accept(this);
3148 offset
[0] = this->result
;
3152 opcode
= TGSI_OPCODE_TXD
;
3153 ir
->lod_info
.grad
.dPdx
->accept(this);
3155 ir
->lod_info
.grad
.dPdy
->accept(this);
3158 ir
->offset
->accept(this);
3159 offset
[0] = this->result
;
3163 opcode
= TGSI_OPCODE_TXQ
;
3164 ir
->lod_info
.lod
->accept(this);
3165 lod_info
= this->result
;
3167 case ir_query_levels
:
3168 opcode
= TGSI_OPCODE_TXQ
;
3169 lod_info
= undef_src
;
3170 levels_src
= get_temp(ir
->type
);
3173 opcode
= TGSI_OPCODE_TXF
;
3174 ir
->lod_info
.lod
->accept(this);
3175 lod_info
= this->result
;
3177 ir
->offset
->accept(this);
3178 offset
[0] = this->result
;
3182 opcode
= TGSI_OPCODE_TXF
;
3183 ir
->lod_info
.sample_index
->accept(this);
3184 sample_index
= this->result
;
3187 opcode
= TGSI_OPCODE_TG4
;
3188 ir
->lod_info
.component
->accept(this);
3189 component
= this->result
;
3191 ir
->offset
->accept(this);
3192 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
3193 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
3194 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
3195 offset
[i
] = this->result
;
3196 offset
[i
].index
+= i
* type_size(elt_type
);
3197 offset
[i
].type
= elt_type
->base_type
;
3198 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
3201 offset
[0] = this->result
;
3206 opcode
= TGSI_OPCODE_LODQ
;
3210 if (ir
->projector
) {
3211 if (opcode
== TGSI_OPCODE_TEX
) {
3212 /* Slot the projector in as the last component of the coord. */
3213 coord_dst
.writemask
= WRITEMASK_W
;
3214 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
3215 coord_dst
.writemask
= WRITEMASK_XYZW
;
3216 opcode
= TGSI_OPCODE_TXP
;
3218 st_src_reg coord_w
= coord
;
3219 coord_w
.swizzle
= SWIZZLE_WWWW
;
3221 /* For the other TEX opcodes there's no projective version
3222 * since the last slot is taken up by LOD info. Do the
3223 * projective divide now.
3225 coord_dst
.writemask
= WRITEMASK_W
;
3226 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
3228 /* In the case where we have to project the coordinates "by hand,"
3229 * the shadow comparator value must also be projected.
3231 st_src_reg tmp_src
= coord
;
3232 if (ir
->shadow_comparitor
) {
3233 /* Slot the shadow value in as the second to last component of the
3236 ir
->shadow_comparitor
->accept(this);
3238 tmp_src
= get_temp(glsl_type::vec4_type
);
3239 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
3241 /* Projective division not allowed for array samplers. */
3242 assert(!sampler_type
->sampler_array
);
3244 tmp_dst
.writemask
= WRITEMASK_Z
;
3245 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
3247 tmp_dst
.writemask
= WRITEMASK_XY
;
3248 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
3251 coord_dst
.writemask
= WRITEMASK_XYZ
;
3252 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
3254 coord_dst
.writemask
= WRITEMASK_XYZW
;
3255 coord
.swizzle
= SWIZZLE_XYZW
;
3259 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
3260 * comparator was put in the correct place (and projected) by the code,
3261 * above, that handles by-hand projection.
3263 if (ir
->shadow_comparitor
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
3264 /* Slot the shadow value in as the second to last component of the
3267 ir
->shadow_comparitor
->accept(this);
3269 if (is_cube_array
) {
3270 cube_sc
= get_temp(glsl_type::float_type
);
3271 cube_sc_dst
= st_dst_reg(cube_sc
);
3272 cube_sc_dst
.writemask
= WRITEMASK_X
;
3273 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
3274 cube_sc_dst
.writemask
= WRITEMASK_X
;
3277 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
3278 sampler_type
->sampler_array
) ||
3279 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
3280 coord_dst
.writemask
= WRITEMASK_W
;
3282 coord_dst
.writemask
= WRITEMASK_Z
;
3284 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3285 coord_dst
.writemask
= WRITEMASK_XYZW
;
3289 if (ir
->op
== ir_txf_ms
) {
3290 coord_dst
.writemask
= WRITEMASK_W
;
3291 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
3292 coord_dst
.writemask
= WRITEMASK_XYZW
;
3293 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
3294 opcode
== TGSI_OPCODE_TXF
) {
3295 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
3296 coord_dst
.writemask
= WRITEMASK_W
;
3297 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
3298 coord_dst
.writemask
= WRITEMASK_XYZW
;
3301 if (sampler_index
) {
3302 sampler_index
->accept(this);
3303 emit_arl(ir
, sampler_reladdr
, this->result
);
3306 if (opcode
== TGSI_OPCODE_TXD
)
3307 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
3308 else if (opcode
== TGSI_OPCODE_TXQ
) {
3309 if (ir
->op
== ir_query_levels
) {
3310 /* the level is stored in W */
3311 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
3312 result_dst
.writemask
= WRITEMASK_X
;
3313 levels_src
.swizzle
= SWIZZLE_WWWW
;
3314 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
3316 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
3317 } else if (opcode
== TGSI_OPCODE_TXF
) {
3318 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3319 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
3320 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
3321 } else if (opcode
== TGSI_OPCODE_TEX2
) {
3322 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3323 } else if (opcode
== TGSI_OPCODE_TG4
) {
3324 if (is_cube_array
&& ir
->shadow_comparitor
) {
3325 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
3327 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
3330 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
3332 if (ir
->shadow_comparitor
)
3333 inst
->tex_shadow
= GL_TRUE
;
3335 inst
->sampler
.index
= _mesa_get_sampler_uniform_value(ir
->sampler
,
3336 this->shader_program
,
3338 if (sampler_index
) {
3339 inst
->sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3340 memcpy(inst
->sampler
.reladdr
, &sampler_reladdr
, sizeof(sampler_reladdr
));
3341 inst
->sampler_array_size
=
3342 ir
->sampler
->as_dereference_array()->array
->type
->array_size();
3344 inst
->sampler_array_size
= 1;
3348 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
3349 inst
->tex_offsets
[i
] = offset
[i
];
3350 inst
->tex_offset_num_offset
= i
;
3353 switch (sampler_type
->sampler_dimensionality
) {
3354 case GLSL_SAMPLER_DIM_1D
:
3355 inst
->tex_target
= (sampler_type
->sampler_array
)
3356 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3358 case GLSL_SAMPLER_DIM_2D
:
3359 inst
->tex_target
= (sampler_type
->sampler_array
)
3360 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3362 case GLSL_SAMPLER_DIM_3D
:
3363 inst
->tex_target
= TEXTURE_3D_INDEX
;
3365 case GLSL_SAMPLER_DIM_CUBE
:
3366 inst
->tex_target
= (sampler_type
->sampler_array
)
3367 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3369 case GLSL_SAMPLER_DIM_RECT
:
3370 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3372 case GLSL_SAMPLER_DIM_BUF
:
3373 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3375 case GLSL_SAMPLER_DIM_EXTERNAL
:
3376 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3378 case GLSL_SAMPLER_DIM_MS
:
3379 inst
->tex_target
= (sampler_type
->sampler_array
)
3380 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3383 assert(!"Should not get here.");
3386 inst
->tex_type
= ir
->type
->base_type
;
3388 this->result
= result_src
;
3392 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
3394 if (ir
->get_value()) {
3398 assert(current_function
);
3400 ir
->get_value()->accept(this);
3401 st_src_reg r
= this->result
;
3403 l
= st_dst_reg(current_function
->return_reg
);
3405 for (i
= 0; i
< type_size(current_function
->sig
->return_type
); i
++) {
3406 emit_asm(ir
, TGSI_OPCODE_MOV
, l
, r
);
3412 emit_asm(ir
, TGSI_OPCODE_RET
);
3416 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
3418 if (ir
->condition
) {
3419 ir
->condition
->accept(this);
3420 st_src_reg condition
= this->result
;
3422 /* Convert the bool condition to a float so we can negate. */
3423 if (native_integers
) {
3424 st_src_reg temp
= get_temp(ir
->condition
->type
);
3425 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
3426 condition
, st_src_reg_for_float(1.0));
3430 condition
.negate
= ~condition
.negate
;
3431 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
3433 /* unconditional kil */
3434 emit_asm(ir
, TGSI_OPCODE_KILL
);
3439 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
3442 glsl_to_tgsi_instruction
*if_inst
;
3444 ir
->condition
->accept(this);
3445 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3447 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
3449 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
3451 this->instructions
.push_tail(if_inst
);
3453 visit_exec_list(&ir
->then_instructions
, this);
3455 if (!ir
->else_instructions
.is_empty()) {
3456 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
3457 visit_exec_list(&ir
->else_instructions
, this);
3460 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
3465 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
3467 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3469 ir
->stream
->accept(this);
3470 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
3474 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
3476 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
3478 ir
->stream
->accept(this);
3479 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
3483 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
3485 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
3486 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
3488 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
3491 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
3493 result
.file
= PROGRAM_UNDEFINED
;
3498 num_input_arrays
= 0;
3499 num_output_arrays
= 0;
3500 next_signature_id
= 1;
3502 current_function
= NULL
;
3503 num_address_regs
= 0;
3505 indirect_addr_consts
= false;
3506 wpos_transform_const
= -1;
3508 native_integers
= false;
3509 mem_ctx
= ralloc_context(NULL
);
3512 shader_program
= NULL
;
3519 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
3522 ralloc_free(mem_ctx
);
3525 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
3532 * Count resources used by the given gpu program (number of texture
3536 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
3538 v
->samplers_used
= 0;
3540 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
3541 if (is_tex_instruction(inst
->op
)) {
3542 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
3543 unsigned idx
= inst
->sampler
.index
+ i
;
3544 v
->samplers_used
|= 1 << idx
;
3546 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
3547 v
->sampler_types
[idx
] = inst
->tex_type
;
3548 v
->sampler_targets
[idx
] =
3549 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
3551 if (inst
->tex_shadow
) {
3552 prog
->ShadowSamplers
|= 1 << (inst
->sampler
.index
+ i
);
3557 prog
->SamplersUsed
= v
->samplers_used
;
3559 if (v
->shader_program
!= NULL
)
3560 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
3564 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
3565 * are read from the given src in this instruction
3568 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
3570 int read_mask
= 0, comp
;
3572 /* Now, given the src swizzle and the written channels, find which
3573 * components are actually read
3575 for (comp
= 0; comp
< 4; ++comp
) {
3576 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
3578 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
3579 read_mask
|= 1 << coord
;
3586 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
3587 * instruction is the first instruction to write to register T0. There are
3588 * several lowering passes done in GLSL IR (e.g. branches and
3589 * relative addressing) that create a large number of conditional assignments
3590 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
3592 * Here is why this conversion is safe:
3593 * CMP T0, T1 T2 T0 can be expanded to:
3599 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
3600 * as the original program. If (T1 < 0.0) evaluates to false, executing
3601 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
3602 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
3603 * because any instruction that was going to read from T0 after this was going
3604 * to read a garbage value anyway.
3607 glsl_to_tgsi_visitor::simplify_cmp(void)
3609 int tempWritesSize
= 0;
3610 unsigned *tempWrites
= NULL
;
3611 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
3613 memset(outputWrites
, 0, sizeof(outputWrites
));
3615 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3616 unsigned prevWriteMask
= 0;
3618 /* Give up if we encounter relative addressing or flow control. */
3619 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
3620 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
3621 tgsi_get_opcode_info(inst
->op
)->is_branch
||
3622 inst
->op
== TGSI_OPCODE_BGNSUB
||
3623 inst
->op
== TGSI_OPCODE_CONT
||
3624 inst
->op
== TGSI_OPCODE_END
||
3625 inst
->op
== TGSI_OPCODE_ENDSUB
||
3626 inst
->op
== TGSI_OPCODE_RET
) {
3630 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
3631 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
3632 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
3633 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3634 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
3635 if (inst
->dst
[0].index
>= tempWritesSize
) {
3636 const int inc
= 4096;
3638 tempWrites
= (unsigned*)
3640 (tempWritesSize
+ inc
) * sizeof(unsigned));
3644 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
3645 tempWritesSize
+= inc
;
3648 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
3649 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
3653 /* For a CMP to be considered a conditional write, the destination
3654 * register and source register two must be the same. */
3655 if (inst
->op
== TGSI_OPCODE_CMP
3656 && !(inst
->dst
[0].writemask
& prevWriteMask
)
3657 && inst
->src
[2].file
== inst
->dst
[0].file
3658 && inst
->src
[2].index
== inst
->dst
[0].index
3659 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
3661 inst
->op
= TGSI_OPCODE_MOV
;
3662 inst
->src
[0] = inst
->src
[1];
3669 /* Replaces all references to a temporary register index with another index. */
3671 glsl_to_tgsi_visitor::rename_temp_register(int index
, int new_index
)
3673 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3676 for (j
= 0; j
< num_inst_src_regs(inst
->op
); j
++) {
3677 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
&&
3678 inst
->src
[j
].index
== index
) {
3679 inst
->src
[j
].index
= new_index
;
3683 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3684 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
&&
3685 inst
->tex_offsets
[j
].index
== index
) {
3686 inst
->tex_offsets
[j
].index
= new_index
;
3690 for (j
= 0; j
< num_inst_dst_regs(inst
->op
); j
++) {
3691 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[j
].index
== index
) {
3692 inst
->dst
[j
].index
= new_index
;
3699 glsl_to_tgsi_visitor::get_first_temp_read(int index
)
3701 int depth
= 0; /* loop depth */
3702 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3705 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3706 for (j
= 0; j
< num_inst_src_regs(inst
->op
); j
++) {
3707 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
&&
3708 inst
->src
[j
].index
== index
) {
3709 return (depth
== 0) ? i
: loop_start
;
3712 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3713 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
&&
3714 inst
->tex_offsets
[j
].index
== index
) {
3715 return (depth
== 0) ? i
: loop_start
;
3718 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3721 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3732 glsl_to_tgsi_visitor::get_first_temp_write(int index
)
3734 int depth
= 0; /* loop depth */
3735 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
3739 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3740 for (j
= 0; j
< num_inst_dst_regs(inst
->op
); j
++) {
3741 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[j
].index
== index
) {
3742 return (depth
== 0) ? i
: loop_start
;
3745 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
3748 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
3759 glsl_to_tgsi_visitor::get_last_temp_read(int index
)
3761 int depth
= 0; /* loop depth */
3762 int last
= -1; /* index of last instruction that reads the temporary */
3765 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3766 for (j
= 0; j
< num_inst_src_regs(inst
->op
); j
++) {
3767 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
&&
3768 inst
->src
[j
].index
== index
) {
3769 last
= (depth
== 0) ? i
: -2;
3772 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
3773 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
&&
3774 inst
->tex_offsets
[j
].index
== index
)
3775 last
= (depth
== 0) ? i
: -2;
3777 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
3779 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
3780 if (--depth
== 0 && last
== -2)
3790 glsl_to_tgsi_visitor::get_last_temp_write(int index
)
3792 int depth
= 0; /* loop depth */
3793 int last
= -1; /* index of last instruction that writes to the temporary */
3797 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3798 for (j
= 0; j
< num_inst_dst_regs(inst
->op
); j
++) {
3799 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[j
].index
== index
)
3800 last
= (depth
== 0) ? i
: -2;
3803 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
3805 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
3806 if (--depth
== 0 && last
== -2)
3816 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
3817 * channels for copy propagation and updates following instructions to
3818 * use the original versions.
3820 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
3821 * will occur. As an example, a TXP production before this pass:
3823 * 0: MOV TEMP[1], INPUT[4].xyyy;
3824 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3825 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
3829 * 0: MOV TEMP[1], INPUT[4].xyyy;
3830 * 1: MOV TEMP[1].w, INPUT[4].wwww;
3831 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
3833 * which allows for dead code elimination on TEMP[1]'s writes.
3836 glsl_to_tgsi_visitor::copy_propagate(void)
3838 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
3839 glsl_to_tgsi_instruction
*,
3840 this->next_temp
* 4);
3841 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
3844 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
3845 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
3846 || inst
->dst
[0].index
< this->next_temp
);
3848 /* First, do any copy propagation possible into the src regs. */
3849 for (int r
= 0; r
< 3; r
++) {
3850 glsl_to_tgsi_instruction
*first
= NULL
;
3852 int acp_base
= inst
->src
[r
].index
* 4;
3854 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
3855 inst
->src
[r
].reladdr
||
3856 inst
->src
[r
].reladdr2
)
3859 /* See if we can find entries in the ACP consisting of MOVs
3860 * from the same src register for all the swizzled channels
3861 * of this src register reference.
3863 for (int i
= 0; i
< 4; i
++) {
3864 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3865 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
3872 assert(acp_level
[acp_base
+ src_chan
] <= level
);
3877 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
3878 first
->src
[0].index
!= copy_chan
->src
[0].index
||
3879 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
3880 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
3888 /* We've now validated that we can copy-propagate to
3889 * replace this src register reference. Do it.
3891 inst
->src
[r
].file
= first
->src
[0].file
;
3892 inst
->src
[r
].index
= first
->src
[0].index
;
3893 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
3894 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
3895 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
3896 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
3899 for (int i
= 0; i
< 4; i
++) {
3900 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
3901 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
3902 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
3904 inst
->src
[r
].swizzle
= swizzle
;
3909 case TGSI_OPCODE_BGNLOOP
:
3910 case TGSI_OPCODE_ENDLOOP
:
3911 /* End of a basic block, clear the ACP entirely. */
3912 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3915 case TGSI_OPCODE_IF
:
3916 case TGSI_OPCODE_UIF
:
3920 case TGSI_OPCODE_ENDIF
:
3921 case TGSI_OPCODE_ELSE
:
3922 /* Clear all channels written inside the block from the ACP, but
3923 * leaving those that were not touched.
3925 for (int r
= 0; r
< this->next_temp
; r
++) {
3926 for (int c
= 0; c
< 4; c
++) {
3927 if (!acp
[4 * r
+ c
])
3930 if (acp_level
[4 * r
+ c
] >= level
)
3931 acp
[4 * r
+ c
] = NULL
;
3934 if (inst
->op
== TGSI_OPCODE_ENDIF
)
3939 /* Continuing the block, clear any written channels from
3942 for (int d
= 0; d
< 2; d
++) {
3943 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
3944 /* Any temporary might be written, so no copy propagation
3945 * across this instruction.
3947 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
3948 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
3949 inst
->dst
[d
].reladdr
) {
3950 /* Any output might be written, so no copy propagation
3951 * from outputs across this instruction.
3953 for (int r
= 0; r
< this->next_temp
; r
++) {
3954 for (int c
= 0; c
< 4; c
++) {
3955 if (!acp
[4 * r
+ c
])
3958 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
3959 acp
[4 * r
+ c
] = NULL
;
3962 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
3963 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
3964 /* Clear where it's used as dst. */
3965 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
3966 for (int c
= 0; c
< 4; c
++) {
3967 if (inst
->dst
[d
].writemask
& (1 << c
))
3968 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
3972 /* Clear where it's used as src. */
3973 for (int r
= 0; r
< this->next_temp
; r
++) {
3974 for (int c
= 0; c
< 4; c
++) {
3975 if (!acp
[4 * r
+ c
])
3978 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
3980 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
3981 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
3982 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
3983 acp
[4 * r
+ c
] = NULL
;
3992 /* If this is a copy, add it to the ACP. */
3993 if (inst
->op
== TGSI_OPCODE_MOV
&&
3994 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
3995 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
3996 inst
->dst
[0].index
== inst
->src
[0].index
) &&
3997 !inst
->dst
[0].reladdr
&&
3998 !inst
->dst
[0].reladdr2
&&
4000 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4001 !inst
->src
[0].reladdr
&&
4002 !inst
->src
[0].reladdr2
&&
4003 !inst
->src
[0].negate
) {
4004 for (int i
= 0; i
< 4; i
++) {
4005 if (inst
->dst
[0].writemask
& (1 << i
)) {
4006 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4007 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4013 ralloc_free(acp_level
);
4018 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4021 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4022 * will occur. As an example, a TXP production after copy propagation but
4025 * 0: MOV TEMP[1], INPUT[4].xyyy;
4026 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4027 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4029 * and after this pass:
4031 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4034 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4036 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4037 glsl_to_tgsi_instruction
*,
4038 this->next_temp
* 4);
4039 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4043 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4044 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4045 || inst
->dst
[0].index
< this->next_temp
);
4048 case TGSI_OPCODE_BGNLOOP
:
4049 case TGSI_OPCODE_ENDLOOP
:
4050 case TGSI_OPCODE_CONT
:
4051 case TGSI_OPCODE_BRK
:
4052 /* End of a basic block, clear the write array entirely.
4054 * This keeps us from killing dead code when the writes are
4055 * on either side of a loop, even when the register isn't touched
4056 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4057 * dead code of this type, so it shouldn't make a difference as long as
4058 * the dead code elimination pass in the GLSL compiler does its job.
4060 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4063 case TGSI_OPCODE_ENDIF
:
4064 case TGSI_OPCODE_ELSE
:
4065 /* Promote the recorded level of all channels written inside the
4066 * preceding if or else block to the level above the if/else block.
4068 for (int r
= 0; r
< this->next_temp
; r
++) {
4069 for (int c
= 0; c
< 4; c
++) {
4070 if (!writes
[4 * r
+ c
])
4073 if (write_level
[4 * r
+ c
] == level
)
4074 write_level
[4 * r
+ c
] = level
-1;
4077 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4081 case TGSI_OPCODE_IF
:
4082 case TGSI_OPCODE_UIF
:
4084 /* fallthrough to default case to mark the condition as read */
4086 /* Continuing the block, clear any channels from the write array that
4087 * are read by this instruction.
4089 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4090 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4091 /* Any temporary might be read, so no dead code elimination
4092 * across this instruction.
4094 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4095 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4096 /* Clear where it's used as src. */
4097 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4098 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4099 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4100 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4102 for (int c
= 0; c
< 4; c
++) {
4103 if (src_chans
& (1 << c
))
4104 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4108 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4109 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4110 /* Any temporary might be read, so no dead code elimination
4111 * across this instruction.
4113 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4114 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4115 /* Clear where it's used as src. */
4116 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4117 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4118 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4119 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4121 for (int c
= 0; c
< 4; c
++) {
4122 if (src_chans
& (1 << c
))
4123 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4130 /* If this instruction writes to a temporary, add it to the write array.
4131 * If there is already an instruction in the write array for one or more
4132 * of the channels, flag that channel write as dead.
4134 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4135 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
4136 !inst
->dst
[i
].reladdr
&&
4138 for (int c
= 0; c
< 4; c
++) {
4139 if (inst
->dst
[i
].writemask
& (1 << c
)) {
4140 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
4141 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
4144 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
4146 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
4147 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
4154 /* Anything still in the write array at this point is dead code. */
4155 for (int r
= 0; r
< this->next_temp
; r
++) {
4156 for (int c
= 0; c
< 4; c
++) {
4157 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
4159 inst
->dead_mask
|= (1 << c
);
4163 /* Now actually remove the instructions that are completely dead and update
4164 * the writemask of other instructions with dead channels.
4166 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4167 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
4169 else if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
4174 if (inst
->dst
[0].type
== GLSL_TYPE_DOUBLE
) {
4175 if (inst
->dead_mask
== WRITEMASK_XY
||
4176 inst
->dead_mask
== WRITEMASK_ZW
)
4177 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4179 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
4183 ralloc_free(write_level
);
4184 ralloc_free(writes
);
4189 /* merge DFRACEXP instructions into one. */
4191 glsl_to_tgsi_visitor::merge_two_dsts(void)
4193 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4194 glsl_to_tgsi_instruction
*inst2
;
4196 if (num_inst_dst_regs(inst
->op
) != 2)
4199 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
4200 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
4203 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
4206 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
4207 inst
->src
[0].index
== inst2
->src
[0].index
&&
4208 inst
->src
[0].type
== inst2
->src
[0].type
&&
4209 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
4211 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
4217 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
4219 inst
->dst
[0] = inst2
->dst
[0];
4220 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
4221 inst
->dst
[1] = inst2
->dst
[1];
4232 /* Merges temporary registers together where possible to reduce the number of
4233 * registers needed to run a program.
4235 * Produces optimal code only after copy propagation and dead code elimination
4238 glsl_to_tgsi_visitor::merge_registers(void)
4240 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4241 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
4244 /* Read the indices of the last read and first write to each temp register
4245 * into an array so that we don't have to traverse the instruction list as
4247 for (i
= 0; i
< this->next_temp
; i
++) {
4248 last_reads
[i
] = get_last_temp_read(i
);
4249 first_writes
[i
] = get_first_temp_write(i
);
4252 /* Start looking for registers with non-overlapping usages that can be
4253 * merged together. */
4254 for (i
= 0; i
< this->next_temp
; i
++) {
4255 /* Don't touch unused registers. */
4256 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
4258 for (j
= 0; j
< this->next_temp
; j
++) {
4259 /* Don't touch unused registers. */
4260 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
4262 /* We can merge the two registers if the first write to j is after or
4263 * in the same instruction as the last read from i. Note that the
4264 * register at index i will always be used earlier or at the same time
4265 * as the register at index j. */
4266 if (first_writes
[i
] <= first_writes
[j
] &&
4267 last_reads
[i
] <= first_writes
[j
]) {
4268 rename_temp_register(j
, i
); /* Replace all references to j with i.*/
4270 /* Update the first_writes and last_reads arrays with the new
4271 * values for the merged register index, and mark the newly unused
4272 * register index as such. */
4273 last_reads
[i
] = last_reads
[j
];
4274 first_writes
[j
] = -1;
4280 ralloc_free(last_reads
);
4281 ralloc_free(first_writes
);
4284 /* Reassign indices to temporary registers by reusing unused indices created
4285 * by optimization passes. */
4287 glsl_to_tgsi_visitor::renumber_registers(void)
4292 for (i
= 0; i
< this->next_temp
; i
++) {
4293 if (get_first_temp_read(i
) < 0) continue;
4295 rename_temp_register(i
, new_index
);
4299 this->next_temp
= new_index
;
4303 * Returns a fragment program which implements the current pixel transfer ops.
4304 * Based on get_pixel_transfer_program in st_atom_pixeltransfer.c.
4307 get_pixel_transfer_visitor(struct st_fragment_program
*fp
,
4308 glsl_to_tgsi_visitor
*original
,
4309 int scale_and_bias
, int pixel_maps
)
4311 glsl_to_tgsi_visitor
*v
= new glsl_to_tgsi_visitor();
4312 struct st_context
*st
= st_context(original
->ctx
);
4313 struct gl_program
*prog
= &fp
->Base
.Base
;
4314 struct gl_program_parameter_list
*params
= _mesa_new_parameter_list();
4315 st_src_reg coord
, src0
;
4317 glsl_to_tgsi_instruction
*inst
;
4319 /* Copy attributes of the glsl_to_tgsi_visitor in the original shader. */
4320 v
->ctx
= original
->ctx
;
4322 v
->shader_program
= NULL
;
4324 v
->glsl_version
= original
->glsl_version
;
4325 v
->native_integers
= original
->native_integers
;
4326 v
->options
= original
->options
;
4327 v
->next_temp
= original
->next_temp
;
4328 v
->num_address_regs
= original
->num_address_regs
;
4329 v
->samplers_used
= prog
->SamplersUsed
= original
->samplers_used
;
4330 v
->indirect_addr_consts
= original
->indirect_addr_consts
;
4331 memcpy(&v
->immediates
, &original
->immediates
, sizeof(v
->immediates
));
4332 v
->num_immediates
= original
->num_immediates
;
4335 * Get initial pixel color from the texture.
4336 * TEX colorTemp, fragment.texcoord[0], texture[0], 2D;
4338 coord
= st_src_reg(PROGRAM_INPUT
, VARYING_SLOT_TEX0
, glsl_type::vec2_type
);
4339 src0
= v
->get_temp(glsl_type::vec4_type
);
4340 dst0
= st_dst_reg(src0
);
4341 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, dst0
, coord
);
4342 inst
->sampler_array_size
= 1;
4343 inst
->tex_target
= TEXTURE_2D_INDEX
;
4345 prog
->InputsRead
|= VARYING_BIT_TEX0
;
4346 prog
->SamplersUsed
|= (1 << 0); /* mark sampler 0 as used */
4347 v
->samplers_used
|= (1 << 0);
4349 if (scale_and_bias
) {
4350 static const gl_state_index scale_state
[STATE_LENGTH
] =
4351 { STATE_INTERNAL
, STATE_PT_SCALE
,
4352 (gl_state_index
) 0, (gl_state_index
) 0, (gl_state_index
) 0 };
4353 static const gl_state_index bias_state
[STATE_LENGTH
] =
4354 { STATE_INTERNAL
, STATE_PT_BIAS
,
4355 (gl_state_index
) 0, (gl_state_index
) 0, (gl_state_index
) 0 };
4356 GLint scale_p
, bias_p
;
4357 st_src_reg scale
, bias
;
4359 scale_p
= _mesa_add_state_reference(params
, scale_state
);
4360 bias_p
= _mesa_add_state_reference(params
, bias_state
);
4362 /* MAD colorTemp, colorTemp, scale, bias; */
4363 scale
= st_src_reg(PROGRAM_STATE_VAR
, scale_p
, GLSL_TYPE_FLOAT
);
4364 bias
= st_src_reg(PROGRAM_STATE_VAR
, bias_p
, GLSL_TYPE_FLOAT
);
4365 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_MAD
, dst0
, src0
, scale
, bias
);
4369 st_src_reg temp
= v
->get_temp(glsl_type::vec4_type
);
4370 st_dst_reg temp_dst
= st_dst_reg(temp
);
4372 assert(st
->pixel_xfer
.pixelmap_texture
);
4375 /* With a little effort, we can do four pixel map look-ups with
4376 * two TEX instructions:
4379 /* TEX temp.rg, colorTemp.rgba, texture[1], 2D; */
4380 temp_dst
.writemask
= WRITEMASK_XY
; /* write R,G */
4381 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, temp_dst
, src0
);
4382 inst
->sampler
.index
= 1;
4383 inst
->sampler_array_size
= 1;
4384 inst
->tex_target
= TEXTURE_2D_INDEX
;
4386 /* TEX temp.ba, colorTemp.baba, texture[1], 2D; */
4387 src0
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
4388 temp_dst
.writemask
= WRITEMASK_ZW
; /* write B,A */
4389 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, temp_dst
, src0
);
4390 inst
->sampler
.index
= 1;
4391 inst
->sampler_array_size
= 1;
4392 inst
->tex_target
= TEXTURE_2D_INDEX
;
4394 prog
->SamplersUsed
|= (1 << 1); /* mark sampler 1 as used */
4395 v
->samplers_used
|= (1 << 1);
4397 /* MOV colorTemp, temp; */
4398 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_MOV
, dst0
, temp
);
4401 /* Now copy the instructions from the original glsl_to_tgsi_visitor into the
4403 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &original
->instructions
) {
4404 glsl_to_tgsi_instruction
*newinst
;
4405 st_src_reg src_regs
[3];
4407 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
)
4408 prog
->OutputsWritten
|= BITFIELD64_BIT(inst
->dst
[0].index
);
4410 for (int i
= 0; i
< 3; i
++) {
4411 src_regs
[i
] = inst
->src
[i
];
4412 if (src_regs
[i
].file
== PROGRAM_INPUT
&&
4413 src_regs
[i
].index
== VARYING_SLOT_COL0
) {
4414 src_regs
[i
].file
= PROGRAM_TEMPORARY
;
4415 src_regs
[i
].index
= src0
.index
;
4417 else if (src_regs
[i
].file
== PROGRAM_INPUT
)
4418 prog
->InputsRead
|= BITFIELD64_BIT(src_regs
[i
].index
);
4421 newinst
= v
->emit_asm(NULL
, inst
->op
, inst
->dst
[0], src_regs
[0], src_regs
[1], src_regs
[2]);
4422 newinst
->tex_target
= inst
->tex_target
;
4423 newinst
->sampler_array_size
= inst
->sampler_array_size
;
4426 /* Make modifications to fragment program info. */
4427 prog
->Parameters
= _mesa_combine_parameter_lists(params
,
4428 original
->prog
->Parameters
);
4429 _mesa_free_parameter_list(params
);
4430 count_resources(v
, prog
);
4431 fp
->glsl_to_tgsi
= v
;
4435 * Make fragment program for glBitmap:
4436 * Sample the texture and kill the fragment if the bit is 0.
4437 * This program will be combined with the user's fragment program.
4439 * Based on make_bitmap_fragment_program in st_cb_bitmap.c.
4442 get_bitmap_visitor(struct st_fragment_program
*fp
,
4443 glsl_to_tgsi_visitor
*original
, int samplerIndex
)
4445 glsl_to_tgsi_visitor
*v
= new glsl_to_tgsi_visitor();
4446 struct st_context
*st
= st_context(original
->ctx
);
4447 struct gl_program
*prog
= &fp
->Base
.Base
;
4448 st_src_reg coord
, src0
;
4450 glsl_to_tgsi_instruction
*inst
;
4452 /* Copy attributes of the glsl_to_tgsi_visitor in the original shader. */
4453 v
->ctx
= original
->ctx
;
4455 v
->shader_program
= NULL
;
4457 v
->glsl_version
= original
->glsl_version
;
4458 v
->native_integers
= original
->native_integers
;
4459 v
->options
= original
->options
;
4460 v
->next_temp
= original
->next_temp
;
4461 v
->num_address_regs
= original
->num_address_regs
;
4462 v
->samplers_used
= prog
->SamplersUsed
= original
->samplers_used
;
4463 v
->indirect_addr_consts
= original
->indirect_addr_consts
;
4464 memcpy(&v
->immediates
, &original
->immediates
, sizeof(v
->immediates
));
4465 v
->num_immediates
= original
->num_immediates
;
4467 /* TEX tmp0, fragment.texcoord[0], texture[0], 2D; */
4468 coord
= st_src_reg(PROGRAM_INPUT
, VARYING_SLOT_TEX0
, glsl_type::vec2_type
);
4469 src0
= v
->get_temp(glsl_type::vec4_type
);
4470 dst0
= st_dst_reg(src0
);
4471 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_TEX
, dst0
, coord
);
4472 inst
->sampler
.index
= samplerIndex
;
4473 inst
->sampler_array_size
= 1;
4474 inst
->tex_target
= TEXTURE_2D_INDEX
;
4476 prog
->InputsRead
|= VARYING_BIT_TEX0
;
4477 prog
->SamplersUsed
|= (1 << samplerIndex
); /* mark sampler as used */
4478 v
->samplers_used
|= (1 << samplerIndex
);
4480 /* KIL if -tmp0 < 0 # texel=0 -> keep / texel=0 -> discard */
4481 src0
.negate
= NEGATE_XYZW
;
4482 if (st
->bitmap
.tex_format
== PIPE_FORMAT_L8_UNORM
)
4483 src0
.swizzle
= SWIZZLE_XXXX
;
4484 inst
= v
->emit_asm(NULL
, TGSI_OPCODE_KILL_IF
, undef_dst
, src0
);
4486 /* Now copy the instructions from the original glsl_to_tgsi_visitor into the
4488 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &original
->instructions
) {
4489 glsl_to_tgsi_instruction
*newinst
;
4490 st_src_reg src_regs
[3];
4492 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
)
4493 prog
->OutputsWritten
|= BITFIELD64_BIT(inst
->dst
[0].index
);
4495 for (int i
= 0; i
< 3; i
++) {
4496 src_regs
[i
] = inst
->src
[i
];
4497 if (src_regs
[i
].file
== PROGRAM_INPUT
)
4498 prog
->InputsRead
|= BITFIELD64_BIT(src_regs
[i
].index
);
4501 newinst
= v
->emit_asm(NULL
, inst
->op
, inst
->dst
[0], src_regs
[0], src_regs
[1], src_regs
[2]);
4502 newinst
->tex_target
= inst
->tex_target
;
4503 newinst
->sampler_array_size
= inst
->sampler_array_size
;
4506 /* Make modifications to fragment program info. */
4507 prog
->Parameters
= _mesa_clone_parameter_list(original
->prog
->Parameters
);
4508 count_resources(v
, prog
);
4509 fp
->glsl_to_tgsi
= v
;
4512 /* ------------------------- TGSI conversion stuff -------------------------- */
4514 unsigned branch_target
;
4519 * Intermediate state used during shader translation.
4521 struct st_translate
{
4522 struct ureg_program
*ureg
;
4524 unsigned temps_size
;
4525 struct ureg_dst
*temps
;
4527 struct ureg_dst
*arrays
;
4528 unsigned num_temp_arrays
;
4529 struct ureg_src
*constants
;
4531 struct ureg_src
*immediates
;
4533 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
4534 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
4535 struct ureg_dst address
[3];
4536 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
4537 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
4538 struct tgsi_texture_offset tex_offsets
[MAX_GLSL_TEXTURE_OFFSET
];
4539 unsigned *array_sizes
;
4540 struct array_decl
*input_arrays
;
4541 struct array_decl
*output_arrays
;
4543 const GLuint
*inputMapping
;
4544 const GLuint
*outputMapping
;
4546 /* For every instruction that contains a label (eg CALL), keep
4547 * details so that we can go back afterwards and emit the correct
4548 * tgsi instruction number for each label.
4550 struct label
*labels
;
4551 unsigned labels_size
;
4552 unsigned labels_count
;
4554 /* Keep a record of the tgsi instruction number that each mesa
4555 * instruction starts at, will be used to fix up labels after
4560 unsigned insn_count
;
4562 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
4567 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
4568 const unsigned _mesa_sysval_to_semantic
[SYSTEM_VALUE_MAX
] = {
4571 TGSI_SEMANTIC_VERTEXID
,
4572 TGSI_SEMANTIC_INSTANCEID
,
4573 TGSI_SEMANTIC_VERTEXID_NOBASE
,
4574 TGSI_SEMANTIC_BASEVERTEX
,
4578 TGSI_SEMANTIC_INVOCATIONID
,
4583 TGSI_SEMANTIC_SAMPLEID
,
4584 TGSI_SEMANTIC_SAMPLEPOS
,
4585 TGSI_SEMANTIC_SAMPLEMASK
,
4587 /* Tessellation shaders
4589 TGSI_SEMANTIC_TESSCOORD
,
4590 TGSI_SEMANTIC_VERTICESIN
,
4591 TGSI_SEMANTIC_PRIMID
,
4592 TGSI_SEMANTIC_TESSOUTER
,
4593 TGSI_SEMANTIC_TESSINNER
,
4597 * Make note of a branch to a label in the TGSI code.
4598 * After we've emitted all instructions, we'll go over the list
4599 * of labels built here and patch the TGSI code with the actual
4600 * location of each label.
4602 static unsigned *get_label(struct st_translate
*t
, unsigned branch_target
)
4606 if (t
->labels_count
+ 1 >= t
->labels_size
) {
4607 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
4608 t
->labels
= (struct label
*)realloc(t
->labels
,
4609 t
->labels_size
* sizeof(struct label
));
4610 if (t
->labels
== NULL
) {
4611 static unsigned dummy
;
4617 i
= t
->labels_count
++;
4618 t
->labels
[i
].branch_target
= branch_target
;
4619 return &t
->labels
[i
].token
;
4623 * Called prior to emitting the TGSI code for each instruction.
4624 * Allocate additional space for instructions if needed.
4625 * Update the insn[] array so the next glsl_to_tgsi_instruction points to
4626 * the next TGSI instruction.
4628 static void set_insn_start(struct st_translate
*t
, unsigned start
)
4630 if (t
->insn_count
+ 1 >= t
->insn_size
) {
4631 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
4632 t
->insn
= (unsigned *)realloc(t
->insn
, t
->insn_size
* sizeof(t
->insn
[0]));
4633 if (t
->insn
== NULL
) {
4639 t
->insn
[t
->insn_count
++] = start
;
4643 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
4645 static struct ureg_src
4646 emit_immediate(struct st_translate
*t
,
4647 gl_constant_value values
[4],
4650 struct ureg_program
*ureg
= t
->ureg
;
4655 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
4657 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
4659 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
4660 case GL_UNSIGNED_INT
:
4662 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
4664 assert(!"should not get here - type must be float, int, uint, or bool");
4665 return ureg_src_undef();
4670 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
4672 static struct ureg_dst
4673 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
4679 case PROGRAM_UNDEFINED
:
4680 return ureg_dst_undef();
4682 case PROGRAM_TEMPORARY
:
4683 /* Allocate space for temporaries on demand. */
4684 if (index
>= t
->temps_size
) {
4685 const int inc
= 4096;
4687 t
->temps
= (struct ureg_dst
*)
4689 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
4691 return ureg_dst_undef();
4693 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
4694 t
->temps_size
+= inc
;
4697 if (ureg_dst_is_undef(t
->temps
[index
]))
4698 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
4700 return t
->temps
[index
];
4703 array
= index
>> 16;
4705 assert(array
< t
->num_temp_arrays
);
4707 if (ureg_dst_is_undef(t
->arrays
[array
]))
4708 t
->arrays
[array
] = ureg_DECL_array_temporary(
4709 t
->ureg
, t
->array_sizes
[array
], TRUE
);
4711 return ureg_dst_array_offset(t
->arrays
[array
],
4712 (int)(index
& 0xFFFF) - 0x8000);
4714 case PROGRAM_OUTPUT
:
4716 if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
4717 assert(index
< FRAG_RESULT_MAX
);
4718 else if (t
->procType
== TGSI_PROCESSOR_TESS_CTRL
||
4719 t
->procType
== TGSI_PROCESSOR_TESS_EVAL
)
4720 assert(index
< VARYING_SLOT_TESS_MAX
);
4722 assert(index
< VARYING_SLOT_MAX
);
4724 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
4725 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
4726 return t
->outputs
[t
->outputMapping
[index
]];
4729 struct array_decl
*decl
= &t
->output_arrays
[array_id
-1];
4730 unsigned mesa_index
= decl
->mesa_index
;
4731 int slot
= t
->outputMapping
[mesa_index
];
4733 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
4734 assert(t
->outputs
[slot
].ArrayID
== array_id
);
4735 return ureg_dst_array_offset(t
->outputs
[slot
], index
- mesa_index
);
4738 case PROGRAM_ADDRESS
:
4739 return t
->address
[index
];
4742 assert(!"unknown dst register file");
4743 return ureg_dst_undef();
4748 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
4750 static struct ureg_src
4751 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
4753 int index
= reg
->index
;
4754 int double_reg2
= reg
->double_reg2
? 1 : 0;
4757 case PROGRAM_UNDEFINED
:
4758 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4760 case PROGRAM_TEMPORARY
:
4762 case PROGRAM_OUTPUT
:
4763 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
4765 case PROGRAM_UNIFORM
:
4766 assert(reg
->index
>= 0);
4767 return reg
->index
< t
->num_constants
?
4768 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4769 case PROGRAM_STATE_VAR
:
4770 case PROGRAM_CONSTANT
: /* ie, immediate */
4771 if (reg
->has_index2
)
4772 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
4774 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
4775 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
4777 case PROGRAM_IMMEDIATE
:
4778 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
4779 return t
->immediates
[reg
->index
];
4782 /* GLSL inputs are 64-bit containers, so we have to
4783 * map back to the original index and add the offset after
4785 index
-= double_reg2
;
4786 if (!reg
->array_id
) {
4787 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
4788 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
4789 return t
->inputs
[t
->inputMapping
[index
]];
4792 struct array_decl
*decl
= &t
->input_arrays
[reg
->array_id
-1];
4793 unsigned mesa_index
= decl
->mesa_index
;
4794 int slot
= t
->inputMapping
[mesa_index
];
4796 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
4797 assert(t
->inputs
[slot
].ArrayID
== reg
->array_id
);
4798 return ureg_src_array_offset(t
->inputs
[slot
], index
- mesa_index
);
4801 case PROGRAM_ADDRESS
:
4802 return ureg_src(t
->address
[reg
->index
]);
4804 case PROGRAM_SYSTEM_VALUE
:
4805 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
4806 return t
->systemValues
[reg
->index
];
4809 assert(!"unknown src register file");
4810 return ureg_src_undef();
4815 * Create a TGSI ureg_dst register from an st_dst_reg.
4817 static struct ureg_dst
4818 translate_dst(struct st_translate
*t
,
4819 const st_dst_reg
*dst_reg
,
4820 bool saturate
, bool clamp_color
)
4822 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
4825 if (dst
.File
== TGSI_FILE_NULL
)
4828 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
4831 dst
= ureg_saturate(dst
);
4832 else if (clamp_color
&& dst_reg
->file
== PROGRAM_OUTPUT
) {
4833 /* Clamp colors for ARB_color_buffer_float. */
4834 switch (t
->procType
) {
4835 case TGSI_PROCESSOR_VERTEX
:
4836 /* This can only occur with a compatibility profile, which doesn't
4837 * support geometry shaders. */
4838 if (dst_reg
->index
== VARYING_SLOT_COL0
||
4839 dst_reg
->index
== VARYING_SLOT_COL1
||
4840 dst_reg
->index
== VARYING_SLOT_BFC0
||
4841 dst_reg
->index
== VARYING_SLOT_BFC1
) {
4842 dst
= ureg_saturate(dst
);
4846 case TGSI_PROCESSOR_FRAGMENT
:
4847 if (dst_reg
->index
== FRAG_RESULT_COLOR
||
4848 dst_reg
->index
>= FRAG_RESULT_DATA0
) {
4849 dst
= ureg_saturate(dst
);
4855 if (dst_reg
->reladdr
!= NULL
) {
4856 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
4857 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
4860 if (dst_reg
->has_index2
) {
4861 if (dst_reg
->reladdr2
)
4862 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
4865 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
4872 * Create a TGSI ureg_src register from an st_src_reg.
4874 static struct ureg_src
4875 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
4877 struct ureg_src src
= src_register(t
, src_reg
);
4879 if (src_reg
->has_index2
) {
4880 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
4881 * and UBO constant buffers (buffer, position).
4883 if (src_reg
->reladdr2
)
4884 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
4887 src
= ureg_src_dimension(src
, src_reg
->index2D
);
4890 src
= ureg_swizzle(src
,
4891 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
4892 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
4893 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
4894 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
4896 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
4897 src
= ureg_negate(src
);
4899 if (src_reg
->reladdr
!= NULL
) {
4900 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
4901 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
4907 static struct tgsi_texture_offset
4908 translate_tex_offset(struct st_translate
*t
,
4909 const st_src_reg
*in_offset
, int idx
)
4911 struct tgsi_texture_offset offset
;
4912 struct ureg_src imm_src
;
4913 struct ureg_dst dst
;
4916 switch (in_offset
->file
) {
4917 case PROGRAM_IMMEDIATE
:
4918 assert(in_offset
->index
>= 0 && in_offset
->index
< t
->num_immediates
);
4919 imm_src
= t
->immediates
[in_offset
->index
];
4921 offset
.File
= imm_src
.File
;
4922 offset
.Index
= imm_src
.Index
;
4923 offset
.SwizzleX
= imm_src
.SwizzleX
;
4924 offset
.SwizzleY
= imm_src
.SwizzleY
;
4925 offset
.SwizzleZ
= imm_src
.SwizzleZ
;
4928 case PROGRAM_TEMPORARY
:
4929 imm_src
= ureg_src(t
->temps
[in_offset
->index
]);
4930 offset
.File
= imm_src
.File
;
4931 offset
.Index
= imm_src
.Index
;
4932 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4933 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4934 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4938 array
= in_offset
->index
>> 16;
4941 assert(array
< (int)t
->num_temp_arrays
);
4943 dst
= t
->arrays
[array
];
4944 offset
.File
= dst
.File
;
4945 offset
.Index
= dst
.Index
+ (in_offset
->index
& 0xFFFF) - 0x8000;
4946 offset
.SwizzleX
= GET_SWZ(in_offset
->swizzle
, 0);
4947 offset
.SwizzleY
= GET_SWZ(in_offset
->swizzle
, 1);
4948 offset
.SwizzleZ
= GET_SWZ(in_offset
->swizzle
, 2);
4958 compile_tgsi_instruction(struct st_translate
*t
,
4959 const glsl_to_tgsi_instruction
*inst
,
4960 bool clamp_dst_color_output
)
4962 struct ureg_program
*ureg
= t
->ureg
;
4964 struct ureg_dst dst
[2];
4965 struct ureg_src src
[4];
4966 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
4970 unsigned tex_target
;
4972 num_dst
= num_inst_dst_regs(inst
->op
);
4973 num_src
= num_inst_src_regs(inst
->op
);
4975 for (i
= 0; i
< num_dst
; i
++)
4976 dst
[i
] = translate_dst(t
,
4979 clamp_dst_color_output
);
4981 for (i
= 0; i
< num_src
; i
++)
4982 src
[i
] = translate_src(t
, &inst
->src
[i
]);
4985 case TGSI_OPCODE_BGNLOOP
:
4986 case TGSI_OPCODE_CAL
:
4987 case TGSI_OPCODE_ELSE
:
4988 case TGSI_OPCODE_ENDLOOP
:
4989 case TGSI_OPCODE_IF
:
4990 case TGSI_OPCODE_UIF
:
4991 assert(num_dst
== 0);
4992 ureg_label_insn(ureg
,
4996 inst
->op
== TGSI_OPCODE_CAL
? inst
->function
->sig_id
: 0));
4999 case TGSI_OPCODE_TEX
:
5000 case TGSI_OPCODE_TXB
:
5001 case TGSI_OPCODE_TXD
:
5002 case TGSI_OPCODE_TXL
:
5003 case TGSI_OPCODE_TXP
:
5004 case TGSI_OPCODE_TXQ
:
5005 case TGSI_OPCODE_TXF
:
5006 case TGSI_OPCODE_TEX2
:
5007 case TGSI_OPCODE_TXB2
:
5008 case TGSI_OPCODE_TXL2
:
5009 case TGSI_OPCODE_TG4
:
5010 case TGSI_OPCODE_LODQ
:
5011 src
[num_src
] = t
->samplers
[inst
->sampler
.index
];
5012 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5013 if (inst
->sampler
.reladdr
)
5015 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5017 for (i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5018 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
], i
);
5020 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5026 texoffsets
, inst
->tex_offset_num_offset
,
5030 case TGSI_OPCODE_SCS
:
5031 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5032 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5045 * Emit the TGSI instructions for inverting and adjusting WPOS.
5046 * This code is unavoidable because it also depends on whether
5047 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5050 emit_wpos_adjustment( struct st_translate
*t
,
5051 int wpos_transform_const
,
5053 GLfloat adjX
, GLfloat adjY
[2])
5055 struct ureg_program
*ureg
= t
->ureg
;
5057 assert(wpos_transform_const
>= 0);
5059 /* Fragment program uses fragment position input.
5060 * Need to replace instances of INPUT[WPOS] with temp T
5061 * where T = INPUT[WPOS] is inverted by Y.
5063 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5064 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5065 struct ureg_src wpos_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5067 /* First, apply the coordinate shift: */
5068 if (adjX
|| adjY
[0] || adjY
[1]) {
5069 if (adjY
[0] != adjY
[1]) {
5070 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5071 * depending on whether inversion is actually going to be applied
5072 * or not, which is determined by testing against the inversion
5073 * state variable used below, which will be either +1 or -1.
5075 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5077 ureg_CMP(ureg
, adj_temp
,
5078 ureg_scalar(wpostrans
, invert
? 2 : 0),
5079 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5080 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5081 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5083 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5084 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5086 wpos_input
= ureg_src(wpos_temp
);
5088 /* MOV wpos_temp, input[wpos]
5090 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5093 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5094 * inversion/identity, or the other way around if we're drawing to an FBO.
5097 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5100 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5102 ureg_scalar(wpostrans
, 0),
5103 ureg_scalar(wpostrans
, 1));
5105 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5108 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5110 ureg_scalar(wpostrans
, 2),
5111 ureg_scalar(wpostrans
, 3));
5114 /* Use wpos_temp as position input from here on:
5116 t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]] = ureg_src(wpos_temp
);
5121 * Emit fragment position/ooordinate code.
5124 emit_wpos(struct st_context
*st
,
5125 struct st_translate
*t
,
5126 const struct gl_program
*program
,
5127 struct ureg_program
*ureg
,
5128 int wpos_transform_const
)
5130 const struct gl_fragment_program
*fp
=
5131 (const struct gl_fragment_program
*) program
;
5132 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5133 GLfloat adjX
= 0.0f
;
5134 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5135 boolean invert
= FALSE
;
5137 /* Query the pixel center conventions supported by the pipe driver and set
5138 * adjX, adjY to help out if it cannot handle the requested one internally.
5140 * The bias of the y-coordinate depends on whether y-inversion takes place
5141 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5142 * drawing to an FBO (causes additional inversion), and whether the the pipe
5143 * driver origin and the requested origin differ (the latter condition is
5144 * stored in the 'invert' variable).
5146 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5148 * center shift only:
5153 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5154 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5155 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5156 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5158 * inversion and center shift:
5159 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5160 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5161 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5162 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5164 if (fp
->OriginUpperLeft
) {
5165 /* Fragment shader wants origin in upper-left */
5166 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5167 /* the driver supports upper-left origin */
5169 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5170 /* the driver supports lower-left origin, need to invert Y */
5171 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5172 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5179 /* Fragment shader wants origin in lower-left */
5180 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5181 /* the driver supports lower-left origin */
5182 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5183 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5184 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5185 /* the driver supports upper-left origin, need to invert Y */
5191 if (fp
->PixelCenterInteger
) {
5192 /* Fragment shader wants pixel center integer */
5193 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5194 /* the driver supports pixel center integer */
5196 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5197 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5199 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5200 /* the driver supports pixel center half integer, need to bias X,Y */
5209 /* Fragment shader wants pixel center half integer */
5210 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5211 /* the driver supports pixel center half integer */
5213 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5214 /* the driver supports pixel center integer, need to bias X,Y */
5215 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5216 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5217 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5223 /* we invert after adjustment so that we avoid the MOV to temporary,
5224 * and reuse the adjustment ADD instead */
5225 emit_wpos_adjustment(t
, wpos_transform_const
, invert
, adjX
, adjY
);
5229 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5230 * TGSI uses +1 for front, -1 for back.
5231 * This function converts the TGSI value to the GL value. Simply clamping/
5232 * saturating the value to [0,1] does the job.
5235 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5237 struct ureg_program
*ureg
= t
->ureg
;
5238 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5239 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5241 if (ctx
->Const
.NativeIntegers
) {
5242 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5245 /* MOV_SAT face_temp, input[face] */
5246 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5249 /* Use face_temp as face input from here on: */
5250 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5254 emit_edgeflags(struct st_translate
*t
)
5256 struct ureg_program
*ureg
= t
->ureg
;
5257 struct ureg_dst edge_dst
= t
->outputs
[t
->outputMapping
[VARYING_SLOT_EDGE
]];
5258 struct ureg_src edge_src
= t
->inputs
[t
->inputMapping
[VERT_ATTRIB_EDGEFLAG
]];
5260 ureg_MOV(ureg
, edge_dst
, edge_src
);
5264 find_array(unsigned attr
, struct array_decl
*arrays
, unsigned count
,
5265 unsigned *array_id
, unsigned *array_size
)
5269 for (i
= 0; i
< count
; i
++) {
5270 struct array_decl
*decl
= &arrays
[i
];
5272 if (attr
== decl
->mesa_index
) {
5273 *array_id
= decl
->array_id
;
5274 *array_size
= decl
->array_size
;
5275 assert(*array_size
);
5283 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5284 * \param program the program to translate
5285 * \param numInputs number of input registers used
5286 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5288 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5289 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5291 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5292 * \param interpLocation the TGSI_INTERPOLATE_LOC_* location for each input
5293 * \param numOutputs number of output registers used
5294 * \param outputMapping maps Mesa fragment program outputs to TGSI
5296 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5297 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5300 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5302 extern "C" enum pipe_error
5303 st_translate_program(
5304 struct gl_context
*ctx
,
5306 struct ureg_program
*ureg
,
5307 glsl_to_tgsi_visitor
*program
,
5308 const struct gl_program
*proginfo
,
5310 const GLuint inputMapping
[],
5311 const GLuint inputSlotToAttr
[],
5312 const ubyte inputSemanticName
[],
5313 const ubyte inputSemanticIndex
[],
5314 const GLuint interpMode
[],
5315 const GLuint interpLocation
[],
5317 const GLuint outputMapping
[],
5318 const GLuint outputSlotToAttr
[],
5319 const ubyte outputSemanticName
[],
5320 const ubyte outputSemanticIndex
[],
5321 boolean passthrough_edgeflags
,
5322 boolean clamp_color
)
5324 struct st_translate
*t
;
5326 enum pipe_error ret
= PIPE_OK
;
5328 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
5329 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
5331 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_FRONT_FACE
] ==
5332 TGSI_SEMANTIC_FACE
);
5333 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID
] ==
5334 TGSI_SEMANTIC_VERTEXID
);
5335 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INSTANCE_ID
] ==
5336 TGSI_SEMANTIC_INSTANCEID
);
5337 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_ID
] ==
5338 TGSI_SEMANTIC_SAMPLEID
);
5339 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_POS
] ==
5340 TGSI_SEMANTIC_SAMPLEPOS
);
5341 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_SAMPLE_MASK_IN
] ==
5342 TGSI_SEMANTIC_SAMPLEMASK
);
5343 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_INVOCATION_ID
] ==
5344 TGSI_SEMANTIC_INVOCATIONID
);
5345 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
] ==
5346 TGSI_SEMANTIC_VERTEXID_NOBASE
);
5347 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_BASE_VERTEX
] ==
5348 TGSI_SEMANTIC_BASEVERTEX
);
5349 assert(_mesa_sysval_to_semantic
[SYSTEM_VALUE_TESS_COORD
] ==
5350 TGSI_SEMANTIC_TESSCOORD
);
5352 t
= CALLOC_STRUCT(st_translate
);
5354 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5358 t
->procType
= procType
;
5359 t
->inputMapping
= inputMapping
;
5360 t
->outputMapping
= outputMapping
;
5362 t
->num_temp_arrays
= program
->next_array
;
5363 if (t
->num_temp_arrays
)
5364 t
->arrays
= (struct ureg_dst
*)
5365 calloc(1, sizeof(t
->arrays
[0]) * t
->num_temp_arrays
);
5368 * Declare input attributes.
5371 case TGSI_PROCESSOR_FRAGMENT
:
5372 for (i
= 0; i
< numInputs
; i
++) {
5373 unsigned array_id
= 0;
5374 unsigned array_size
;
5376 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5377 program
->num_input_arrays
, &array_id
, &array_size
)) {
5378 /* We've found an array. Declare it so. */
5379 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5380 inputSemanticName
[i
], inputSemanticIndex
[i
],
5381 interpMode
[i
], 0, interpLocation
[i
],
5382 array_id
, array_size
);
5383 i
+= array_size
- 1;
5386 t
->inputs
[i
] = ureg_DECL_fs_input_cyl_centroid(ureg
,
5387 inputSemanticName
[i
], inputSemanticIndex
[i
],
5388 interpMode
[i
], 0, interpLocation
[i
], 0, 1);
5392 case TGSI_PROCESSOR_GEOMETRY
:
5393 case TGSI_PROCESSOR_TESS_EVAL
:
5394 case TGSI_PROCESSOR_TESS_CTRL
:
5395 for (i
= 0; i
< numInputs
; i
++) {
5396 unsigned array_id
= 0;
5397 unsigned array_size
;
5399 if (find_array(inputSlotToAttr
[i
], program
->input_arrays
,
5400 program
->num_input_arrays
, &array_id
, &array_size
)) {
5401 /* We've found an array. Declare it so. */
5402 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
5403 inputSemanticIndex
[i
],
5404 array_id
, array_size
);
5405 i
+= array_size
- 1;
5408 t
->inputs
[i
] = ureg_DECL_input(ureg
, inputSemanticName
[i
],
5409 inputSemanticIndex
[i
], 0, 1);
5413 case TGSI_PROCESSOR_VERTEX
:
5414 for (i
= 0; i
< numInputs
; i
++) {
5415 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
5423 * Declare output attributes.
5426 case TGSI_PROCESSOR_FRAGMENT
:
5428 case TGSI_PROCESSOR_GEOMETRY
:
5429 case TGSI_PROCESSOR_TESS_EVAL
:
5430 case TGSI_PROCESSOR_TESS_CTRL
:
5431 case TGSI_PROCESSOR_VERTEX
:
5432 for (i
= 0; i
< numOutputs
; i
++) {
5433 unsigned array_id
= 0;
5434 unsigned array_size
;
5436 if (find_array(outputSlotToAttr
[i
], program
->output_arrays
,
5437 program
->num_output_arrays
, &array_id
, &array_size
)) {
5438 /* We've found an array. Declare it so. */
5439 t
->outputs
[i
] = ureg_DECL_output_array(ureg
,
5440 outputSemanticName
[i
],
5441 outputSemanticIndex
[i
],
5442 array_id
, array_size
);
5443 i
+= array_size
- 1;
5446 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5447 outputSemanticName
[i
],
5448 outputSemanticIndex
[i
]);
5456 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
5457 if (proginfo
->InputsRead
& VARYING_BIT_POS
) {
5458 /* Must do this after setting up t->inputs. */
5459 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
5460 program
->wpos_transform_const
);
5463 if (proginfo
->InputsRead
& VARYING_BIT_FACE
)
5464 emit_face_var(ctx
, t
);
5466 for (i
= 0; i
< numOutputs
; i
++) {
5467 switch (outputSemanticName
[i
]) {
5468 case TGSI_SEMANTIC_POSITION
:
5469 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5470 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
5471 outputSemanticIndex
[i
]);
5472 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
5474 case TGSI_SEMANTIC_STENCIL
:
5475 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5476 TGSI_SEMANTIC_STENCIL
, /* Stencil */
5477 outputSemanticIndex
[i
]);
5478 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
5480 case TGSI_SEMANTIC_COLOR
:
5481 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5482 TGSI_SEMANTIC_COLOR
,
5483 outputSemanticIndex
[i
]);
5485 case TGSI_SEMANTIC_SAMPLEMASK
:
5486 t
->outputs
[i
] = ureg_DECL_output(ureg
,
5487 TGSI_SEMANTIC_SAMPLEMASK
,
5488 outputSemanticIndex
[i
]);
5489 /* TODO: If we ever support more than 32 samples, this will have
5490 * to become an array.
5492 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5495 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
5496 ret
= PIPE_ERROR_BAD_INPUT
;
5501 else if (procType
== TGSI_PROCESSOR_VERTEX
) {
5502 for (i
= 0; i
< numOutputs
; i
++) {
5503 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
5504 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
5506 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
5507 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
5508 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
5511 if (passthrough_edgeflags
)
5515 /* Declare address register.
5517 if (program
->num_address_regs
> 0) {
5518 assert(program
->num_address_regs
<= 3);
5519 for (int i
= 0; i
< program
->num_address_regs
; i
++)
5520 t
->address
[i
] = ureg_DECL_address(ureg
);
5523 /* Declare misc input registers
5526 GLbitfield sysInputs
= proginfo
->SystemValuesRead
;
5527 unsigned numSys
= 0;
5528 for (i
= 0; sysInputs
; i
++) {
5529 if (sysInputs
& (1 << i
)) {
5530 unsigned semName
= _mesa_sysval_to_semantic
[i
];
5531 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, numSys
, semName
, 0);
5532 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
5533 semName
== TGSI_SEMANTIC_VERTEXID
) {
5534 /* From Gallium perspective, these system values are always
5535 * integer, and require native integer support. However, if
5536 * native integer is supported on the vertex stage but not the
5537 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
5538 * assumes these system values are floats. To resolve the
5539 * inconsistency, we insert a U2F.
5541 struct st_context
*st
= st_context(ctx
);
5542 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5543 assert(procType
== TGSI_PROCESSOR_VERTEX
);
5544 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
5546 if (!ctx
->Const
.NativeIntegers
) {
5547 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
5548 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
5549 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
5553 sysInputs
&= ~(1 << i
);
5558 t
->array_sizes
= program
->array_sizes
;
5559 t
->input_arrays
= program
->input_arrays
;
5560 t
->output_arrays
= program
->output_arrays
;
5562 /* Emit constants and uniforms. TGSI uses a single index space for these,
5563 * so we put all the translated regs in t->constants.
5565 if (proginfo
->Parameters
) {
5566 t
->constants
= (struct ureg_src
*)
5567 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
5568 if (t
->constants
== NULL
) {
5569 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5572 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
5574 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
5575 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
5576 case PROGRAM_STATE_VAR
:
5577 case PROGRAM_UNIFORM
:
5578 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5581 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
5582 * addressing of the const buffer.
5583 * FIXME: Be smarter and recognize param arrays:
5584 * indirect addressing is only valid within the referenced
5587 case PROGRAM_CONSTANT
:
5588 if (program
->indirect_addr_consts
)
5589 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
5591 t
->constants
[i
] = emit_immediate(t
,
5592 proginfo
->Parameters
->ParameterValues
[i
],
5593 proginfo
->Parameters
->Parameters
[i
].DataType
,
5602 if (program
->shader
) {
5603 unsigned num_ubos
= program
->shader
->NumUniformBlocks
;
5605 for (i
= 0; i
< num_ubos
; i
++) {
5606 unsigned size
= program
->shader
->UniformBlocks
[i
].UniformBufferSize
;
5607 unsigned num_const_vecs
= (size
+ 15) / 16;
5608 unsigned first
, last
;
5609 assert(num_const_vecs
> 0);
5611 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
5612 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
5616 /* Emit immediate values.
5618 t
->immediates
= (struct ureg_src
*)
5619 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
5620 if (t
->immediates
== NULL
) {
5621 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
5624 t
->num_immediates
= program
->num_immediates
;
5627 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
5628 assert(i
< program
->num_immediates
);
5629 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
5631 assert(i
== program
->num_immediates
);
5633 /* texture samplers */
5634 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
5635 if (program
->samplers_used
& (1 << i
)) {
5638 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
5640 switch (program
->sampler_types
[i
]) {
5642 type
= TGSI_RETURN_TYPE_SINT
;
5644 case GLSL_TYPE_UINT
:
5645 type
= TGSI_RETURN_TYPE_UINT
;
5647 case GLSL_TYPE_FLOAT
:
5648 type
= TGSI_RETURN_TYPE_FLOAT
;
5651 unreachable("not reached");
5654 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
5655 type
, type
, type
, type
);
5659 /* Emit each instruction in turn:
5661 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
) {
5662 set_insn_start(t
, ureg_get_instruction_number(ureg
));
5663 compile_tgsi_instruction(t
, inst
, clamp_color
);
5666 /* Fix up all emitted labels:
5668 for (i
= 0; i
< t
->labels_count
; i
++) {
5669 ureg_fixup_label(ureg
, t
->labels
[i
].token
,
5670 t
->insn
[t
->labels
[i
].branch_target
]);
5680 t
->num_constants
= 0;
5681 free(t
->immediates
);
5682 t
->num_immediates
= 0;
5685 debug_printf("%s: translate error flag set\n", __func__
);
5693 /* ----------------------------- End TGSI code ------------------------------ */
5697 shader_stage_to_ptarget(gl_shader_stage stage
)
5700 case MESA_SHADER_VERTEX
:
5701 return PIPE_SHADER_VERTEX
;
5702 case MESA_SHADER_FRAGMENT
:
5703 return PIPE_SHADER_FRAGMENT
;
5704 case MESA_SHADER_GEOMETRY
:
5705 return PIPE_SHADER_GEOMETRY
;
5706 case MESA_SHADER_TESS_CTRL
:
5707 return PIPE_SHADER_TESS_CTRL
;
5708 case MESA_SHADER_TESS_EVAL
:
5709 return PIPE_SHADER_TESS_EVAL
;
5710 case MESA_SHADER_COMPUTE
:
5711 return PIPE_SHADER_COMPUTE
;
5714 assert(!"should not be reached");
5715 return PIPE_SHADER_VERTEX
;
5720 * Convert a shader's GLSL IR into a Mesa gl_program, although without
5721 * generating Mesa IR.
5723 static struct gl_program
*
5724 get_mesa_program(struct gl_context
*ctx
,
5725 struct gl_shader_program
*shader_program
,
5726 struct gl_shader
*shader
)
5728 glsl_to_tgsi_visitor
* v
;
5729 struct gl_program
*prog
;
5730 GLenum target
= _mesa_shader_stage_to_program(shader
->Stage
);
5732 struct gl_shader_compiler_options
*options
=
5733 &ctx
->Const
.ShaderCompilerOptions
[_mesa_shader_enum_to_shader_stage(shader
->Type
)];
5734 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5735 unsigned ptarget
= shader_stage_to_ptarget(shader
->Stage
);
5737 validate_ir_tree(shader
->ir
);
5739 prog
= ctx
->Driver
.NewProgram(ctx
, target
, shader_program
->Name
);
5742 prog
->Parameters
= _mesa_new_parameter_list();
5743 v
= new glsl_to_tgsi_visitor();
5746 v
->shader_program
= shader_program
;
5748 v
->options
= options
;
5749 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
5750 v
->native_integers
= ctx
->Const
.NativeIntegers
;
5752 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
5753 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
5754 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
5755 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
5757 _mesa_copy_linked_program_data(shader
->Stage
, shader_program
, prog
);
5758 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
5761 /* Remove reads from output registers. */
5762 lower_output_reads(shader
->Stage
, shader
->ir
);
5764 /* Emit intermediate IR for main(). */
5765 visit_exec_list(shader
->ir
, v
);
5767 /* Now emit bodies for any functions that were used. */
5769 progress
= GL_FALSE
;
5771 foreach_in_list(function_entry
, entry
, &v
->function_signatures
) {
5772 if (!entry
->bgn_inst
) {
5773 v
->current_function
= entry
;
5775 entry
->bgn_inst
= v
->emit_asm(NULL
, TGSI_OPCODE_BGNSUB
);
5776 entry
->bgn_inst
->function
= entry
;
5778 visit_exec_list(&entry
->sig
->body
, v
);
5780 glsl_to_tgsi_instruction
*last
;
5781 last
= (glsl_to_tgsi_instruction
*)v
->instructions
.get_tail();
5782 if (last
->op
!= TGSI_OPCODE_RET
)
5783 v
->emit_asm(NULL
, TGSI_OPCODE_RET
);
5785 glsl_to_tgsi_instruction
*end
;
5786 end
= v
->emit_asm(NULL
, TGSI_OPCODE_ENDSUB
);
5787 end
->function
= entry
;
5795 /* Print out some information (for debugging purposes) used by the
5796 * optimization passes. */
5797 for (i
= 0; i
< v
->next_temp
; i
++) {
5798 int fr
= v
->get_first_temp_read(i
);
5799 int fw
= v
->get_first_temp_write(i
);
5800 int lr
= v
->get_last_temp_read(i
);
5801 int lw
= v
->get_last_temp_write(i
);
5803 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, fr
, fw
, lr
, lw
);
5808 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
5811 if (shader
->Type
!= GL_TESS_CONTROL_SHADER
&&
5812 shader
->Type
!= GL_TESS_EVALUATION_SHADER
)
5813 v
->copy_propagate();
5815 while (v
->eliminate_dead_code());
5817 v
->merge_two_dsts();
5818 v
->merge_registers();
5819 v
->renumber_registers();
5821 /* Write the END instruction. */
5822 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
5824 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
5826 _mesa_log("GLSL IR for linked %s program %d:\n",
5827 _mesa_shader_stage_to_string(shader
->Stage
),
5828 shader_program
->Name
);
5829 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
5833 prog
->Instructions
= NULL
;
5834 prog
->NumInstructions
= 0;
5836 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
5837 shrink_array_declarations(v
->input_arrays
, v
->num_input_arrays
,
5838 prog
->InputsRead
, prog
->PatchInputsRead
);
5839 shrink_array_declarations(v
->output_arrays
, v
->num_output_arrays
,
5840 prog
->OutputsWritten
, prog
->PatchOutputsWritten
);
5841 count_resources(v
, prog
);
5843 /* This must be done before the uniform storage is associated. */
5844 if (shader
->Type
== GL_FRAGMENT_SHADER
&&
5845 prog
->InputsRead
& VARYING_BIT_POS
){
5846 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
5847 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
5850 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
5851 wposTransformState
);
5854 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
5856 /* This has to be done last. Any operation the can cause
5857 * prog->ParameterValues to get reallocated (e.g., anything that adds a
5858 * program constant) has to happen before creating this linkage.
5860 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
5861 if (!shader_program
->LinkStatus
) {
5862 free_glsl_to_tgsi_visitor(v
);
5866 struct st_vertex_program
*stvp
;
5867 struct st_fragment_program
*stfp
;
5868 struct st_geometry_program
*stgp
;
5869 struct st_tessctrl_program
*sttcp
;
5870 struct st_tesseval_program
*sttep
;
5872 switch (shader
->Type
) {
5873 case GL_VERTEX_SHADER
:
5874 stvp
= (struct st_vertex_program
*)prog
;
5875 stvp
->glsl_to_tgsi
= v
;
5877 case GL_FRAGMENT_SHADER
:
5878 stfp
= (struct st_fragment_program
*)prog
;
5879 stfp
->glsl_to_tgsi
= v
;
5881 case GL_GEOMETRY_SHADER
:
5882 stgp
= (struct st_geometry_program
*)prog
;
5883 stgp
->glsl_to_tgsi
= v
;
5885 case GL_TESS_CONTROL_SHADER
:
5886 sttcp
= (struct st_tessctrl_program
*)prog
;
5887 sttcp
->glsl_to_tgsi
= v
;
5889 case GL_TESS_EVALUATION_SHADER
:
5890 sttep
= (struct st_tesseval_program
*)prog
;
5891 sttep
->glsl_to_tgsi
= v
;
5894 assert(!"should not be reached");
5905 * Called via ctx->Driver.LinkShader()
5906 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
5907 * with code lowering and other optimizations.
5910 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
5912 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
5913 assert(prog
->LinkStatus
);
5915 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5916 if (prog
->_LinkedShaders
[i
] == NULL
)
5920 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
5921 gl_shader_stage stage
= _mesa_shader_enum_to_shader_stage(prog
->_LinkedShaders
[i
]->Type
);
5922 const struct gl_shader_compiler_options
*options
=
5923 &ctx
->Const
.ShaderCompilerOptions
[stage
];
5924 unsigned ptarget
= shader_stage_to_ptarget(stage
);
5925 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
5926 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
5927 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
5928 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
5930 /* If there are forms of indirect addressing that the driver
5931 * cannot handle, perform the lowering pass.
5933 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
5934 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
5935 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
5936 options
->EmitNoIndirectInput
,
5937 options
->EmitNoIndirectOutput
,
5938 options
->EmitNoIndirectTemp
,
5939 options
->EmitNoIndirectUniform
);
5942 if (ctx
->Extensions
.ARB_shading_language_packing
) {
5943 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
5944 LOWER_UNPACK_SNORM_2x16
|
5945 LOWER_PACK_UNORM_2x16
|
5946 LOWER_UNPACK_UNORM_2x16
|
5947 LOWER_PACK_SNORM_4x8
|
5948 LOWER_UNPACK_SNORM_4x8
|
5949 LOWER_UNPACK_UNORM_4x8
|
5950 LOWER_PACK_UNORM_4x8
|
5951 LOWER_PACK_HALF_2x16
|
5952 LOWER_UNPACK_HALF_2x16
;
5954 lower_packing_builtins(ir
, lower_inst
);
5957 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
5958 lower_offset_arrays(ir
);
5959 do_mat_op_to_vec(ir
);
5960 lower_instructions(ir
,
5966 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
5969 (have_dround
? 0 : DOPS_TO_DFRAC
) |
5970 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
5971 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
5972 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0));
5974 lower_ubo_reference(prog
->_LinkedShaders
[i
], ir
);
5975 do_vec_index_to_cond_assign(ir
);
5976 lower_vector_insert(ir
, true);
5977 lower_quadop_vector(ir
, false);
5979 if (options
->MaxIfDepth
== 0) {
5986 progress
= do_lower_jumps(ir
, true, true, options
->EmitNoMainReturn
, options
->EmitNoCont
, options
->EmitNoLoops
) || progress
;
5988 progress
= do_common_optimization(ir
, true, true, options
,
5989 ctx
->Const
.NativeIntegers
)
5992 progress
= lower_if_to_cond_assign(ir
, options
->MaxIfDepth
) || progress
;
5996 validate_ir_tree(ir
);
5999 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6000 struct gl_program
*linked_prog
;
6002 if (prog
->_LinkedShaders
[i
] == NULL
)
6005 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6008 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6010 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6011 _mesa_shader_stage_to_program(i
),
6013 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6015 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6020 _mesa_reference_program(ctx
, &linked_prog
, NULL
);
6027 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6028 const GLuint outputMapping
[],
6029 struct pipe_stream_output_info
*so
)
6032 struct gl_transform_feedback_info
*info
=
6033 &glsl_to_tgsi
->shader_program
->LinkedTransformFeedback
;
6035 for (i
= 0; i
< info
->NumOutputs
; i
++) {
6036 so
->output
[i
].register_index
=
6037 outputMapping
[info
->Outputs
[i
].OutputRegister
];
6038 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
6039 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
6040 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
6041 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
6042 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
6045 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
6046 so
->stride
[i
] = info
->BufferStride
[i
];
6048 so
->num_outputs
= info
->NumOutputs
;