2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
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18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
64 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static int swizzle_for_size(int size
);
71 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
73 unsigned num_elements
= 4;
76 type
= type
->without_array();
77 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
78 num_elements
= type
->vector_elements
;
81 int swizzle
= swizzle_for_size(num_elements
);
82 assert(num_elements
+ component
<= 4);
84 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
89 * This struct is a corresponding struct to TGSI ureg_src.
93 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
94 int component
= 0, unsigned array_id
= 0)
96 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
99 this->swizzle
= swizzle_for_type(type
, component
);
103 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
104 this->reladdr
= NULL
;
105 this->reladdr2
= NULL
;
106 this->has_index2
= false;
107 this->double_reg2
= false;
108 this->array_id
= array_id
;
109 this->is_double_vertex_input
= false;
112 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
114 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
119 this->swizzle
= SWIZZLE_XYZW
;
122 this->reladdr
= NULL
;
123 this->reladdr2
= NULL
;
124 this->has_index2
= false;
125 this->double_reg2
= false;
127 this->is_double_vertex_input
= false;
130 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
132 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
136 this->index2D
= index2D
;
137 this->swizzle
= SWIZZLE_XYZW
;
140 this->reladdr
= NULL
;
141 this->reladdr2
= NULL
;
142 this->has_index2
= false;
143 this->double_reg2
= false;
145 this->is_double_vertex_input
= false;
150 this->type
= GLSL_TYPE_ERROR
;
151 this->file
= PROGRAM_UNDEFINED
;
157 this->reladdr
= NULL
;
158 this->reladdr2
= NULL
;
159 this->has_index2
= false;
160 this->double_reg2
= false;
162 this->is_double_vertex_input
= false;
165 explicit st_src_reg(st_dst_reg reg
);
167 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
169 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
170 int negate
:4; /**< NEGATE_XYZW mask from mesa */
172 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
173 unsigned has_index2
:1;
174 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
176 * Is this the second half of a double register pair?
177 * currently used for input mapping only.
179 unsigned double_reg2
:1;
180 unsigned is_double_vertex_input
:1;
181 unsigned array_id
:10;
183 /** Register index should be offset by the integer in this reg. */
185 st_src_reg
*reladdr2
;
189 st_src_reg reg
= *this;
198 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
200 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
204 this->writemask
= writemask
;
205 this->reladdr
= NULL
;
206 this->reladdr2
= NULL
;
207 this->has_index2
= false;
212 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
214 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
218 this->writemask
= writemask
;
219 this->reladdr
= NULL
;
220 this->reladdr2
= NULL
;
221 this->has_index2
= false;
228 this->type
= GLSL_TYPE_ERROR
;
229 this->file
= PROGRAM_UNDEFINED
;
233 this->reladdr
= NULL
;
234 this->reladdr2
= NULL
;
235 this->has_index2
= false;
239 explicit st_dst_reg(st_src_reg reg
);
241 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
243 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
244 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
245 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
246 unsigned has_index2
:1;
247 unsigned array_id
:10;
249 /** Register index should be offset by the integer in this reg. */
251 st_src_reg
*reladdr2
;
254 st_src_reg::st_src_reg(st_dst_reg reg
)
256 this->type
= reg
.type
;
257 this->file
= reg
.file
;
258 this->index
= reg
.index
;
259 this->swizzle
= SWIZZLE_XYZW
;
262 this->reladdr
= reg
.reladdr
;
263 this->index2D
= reg
.index2D
;
264 this->reladdr2
= reg
.reladdr2
;
265 this->has_index2
= reg
.has_index2
;
266 this->double_reg2
= false;
267 this->array_id
= reg
.array_id
;
268 this->is_double_vertex_input
= false;
271 st_dst_reg::st_dst_reg(st_src_reg reg
)
273 this->type
= reg
.type
;
274 this->file
= reg
.file
;
275 this->index
= reg
.index
;
276 this->writemask
= WRITEMASK_XYZW
;
277 this->reladdr
= reg
.reladdr
;
278 this->index2D
= reg
.index2D
;
279 this->reladdr2
= reg
.reladdr2
;
280 this->has_index2
= reg
.has_index2
;
281 this->array_id
= reg
.array_id
;
284 class glsl_to_tgsi_instruction
: public exec_node
{
286 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
290 st_src_reg resource
; /**< sampler or buffer register */
291 st_src_reg
*tex_offsets
;
293 /** Pointer to the ir source this tree came from for debugging */
296 unsigned op
:8; /**< TGSI opcode */
298 unsigned is_64bit_expanded
:1;
299 unsigned sampler_base
:5;
300 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
301 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
302 glsl_base_type tex_type
:5;
303 unsigned tex_shadow
:1;
304 unsigned image_format
:9;
305 unsigned tex_offset_num_offset
:3;
306 unsigned dead_mask
:4; /**< Used in dead code elimination */
307 unsigned buffer_access
:3; /**< buffer access type */
309 const struct tgsi_opcode_info
*info
;
312 class variable_storage
: public exec_node
{
314 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
315 unsigned array_id
= 0)
316 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
318 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
321 gl_register_file file
;
324 /* Explicit component location. This is given in terms of the GLSL-style
325 * swizzles where each double is a single component, i.e. for 64-bit types
326 * it can only be 0 or 1.
329 ir_variable
*var
; /* variable that maps to this, if any */
333 class immediate_storage
: public exec_node
{
335 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
337 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
338 this->size32
= size32
;
342 /* doubles are stored across 2 gl_constant_values */
343 gl_constant_value values
[4];
344 int size32
; /**< Number of 32-bit components (1-4) */
345 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
348 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
349 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
353 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
356 unsigned gs_out_streams
;
357 enum glsl_interp_mode interp
;
358 enum glsl_base_type base_type
;
359 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
362 static struct inout_decl
*
363 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
365 assert(array_id
!= 0);
367 for (unsigned i
= 0; i
< count
; i
++) {
368 struct inout_decl
*decl
= &decls
[i
];
370 if (array_id
== decl
->array_id
) {
378 static enum glsl_base_type
379 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
382 return GLSL_TYPE_ERROR
;
383 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
385 return decl
->base_type
;
386 return GLSL_TYPE_ERROR
;
389 struct rename_reg_pair
{
394 struct glsl_to_tgsi_visitor
: public ir_visitor
{
396 glsl_to_tgsi_visitor();
397 ~glsl_to_tgsi_visitor();
399 struct gl_context
*ctx
;
400 struct gl_program
*prog
;
401 struct gl_shader_program
*shader_program
;
402 struct gl_linked_shader
*shader
;
403 struct gl_shader_compiler_options
*options
;
407 unsigned *array_sizes
;
408 unsigned max_num_arrays
;
411 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
413 unsigned num_input_arrays
;
414 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
415 unsigned num_outputs
;
416 unsigned num_output_arrays
;
418 int num_address_regs
;
419 uint32_t samplers_used
;
420 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
421 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
424 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
425 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
426 bool indirect_addr_consts
;
427 int wpos_transform_const
;
430 bool native_integers
;
433 bool use_shared_memory
;
435 variable_storage
*find_variable_storage(ir_variable
*var
);
437 int add_constant(gl_register_file file
, gl_constant_value values
[8],
438 int size
, int datatype
, uint16_t *swizzle_out
);
440 st_src_reg
get_temp(const glsl_type
*type
);
441 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
443 st_src_reg
st_src_reg_for_double(double val
);
444 st_src_reg
st_src_reg_for_float(float val
);
445 st_src_reg
st_src_reg_for_int(int val
);
446 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
449 * \name Visit methods
451 * As typical for the visitor pattern, there must be one \c visit method for
452 * each concrete subclass of \c ir_instruction. Virtual base classes within
453 * the hierarchy should not have \c visit methods.
456 virtual void visit(ir_variable
*);
457 virtual void visit(ir_loop
*);
458 virtual void visit(ir_loop_jump
*);
459 virtual void visit(ir_function_signature
*);
460 virtual void visit(ir_function
*);
461 virtual void visit(ir_expression
*);
462 virtual void visit(ir_swizzle
*);
463 virtual void visit(ir_dereference_variable
*);
464 virtual void visit(ir_dereference_array
*);
465 virtual void visit(ir_dereference_record
*);
466 virtual void visit(ir_assignment
*);
467 virtual void visit(ir_constant
*);
468 virtual void visit(ir_call
*);
469 virtual void visit(ir_return
*);
470 virtual void visit(ir_discard
*);
471 virtual void visit(ir_texture
*);
472 virtual void visit(ir_if
*);
473 virtual void visit(ir_emit_vertex
*);
474 virtual void visit(ir_end_primitive
*);
475 virtual void visit(ir_barrier
*);
478 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
480 void visit_atomic_counter_intrinsic(ir_call
*);
481 void visit_ssbo_intrinsic(ir_call
*);
482 void visit_membar_intrinsic(ir_call
*);
483 void visit_shared_intrinsic(ir_call
*);
484 void visit_image_intrinsic(ir_call
*);
488 /** List of variable_storage */
491 /** List of immediate_storage */
492 exec_list immediates
;
493 unsigned num_immediates
;
495 /** List of glsl_to_tgsi_instruction */
496 exec_list instructions
;
498 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
499 st_dst_reg dst
= undef_dst
,
500 st_src_reg src0
= undef_src
,
501 st_src_reg src1
= undef_src
,
502 st_src_reg src2
= undef_src
,
503 st_src_reg src3
= undef_src
);
505 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
506 st_dst_reg dst
, st_dst_reg dst1
,
507 st_src_reg src0
= undef_src
,
508 st_src_reg src1
= undef_src
,
509 st_src_reg src2
= undef_src
,
510 st_src_reg src3
= undef_src
);
512 unsigned get_opcode(unsigned op
,
514 st_src_reg src0
, st_src_reg src1
);
517 * Emit the correct dot-product instruction for the type of arguments
519 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
525 void emit_scalar(ir_instruction
*ir
, unsigned op
,
526 st_dst_reg dst
, st_src_reg src0
);
528 void emit_scalar(ir_instruction
*ir
, unsigned op
,
529 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
531 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
533 void get_deref_offsets(ir_dereference
*ir
,
534 unsigned *array_size
,
539 void calc_deref_offsets(ir_dereference
*tail
,
540 unsigned *array_elements
,
542 st_src_reg
*indirect
,
544 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
546 bool try_emit_mad(ir_expression
*ir
,
548 bool try_emit_mad_for_and_not(ir_expression
*ir
,
551 void emit_swz(ir_expression
*ir
);
553 bool process_move_condition(ir_rvalue
*ir
);
555 void simplify_cmp(void);
557 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
558 void get_first_temp_read(int *first_reads
);
559 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
560 void get_last_temp_write(int *last_writes
);
562 void copy_propagate(void);
563 int eliminate_dead_code(void);
565 void merge_two_dsts(void);
566 void merge_registers(void);
567 void renumber_registers(void);
569 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
570 st_dst_reg
*l
, st_src_reg
*r
,
571 st_src_reg
*cond
, bool cond_swap
);
576 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
577 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
578 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
581 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
584 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
588 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
591 prog
->data
->LinkStatus
= linking_failure
;
595 swizzle_for_size(int size
)
597 static const int size_swizzles
[4] = {
598 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
599 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
600 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
601 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
604 assert((size
>= 1) && (size
<= 4));
605 return size_swizzles
[size
- 1];
609 is_resource_instruction(unsigned opcode
)
612 case TGSI_OPCODE_RESQ
:
613 case TGSI_OPCODE_LOAD
:
614 case TGSI_OPCODE_ATOMUADD
:
615 case TGSI_OPCODE_ATOMXCHG
:
616 case TGSI_OPCODE_ATOMCAS
:
617 case TGSI_OPCODE_ATOMAND
:
618 case TGSI_OPCODE_ATOMOR
:
619 case TGSI_OPCODE_ATOMXOR
:
620 case TGSI_OPCODE_ATOMUMIN
:
621 case TGSI_OPCODE_ATOMUMAX
:
622 case TGSI_OPCODE_ATOMIMIN
:
623 case TGSI_OPCODE_ATOMIMAX
:
631 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
633 return op
->info
->num_dst
;
637 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
639 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
640 op
->info
->num_src
- 1 : op
->info
->num_src
;
643 glsl_to_tgsi_instruction
*
644 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
645 st_dst_reg dst
, st_dst_reg dst1
,
646 st_src_reg src0
, st_src_reg src1
,
647 st_src_reg src2
, st_src_reg src3
)
649 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
650 int num_reladdr
= 0, i
, j
;
651 bool dst_is_64bit
[2];
653 op
= get_opcode(op
, dst
, src0
, src1
);
655 /* If we have to do relative addressing, we want to load the ARL
656 * reg directly for one of the regs, and preload the other reladdr
657 * sources into temps.
659 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
660 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
661 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
662 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
663 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
664 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
666 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
667 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
668 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
669 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
671 if (dst
.reladdr
|| dst
.reladdr2
) {
673 emit_arl(ir
, address_reg
, *dst
.reladdr
);
675 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
679 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
682 assert(num_reladdr
== 0);
684 /* inst->op has only 8 bits. */
685 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
688 inst
->info
= tgsi_get_opcode_info(op
);
695 inst
->is_64bit_expanded
= false;
698 inst
->tex_offsets
= NULL
;
699 inst
->tex_offset_num_offset
= 0;
701 inst
->tex_shadow
= 0;
702 /* default to float, for paths where this is not initialized
703 * (since 0==UINT which is likely wrong):
705 inst
->tex_type
= GLSL_TYPE_FLOAT
;
707 /* Update indirect addressing status used by TGSI */
708 if (dst
.reladdr
|| dst
.reladdr2
) {
710 case PROGRAM_STATE_VAR
:
711 case PROGRAM_CONSTANT
:
712 case PROGRAM_UNIFORM
:
713 this->indirect_addr_consts
= true;
715 case PROGRAM_IMMEDIATE
:
716 assert(!"immediates should not have indirect addressing");
723 for (i
= 0; i
< 4; i
++) {
724 if(inst
->src
[i
].reladdr
) {
725 switch(inst
->src
[i
].file
) {
726 case PROGRAM_STATE_VAR
:
727 case PROGRAM_CONSTANT
:
728 case PROGRAM_UNIFORM
:
729 this->indirect_addr_consts
= true;
731 case PROGRAM_IMMEDIATE
:
732 assert(!"immediates should not have indirect addressing");
742 * This section contains the double processing.
743 * GLSL just represents doubles as single channel values,
744 * however most HW and TGSI represent doubles as pairs of register channels.
746 * so we have to fixup destination writemask/index and src swizzle/indexes.
747 * dest writemasks need to translate from single channel write mask
748 * to a dual-channel writemask, but also need to modify the index,
749 * if we are touching the Z,W fields in the pre-translated writemask.
751 * src channels have similiar index modifications along with swizzle
752 * changes to we pick the XY, ZW pairs from the correct index.
754 * GLSL [0].x -> TGSI [0].xy
755 * GLSL [0].y -> TGSI [0].zw
756 * GLSL [0].z -> TGSI [1].xy
757 * GLSL [0].w -> TGSI [1].zw
759 for (j
= 0; j
< 2; j
++) {
760 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
761 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
762 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
763 if (glsl_base_type_is_64bit(type
))
764 dst_is_64bit
[j
] = true;
768 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
769 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
770 glsl_to_tgsi_instruction
*dinst
= NULL
;
771 int initial_src_swz
[4], initial_src_idx
[4];
772 int initial_dst_idx
[2], initial_dst_writemask
[2];
773 /* select the writemask for dst0 or dst1 */
774 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
776 /* copy out the writemask, index and swizzles for all src/dsts. */
777 for (j
= 0; j
< 2; j
++) {
778 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
779 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
782 for (j
= 0; j
< 4; j
++) {
783 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
784 initial_src_idx
[j
] = inst
->src
[j
].index
;
788 * scan all the components in the dst writemask
789 * generate an instruction for each of them if required.
794 int i
= u_bit_scan(&writemask
);
796 /* before emitting the instruction, see if we have to adjust load / store
798 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
799 addr
.file
== PROGRAM_UNDEFINED
) {
800 /* We have to advance the buffer address by 16 */
801 addr
= get_temp(glsl_type::uint_type
);
802 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
803 inst
->src
[0], st_src_reg_for_int(16));
806 /* first time use previous instruction */
810 /* create a new instructions for subsequent attempts */
811 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
816 this->instructions
.push_tail(dinst
);
817 dinst
->is_64bit_expanded
= true;
819 /* modify the destination if we are splitting */
820 for (j
= 0; j
< 2; j
++) {
821 if (dst_is_64bit
[j
]) {
822 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
823 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
825 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
826 dinst
->src
[0] = addr
;
827 if (dinst
->op
!= TGSI_OPCODE_STORE
)
828 dinst
->dst
[j
].index
++;
831 /* if we aren't writing to a double, just get the bit of the initial writemask
833 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
837 /* modify the src registers */
838 for (j
= 0; j
< 4; j
++) {
839 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
841 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
842 dinst
->src
[j
].index
= initial_src_idx
[j
];
844 dinst
->src
[j
].double_reg2
= true;
845 dinst
->src
[j
].index
++;
849 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
851 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
854 /* some opcodes are special case in what they use as sources
855 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
856 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
857 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
858 op
== TGSI_OPCODE_DLDEXP
||
859 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
860 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
867 this->instructions
.push_tail(inst
);
874 glsl_to_tgsi_instruction
*
875 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
877 st_src_reg src0
, st_src_reg src1
,
878 st_src_reg src2
, st_src_reg src3
)
880 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
884 * Determines whether to use an integer, unsigned integer, or float opcode
885 * based on the operands and input opcode, then emits the result.
888 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
890 st_src_reg src0
, st_src_reg src1
)
892 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
894 if (op
== TGSI_OPCODE_MOV
)
897 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
898 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
899 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
900 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
902 if (is_resource_instruction(op
))
904 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
905 type
= GLSL_TYPE_INT64
;
906 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
907 type
= GLSL_TYPE_UINT64
;
908 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
909 type
= GLSL_TYPE_DOUBLE
;
910 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
911 type
= GLSL_TYPE_FLOAT
;
912 else if (native_integers
)
913 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
915 #define case7(c, f, i, u, d, i64, ui64) \
916 case TGSI_OPCODE_##c: \
917 if (type == GLSL_TYPE_UINT64) \
918 op = TGSI_OPCODE_##ui64; \
919 else if (type == GLSL_TYPE_INT64) \
920 op = TGSI_OPCODE_##i64; \
921 else if (type == GLSL_TYPE_DOUBLE) \
922 op = TGSI_OPCODE_##d; \
923 else if (type == GLSL_TYPE_INT) \
924 op = TGSI_OPCODE_##i; \
925 else if (type == GLSL_TYPE_UINT) \
926 op = TGSI_OPCODE_##u; \
928 op = TGSI_OPCODE_##f; \
930 #define case5(c, f, i, u, d) \
931 case TGSI_OPCODE_##c: \
932 if (type == GLSL_TYPE_DOUBLE) \
933 op = TGSI_OPCODE_##d; \
934 else if (type == GLSL_TYPE_INT) \
935 op = TGSI_OPCODE_##i; \
936 else if (type == GLSL_TYPE_UINT) \
937 op = TGSI_OPCODE_##u; \
939 op = TGSI_OPCODE_##f; \
942 #define case4(c, f, i, u) \
943 case TGSI_OPCODE_##c: \
944 if (type == GLSL_TYPE_INT) \
945 op = TGSI_OPCODE_##i; \
946 else if (type == GLSL_TYPE_UINT) \
947 op = TGSI_OPCODE_##u; \
949 op = TGSI_OPCODE_##f; \
952 #define case3(f, i, u) case4(f, f, i, u)
953 #define case6d(f, i, u, d, i64, u64) case7(f, f, i, u, d, i64, u64)
954 #define case3fid(f, i, d) case5(f, f, i, i, d)
955 #define case3fid64(f, i, d, i64) case7(f, f, i, i, d, i64, i64)
956 #define case2fi(f, i) case4(f, f, i, i)
957 #define case2iu(i, u) case4(i, LAST, i, u)
959 #define case2iu64(i, i64) case7(i, LAST, i, i, LAST, i64, i64)
960 #define case4iu64(i, u, i64, u64) case7(i, LAST, i, u, LAST, i64, u64)
962 #define casecomp(c, f, i, u, d, i64, ui64) \
963 case TGSI_OPCODE_##c: \
964 if (type == GLSL_TYPE_INT64) \
965 op = TGSI_OPCODE_##i64; \
966 else if (type == GLSL_TYPE_UINT64) \
967 op = TGSI_OPCODE_##ui64; \
968 else if (type == GLSL_TYPE_DOUBLE) \
969 op = TGSI_OPCODE_##d; \
970 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
971 op = TGSI_OPCODE_##i; \
972 else if (type == GLSL_TYPE_UINT) \
973 op = TGSI_OPCODE_##u; \
974 else if (native_integers) \
975 op = TGSI_OPCODE_##f; \
977 op = TGSI_OPCODE_##c; \
981 case3fid64(ADD
, UADD
, DADD
, U64ADD
);
982 case3fid64(MUL
, UMUL
, DMUL
, U64MUL
);
983 case3fid(MAD
, UMAD
, DMAD
);
984 case3fid(FMA
, UMAD
, DFMA
);
985 case6d(DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
986 case6d(MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
987 case6d(MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
988 case4iu64(MOD
, UMOD
, I64MOD
, U64MOD
);
990 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
991 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
992 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
993 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
995 case2iu64(SHL
, U64SHL
);
996 case4iu64(ISHR
, USHR
, I64SHR
, U64SHR
);
998 case3fid64(SSG
, ISSG
, DSSG
, I64SSG
);
1000 case2iu(IBFE
, UBFE
);
1001 case2iu(IMSB
, UMSB
);
1002 case2iu(IMUL_HI
, UMUL_HI
);
1004 case3fid(SQRT
, SQRT
, DSQRT
);
1006 case3fid(RCP
, RCP
, DRCP
);
1007 case3fid(RSQ
, RSQ
, DRSQ
);
1009 case3fid(FRC
, FRC
, DFRAC
);
1010 case3fid(TRUNC
, TRUNC
, DTRUNC
);
1011 case3fid(CEIL
, CEIL
, DCEIL
);
1012 case3fid(FLR
, FLR
, DFLR
);
1013 case3fid(ROUND
, ROUND
, DROUND
);
1015 case2iu(ATOMIMAX
, ATOMUMAX
);
1016 case2iu(ATOMIMIN
, ATOMUMIN
);
1021 assert(op
!= TGSI_OPCODE_LAST
);
1025 glsl_to_tgsi_instruction
*
1026 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
1027 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1030 static const unsigned dot_opcodes
[] = {
1031 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1034 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1038 * Emits TGSI scalar opcodes to produce unique answers across channels.
1040 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1041 * channel determines the result across all channels. So to do a vec4
1042 * of this operation, we want to emit a scalar per source channel used
1043 * to produce dest channels.
1046 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1048 st_src_reg orig_src0
, st_src_reg orig_src1
)
1051 int done_mask
= ~dst
.writemask
;
1053 /* TGSI RCP is a scalar operation splatting results to all channels,
1054 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1057 for (i
= 0; i
< 4; i
++) {
1058 GLuint this_mask
= (1 << i
);
1059 st_src_reg src0
= orig_src0
;
1060 st_src_reg src1
= orig_src1
;
1062 if (done_mask
& this_mask
)
1065 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1066 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1067 for (j
= i
+ 1; j
< 4; j
++) {
1068 /* If there is another enabled component in the destination that is
1069 * derived from the same inputs, generate its value on this pass as
1072 if (!(done_mask
& (1 << j
)) &&
1073 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1074 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1075 this_mask
|= (1 << j
);
1078 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1079 src0_swiz
, src0_swiz
);
1080 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1081 src1_swiz
, src1_swiz
);
1083 dst
.writemask
= this_mask
;
1084 emit_asm(ir
, op
, dst
, src0
, src1
);
1085 done_mask
|= this_mask
;
1090 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1091 st_dst_reg dst
, st_src_reg src0
)
1093 st_src_reg undef
= undef_src
;
1095 undef
.swizzle
= SWIZZLE_XXXX
;
1097 emit_scalar(ir
, op
, dst
, src0
, undef
);
1101 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1102 st_dst_reg dst
, st_src_reg src0
)
1104 int op
= TGSI_OPCODE_ARL
;
1106 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1107 op
= TGSI_OPCODE_UARL
;
1109 assert(dst
.file
== PROGRAM_ADDRESS
);
1110 if (dst
.index
>= this->num_address_regs
)
1111 this->num_address_regs
= dst
.index
+ 1;
1113 emit_asm(NULL
, op
, dst
, src0
);
1117 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1118 gl_constant_value values
[8], int size
, int datatype
,
1119 uint16_t *swizzle_out
)
1121 if (file
== PROGRAM_CONSTANT
) {
1122 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1123 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1124 size
, datatype
, &swizzle
);
1126 *swizzle_out
= swizzle
;
1130 assert(file
== PROGRAM_IMMEDIATE
);
1133 immediate_storage
*entry
;
1134 int size32
= size
* ((datatype
== GL_DOUBLE
||
1135 datatype
== GL_INT64_ARB
||
1136 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
1139 /* Search immediate storage to see if we already have an identical
1140 * immediate that we can use instead of adding a duplicate entry.
1142 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1143 immediate_storage
*tmp
= entry
;
1145 for (i
= 0; i
* 4 < size32
; i
++) {
1146 int slot_size
= MIN2(size32
- (i
* 4), 4);
1147 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1149 if (memcmp(tmp
->values
, &values
[i
* 4],
1150 slot_size
* sizeof(gl_constant_value
)))
1153 /* Everything matches, keep going until the full size is matched */
1154 tmp
= (immediate_storage
*)tmp
->next
;
1157 /* The full value matched */
1158 if (i
* 4 >= size32
)
1164 for (i
= 0; i
* 4 < size32
; i
++) {
1165 int slot_size
= MIN2(size32
- (i
* 4), 4);
1166 /* Add this immediate to the list. */
1167 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1168 this->immediates
.push_tail(entry
);
1169 this->num_immediates
++;
1175 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1177 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1178 union gl_constant_value uval
;
1181 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1187 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1189 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1190 union gl_constant_value uval
[2];
1192 memcpy(uval
, &val
, sizeof(uval
));
1193 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1194 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1199 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1201 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1202 union gl_constant_value uval
;
1204 assert(native_integers
);
1207 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1213 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1215 if (native_integers
)
1216 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1217 st_src_reg_for_int(val
);
1219 return st_src_reg_for_float(val
);
1223 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1225 return st_glsl_attrib_type_size(type
, is_vs_input
);
1229 type_size(const struct glsl_type
*type
)
1231 return st_glsl_type_size(type
);
1235 * If the given GLSL type is an array or matrix or a structure containing
1236 * an array/matrix member, return true. Else return false.
1238 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1239 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1240 * we have an array that might be indexed with a variable, we need to use
1241 * the later storage type.
1244 type_has_array_or_matrix(const glsl_type
*type
)
1246 if (type
->is_array() || type
->is_matrix())
1249 if (type
->is_record()) {
1250 for (unsigned i
= 0; i
< type
->length
; i
++) {
1251 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1262 * In the initial pass of codegen, we assign temporary numbers to
1263 * intermediate results. (not SSA -- variable assignments will reuse
1267 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1271 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1276 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1277 if (next_array
>= max_num_arrays
) {
1278 max_num_arrays
+= 32;
1279 array_sizes
= (unsigned*)
1280 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1283 src
.file
= PROGRAM_ARRAY
;
1285 src
.array_id
= next_array
+ 1;
1286 array_sizes
[next_array
] = type_size(type
);
1290 src
.file
= PROGRAM_TEMPORARY
;
1291 src
.index
= next_temp
;
1292 next_temp
+= type_size(type
);
1295 if (type
->is_array() || type
->is_record()) {
1296 src
.swizzle
= SWIZZLE_NOOP
;
1298 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1305 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1308 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1309 if (entry
->var
== var
)
1317 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1319 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1320 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1321 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1324 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1326 const ir_state_slot
*const slots
= ir
->get_state_slots();
1327 assert(slots
!= NULL
);
1329 /* Check if this statevar's setup in the STATE file exactly
1330 * matches how we'll want to reference it as a
1331 * struct/array/whatever. If not, then we need to move it into
1332 * temporary storage and hope that it'll get copy-propagated
1335 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1336 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1341 variable_storage
*storage
;
1343 if (i
== ir
->get_num_state_slots()) {
1344 /* We'll set the index later. */
1345 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1346 this->variables
.push_tail(storage
);
1350 /* The variable_storage constructor allocates slots based on the size
1351 * of the type. However, this had better match the number of state
1352 * elements that we're going to copy into the new temporary.
1354 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1356 dst
= st_dst_reg(get_temp(ir
->type
));
1358 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1361 this->variables
.push_tail(storage
);
1365 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1366 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1367 (gl_state_index
*)slots
[i
].tokens
);
1369 if (storage
->file
== PROGRAM_STATE_VAR
) {
1370 if (storage
->index
== -1) {
1371 storage
->index
= index
;
1373 assert(index
== storage
->index
+ (int)i
);
1376 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1377 * the data being moved since MOV does not care about the type of
1378 * data it is moving, and we don't want to declare registers with
1379 * array or struct types.
1381 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1382 src
.swizzle
= slots
[i
].swizzle
;
1383 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1384 /* even a float takes up a whole vec4 reg in a struct/array. */
1389 if (storage
->file
== PROGRAM_TEMPORARY
&&
1390 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1391 fail_link(this->shader_program
,
1392 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1393 ir
->name
, dst
.index
- storage
->index
,
1394 type_size(ir
->type
));
1400 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1402 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1404 visit_exec_list(&ir
->body_instructions
, this);
1406 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1410 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1413 case ir_loop_jump::jump_break
:
1414 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1416 case ir_loop_jump::jump_continue
:
1417 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1424 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1431 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1433 /* Ignore function bodies other than main() -- we shouldn't see calls to
1434 * them since they should all be inlined before we get to glsl_to_tgsi.
1436 if (strcmp(ir
->name
, "main") == 0) {
1437 const ir_function_signature
*sig
;
1440 sig
= ir
->matching_signature(NULL
, &empty
, false);
1444 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1451 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1453 int nonmul_operand
= 1 - mul_operand
;
1455 st_dst_reg result_dst
;
1457 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1458 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1461 expr
->operands
[0]->accept(this);
1463 expr
->operands
[1]->accept(this);
1465 ir
->operands
[nonmul_operand
]->accept(this);
1468 this->result
= get_temp(ir
->type
);
1469 result_dst
= st_dst_reg(this->result
);
1470 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1471 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1477 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1479 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1480 * implemented using multiplication, and logical-or is implemented using
1481 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1482 * As result, the logical expression (a & !b) can be rewritten as:
1486 * - (a * 1) - (a * b)
1490 * This final expression can be implemented as a single MAD(a, -b, a)
1494 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1496 const int other_operand
= 1 - try_operand
;
1499 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1500 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1503 ir
->operands
[other_operand
]->accept(this);
1505 expr
->operands
[0]->accept(this);
1508 b
.negate
= ~b
.negate
;
1510 this->result
= get_temp(ir
->type
);
1511 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1517 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1518 st_src_reg
*reg
, int *num_reladdr
)
1520 if (!reg
->reladdr
&& !reg
->reladdr2
)
1523 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1524 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1526 if (*num_reladdr
!= 1) {
1527 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1529 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1537 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1539 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1541 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1543 if (ir
->operation
== ir_binop_add
) {
1544 if (try_emit_mad(ir
, 1))
1546 if (try_emit_mad(ir
, 0))
1550 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1552 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1553 if (try_emit_mad_for_and_not(ir
, 1))
1555 if (try_emit_mad_for_and_not(ir
, 0))
1559 if (ir
->operation
== ir_quadop_vector
)
1560 assert(!"ir_quadop_vector should have been lowered");
1562 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1563 this->result
.file
= PROGRAM_UNDEFINED
;
1564 ir
->operands
[operand
]->accept(this);
1565 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1566 printf("Failed to get tree for expression operand:\n");
1567 ir
->operands
[operand
]->print();
1571 op
[operand
] = this->result
;
1573 /* Matrix expression operands should have been broken down to vector
1574 * operations already.
1576 assert(!ir
->operands
[operand
]->type
->is_matrix());
1579 visit_expression(ir
, op
);
1582 /* The non-recursive part of the expression visitor lives in a separate
1583 * function and should be prevented from being inlined, to avoid a stack
1584 * explosion when deeply nested expressions are visited.
1587 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1589 st_src_reg result_src
;
1590 st_dst_reg result_dst
;
1592 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1593 if (ir
->operands
[1]) {
1594 vector_elements
= MAX2(vector_elements
,
1595 ir
->operands
[1]->type
->vector_elements
);
1598 this->result
.file
= PROGRAM_UNDEFINED
;
1600 /* Storage for our result. Ideally for an assignment we'd be using
1601 * the actual storage for the result here, instead.
1603 result_src
= get_temp(ir
->type
);
1604 /* convenience for the emit functions below. */
1605 result_dst
= st_dst_reg(result_src
);
1606 /* Limit writes to the channels that will be used by result_src later.
1607 * This does limit this temp's use as a temporary for multi-instruction
1610 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1612 switch (ir
->operation
) {
1613 case ir_unop_logic_not
:
1614 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1615 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1617 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1618 * older GPUs implement SEQ using multiple instructions (i915 uses two
1619 * SGE instructions and a MUL instruction). Since our logic values are
1620 * 0.0 and 1.0, 1-x also implements !x.
1622 op
[0].negate
= ~op
[0].negate
;
1623 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1627 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1628 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1629 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1630 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1631 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1632 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1634 op
[0].negate
= ~op
[0].negate
;
1638 case ir_unop_subroutine_to_int
:
1639 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1642 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1643 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1644 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1645 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1646 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1647 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1649 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1652 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1655 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1659 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1663 assert(!"not reached: should be handled by ir_explog_to_explog2");
1666 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1669 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1672 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1674 case ir_unop_saturate
: {
1675 glsl_to_tgsi_instruction
*inst
;
1676 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1677 inst
->saturate
= true;
1682 case ir_unop_dFdx_coarse
:
1683 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1685 case ir_unop_dFdx_fine
:
1686 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1689 case ir_unop_dFdy_coarse
:
1690 case ir_unop_dFdy_fine
:
1692 /* The X component contains 1 or -1 depending on whether the framebuffer
1693 * is a FBO or the window system buffer, respectively.
1694 * It is then multiplied with the source operand of DDY.
1696 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1697 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1699 unsigned transform_y_index
=
1700 _mesa_add_state_reference(this->prog
->Parameters
,
1703 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1705 glsl_type::vec4_type
);
1706 transform_y
.swizzle
= SWIZZLE_XXXX
;
1708 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1710 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1711 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1712 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1716 case ir_unop_frexp_sig
:
1717 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1720 case ir_unop_frexp_exp
:
1721 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1724 case ir_unop_noise
: {
1725 /* At some point, a motivated person could add a better
1726 * implementation of noise. Currently not even the nvidia
1727 * binary drivers do anything more than this. In any case, the
1728 * place to do this is in the GL state tracker, not the poor
1731 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1736 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1739 op
[1].negate
= ~op
[1].negate
;
1740 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1744 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1747 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1750 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1751 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1753 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1757 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1759 case ir_binop_greater
:
1760 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1762 case ir_binop_lequal
:
1763 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1765 case ir_binop_gequal
:
1766 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1768 case ir_binop_equal
:
1769 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1771 case ir_binop_nequal
:
1772 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1774 case ir_binop_all_equal
:
1775 /* "==" operator producing a scalar boolean. */
1776 if (ir
->operands
[0]->type
->is_vector() ||
1777 ir
->operands
[1]->type
->is_vector()) {
1778 st_src_reg temp
= get_temp(native_integers
?
1779 glsl_type::uvec4_type
:
1780 glsl_type::vec4_type
);
1782 if (native_integers
) {
1783 st_dst_reg temp_dst
= st_dst_reg(temp
);
1784 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1786 if (ir
->operands
[0]->type
->is_boolean() &&
1787 ir
->operands
[1]->as_constant() &&
1788 ir
->operands
[1]->as_constant()->is_one()) {
1789 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1791 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1794 /* Emit 1-3 AND operations to combine the SEQ results. */
1795 switch (ir
->operands
[0]->type
->vector_elements
) {
1799 temp_dst
.writemask
= WRITEMASK_Y
;
1800 temp1
.swizzle
= SWIZZLE_YYYY
;
1801 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1802 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1805 temp_dst
.writemask
= WRITEMASK_X
;
1806 temp1
.swizzle
= SWIZZLE_XXXX
;
1807 temp2
.swizzle
= SWIZZLE_YYYY
;
1808 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1809 temp_dst
.writemask
= WRITEMASK_Y
;
1810 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1811 temp2
.swizzle
= SWIZZLE_WWWW
;
1812 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1815 temp1
.swizzle
= SWIZZLE_XXXX
;
1816 temp2
.swizzle
= SWIZZLE_YYYY
;
1817 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1819 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1821 /* After the dot-product, the value will be an integer on the
1822 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1824 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1826 /* Negating the result of the dot-product gives values on the range
1827 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1828 * This is achieved using SGE.
1830 st_src_reg sge_src
= result_src
;
1831 sge_src
.negate
= ~sge_src
.negate
;
1832 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1835 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1838 case ir_binop_any_nequal
:
1839 /* "!=" operator producing a scalar boolean. */
1840 if (ir
->operands
[0]->type
->is_vector() ||
1841 ir
->operands
[1]->type
->is_vector()) {
1842 st_src_reg temp
= get_temp(native_integers
?
1843 glsl_type::uvec4_type
:
1844 glsl_type::vec4_type
);
1845 if (ir
->operands
[0]->type
->is_boolean() &&
1846 ir
->operands
[1]->as_constant() &&
1847 ir
->operands
[1]->as_constant()->is_zero()) {
1848 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1850 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1853 if (native_integers
) {
1854 st_dst_reg temp_dst
= st_dst_reg(temp
);
1855 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1857 /* Emit 1-3 OR operations to combine the SNE results. */
1858 switch (ir
->operands
[0]->type
->vector_elements
) {
1862 temp_dst
.writemask
= WRITEMASK_Y
;
1863 temp1
.swizzle
= SWIZZLE_YYYY
;
1864 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1865 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1868 temp_dst
.writemask
= WRITEMASK_X
;
1869 temp1
.swizzle
= SWIZZLE_XXXX
;
1870 temp2
.swizzle
= SWIZZLE_YYYY
;
1871 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1872 temp_dst
.writemask
= WRITEMASK_Y
;
1873 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1874 temp2
.swizzle
= SWIZZLE_WWWW
;
1875 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1878 temp1
.swizzle
= SWIZZLE_XXXX
;
1879 temp2
.swizzle
= SWIZZLE_YYYY
;
1880 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1882 /* After the dot-product, the value will be an integer on the
1883 * range [0,4]. Zero stays zero, and positive values become 1.0.
1885 glsl_to_tgsi_instruction
*const dp
=
1886 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1887 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1888 /* The clamping to [0,1] can be done for free in the fragment
1889 * shader with a saturate.
1891 dp
->saturate
= true;
1893 /* Negating the result of the dot-product gives values on the range
1894 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1895 * achieved using SLT.
1897 st_src_reg slt_src
= result_src
;
1898 slt_src
.negate
= ~slt_src
.negate
;
1899 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1903 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1907 case ir_binop_logic_xor
:
1908 if (native_integers
)
1909 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1911 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1914 case ir_binop_logic_or
: {
1915 if (native_integers
) {
1916 /* If integers are used as booleans, we can use an actual "or"
1919 assert(native_integers
);
1920 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1922 /* After the addition, the value will be an integer on the
1923 * range [0,2]. Zero stays zero, and positive values become 1.0.
1925 glsl_to_tgsi_instruction
*add
=
1926 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1927 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1928 /* The clamping to [0,1] can be done for free in the fragment
1929 * shader with a saturate if floats are being used as boolean values.
1931 add
->saturate
= true;
1933 /* Negating the result of the addition gives values on the range
1934 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1935 * is achieved using SLT.
1937 st_src_reg slt_src
= result_src
;
1938 slt_src
.negate
= ~slt_src
.negate
;
1939 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1945 case ir_binop_logic_and
:
1946 /* If native integers are disabled, the bool args are stored as float 0.0
1947 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1948 * actual AND opcode.
1950 if (native_integers
)
1951 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1953 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1957 assert(ir
->operands
[0]->type
->is_vector());
1958 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1959 emit_dp(ir
, result_dst
, op
[0], op
[1],
1960 ir
->operands
[0]->type
->vector_elements
);
1965 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1967 /* This is the only instruction sequence that makes the game "Risen"
1968 * render correctly. ABS is not required for the game, but since GLSL
1969 * declares negative values as "undefined", allowing us to do whatever
1970 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1973 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1974 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1978 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1981 if (native_integers
) {
1982 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1985 /* fallthrough to next case otherwise */
1987 if (native_integers
) {
1988 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1991 /* fallthrough to next case otherwise */
1994 case ir_unop_i642u64
:
1995 case ir_unop_u642i64
:
1996 /* Converting between signed and unsigned integers is a no-op. */
1998 result_src
.type
= result_dst
.type
;
2001 if (native_integers
) {
2002 /* Booleans are stored as integers using ~0 for true and 0 for false.
2003 * GLSL requires that int(bool) return 1 for true and 0 for false.
2004 * This conversion is done with AND, but it could be done with NEG.
2006 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
2008 /* Booleans and integers are both stored as floats when native
2009 * integers are disabled.
2015 if (native_integers
)
2016 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2018 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2021 if (native_integers
)
2022 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2024 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2026 case ir_unop_bitcast_f2i
:
2027 case ir_unop_bitcast_f2u
:
2028 /* Make sure we don't propagate the negate modifier to integer opcodes. */
2029 if (op
[0].negate
|| op
[0].abs
)
2030 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2033 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2036 case ir_unop_bitcast_i2f
:
2037 case ir_unop_bitcast_u2f
:
2039 result_src
.type
= GLSL_TYPE_FLOAT
;
2042 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2045 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2048 if (native_integers
)
2049 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2051 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2053 case ir_unop_bitcast_u642d
:
2054 case ir_unop_bitcast_i642d
:
2056 result_src
.type
= GLSL_TYPE_DOUBLE
;
2058 case ir_unop_bitcast_d2i64
:
2060 result_src
.type
= GLSL_TYPE_INT64
;
2062 case ir_unop_bitcast_d2u64
:
2064 result_src
.type
= GLSL_TYPE_UINT64
;
2067 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2070 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2073 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2075 case ir_unop_round_even
:
2076 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2079 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2083 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2086 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2089 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2092 case ir_unop_bit_not
:
2093 if (native_integers
) {
2094 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2098 if (native_integers
) {
2099 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2102 case ir_binop_lshift
:
2103 if (native_integers
) {
2104 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2107 case ir_binop_rshift
:
2108 if (native_integers
) {
2109 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2112 case ir_binop_bit_and
:
2113 if (native_integers
) {
2114 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2117 case ir_binop_bit_xor
:
2118 if (native_integers
) {
2119 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2122 case ir_binop_bit_or
:
2123 if (native_integers
) {
2124 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2128 assert(!"GLSL 1.30 features unsupported");
2131 case ir_binop_ubo_load
: {
2132 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2133 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2134 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2135 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2136 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2139 cbuf
.type
= ir
->type
->base_type
;
2140 cbuf
.file
= PROGRAM_CONSTANT
;
2142 cbuf
.reladdr
= NULL
;
2146 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2148 if (const_offset_ir
) {
2149 /* Constant index into constant buffer */
2150 cbuf
.reladdr
= NULL
;
2151 cbuf
.index
= const_offset
/ 16;
2154 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2155 st_src_reg offset
= op
[1];
2157 /* The OpenGL spec is written in such a way that accesses with
2158 * non-constant offset are almost always vec4-aligned. The only
2159 * exception to this are members of structs in arrays of structs:
2160 * each struct in an array of structs is at least vec4-aligned,
2161 * but single-element and [ui]vec2 members of the struct may be at
2162 * an offset that is not a multiple of 16 bytes.
2164 * Here, we extract that offset, relying on previous passes to always
2165 * generate offset expressions of the form (+ expr constant_offset).
2167 * Note that the std430 layout, which allows more cases of alignment
2168 * less than vec4 in arrays, is not supported for uniform blocks, so
2169 * we do not have to deal with it here.
2171 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2172 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2173 if (const_offset_ir
) {
2174 const_offset
= const_offset_ir
->value
.u
[0];
2175 cbuf
.index
= const_offset
/ 16;
2176 offset_expr
->operands
[0]->accept(this);
2177 offset
= this->result
;
2181 /* Relative/variable index into constant buffer */
2182 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2183 st_src_reg_for_int(4));
2184 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2185 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2188 if (const_uniform_block
) {
2189 /* Constant constant buffer */
2190 cbuf
.reladdr2
= NULL
;
2191 cbuf
.index2D
= const_block
;
2192 cbuf
.has_index2
= true;
2195 /* Relative/variable constant buffer */
2196 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2198 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2199 cbuf
.has_index2
= true;
2202 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2203 if (glsl_base_type_is_64bit(cbuf
.type
))
2204 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2205 const_offset
% 16 / 8,
2206 const_offset
% 16 / 8,
2207 const_offset
% 16 / 8);
2209 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2210 const_offset
% 16 / 4,
2211 const_offset
% 16 / 4,
2212 const_offset
% 16 / 4);
2214 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2215 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2217 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2222 /* note: we have to reorder the three args here */
2223 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2226 if (this->ctx
->Const
.NativeIntegers
)
2227 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2229 op
[0].negate
= ~op
[0].negate
;
2230 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2233 case ir_triop_bitfield_extract
:
2234 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2236 case ir_quadop_bitfield_insert
:
2237 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2239 case ir_unop_bitfield_reverse
:
2240 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2242 case ir_unop_bit_count
:
2243 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2245 case ir_unop_find_msb
:
2246 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2248 case ir_unop_find_lsb
:
2249 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2251 case ir_binop_imul_high
:
2252 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2255 /* In theory, MAD is incorrect here. */
2257 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2259 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2261 case ir_unop_interpolate_at_centroid
:
2262 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2264 case ir_binop_interpolate_at_offset
: {
2265 /* The y coordinate needs to be flipped for the default fb */
2266 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2267 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2269 unsigned transform_y_index
=
2270 _mesa_add_state_reference(this->prog
->Parameters
,
2273 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2275 glsl_type::vec4_type
);
2276 transform_y
.swizzle
= SWIZZLE_XXXX
;
2278 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2279 st_dst_reg temp_dst
= st_dst_reg(temp
);
2281 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2282 temp_dst
.writemask
= WRITEMASK_Y
;
2283 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2284 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2287 case ir_binop_interpolate_at_sample
:
2288 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2292 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2295 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2298 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2301 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2304 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2307 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2309 case ir_unop_unpack_double_2x32
:
2310 case ir_unop_pack_double_2x32
:
2311 case ir_unop_unpack_int_2x32
:
2312 case ir_unop_pack_int_2x32
:
2313 case ir_unop_unpack_uint_2x32
:
2314 case ir_unop_pack_uint_2x32
:
2315 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2318 case ir_binop_ldexp
:
2319 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2320 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2322 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2326 case ir_unop_pack_half_2x16
:
2327 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2329 case ir_unop_unpack_half_2x16
:
2330 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2333 case ir_unop_get_buffer_size
: {
2334 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2337 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2338 (const_offset
? const_offset
->value
.u
[0] : 0),
2340 if (!const_offset
) {
2341 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2342 *buffer
.reladdr
= op
[0];
2343 emit_arl(ir
, sampler_reladdr
, op
[0]);
2345 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2349 case ir_unop_vote_any
:
2350 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2352 case ir_unop_vote_all
:
2353 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2355 case ir_unop_vote_eq
:
2356 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2360 case ir_unop_b2i64
: {
2361 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2362 st_dst_reg temp_dst
= st_dst_reg(temp
);
2363 unsigned orig_swz
= op
[0].swizzle
;
2365 * To convert unsigned to 64-bit:
2366 * zero Y channel, copy X channel.
2368 temp_dst
.writemask
= WRITEMASK_Y
;
2369 if (vector_elements
> 1)
2370 temp_dst
.writemask
|= WRITEMASK_W
;
2371 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2372 temp_dst
.writemask
= WRITEMASK_X
;
2373 if (vector_elements
> 1)
2374 temp_dst
.writemask
|= WRITEMASK_Z
;
2375 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2376 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2377 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2378 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2380 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2382 result_src
.type
= GLSL_TYPE_UINT64
;
2383 if (vector_elements
> 2) {
2384 /* Subtle: We rely on the fact that get_temp here returns the next
2385 * TGSI temporary register directly after the temp register used for
2386 * the first two components, so that the result gets picked up
2389 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2390 st_dst_reg temp_dst
= st_dst_reg(temp
);
2391 temp_dst
.writemask
= WRITEMASK_Y
;
2392 if (vector_elements
> 3)
2393 temp_dst
.writemask
|= WRITEMASK_W
;
2394 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2396 temp_dst
.writemask
= WRITEMASK_X
;
2397 if (vector_elements
> 3)
2398 temp_dst
.writemask
|= WRITEMASK_Z
;
2399 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2400 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2401 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2402 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2404 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2411 case ir_unop_i642u
: {
2412 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2413 st_dst_reg temp_dst
= st_dst_reg(temp
);
2414 unsigned orig_swz
= op
[0].swizzle
;
2415 unsigned orig_idx
= op
[0].index
;
2417 temp_dst
.writemask
= WRITEMASK_X
;
2419 for (el
= 0; el
< vector_elements
; el
++) {
2420 unsigned swz
= GET_SWZ(orig_swz
, el
);
2422 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2424 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2426 op
[0].index
= orig_idx
+ 1;
2427 op
[0].type
= GLSL_TYPE_UINT
;
2428 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2429 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2432 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2433 result_src
.type
= GLSL_TYPE_UINT
;
2435 result_src
.type
= GLSL_TYPE_INT
;
2439 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2442 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2445 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2448 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2451 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2454 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2457 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2460 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2463 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2466 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2469 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2471 /* these might be needed */
2472 case ir_unop_pack_snorm_2x16
:
2473 case ir_unop_pack_unorm_2x16
:
2474 case ir_unop_pack_snorm_4x8
:
2475 case ir_unop_pack_unorm_4x8
:
2477 case ir_unop_unpack_snorm_2x16
:
2478 case ir_unop_unpack_unorm_2x16
:
2479 case ir_unop_unpack_snorm_4x8
:
2480 case ir_unop_unpack_unorm_4x8
:
2482 case ir_quadop_vector
:
2483 case ir_binop_vector_extract
:
2484 case ir_triop_vector_insert
:
2485 case ir_binop_carry
:
2486 case ir_binop_borrow
:
2487 case ir_unop_ssbo_unsized_array_length
:
2488 /* This operation is not supported, or should have already been handled.
2490 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2494 this->result
= result_src
;
2499 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2505 /* Note that this is only swizzles in expressions, not those on the left
2506 * hand side of an assignment, which do write masking. See ir_assignment
2510 ir
->val
->accept(this);
2512 assert(src
.file
!= PROGRAM_UNDEFINED
);
2513 assert(ir
->type
->vector_elements
> 0);
2515 for (i
= 0; i
< 4; i
++) {
2516 if (i
< ir
->type
->vector_elements
) {
2519 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2522 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2525 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2528 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2532 /* If the type is smaller than a vec4, replicate the last
2535 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2539 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2544 /* Test if the variable is an array. Note that geometry and
2545 * tessellation shader inputs are outputs are always arrays (except
2546 * for patch inputs), so only the array element type is considered.
2549 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2551 const glsl_type
*type
= var
->type
;
2553 *remove_array
= false;
2555 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2556 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2559 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2560 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2561 stage
== MESA_SHADER_TESS_CTRL
) &&
2563 if (!var
->type
->is_array())
2564 return false; /* a system value probably */
2566 type
= var
->type
->fields
.array
;
2567 *remove_array
= true;
2570 return type
->is_array() || type
->is_matrix();
2574 st_translate_interp_loc(ir_variable
*var
)
2576 if (var
->data
.centroid
)
2577 return TGSI_INTERPOLATE_LOC_CENTROID
;
2578 else if (var
->data
.sample
)
2579 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2581 return TGSI_INTERPOLATE_LOC_CENTER
;
2585 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2587 variable_storage
*entry
= find_variable_storage(ir
->var
);
2588 ir_variable
*var
= ir
->var
;
2592 switch (var
->data
.mode
) {
2593 case ir_var_uniform
:
2594 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2595 var
->data
.param_index
);
2596 this->variables
.push_tail(entry
);
2598 case ir_var_shader_in
: {
2599 /* The linker assigns locations for varyings and attributes,
2600 * including deprecated builtins (like gl_Color), user-assign
2601 * generic attributes (glBindVertexLocation), and
2602 * user-defined varyings.
2604 assert(var
->data
.location
!= -1);
2606 const glsl_type
*type_without_array
= var
->type
->without_array();
2607 struct inout_decl
*decl
= &inputs
[num_inputs
];
2608 unsigned component
= var
->data
.location_frac
;
2609 unsigned num_components
;
2612 if (type_without_array
->is_64bit())
2613 component
= component
/ 2;
2614 if (type_without_array
->vector_elements
)
2615 num_components
= type_without_array
->vector_elements
;
2619 decl
->mesa_index
= var
->data
.location
;
2620 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2621 decl
->interp_loc
= st_translate_interp_loc(var
);
2622 decl
->base_type
= type_without_array
->base_type
;
2623 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2625 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2626 decl
->array_id
= num_input_arrays
+ 1;
2633 decl
->size
= type_size(var
->type
->fields
.array
);
2635 decl
->size
= type_size(var
->type
);
2637 entry
= new(mem_ctx
) variable_storage(var
,
2641 entry
->component
= component
;
2643 this->variables
.push_tail(entry
);
2646 case ir_var_shader_out
: {
2647 assert(var
->data
.location
!= -1);
2649 const glsl_type
*type_without_array
= var
->type
->without_array();
2650 struct inout_decl
*decl
= &outputs
[num_outputs
];
2651 unsigned component
= var
->data
.location_frac
;
2652 unsigned num_components
;
2655 if (type_without_array
->is_64bit())
2656 component
= component
/ 2;
2657 if (type_without_array
->vector_elements
)
2658 num_components
= type_without_array
->vector_elements
;
2662 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2663 decl
->base_type
= type_without_array
->base_type
;
2664 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2665 if (var
->data
.stream
& (1u << 31)) {
2666 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2668 assert(var
->data
.stream
< 4);
2669 decl
->gs_out_streams
= 0;
2670 for (unsigned i
= 0; i
< num_components
; ++i
)
2671 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2674 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2675 decl
->array_id
= num_output_arrays
+ 1;
2676 num_output_arrays
++;
2682 decl
->size
= type_size(var
->type
->fields
.array
);
2684 decl
->size
= type_size(var
->type
);
2686 if (var
->data
.fb_fetch_output
) {
2687 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2688 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2689 var
->type
, component
, decl
->array_id
);
2690 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2691 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2694 entry
= new(mem_ctx
) variable_storage(var
,
2699 entry
->component
= component
;
2701 this->variables
.push_tail(entry
);
2704 case ir_var_system_value
:
2705 entry
= new(mem_ctx
) variable_storage(var
,
2706 PROGRAM_SYSTEM_VALUE
,
2707 var
->data
.location
);
2710 case ir_var_temporary
:
2711 st_src_reg src
= get_temp(var
->type
);
2713 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2715 this->variables
.push_tail(entry
);
2721 printf("Failed to make storage for %s\n", var
->name
);
2726 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2727 entry
->component
, entry
->array_id
);
2728 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2729 this->result
.is_double_vertex_input
= true;
2730 if (!native_integers
)
2731 this->result
.type
= GLSL_TYPE_FLOAT
;
2735 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2736 GLbitfield64
* usage_mask
,
2737 GLbitfield64 double_usage_mask
,
2738 GLbitfield
* patch_usage_mask
)
2743 /* Fix array declarations by removing unused array elements at both ends
2744 * of the arrays. For example, mat4[3] where only mat[1] is used.
2746 for (i
= 0; i
< count
; i
++) {
2747 struct inout_decl
*decl
= &decls
[i
];
2748 if (!decl
->array_id
)
2751 /* Shrink the beginning. */
2752 for (j
= 0; j
< (int)decl
->size
; j
++) {
2753 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2754 if (*patch_usage_mask
&
2755 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2759 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2761 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2770 /* Shrink the end. */
2771 for (j
= decl
->size
-1; j
>= 0; j
--) {
2772 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2773 if (*patch_usage_mask
&
2774 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2778 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2780 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2787 /* When not all entries of an array are accessed, we mark them as used
2788 * here anyway, to ensure that the input/output mapping logic doesn't get
2791 * TODO This happens when an array isn't used via indirect access, which
2792 * some game ports do (at least eON-based). There is an optimization
2793 * opportunity here by replacing the array declaration with non-array
2794 * declarations of those slots that are actually used.
2796 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2797 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2798 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2800 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2806 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2810 int element_size
= type_size(ir
->type
);
2813 index
= ir
->array_index
->constant_expression_value();
2815 ir
->array
->accept(this);
2818 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2819 switch (this->prog
->Target
) {
2820 case GL_TESS_CONTROL_PROGRAM_NV
:
2821 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2822 !ir
->variable_referenced()->data
.patch
;
2824 case GL_TESS_EVALUATION_PROGRAM_NV
:
2825 is_2D
= src
.file
== PROGRAM_INPUT
&&
2826 !ir
->variable_referenced()->data
.patch
;
2828 case GL_GEOMETRY_PROGRAM_NV
:
2829 is_2D
= src
.file
== PROGRAM_INPUT
;
2839 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2840 src
.file
== PROGRAM_INPUT
)
2841 element_size
= attrib_type_size(ir
->type
, true);
2843 src
.index2D
= index
->value
.i
[0];
2844 src
.has_index2
= true;
2846 src
.index
+= index
->value
.i
[0] * element_size
;
2848 /* Variable index array dereference. It eats the "vec4" of the
2849 * base of the array and an index that offsets the TGSI register
2852 ir
->array_index
->accept(this);
2854 st_src_reg index_reg
;
2856 if (element_size
== 1) {
2857 index_reg
= this->result
;
2859 index_reg
= get_temp(native_integers
?
2860 glsl_type::int_type
: glsl_type::float_type
);
2862 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2863 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2866 /* If there was already a relative address register involved, add the
2867 * new and the old together to get the new offset.
2869 if (!is_2D
&& src
.reladdr
!= NULL
) {
2870 st_src_reg accum_reg
= get_temp(native_integers
?
2871 glsl_type::int_type
: glsl_type::float_type
);
2873 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2874 index_reg
, *src
.reladdr
);
2876 index_reg
= accum_reg
;
2880 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2881 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2883 src
.has_index2
= true;
2885 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2886 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2890 /* Change the register type to the element type of the array. */
2891 src
.type
= ir
->type
->base_type
;
2897 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2900 const glsl_type
*struct_type
= ir
->record
->type
;
2903 ir
->record
->accept(this);
2905 for (i
= 0; i
< struct_type
->length
; i
++) {
2906 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2908 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2911 /* If the type is smaller than a vec4, replicate the last channel out. */
2912 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2913 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2915 this->result
.swizzle
= SWIZZLE_NOOP
;
2917 this->result
.index
+= offset
;
2918 this->result
.type
= ir
->type
->base_type
;
2922 * We want to be careful in assignment setup to hit the actual storage
2923 * instead of potentially using a temporary like we might with the
2924 * ir_dereference handler.
2927 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2929 /* The LHS must be a dereference. If the LHS is a variable indexed array
2930 * access of a vector, it must be separated into a series conditional moves
2931 * before reaching this point (see ir_vec_index_to_cond_assign).
2933 assert(ir
->as_dereference());
2934 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2936 assert(!deref_array
->array
->type
->is_vector());
2939 /* Use the rvalue deref handler for the most part. We write swizzles using
2940 * the writemask, but we do extract the base component for enhanced layouts
2941 * from the source swizzle.
2944 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2945 return st_dst_reg(v
->result
);
2949 * Process the condition of a conditional assignment
2951 * Examines the condition of a conditional assignment to generate the optimal
2952 * first operand of a \c CMP instruction. If the condition is a relational
2953 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2954 * used as the source for the \c CMP instruction. Otherwise the comparison
2955 * is processed to a boolean result, and the boolean result is used as the
2956 * operand to the CMP instruction.
2959 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2961 ir_rvalue
*src_ir
= ir
;
2963 bool switch_order
= false;
2965 ir_expression
*const expr
= ir
->as_expression();
2967 if (native_integers
) {
2968 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2969 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2970 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2971 type
== GLSL_TYPE_BOOL
) {
2972 if (expr
->operation
== ir_binop_equal
) {
2973 if (expr
->operands
[0]->is_zero()) {
2974 src_ir
= expr
->operands
[1];
2975 switch_order
= true;
2977 else if (expr
->operands
[1]->is_zero()) {
2978 src_ir
= expr
->operands
[0];
2979 switch_order
= true;
2982 else if (expr
->operation
== ir_binop_nequal
) {
2983 if (expr
->operands
[0]->is_zero()) {
2984 src_ir
= expr
->operands
[1];
2986 else if (expr
->operands
[1]->is_zero()) {
2987 src_ir
= expr
->operands
[0];
2993 src_ir
->accept(this);
2994 return switch_order
;
2997 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2998 bool zero_on_left
= false;
3000 if (expr
->operands
[0]->is_zero()) {
3001 src_ir
= expr
->operands
[1];
3002 zero_on_left
= true;
3003 } else if (expr
->operands
[1]->is_zero()) {
3004 src_ir
= expr
->operands
[0];
3005 zero_on_left
= false;
3009 * (a < 0) T F F ( a < 0) T F F
3010 * (0 < a) F F T (-a < 0) F F T
3011 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
3012 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
3013 * (a > 0) F F T (-a < 0) F F T
3014 * (0 > a) T F F ( a < 0) T F F
3015 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
3016 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
3018 * Note that exchanging the order of 0 and 'a' in the comparison simply
3019 * means that the value of 'a' should be negated.
3022 switch (expr
->operation
) {
3024 switch_order
= false;
3025 negate
= zero_on_left
;
3028 case ir_binop_greater
:
3029 switch_order
= false;
3030 negate
= !zero_on_left
;
3033 case ir_binop_lequal
:
3034 switch_order
= true;
3035 negate
= !zero_on_left
;
3038 case ir_binop_gequal
:
3039 switch_order
= true;
3040 negate
= zero_on_left
;
3044 /* This isn't the right kind of comparison afterall, so make sure
3045 * the whole condition is visited.
3053 src_ir
->accept(this);
3055 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3056 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3057 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3058 * computing the condition.
3061 this->result
.negate
= ~this->result
.negate
;
3063 return switch_order
;
3067 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3068 st_dst_reg
*l
, st_src_reg
*r
,
3069 st_src_reg
*cond
, bool cond_swap
)
3071 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
3072 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3073 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3079 if (type
->is_array()) {
3080 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3081 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3086 if (type
->is_matrix()) {
3087 const struct glsl_type
*vec_type
;
3089 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3090 type
->vector_elements
, 1);
3092 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3093 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3098 assert(type
->is_scalar() || type
->is_vector());
3100 l
->type
= type
->base_type
;
3101 r
->type
= type
->base_type
;
3103 st_src_reg l_src
= st_src_reg(*l
);
3104 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
3106 if (native_integers
) {
3107 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3108 cond_swap
? l_src
: *r
,
3109 cond_swap
? *r
: l_src
);
3111 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3112 cond_swap
? l_src
: *r
,
3113 cond_swap
? *r
: l_src
);
3116 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3120 if (type
->is_dual_slot()) {
3122 if (r
->is_double_vertex_input
== false)
3128 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3134 ir
->rhs
->accept(this);
3137 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3141 int first_enabled_chan
= 0;
3143 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3145 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3146 variable
->data
.mode
== ir_var_shader_out
&&
3147 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3148 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3149 assert(ir
->lhs
->type
->is_scalar());
3150 assert(ir
->write_mask
== WRITEMASK_X
);
3152 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3153 l
.writemask
= WRITEMASK_Z
;
3155 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3156 l
.writemask
= WRITEMASK_Y
;
3158 } else if (ir
->write_mask
== 0) {
3159 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3161 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
3164 l
.writemask
= u_bit_consecutive(0, num_elements
);
3166 /* The type is a struct or an array of (array of) structs. */
3167 l
.writemask
= WRITEMASK_XYZW
;
3170 l
.writemask
= ir
->write_mask
;
3173 for (int i
= 0; i
< 4; i
++) {
3174 if (l
.writemask
& (1 << i
)) {
3175 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3180 l
.writemask
= l
.writemask
<< dst_component
;
3182 /* Swizzle a small RHS vector into the channels being written.
3184 * glsl ir treats write_mask as dictating how many channels are
3185 * present on the RHS while TGSI treats write_mask as just
3186 * showing which channels of the vec4 RHS get written.
3188 for (int i
= 0; i
< 4; i
++) {
3189 if (l
.writemask
& (1 << i
))
3190 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3192 swizzles
[i
] = first_enabled_chan
;
3194 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3195 swizzles
[2], swizzles
[3]);
3198 assert(l
.file
!= PROGRAM_UNDEFINED
);
3199 assert(r
.file
!= PROGRAM_UNDEFINED
);
3201 if (ir
->condition
) {
3202 const bool switch_order
= this->process_move_condition(ir
->condition
);
3203 st_src_reg condition
= this->result
;
3205 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3206 } else if (ir
->rhs
->as_expression() &&
3207 this->instructions
.get_tail() &&
3208 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3209 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3210 type_size(ir
->lhs
->type
) == 1 &&
3211 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3212 /* To avoid emitting an extra MOV when assigning an expression to a
3213 * variable, emit the last instruction of the expression again, but
3214 * replace the destination register with the target of the assignment.
3215 * Dead code elimination will remove the original instruction.
3217 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3218 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3219 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3220 new_inst
->saturate
= inst
->saturate
;
3221 inst
->dead_mask
= inst
->dst
[0].writemask
;
3223 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3229 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3232 GLdouble stack_vals
[4] = { 0 };
3233 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3234 GLenum gl_type
= GL_NONE
;
3236 static int in_array
= 0;
3237 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3239 /* Unfortunately, 4 floats is all we can get into
3240 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3241 * aggregate constant and move each constant value into it. If we
3242 * get lucky, copy propagation will eliminate the extra moves.
3244 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
3245 st_src_reg temp_base
= get_temp(ir
->type
);
3246 st_dst_reg temp
= st_dst_reg(temp_base
);
3248 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3249 int size
= type_size(field_value
->type
);
3253 field_value
->accept(this);
3256 for (i
= 0; i
< (unsigned int)size
; i
++) {
3257 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3263 this->result
= temp_base
;
3267 if (ir
->type
->is_array()) {
3268 st_src_reg temp_base
= get_temp(ir
->type
);
3269 st_dst_reg temp
= st_dst_reg(temp_base
);
3270 int size
= type_size(ir
->type
->fields
.array
);
3275 for (i
= 0; i
< ir
->type
->length
; i
++) {
3276 ir
->array_elements
[i
]->accept(this);
3278 for (int j
= 0; j
< size
; j
++) {
3279 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3285 this->result
= temp_base
;
3290 if (ir
->type
->is_matrix()) {
3291 st_src_reg mat
= get_temp(ir
->type
);
3292 st_dst_reg mat_column
= st_dst_reg(mat
);
3294 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3295 switch (ir
->type
->base_type
) {
3296 case GLSL_TYPE_FLOAT
:
3297 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3299 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3300 src
.index
= add_constant(file
,
3302 ir
->type
->vector_elements
,
3305 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3307 case GLSL_TYPE_DOUBLE
:
3308 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3309 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3310 src
.index
= add_constant(file
,
3312 ir
->type
->vector_elements
,
3315 if (ir
->type
->vector_elements
>= 2) {
3316 mat_column
.writemask
= WRITEMASK_XY
;
3317 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3318 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3320 mat_column
.writemask
= WRITEMASK_X
;
3321 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3322 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3325 if (ir
->type
->vector_elements
> 2) {
3326 if (ir
->type
->vector_elements
== 4) {
3327 mat_column
.writemask
= WRITEMASK_ZW
;
3328 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3329 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3331 mat_column
.writemask
= WRITEMASK_Z
;
3332 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3333 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3334 mat_column
.writemask
= WRITEMASK_XYZW
;
3335 src
.swizzle
= SWIZZLE_XYZW
;
3341 unreachable("Illegal matrix constant type.\n");
3350 switch (ir
->type
->base_type
) {
3351 case GLSL_TYPE_FLOAT
:
3353 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3354 values
[i
].f
= ir
->value
.f
[i
];
3357 case GLSL_TYPE_DOUBLE
:
3358 gl_type
= GL_DOUBLE
;
3359 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3360 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3363 case GLSL_TYPE_INT64
:
3364 gl_type
= GL_INT64_ARB
;
3365 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3366 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3369 case GLSL_TYPE_UINT64
:
3370 gl_type
= GL_UNSIGNED_INT64_ARB
;
3371 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3372 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3375 case GLSL_TYPE_UINT
:
3376 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3377 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3378 if (native_integers
)
3379 values
[i
].u
= ir
->value
.u
[i
];
3381 values
[i
].f
= ir
->value
.u
[i
];
3385 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3386 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3387 if (native_integers
)
3388 values
[i
].i
= ir
->value
.i
[i
];
3390 values
[i
].f
= ir
->value
.i
[i
];
3393 case GLSL_TYPE_BOOL
:
3394 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3395 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3396 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3400 assert(!"Non-float/uint/int/bool constant");
3403 this->result
= st_src_reg(file
, -1, ir
->type
);
3404 this->result
.index
= add_constant(file
,
3406 ir
->type
->vector_elements
,
3408 &this->result
.swizzle
);
3412 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3414 exec_node
*param
= ir
->actual_parameters
.get_head();
3415 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3416 ir_variable
*location
= deref
->variable_referenced();
3419 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3421 /* Calculate the surface offset */
3423 unsigned array_size
= 0, base
= 0;
3426 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3428 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3429 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3430 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3431 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3432 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3434 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3437 ir
->return_deref
->accept(this);
3438 st_dst_reg
dst(this->result
);
3439 dst
.writemask
= WRITEMASK_X
;
3441 glsl_to_tgsi_instruction
*inst
;
3443 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3444 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3445 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3446 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3447 st_src_reg_for_int(1));
3448 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3449 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3450 st_src_reg_for_int(-1));
3451 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3453 param
= param
->get_next();
3454 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3457 st_src_reg data
= this->result
, data2
= undef_src
;
3459 switch (ir
->callee
->intrinsic_id
) {
3460 case ir_intrinsic_atomic_counter_add
:
3461 opcode
= TGSI_OPCODE_ATOMUADD
;
3463 case ir_intrinsic_atomic_counter_min
:
3464 opcode
= TGSI_OPCODE_ATOMIMIN
;
3466 case ir_intrinsic_atomic_counter_max
:
3467 opcode
= TGSI_OPCODE_ATOMIMAX
;
3469 case ir_intrinsic_atomic_counter_and
:
3470 opcode
= TGSI_OPCODE_ATOMAND
;
3472 case ir_intrinsic_atomic_counter_or
:
3473 opcode
= TGSI_OPCODE_ATOMOR
;
3475 case ir_intrinsic_atomic_counter_xor
:
3476 opcode
= TGSI_OPCODE_ATOMXOR
;
3478 case ir_intrinsic_atomic_counter_exchange
:
3479 opcode
= TGSI_OPCODE_ATOMXCHG
;
3481 case ir_intrinsic_atomic_counter_comp_swap
: {
3482 opcode
= TGSI_OPCODE_ATOMCAS
;
3483 param
= param
->get_next();
3484 val
= ((ir_instruction
*)param
)->as_rvalue();
3486 data2
= this->result
;
3490 assert(!"Unexpected intrinsic");
3494 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3497 inst
->resource
= buffer
;
3501 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3503 exec_node
*param
= ir
->actual_parameters
.get_head();
3505 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3507 param
= param
->get_next();
3508 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3510 ir_constant
*const_block
= block
->as_constant();
3514 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3515 (const_block
? const_block
->value
.u
[0] : 0),
3519 block
->accept(this);
3520 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3521 *buffer
.reladdr
= this->result
;
3522 emit_arl(ir
, sampler_reladdr
, this->result
);
3525 /* Calculate the surface offset */
3526 offset
->accept(this);
3527 st_src_reg off
= this->result
;
3529 st_dst_reg dst
= undef_dst
;
3530 if (ir
->return_deref
) {
3531 ir
->return_deref
->accept(this);
3532 dst
= st_dst_reg(this->result
);
3533 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3536 glsl_to_tgsi_instruction
*inst
;
3538 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3539 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3540 if (dst
.type
== GLSL_TYPE_BOOL
)
3541 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3542 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3543 param
= param
->get_next();
3544 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3547 param
= param
->get_next();
3548 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3550 dst
.writemask
= write_mask
->value
.u
[0];
3552 dst
.type
= this->result
.type
;
3553 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3555 param
= param
->get_next();
3556 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3559 st_src_reg data
= this->result
, data2
= undef_src
;
3561 switch (ir
->callee
->intrinsic_id
) {
3562 case ir_intrinsic_ssbo_atomic_add
:
3563 opcode
= TGSI_OPCODE_ATOMUADD
;
3565 case ir_intrinsic_ssbo_atomic_min
:
3566 opcode
= TGSI_OPCODE_ATOMIMIN
;
3568 case ir_intrinsic_ssbo_atomic_max
:
3569 opcode
= TGSI_OPCODE_ATOMIMAX
;
3571 case ir_intrinsic_ssbo_atomic_and
:
3572 opcode
= TGSI_OPCODE_ATOMAND
;
3574 case ir_intrinsic_ssbo_atomic_or
:
3575 opcode
= TGSI_OPCODE_ATOMOR
;
3577 case ir_intrinsic_ssbo_atomic_xor
:
3578 opcode
= TGSI_OPCODE_ATOMXOR
;
3580 case ir_intrinsic_ssbo_atomic_exchange
:
3581 opcode
= TGSI_OPCODE_ATOMXCHG
;
3583 case ir_intrinsic_ssbo_atomic_comp_swap
:
3584 opcode
= TGSI_OPCODE_ATOMCAS
;
3585 param
= param
->get_next();
3586 val
= ((ir_instruction
*)param
)->as_rvalue();
3588 data2
= this->result
;
3591 assert(!"Unexpected intrinsic");
3595 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3598 param
= param
->get_next();
3599 ir_constant
*access
= NULL
;
3600 if (!param
->is_tail_sentinel()) {
3601 access
= ((ir_instruction
*)param
)->as_constant();
3605 /* The emit_asm() might have actually split the op into pieces, e.g. for
3606 * double stores. We have to go back and fix up all the generated ops.
3608 unsigned op
= inst
->op
;
3610 inst
->resource
= buffer
;
3612 inst
->buffer_access
= access
->value
.u
[0];
3613 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3614 if (inst
->op
== TGSI_OPCODE_UADD
)
3615 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3616 } while (inst
&& inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3620 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3622 switch (ir
->callee
->intrinsic_id
) {
3623 case ir_intrinsic_memory_barrier
:
3624 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3625 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3626 TGSI_MEMBAR_ATOMIC_BUFFER
|
3627 TGSI_MEMBAR_SHADER_IMAGE
|
3628 TGSI_MEMBAR_SHARED
));
3630 case ir_intrinsic_memory_barrier_atomic_counter
:
3631 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3632 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3634 case ir_intrinsic_memory_barrier_buffer
:
3635 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3636 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3638 case ir_intrinsic_memory_barrier_image
:
3639 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3640 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3642 case ir_intrinsic_memory_barrier_shared
:
3643 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3644 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3646 case ir_intrinsic_group_memory_barrier
:
3647 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3648 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3649 TGSI_MEMBAR_ATOMIC_BUFFER
|
3650 TGSI_MEMBAR_SHADER_IMAGE
|
3651 TGSI_MEMBAR_SHARED
|
3652 TGSI_MEMBAR_THREAD_GROUP
));
3655 assert(!"Unexpected memory barrier intrinsic");
3660 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3662 exec_node
*param
= ir
->actual_parameters
.get_head();
3664 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3666 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3668 /* Calculate the surface offset */
3669 offset
->accept(this);
3670 st_src_reg off
= this->result
;
3672 st_dst_reg dst
= undef_dst
;
3673 if (ir
->return_deref
) {
3674 ir
->return_deref
->accept(this);
3675 dst
= st_dst_reg(this->result
);
3676 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3679 glsl_to_tgsi_instruction
*inst
;
3681 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3682 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3683 inst
->resource
= buffer
;
3684 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3685 param
= param
->get_next();
3686 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3689 param
= param
->get_next();
3690 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3692 dst
.writemask
= write_mask
->value
.u
[0];
3694 dst
.type
= this->result
.type
;
3695 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3696 inst
->resource
= buffer
;
3698 param
= param
->get_next();
3699 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3702 st_src_reg data
= this->result
, data2
= undef_src
;
3704 switch (ir
->callee
->intrinsic_id
) {
3705 case ir_intrinsic_shared_atomic_add
:
3706 opcode
= TGSI_OPCODE_ATOMUADD
;
3708 case ir_intrinsic_shared_atomic_min
:
3709 opcode
= TGSI_OPCODE_ATOMIMIN
;
3711 case ir_intrinsic_shared_atomic_max
:
3712 opcode
= TGSI_OPCODE_ATOMIMAX
;
3714 case ir_intrinsic_shared_atomic_and
:
3715 opcode
= TGSI_OPCODE_ATOMAND
;
3717 case ir_intrinsic_shared_atomic_or
:
3718 opcode
= TGSI_OPCODE_ATOMOR
;
3720 case ir_intrinsic_shared_atomic_xor
:
3721 opcode
= TGSI_OPCODE_ATOMXOR
;
3723 case ir_intrinsic_shared_atomic_exchange
:
3724 opcode
= TGSI_OPCODE_ATOMXCHG
;
3726 case ir_intrinsic_shared_atomic_comp_swap
:
3727 opcode
= TGSI_OPCODE_ATOMCAS
;
3728 param
= param
->get_next();
3729 val
= ((ir_instruction
*)param
)->as_rvalue();
3731 data2
= this->result
;
3734 assert(!"Unexpected intrinsic");
3738 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3739 inst
->resource
= buffer
;
3744 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3746 exec_node
*param
= ir
->actual_parameters
.get_head();
3748 ir_dereference
*img
= (ir_dereference
*)param
;
3749 const ir_variable
*imgvar
= img
->variable_referenced();
3750 const glsl_type
*type
= imgvar
->type
->without_array();
3751 unsigned sampler_array_size
= 1, sampler_base
= 0;
3754 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3756 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3757 (uint16_t*)&image
.index
, &reladdr
, true);
3759 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3760 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3761 *image
.reladdr
= reladdr
;
3762 emit_arl(ir
, sampler_reladdr
, reladdr
);
3765 st_dst_reg dst
= undef_dst
;
3766 if (ir
->return_deref
) {
3767 ir
->return_deref
->accept(this);
3768 dst
= st_dst_reg(this->result
);
3769 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3772 glsl_to_tgsi_instruction
*inst
;
3774 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3775 dst
.writemask
= WRITEMASK_XYZ
;
3776 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3777 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3778 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3779 st_dst_reg dstres
= st_dst_reg(res
);
3780 dstres
.writemask
= WRITEMASK_W
;
3781 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3782 res
.swizzle
= SWIZZLE_WWWW
;
3783 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3785 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3787 st_dst_reg coord_dst
;
3788 coord
= get_temp(glsl_type::ivec4_type
);
3789 coord_dst
= st_dst_reg(coord
);
3790 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3791 param
= param
->get_next();
3792 ((ir_dereference
*)param
)->accept(this);
3793 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3794 coord
.swizzle
= SWIZZLE_XXXX
;
3795 switch (type
->coordinate_components()) {
3796 case 4: assert(!"unexpected coord count");
3798 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3800 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3803 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3804 param
= param
->get_next();
3805 ((ir_dereference
*)param
)->accept(this);
3806 st_src_reg sample
= this->result
;
3807 sample
.swizzle
= SWIZZLE_XXXX
;
3808 coord_dst
.writemask
= WRITEMASK_W
;
3809 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3810 coord
.swizzle
|= SWIZZLE_W
<< 9;
3813 param
= param
->get_next();
3814 if (!param
->is_tail_sentinel()) {
3815 ((ir_dereference
*)param
)->accept(this);
3816 arg1
= this->result
;
3817 param
= param
->get_next();
3820 if (!param
->is_tail_sentinel()) {
3821 ((ir_dereference
*)param
)->accept(this);
3822 arg2
= this->result
;
3823 param
= param
->get_next();
3826 assert(param
->is_tail_sentinel());
3829 switch (ir
->callee
->intrinsic_id
) {
3830 case ir_intrinsic_image_load
:
3831 opcode
= TGSI_OPCODE_LOAD
;
3833 case ir_intrinsic_image_store
:
3834 opcode
= TGSI_OPCODE_STORE
;
3836 case ir_intrinsic_image_atomic_add
:
3837 opcode
= TGSI_OPCODE_ATOMUADD
;
3839 case ir_intrinsic_image_atomic_min
:
3840 opcode
= TGSI_OPCODE_ATOMIMIN
;
3842 case ir_intrinsic_image_atomic_max
:
3843 opcode
= TGSI_OPCODE_ATOMIMAX
;
3845 case ir_intrinsic_image_atomic_and
:
3846 opcode
= TGSI_OPCODE_ATOMAND
;
3848 case ir_intrinsic_image_atomic_or
:
3849 opcode
= TGSI_OPCODE_ATOMOR
;
3851 case ir_intrinsic_image_atomic_xor
:
3852 opcode
= TGSI_OPCODE_ATOMXOR
;
3854 case ir_intrinsic_image_atomic_exchange
:
3855 opcode
= TGSI_OPCODE_ATOMXCHG
;
3857 case ir_intrinsic_image_atomic_comp_swap
:
3858 opcode
= TGSI_OPCODE_ATOMCAS
;
3861 assert(!"Unexpected intrinsic");
3865 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3866 if (opcode
== TGSI_OPCODE_STORE
)
3867 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3870 inst
->resource
= image
;
3871 inst
->sampler_array_size
= sampler_array_size
;
3872 inst
->sampler_base
= sampler_base
;
3874 switch (type
->sampler_dimensionality
) {
3875 case GLSL_SAMPLER_DIM_1D
:
3876 inst
->tex_target
= (type
->sampler_array
)
3877 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3879 case GLSL_SAMPLER_DIM_2D
:
3880 inst
->tex_target
= (type
->sampler_array
)
3881 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3883 case GLSL_SAMPLER_DIM_3D
:
3884 inst
->tex_target
= TEXTURE_3D_INDEX
;
3886 case GLSL_SAMPLER_DIM_CUBE
:
3887 inst
->tex_target
= (type
->sampler_array
)
3888 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3890 case GLSL_SAMPLER_DIM_RECT
:
3891 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3893 case GLSL_SAMPLER_DIM_BUF
:
3894 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3896 case GLSL_SAMPLER_DIM_EXTERNAL
:
3897 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3899 case GLSL_SAMPLER_DIM_MS
:
3900 inst
->tex_target
= (type
->sampler_array
)
3901 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3904 assert(!"Should not get here.");
3907 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3908 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3910 if (imgvar
->data
.image_coherent
)
3911 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3912 if (imgvar
->data
.image_restrict
)
3913 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3914 if (imgvar
->data
.image_volatile
)
3915 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3919 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3921 ir_function_signature
*sig
= ir
->callee
;
3923 /* Filter out intrinsics */
3924 switch (sig
->intrinsic_id
) {
3925 case ir_intrinsic_atomic_counter_read
:
3926 case ir_intrinsic_atomic_counter_increment
:
3927 case ir_intrinsic_atomic_counter_predecrement
:
3928 case ir_intrinsic_atomic_counter_add
:
3929 case ir_intrinsic_atomic_counter_min
:
3930 case ir_intrinsic_atomic_counter_max
:
3931 case ir_intrinsic_atomic_counter_and
:
3932 case ir_intrinsic_atomic_counter_or
:
3933 case ir_intrinsic_atomic_counter_xor
:
3934 case ir_intrinsic_atomic_counter_exchange
:
3935 case ir_intrinsic_atomic_counter_comp_swap
:
3936 visit_atomic_counter_intrinsic(ir
);
3939 case ir_intrinsic_ssbo_load
:
3940 case ir_intrinsic_ssbo_store
:
3941 case ir_intrinsic_ssbo_atomic_add
:
3942 case ir_intrinsic_ssbo_atomic_min
:
3943 case ir_intrinsic_ssbo_atomic_max
:
3944 case ir_intrinsic_ssbo_atomic_and
:
3945 case ir_intrinsic_ssbo_atomic_or
:
3946 case ir_intrinsic_ssbo_atomic_xor
:
3947 case ir_intrinsic_ssbo_atomic_exchange
:
3948 case ir_intrinsic_ssbo_atomic_comp_swap
:
3949 visit_ssbo_intrinsic(ir
);
3952 case ir_intrinsic_memory_barrier
:
3953 case ir_intrinsic_memory_barrier_atomic_counter
:
3954 case ir_intrinsic_memory_barrier_buffer
:
3955 case ir_intrinsic_memory_barrier_image
:
3956 case ir_intrinsic_memory_barrier_shared
:
3957 case ir_intrinsic_group_memory_barrier
:
3958 visit_membar_intrinsic(ir
);
3961 case ir_intrinsic_shared_load
:
3962 case ir_intrinsic_shared_store
:
3963 case ir_intrinsic_shared_atomic_add
:
3964 case ir_intrinsic_shared_atomic_min
:
3965 case ir_intrinsic_shared_atomic_max
:
3966 case ir_intrinsic_shared_atomic_and
:
3967 case ir_intrinsic_shared_atomic_or
:
3968 case ir_intrinsic_shared_atomic_xor
:
3969 case ir_intrinsic_shared_atomic_exchange
:
3970 case ir_intrinsic_shared_atomic_comp_swap
:
3971 visit_shared_intrinsic(ir
);
3974 case ir_intrinsic_image_load
:
3975 case ir_intrinsic_image_store
:
3976 case ir_intrinsic_image_atomic_add
:
3977 case ir_intrinsic_image_atomic_min
:
3978 case ir_intrinsic_image_atomic_max
:
3979 case ir_intrinsic_image_atomic_and
:
3980 case ir_intrinsic_image_atomic_or
:
3981 case ir_intrinsic_image_atomic_xor
:
3982 case ir_intrinsic_image_atomic_exchange
:
3983 case ir_intrinsic_image_atomic_comp_swap
:
3984 case ir_intrinsic_image_size
:
3985 case ir_intrinsic_image_samples
:
3986 visit_image_intrinsic(ir
);
3989 case ir_intrinsic_invalid
:
3990 case ir_intrinsic_generic_load
:
3991 case ir_intrinsic_generic_store
:
3992 case ir_intrinsic_generic_atomic_add
:
3993 case ir_intrinsic_generic_atomic_and
:
3994 case ir_intrinsic_generic_atomic_or
:
3995 case ir_intrinsic_generic_atomic_xor
:
3996 case ir_intrinsic_generic_atomic_min
:
3997 case ir_intrinsic_generic_atomic_max
:
3998 case ir_intrinsic_generic_atomic_exchange
:
3999 case ir_intrinsic_generic_atomic_comp_swap
:
4000 case ir_intrinsic_shader_clock
:
4001 unreachable("Invalid intrinsic");
4006 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4007 unsigned *array_elements
,
4009 st_src_reg
*indirect
,
4012 switch (tail
->ir_type
) {
4013 case ir_type_dereference_record
: {
4014 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4015 const glsl_type
*struct_type
= deref_record
->record
->type
;
4016 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
4018 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4020 assert(field_index
>= 0);
4021 *location
+= struct_type
->record_location_offset(field_index
);
4025 case ir_type_dereference_array
: {
4026 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4027 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
4030 st_src_reg temp_reg
;
4031 st_dst_reg temp_dst
;
4033 temp_reg
= get_temp(glsl_type::uint_type
);
4034 temp_dst
= st_dst_reg(temp_reg
);
4035 temp_dst
.writemask
= 1;
4037 deref_arr
->array_index
->accept(this);
4038 if (*array_elements
!= 1)
4039 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4041 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4043 if (indirect
->file
== PROGRAM_UNDEFINED
)
4044 *indirect
= temp_reg
;
4046 temp_dst
= st_dst_reg(*indirect
);
4047 temp_dst
.writemask
= 1;
4048 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4051 *index
+= array_index
->value
.u
[0] * *array_elements
;
4053 *array_elements
*= deref_arr
->array
->type
->length
;
4055 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4064 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4065 unsigned *array_size
,
4068 st_src_reg
*reladdr
,
4071 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4072 unsigned location
= 0;
4073 ir_variable
*var
= ir
->variable_referenced();
4075 memset(reladdr
, 0, sizeof(*reladdr
));
4076 reladdr
->file
= PROGRAM_UNDEFINED
;
4082 location
= var
->data
.location
;
4083 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4086 * If we end up with no indirect then adjust the base to the index,
4087 * and set the array size to 1.
4089 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4095 assert(location
!= 0xffffffff);
4096 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4097 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4102 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4104 if (offset
.reladdr
|| offset
.reladdr2
) {
4105 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4106 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4107 tmp_dst
.writemask
= WRITEMASK_XY
;
4108 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4116 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4118 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4119 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4120 st_src_reg levels_src
, reladdr
;
4121 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4122 glsl_to_tgsi_instruction
*inst
= NULL
;
4123 unsigned opcode
= TGSI_OPCODE_NOP
;
4124 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4125 unsigned sampler_array_size
= 1, sampler_base
= 0;
4126 uint16_t sampler_index
= 0;
4127 bool is_cube_array
= false;
4130 /* if we are a cube array sampler */
4131 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
4132 sampler_type
->sampler_array
)) {
4133 is_cube_array
= true;
4136 if (ir
->coordinate
) {
4137 ir
->coordinate
->accept(this);
4139 /* Put our coords in a temp. We'll need to modify them for shadow,
4140 * projection, or LOD, so the only case we'd use it as-is is if
4141 * we're doing plain old texturing. The optimization passes on
4142 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4144 coord
= get_temp(glsl_type::vec4_type
);
4145 coord_dst
= st_dst_reg(coord
);
4146 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4147 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4150 if (ir
->projector
) {
4151 ir
->projector
->accept(this);
4152 projector
= this->result
;
4155 /* Storage for our result. Ideally for an assignment we'd be using
4156 * the actual storage for the result here, instead.
4158 result_src
= get_temp(ir
->type
);
4159 result_dst
= st_dst_reg(result_src
);
4163 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4165 ir
->offset
->accept(this);
4166 offset
[0] = this->result
;
4170 if (is_cube_array
||
4171 sampler_type
== glsl_type::samplerCubeShadow_type
) {
4172 opcode
= TGSI_OPCODE_TXB2
;
4175 opcode
= TGSI_OPCODE_TXB
;
4177 ir
->lod_info
.bias
->accept(this);
4178 lod_info
= this->result
;
4180 ir
->offset
->accept(this);
4181 offset
[0] = this->result
;
4185 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4186 ir
->lod_info
.lod
->accept(this);
4187 lod_info
= this->result
;
4189 ir
->offset
->accept(this);
4190 offset
[0] = this->result
;
4194 opcode
= TGSI_OPCODE_TXD
;
4195 ir
->lod_info
.grad
.dPdx
->accept(this);
4197 ir
->lod_info
.grad
.dPdy
->accept(this);
4200 ir
->offset
->accept(this);
4201 offset
[0] = this->result
;
4205 opcode
= TGSI_OPCODE_TXQ
;
4206 ir
->lod_info
.lod
->accept(this);
4207 lod_info
= this->result
;
4209 case ir_query_levels
:
4210 opcode
= TGSI_OPCODE_TXQ
;
4211 lod_info
= undef_src
;
4212 levels_src
= get_temp(ir
->type
);
4215 opcode
= TGSI_OPCODE_TXF
;
4216 ir
->lod_info
.lod
->accept(this);
4217 lod_info
= this->result
;
4219 ir
->offset
->accept(this);
4220 offset
[0] = this->result
;
4224 opcode
= TGSI_OPCODE_TXF
;
4225 ir
->lod_info
.sample_index
->accept(this);
4226 sample_index
= this->result
;
4229 opcode
= TGSI_OPCODE_TG4
;
4230 ir
->lod_info
.component
->accept(this);
4231 component
= this->result
;
4233 ir
->offset
->accept(this);
4234 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4235 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4236 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4237 offset
[i
] = this->result
;
4238 offset
[i
].index
+= i
* type_size(elt_type
);
4239 offset
[i
].type
= elt_type
->base_type
;
4240 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4241 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4244 offset
[0] = canonicalize_gather_offset(this->result
);
4249 opcode
= TGSI_OPCODE_LODQ
;
4251 case ir_texture_samples
:
4252 opcode
= TGSI_OPCODE_TXQS
;
4254 case ir_samples_identical
:
4255 unreachable("Unexpected ir_samples_identical opcode");
4258 if (ir
->projector
) {
4259 if (opcode
== TGSI_OPCODE_TEX
) {
4260 /* Slot the projector in as the last component of the coord. */
4261 coord_dst
.writemask
= WRITEMASK_W
;
4262 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4263 coord_dst
.writemask
= WRITEMASK_XYZW
;
4264 opcode
= TGSI_OPCODE_TXP
;
4266 st_src_reg coord_w
= coord
;
4267 coord_w
.swizzle
= SWIZZLE_WWWW
;
4269 /* For the other TEX opcodes there's no projective version
4270 * since the last slot is taken up by LOD info. Do the
4271 * projective divide now.
4273 coord_dst
.writemask
= WRITEMASK_W
;
4274 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4276 /* In the case where we have to project the coordinates "by hand,"
4277 * the shadow comparator value must also be projected.
4279 st_src_reg tmp_src
= coord
;
4280 if (ir
->shadow_comparator
) {
4281 /* Slot the shadow value in as the second to last component of the
4284 ir
->shadow_comparator
->accept(this);
4286 tmp_src
= get_temp(glsl_type::vec4_type
);
4287 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4289 /* Projective division not allowed for array samplers. */
4290 assert(!sampler_type
->sampler_array
);
4292 tmp_dst
.writemask
= WRITEMASK_Z
;
4293 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4295 tmp_dst
.writemask
= WRITEMASK_XY
;
4296 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4299 coord_dst
.writemask
= WRITEMASK_XYZ
;
4300 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4302 coord_dst
.writemask
= WRITEMASK_XYZW
;
4303 coord
.swizzle
= SWIZZLE_XYZW
;
4307 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4308 * comparator was put in the correct place (and projected) by the code,
4309 * above, that handles by-hand projection.
4311 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4312 /* Slot the shadow value in as the second to last component of the
4315 ir
->shadow_comparator
->accept(this);
4317 if (is_cube_array
) {
4318 cube_sc
= get_temp(glsl_type::float_type
);
4319 cube_sc_dst
= st_dst_reg(cube_sc
);
4320 cube_sc_dst
.writemask
= WRITEMASK_X
;
4321 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4322 cube_sc_dst
.writemask
= WRITEMASK_X
;
4325 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4326 sampler_type
->sampler_array
) ||
4327 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4328 coord_dst
.writemask
= WRITEMASK_W
;
4330 coord_dst
.writemask
= WRITEMASK_Z
;
4332 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4333 coord_dst
.writemask
= WRITEMASK_XYZW
;
4337 if (ir
->op
== ir_txf_ms
) {
4338 coord_dst
.writemask
= WRITEMASK_W
;
4339 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4340 coord_dst
.writemask
= WRITEMASK_XYZW
;
4341 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4342 opcode
== TGSI_OPCODE_TXF
) {
4343 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4344 coord_dst
.writemask
= WRITEMASK_W
;
4345 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4346 coord_dst
.writemask
= WRITEMASK_XYZW
;
4349 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4350 &sampler_index
, &reladdr
, true);
4351 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4352 emit_arl(ir
, sampler_reladdr
, reladdr
);
4354 if (opcode
== TGSI_OPCODE_TXD
)
4355 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4356 else if (opcode
== TGSI_OPCODE_TXQ
) {
4357 if (ir
->op
== ir_query_levels
) {
4358 /* the level is stored in W */
4359 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4360 result_dst
.writemask
= WRITEMASK_X
;
4361 levels_src
.swizzle
= SWIZZLE_WWWW
;
4362 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4364 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4365 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4366 inst
= emit_asm(ir
, opcode
, result_dst
);
4367 } else if (opcode
== TGSI_OPCODE_TXF
) {
4368 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4369 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4370 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4371 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4372 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4373 } else if (opcode
== TGSI_OPCODE_TG4
) {
4374 if (is_cube_array
&& ir
->shadow_comparator
) {
4375 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4377 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4380 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4382 if (ir
->shadow_comparator
)
4383 inst
->tex_shadow
= GL_TRUE
;
4385 inst
->resource
.index
= sampler_index
;
4386 inst
->sampler_array_size
= sampler_array_size
;
4387 inst
->sampler_base
= sampler_base
;
4389 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4390 inst
->resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4391 memcpy(inst
->resource
.reladdr
, &reladdr
, sizeof(reladdr
));
4395 if (!inst
->tex_offsets
)
4396 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4398 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4399 inst
->tex_offsets
[i
] = offset
[i
];
4400 inst
->tex_offset_num_offset
= i
;
4403 switch (sampler_type
->sampler_dimensionality
) {
4404 case GLSL_SAMPLER_DIM_1D
:
4405 inst
->tex_target
= (sampler_type
->sampler_array
)
4406 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4408 case GLSL_SAMPLER_DIM_2D
:
4409 inst
->tex_target
= (sampler_type
->sampler_array
)
4410 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4412 case GLSL_SAMPLER_DIM_3D
:
4413 inst
->tex_target
= TEXTURE_3D_INDEX
;
4415 case GLSL_SAMPLER_DIM_CUBE
:
4416 inst
->tex_target
= (sampler_type
->sampler_array
)
4417 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4419 case GLSL_SAMPLER_DIM_RECT
:
4420 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4422 case GLSL_SAMPLER_DIM_BUF
:
4423 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4425 case GLSL_SAMPLER_DIM_EXTERNAL
:
4426 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4428 case GLSL_SAMPLER_DIM_MS
:
4429 inst
->tex_target
= (sampler_type
->sampler_array
)
4430 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4433 assert(!"Should not get here.");
4436 inst
->tex_type
= ir
->type
->base_type
;
4438 this->result
= result_src
;
4442 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4444 assert(!ir
->get_value());
4446 emit_asm(ir
, TGSI_OPCODE_RET
);
4450 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4452 if (ir
->condition
) {
4453 ir
->condition
->accept(this);
4454 st_src_reg condition
= this->result
;
4456 /* Convert the bool condition to a float so we can negate. */
4457 if (native_integers
) {
4458 st_src_reg temp
= get_temp(ir
->condition
->type
);
4459 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4460 condition
, st_src_reg_for_float(1.0));
4464 condition
.negate
= ~condition
.negate
;
4465 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4467 /* unconditional kil */
4468 emit_asm(ir
, TGSI_OPCODE_KILL
);
4473 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4476 glsl_to_tgsi_instruction
*if_inst
;
4478 ir
->condition
->accept(this);
4479 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4481 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4483 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4485 this->instructions
.push_tail(if_inst
);
4487 visit_exec_list(&ir
->then_instructions
, this);
4489 if (!ir
->else_instructions
.is_empty()) {
4490 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4491 visit_exec_list(&ir
->else_instructions
, this);
4494 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4499 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4501 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4503 ir
->stream
->accept(this);
4504 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4508 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4510 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4512 ir
->stream
->accept(this);
4513 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4517 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4519 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4520 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4522 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4525 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4527 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4529 result
.file
= PROGRAM_UNDEFINED
;
4536 num_input_arrays
= 0;
4537 num_output_arrays
= 0;
4539 num_address_regs
= 0;
4543 indirect_addr_consts
= false;
4544 wpos_transform_const
= -1;
4546 native_integers
= false;
4547 mem_ctx
= ralloc_context(NULL
);
4550 shader_program
= NULL
;
4555 use_shared_memory
= false;
4558 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4561 ralloc_free(mem_ctx
);
4564 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4571 * Count resources used by the given gpu program (number of texture
4575 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4577 v
->samplers_used
= 0;
4578 v
->buffers_used
= 0;
4581 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4582 if (inst
->info
->is_tex
) {
4583 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4584 unsigned idx
= inst
->sampler_base
+ i
;
4585 v
->samplers_used
|= 1u << idx
;
4587 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4588 v
->sampler_types
[idx
] = inst
->tex_type
;
4589 v
->sampler_targets
[idx
] =
4590 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4592 if (inst
->tex_shadow
) {
4593 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4598 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4599 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4601 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4602 is_resource_instruction(inst
->op
) ||
4603 inst
->op
== TGSI_OPCODE_STORE
)) {
4604 if (inst
->resource
.file
== PROGRAM_BUFFER
) {
4605 v
->buffers_used
|= 1 << inst
->resource
.index
;
4606 } else if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4607 v
->use_shared_memory
= true;
4609 assert(inst
->resource
.file
== PROGRAM_IMAGE
);
4610 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4611 unsigned idx
= inst
->sampler_base
+ i
;
4612 v
->images_used
|= 1 << idx
;
4613 v
->image_targets
[idx
] =
4614 st_translate_texture_target(inst
->tex_target
, false);
4615 v
->image_formats
[idx
] = inst
->image_format
;
4620 prog
->SamplersUsed
= v
->samplers_used
;
4622 if (v
->shader_program
!= NULL
)
4623 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4627 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4628 * are read from the given src in this instruction
4631 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4633 int read_mask
= 0, comp
;
4635 /* Now, given the src swizzle and the written channels, find which
4636 * components are actually read
4638 for (comp
= 0; comp
< 4; ++comp
) {
4639 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4641 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4642 read_mask
|= 1 << coord
;
4649 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4650 * instruction is the first instruction to write to register T0. There are
4651 * several lowering passes done in GLSL IR (e.g. branches and
4652 * relative addressing) that create a large number of conditional assignments
4653 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4655 * Here is why this conversion is safe:
4656 * CMP T0, T1 T2 T0 can be expanded to:
4662 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4663 * as the original program. If (T1 < 0.0) evaluates to false, executing
4664 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4665 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4666 * because any instruction that was going to read from T0 after this was going
4667 * to read a garbage value anyway.
4670 glsl_to_tgsi_visitor::simplify_cmp(void)
4672 int tempWritesSize
= 0;
4673 unsigned *tempWrites
= NULL
;
4674 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4676 memset(outputWrites
, 0, sizeof(outputWrites
));
4678 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4679 unsigned prevWriteMask
= 0;
4681 /* Give up if we encounter relative addressing or flow control. */
4682 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4683 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4684 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4685 inst
->op
== TGSI_OPCODE_CONT
||
4686 inst
->op
== TGSI_OPCODE_END
||
4687 inst
->op
== TGSI_OPCODE_RET
) {
4691 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4692 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4693 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4694 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4695 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4696 if (inst
->dst
[0].index
>= tempWritesSize
) {
4697 const int inc
= 4096;
4699 tempWrites
= (unsigned*)
4701 (tempWritesSize
+ inc
) * sizeof(unsigned));
4705 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4706 tempWritesSize
+= inc
;
4709 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4710 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4714 /* For a CMP to be considered a conditional write, the destination
4715 * register and source register two must be the same. */
4716 if (inst
->op
== TGSI_OPCODE_CMP
4717 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4718 && inst
->src
[2].file
== inst
->dst
[0].file
4719 && inst
->src
[2].index
== inst
->dst
[0].index
4720 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4722 inst
->op
= TGSI_OPCODE_MOV
;
4723 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4724 inst
->src
[0] = inst
->src
[1];
4731 /* Replaces all references to a temporary register index with another index. */
4733 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4735 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4738 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4739 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4740 for (k
= 0; k
< num_renames
; k
++)
4741 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4742 inst
->src
[j
].index
= renames
[k
].new_reg
;
4745 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4746 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4747 for (k
= 0; k
< num_renames
; k
++)
4748 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4749 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4752 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4753 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4754 for (k
= 0; k
< num_renames
; k
++)
4755 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4756 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4762 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4764 int depth
= 0; /* loop depth */
4765 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4768 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4769 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4770 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4771 if (first_reads
[inst
->src
[j
].index
] == -1)
4772 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4775 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4776 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4777 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4778 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4781 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4784 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4794 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4796 int depth
= 0; /* loop depth */
4797 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4800 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4801 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4802 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4803 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4805 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4806 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4807 if (first_writes
[inst
->dst
[j
].index
] == -1)
4808 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4809 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4812 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4813 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4814 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4816 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4819 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4822 for (k
= 0; k
< this->next_temp
; k
++) {
4823 if (last_reads
[k
] == -2) {
4835 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4837 int depth
= 0; /* loop depth */
4841 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4842 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4843 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4844 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4847 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4849 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4851 for (k
= 0; k
< this->next_temp
; k
++) {
4852 if (last_writes
[k
] == -2) {
4863 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4864 * channels for copy propagation and updates following instructions to
4865 * use the original versions.
4867 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4868 * will occur. As an example, a TXP production before this pass:
4870 * 0: MOV TEMP[1], INPUT[4].xyyy;
4871 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4872 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4876 * 0: MOV TEMP[1], INPUT[4].xyyy;
4877 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4878 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4880 * which allows for dead code elimination on TEMP[1]'s writes.
4883 glsl_to_tgsi_visitor::copy_propagate(void)
4885 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4886 glsl_to_tgsi_instruction
*,
4887 this->next_temp
* 4);
4888 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4891 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4892 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4893 || inst
->dst
[0].index
< this->next_temp
);
4895 /* First, do any copy propagation possible into the src regs. */
4896 for (int r
= 0; r
< 3; r
++) {
4897 glsl_to_tgsi_instruction
*first
= NULL
;
4899 int acp_base
= inst
->src
[r
].index
* 4;
4901 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4902 inst
->src
[r
].reladdr
||
4903 inst
->src
[r
].reladdr2
)
4906 /* See if we can find entries in the ACP consisting of MOVs
4907 * from the same src register for all the swizzled channels
4908 * of this src register reference.
4910 for (int i
= 0; i
< 4; i
++) {
4911 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4912 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4919 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4924 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4925 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4926 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4927 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4935 /* We've now validated that we can copy-propagate to
4936 * replace this src register reference. Do it.
4938 inst
->src
[r
].file
= first
->src
[0].file
;
4939 inst
->src
[r
].index
= first
->src
[0].index
;
4940 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4941 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4942 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4943 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4946 for (int i
= 0; i
< 4; i
++) {
4947 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4948 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4949 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4951 inst
->src
[r
].swizzle
= swizzle
;
4956 case TGSI_OPCODE_BGNLOOP
:
4957 case TGSI_OPCODE_ENDLOOP
:
4958 /* End of a basic block, clear the ACP entirely. */
4959 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4962 case TGSI_OPCODE_IF
:
4963 case TGSI_OPCODE_UIF
:
4967 case TGSI_OPCODE_ENDIF
:
4968 case TGSI_OPCODE_ELSE
:
4969 /* Clear all channels written inside the block from the ACP, but
4970 * leaving those that were not touched.
4972 for (int r
= 0; r
< this->next_temp
; r
++) {
4973 for (int c
= 0; c
< 4; c
++) {
4974 if (!acp
[4 * r
+ c
])
4977 if (acp_level
[4 * r
+ c
] >= level
)
4978 acp
[4 * r
+ c
] = NULL
;
4981 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4986 /* Continuing the block, clear any written channels from
4989 for (int d
= 0; d
< 2; d
++) {
4990 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4991 /* Any temporary might be written, so no copy propagation
4992 * across this instruction.
4994 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4995 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4996 inst
->dst
[d
].reladdr
) {
4997 /* Any output might be written, so no copy propagation
4998 * from outputs across this instruction.
5000 for (int r
= 0; r
< this->next_temp
; r
++) {
5001 for (int c
= 0; c
< 4; c
++) {
5002 if (!acp
[4 * r
+ c
])
5005 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5006 acp
[4 * r
+ c
] = NULL
;
5009 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5010 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5011 /* Clear where it's used as dst. */
5012 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5013 for (int c
= 0; c
< 4; c
++) {
5014 if (inst
->dst
[d
].writemask
& (1 << c
))
5015 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5019 /* Clear where it's used as src. */
5020 for (int r
= 0; r
< this->next_temp
; r
++) {
5021 for (int c
= 0; c
< 4; c
++) {
5022 if (!acp
[4 * r
+ c
])
5025 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5027 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5028 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5029 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5030 acp
[4 * r
+ c
] = NULL
;
5039 /* If this is a copy, add it to the ACP. */
5040 if (inst
->op
== TGSI_OPCODE_MOV
&&
5041 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5042 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5043 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5044 !inst
->dst
[0].reladdr
&&
5045 !inst
->dst
[0].reladdr2
&&
5047 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5048 !inst
->src
[0].reladdr
&&
5049 !inst
->src
[0].reladdr2
&&
5050 !inst
->src
[0].negate
&&
5051 !inst
->src
[0].abs
) {
5052 for (int i
= 0; i
< 4; i
++) {
5053 if (inst
->dst
[0].writemask
& (1 << i
)) {
5054 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5055 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5061 ralloc_free(acp_level
);
5066 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5069 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5070 * will occur. As an example, a TXP production after copy propagation but
5073 * 0: MOV TEMP[1], INPUT[4].xyyy;
5074 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5075 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5077 * and after this pass:
5079 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5082 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5084 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5085 glsl_to_tgsi_instruction
*,
5086 this->next_temp
* 4);
5087 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5091 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5092 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5093 || inst
->dst
[0].index
< this->next_temp
);
5096 case TGSI_OPCODE_BGNLOOP
:
5097 case TGSI_OPCODE_ENDLOOP
:
5098 case TGSI_OPCODE_CONT
:
5099 case TGSI_OPCODE_BRK
:
5100 /* End of a basic block, clear the write array entirely.
5102 * This keeps us from killing dead code when the writes are
5103 * on either side of a loop, even when the register isn't touched
5104 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5105 * dead code of this type, so it shouldn't make a difference as long as
5106 * the dead code elimination pass in the GLSL compiler does its job.
5108 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5111 case TGSI_OPCODE_ENDIF
:
5112 case TGSI_OPCODE_ELSE
:
5113 /* Promote the recorded level of all channels written inside the
5114 * preceding if or else block to the level above the if/else block.
5116 for (int r
= 0; r
< this->next_temp
; r
++) {
5117 for (int c
= 0; c
< 4; c
++) {
5118 if (!writes
[4 * r
+ c
])
5121 if (write_level
[4 * r
+ c
] == level
)
5122 write_level
[4 * r
+ c
] = level
-1;
5125 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5129 case TGSI_OPCODE_IF
:
5130 case TGSI_OPCODE_UIF
:
5132 /* fallthrough to default case to mark the condition as read */
5134 /* Continuing the block, clear any channels from the write array that
5135 * are read by this instruction.
5137 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5138 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5139 /* Any temporary might be read, so no dead code elimination
5140 * across this instruction.
5142 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5143 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5144 /* Clear where it's used as src. */
5145 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5146 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5147 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5148 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5150 for (int c
= 0; c
< 4; c
++) {
5151 if (src_chans
& (1 << c
))
5152 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5156 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5157 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5158 /* Any temporary might be read, so no dead code elimination
5159 * across this instruction.
5161 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5162 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5163 /* Clear where it's used as src. */
5164 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5165 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5166 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5167 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5169 for (int c
= 0; c
< 4; c
++) {
5170 if (src_chans
& (1 << c
))
5171 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5178 /* If this instruction writes to a temporary, add it to the write array.
5179 * If there is already an instruction in the write array for one or more
5180 * of the channels, flag that channel write as dead.
5182 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5183 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5184 !inst
->dst
[i
].reladdr
) {
5185 for (int c
= 0; c
< 4; c
++) {
5186 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5187 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5188 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5191 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5193 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5194 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5201 /* Anything still in the write array at this point is dead code. */
5202 for (int r
= 0; r
< this->next_temp
; r
++) {
5203 for (int c
= 0; c
< 4; c
++) {
5204 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5206 inst
->dead_mask
|= (1 << c
);
5210 /* Now actually remove the instructions that are completely dead and update
5211 * the writemask of other instructions with dead channels.
5213 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5214 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5216 /* No amount of dead masks should remove memory stores */
5217 if (inst
->info
->is_store
)
5220 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5225 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5226 if (inst
->dead_mask
== WRITEMASK_XY
||
5227 inst
->dead_mask
== WRITEMASK_ZW
)
5228 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5230 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5234 ralloc_free(write_level
);
5235 ralloc_free(writes
);
5240 /* merge DFRACEXP instructions into one. */
5242 glsl_to_tgsi_visitor::merge_two_dsts(void)
5244 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5245 glsl_to_tgsi_instruction
*inst2
;
5247 if (num_inst_dst_regs(inst
) != 2)
5250 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5251 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5254 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5257 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5258 inst
->src
[0].index
== inst2
->src
[0].index
&&
5259 inst
->src
[0].type
== inst2
->src
[0].type
&&
5260 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5262 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5268 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5270 inst
->dst
[0] = inst2
->dst
[0];
5271 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5272 inst
->dst
[1] = inst2
->dst
[1];
5283 /* Merges temporary registers together where possible to reduce the number of
5284 * registers needed to run a program.
5286 * Produces optimal code only after copy propagation and dead code elimination
5289 glsl_to_tgsi_visitor::merge_registers(void)
5291 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5292 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5293 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5295 int num_renames
= 0;
5297 /* Read the indices of the last read and first write to each temp register
5298 * into an array so that we don't have to traverse the instruction list as
5300 for (i
= 0; i
< this->next_temp
; i
++) {
5302 first_writes
[i
] = -1;
5304 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5306 /* Start looking for registers with non-overlapping usages that can be
5307 * merged together. */
5308 for (i
= 0; i
< this->next_temp
; i
++) {
5309 /* Don't touch unused registers. */
5310 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5312 for (j
= 0; j
< this->next_temp
; j
++) {
5313 /* Don't touch unused registers. */
5314 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5316 /* We can merge the two registers if the first write to j is after or
5317 * in the same instruction as the last read from i. Note that the
5318 * register at index i will always be used earlier or at the same time
5319 * as the register at index j. */
5320 if (first_writes
[i
] <= first_writes
[j
] &&
5321 last_reads
[i
] <= first_writes
[j
]) {
5322 renames
[num_renames
].old_reg
= j
;
5323 renames
[num_renames
].new_reg
= i
;
5326 /* Update the first_writes and last_reads arrays with the new
5327 * values for the merged register index, and mark the newly unused
5328 * register index as such. */
5329 assert(last_reads
[j
] >= last_reads
[i
]);
5330 last_reads
[i
] = last_reads
[j
];
5331 first_writes
[j
] = -1;
5337 rename_temp_registers(num_renames
, renames
);
5338 ralloc_free(renames
);
5339 ralloc_free(last_reads
);
5340 ralloc_free(first_writes
);
5343 /* Reassign indices to temporary registers by reusing unused indices created
5344 * by optimization passes. */
5346 glsl_to_tgsi_visitor::renumber_registers(void)
5350 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5351 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5352 int num_renames
= 0;
5353 for (i
= 0; i
< this->next_temp
; i
++) {
5354 first_reads
[i
] = -1;
5356 get_first_temp_read(first_reads
);
5358 for (i
= 0; i
< this->next_temp
; i
++) {
5359 if (first_reads
[i
] < 0) continue;
5360 if (i
!= new_index
) {
5361 renames
[num_renames
].old_reg
= i
;
5362 renames
[num_renames
].new_reg
= new_index
;
5368 rename_temp_registers(num_renames
, renames
);
5369 this->next_temp
= new_index
;
5370 ralloc_free(renames
);
5371 ralloc_free(first_reads
);
5374 /* ------------------------- TGSI conversion stuff -------------------------- */
5377 * Intermediate state used during shader translation.
5379 struct st_translate
{
5380 struct ureg_program
*ureg
;
5382 unsigned temps_size
;
5383 struct ureg_dst
*temps
;
5385 struct ureg_dst
*arrays
;
5386 unsigned num_temp_arrays
;
5387 struct ureg_src
*constants
;
5389 struct ureg_src
*immediates
;
5391 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5392 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5393 struct ureg_dst address
[3];
5394 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5395 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5396 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5397 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5398 struct ureg_src shared_memory
;
5399 unsigned *array_sizes
;
5400 struct inout_decl
*input_decls
;
5401 unsigned num_input_decls
;
5402 struct inout_decl
*output_decls
;
5403 unsigned num_output_decls
;
5405 const GLuint
*inputMapping
;
5406 const GLuint
*outputMapping
;
5408 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5411 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5413 _mesa_sysval_to_semantic(unsigned sysval
)
5417 case SYSTEM_VALUE_VERTEX_ID
:
5418 return TGSI_SEMANTIC_VERTEXID
;
5419 case SYSTEM_VALUE_INSTANCE_ID
:
5420 return TGSI_SEMANTIC_INSTANCEID
;
5421 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5422 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5423 case SYSTEM_VALUE_BASE_VERTEX
:
5424 return TGSI_SEMANTIC_BASEVERTEX
;
5425 case SYSTEM_VALUE_BASE_INSTANCE
:
5426 return TGSI_SEMANTIC_BASEINSTANCE
;
5427 case SYSTEM_VALUE_DRAW_ID
:
5428 return TGSI_SEMANTIC_DRAWID
;
5430 /* Geometry shader */
5431 case SYSTEM_VALUE_INVOCATION_ID
:
5432 return TGSI_SEMANTIC_INVOCATIONID
;
5434 /* Fragment shader */
5435 case SYSTEM_VALUE_FRAG_COORD
:
5436 return TGSI_SEMANTIC_POSITION
;
5437 case SYSTEM_VALUE_FRONT_FACE
:
5438 return TGSI_SEMANTIC_FACE
;
5439 case SYSTEM_VALUE_SAMPLE_ID
:
5440 return TGSI_SEMANTIC_SAMPLEID
;
5441 case SYSTEM_VALUE_SAMPLE_POS
:
5442 return TGSI_SEMANTIC_SAMPLEPOS
;
5443 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5444 return TGSI_SEMANTIC_SAMPLEMASK
;
5445 case SYSTEM_VALUE_HELPER_INVOCATION
:
5446 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5448 /* Tessellation shader */
5449 case SYSTEM_VALUE_TESS_COORD
:
5450 return TGSI_SEMANTIC_TESSCOORD
;
5451 case SYSTEM_VALUE_VERTICES_IN
:
5452 return TGSI_SEMANTIC_VERTICESIN
;
5453 case SYSTEM_VALUE_PRIMITIVE_ID
:
5454 return TGSI_SEMANTIC_PRIMID
;
5455 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5456 return TGSI_SEMANTIC_TESSOUTER
;
5457 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5458 return TGSI_SEMANTIC_TESSINNER
;
5460 /* Compute shader */
5461 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5462 return TGSI_SEMANTIC_THREAD_ID
;
5463 case SYSTEM_VALUE_WORK_GROUP_ID
:
5464 return TGSI_SEMANTIC_BLOCK_ID
;
5465 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5466 return TGSI_SEMANTIC_GRID_SIZE
;
5467 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5468 return TGSI_SEMANTIC_BLOCK_SIZE
;
5471 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5472 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5473 case SYSTEM_VALUE_VERTEX_CNT
:
5475 assert(!"Unexpected SYSTEM_VALUE_ enum");
5476 return TGSI_SEMANTIC_COUNT
;
5481 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5483 static struct ureg_src
5484 emit_immediate(struct st_translate
*t
,
5485 gl_constant_value values
[4],
5488 struct ureg_program
*ureg
= t
->ureg
;
5493 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5495 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5497 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5498 case GL_UNSIGNED_INT64_ARB
:
5499 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5501 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5502 case GL_UNSIGNED_INT
:
5504 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5506 assert(!"should not get here - type must be float, int, uint, or bool");
5507 return ureg_src_undef();
5512 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5514 static struct ureg_dst
5515 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5521 case PROGRAM_UNDEFINED
:
5522 return ureg_dst_undef();
5524 case PROGRAM_TEMPORARY
:
5525 /* Allocate space for temporaries on demand. */
5526 if (index
>= t
->temps_size
) {
5527 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5529 t
->temps
= (struct ureg_dst
*)
5531 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5533 return ureg_dst_undef();
5535 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5536 t
->temps_size
+= inc
;
5539 if (ureg_dst_is_undef(t
->temps
[index
]))
5540 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5542 return t
->temps
[index
];
5545 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5546 array
= array_id
- 1;
5548 if (ureg_dst_is_undef(t
->arrays
[array
]))
5549 t
->arrays
[array
] = ureg_DECL_array_temporary(
5550 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5552 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5554 case PROGRAM_OUTPUT
:
5556 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5557 assert(index
< 2 * FRAG_RESULT_MAX
);
5558 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5559 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5560 assert(index
< VARYING_SLOT_TESS_MAX
);
5562 assert(index
< VARYING_SLOT_MAX
);
5564 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5565 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5566 return t
->outputs
[t
->outputMapping
[index
]];
5569 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5570 unsigned mesa_index
= decl
->mesa_index
;
5571 int slot
= t
->outputMapping
[mesa_index
];
5573 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5575 struct ureg_dst dst
= t
->outputs
[slot
];
5576 dst
.ArrayID
= array_id
;
5577 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5580 case PROGRAM_ADDRESS
:
5581 return t
->address
[index
];
5584 assert(!"unknown dst register file");
5585 return ureg_dst_undef();
5590 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5592 static struct ureg_src
5593 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5595 int index
= reg
->index
;
5596 int double_reg2
= reg
->double_reg2
? 1 : 0;
5599 case PROGRAM_UNDEFINED
:
5600 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5602 case PROGRAM_TEMPORARY
:
5604 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5606 case PROGRAM_OUTPUT
: {
5607 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5608 assert(dst
.WriteMask
!= 0);
5609 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5610 return ureg_swizzle(ureg_src(dst
),
5614 MIN2(shift
+ 3, 3));
5617 case PROGRAM_UNIFORM
:
5618 assert(reg
->index
>= 0);
5619 return reg
->index
< t
->num_constants
?
5620 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5621 case PROGRAM_STATE_VAR
:
5622 case PROGRAM_CONSTANT
: /* ie, immediate */
5623 if (reg
->has_index2
)
5624 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5626 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5627 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5629 case PROGRAM_IMMEDIATE
:
5630 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5631 return t
->immediates
[reg
->index
];
5634 /* GLSL inputs are 64-bit containers, so we have to
5635 * map back to the original index and add the offset after
5637 index
-= double_reg2
;
5638 if (!reg
->array_id
) {
5639 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5640 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5641 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5644 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5645 unsigned mesa_index
= decl
->mesa_index
;
5646 int slot
= t
->inputMapping
[mesa_index
];
5648 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5650 struct ureg_src src
= t
->inputs
[slot
];
5651 src
.ArrayID
= reg
->array_id
;
5652 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5655 case PROGRAM_ADDRESS
:
5656 return ureg_src(t
->address
[reg
->index
]);
5658 case PROGRAM_SYSTEM_VALUE
:
5659 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5660 return t
->systemValues
[reg
->index
];
5663 assert(!"unknown src register file");
5664 return ureg_src_undef();
5669 * Create a TGSI ureg_dst register from an st_dst_reg.
5671 static struct ureg_dst
5672 translate_dst(struct st_translate
*t
,
5673 const st_dst_reg
*dst_reg
,
5676 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5679 if (dst
.File
== TGSI_FILE_NULL
)
5682 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5685 dst
= ureg_saturate(dst
);
5687 if (dst_reg
->reladdr
!= NULL
) {
5688 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5689 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5692 if (dst_reg
->has_index2
) {
5693 if (dst_reg
->reladdr2
)
5694 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5697 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5704 * Create a TGSI ureg_src register from an st_src_reg.
5706 static struct ureg_src
5707 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5709 struct ureg_src src
= src_register(t
, src_reg
);
5711 if (src_reg
->has_index2
) {
5712 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5713 * and UBO constant buffers (buffer, position).
5715 if (src_reg
->reladdr2
)
5716 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5719 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5722 src
= ureg_swizzle(src
,
5723 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5724 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5725 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5726 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5729 src
= ureg_abs(src
);
5731 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5732 src
= ureg_negate(src
);
5734 if (src_reg
->reladdr
!= NULL
) {
5735 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5736 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5742 static struct tgsi_texture_offset
5743 translate_tex_offset(struct st_translate
*t
,
5744 const st_src_reg
*in_offset
)
5746 struct tgsi_texture_offset offset
;
5747 struct ureg_src src
= translate_src(t
, in_offset
);
5749 offset
.File
= src
.File
;
5750 offset
.Index
= src
.Index
;
5751 offset
.SwizzleX
= src
.SwizzleX
;
5752 offset
.SwizzleY
= src
.SwizzleY
;
5753 offset
.SwizzleZ
= src
.SwizzleZ
;
5756 assert(!src
.Indirect
);
5757 assert(!src
.DimIndirect
);
5758 assert(!src
.Dimension
);
5759 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5760 assert(!src
.Negate
);
5766 compile_tgsi_instruction(struct st_translate
*t
,
5767 const glsl_to_tgsi_instruction
*inst
)
5769 struct ureg_program
*ureg
= t
->ureg
;
5771 struct ureg_dst dst
[2];
5772 struct ureg_src src
[4];
5773 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5777 unsigned tex_target
= 0;
5779 num_dst
= num_inst_dst_regs(inst
);
5780 num_src
= num_inst_src_regs(inst
);
5782 for (i
= 0; i
< num_dst
; i
++)
5783 dst
[i
] = translate_dst(t
,
5787 for (i
= 0; i
< num_src
; i
++)
5788 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5791 case TGSI_OPCODE_BGNLOOP
:
5792 case TGSI_OPCODE_ELSE
:
5793 case TGSI_OPCODE_ENDLOOP
:
5794 case TGSI_OPCODE_IF
:
5795 case TGSI_OPCODE_UIF
:
5796 assert(num_dst
== 0);
5797 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
);
5800 case TGSI_OPCODE_TEX
:
5801 case TGSI_OPCODE_TXB
:
5802 case TGSI_OPCODE_TXD
:
5803 case TGSI_OPCODE_TXL
:
5804 case TGSI_OPCODE_TXP
:
5805 case TGSI_OPCODE_TXQ
:
5806 case TGSI_OPCODE_TXQS
:
5807 case TGSI_OPCODE_TXF
:
5808 case TGSI_OPCODE_TEX2
:
5809 case TGSI_OPCODE_TXB2
:
5810 case TGSI_OPCODE_TXL2
:
5811 case TGSI_OPCODE_TG4
:
5812 case TGSI_OPCODE_LODQ
:
5813 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5814 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5815 if (inst
->resource
.reladdr
)
5817 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5819 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5820 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5822 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5828 texoffsets
, inst
->tex_offset_num_offset
,
5832 case TGSI_OPCODE_RESQ
:
5833 case TGSI_OPCODE_LOAD
:
5834 case TGSI_OPCODE_ATOMUADD
:
5835 case TGSI_OPCODE_ATOMXCHG
:
5836 case TGSI_OPCODE_ATOMCAS
:
5837 case TGSI_OPCODE_ATOMAND
:
5838 case TGSI_OPCODE_ATOMOR
:
5839 case TGSI_OPCODE_ATOMXOR
:
5840 case TGSI_OPCODE_ATOMUMIN
:
5841 case TGSI_OPCODE_ATOMUMAX
:
5842 case TGSI_OPCODE_ATOMIMIN
:
5843 case TGSI_OPCODE_ATOMIMAX
:
5844 for (i
= num_src
- 1; i
>= 0; i
--)
5845 src
[i
+ 1] = src
[i
];
5847 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5848 src
[0] = t
->shared_memory
;
5849 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5850 src
[0] = t
->buffers
[inst
->resource
.index
];
5852 src
[0] = t
->images
[inst
->resource
.index
];
5853 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5855 if (inst
->resource
.reladdr
)
5856 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5857 assert(src
[0].File
!= TGSI_FILE_NULL
);
5858 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5859 inst
->buffer_access
,
5860 tex_target
, inst
->image_format
);
5863 case TGSI_OPCODE_STORE
:
5864 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5865 dst
[0] = ureg_dst(t
->shared_memory
);
5866 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5867 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5869 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5870 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5872 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5873 if (inst
->resource
.reladdr
)
5874 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5875 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5876 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5877 inst
->buffer_access
,
5878 tex_target
, inst
->image_format
);
5881 case TGSI_OPCODE_SCS
:
5882 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5883 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5896 * Emit the TGSI instructions for inverting and adjusting WPOS.
5897 * This code is unavoidable because it also depends on whether
5898 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5901 emit_wpos_adjustment(struct gl_context
*ctx
,
5902 struct st_translate
*t
,
5903 int wpos_transform_const
,
5905 GLfloat adjX
, GLfloat adjY
[2])
5907 struct ureg_program
*ureg
= t
->ureg
;
5909 assert(wpos_transform_const
>= 0);
5911 /* Fragment program uses fragment position input.
5912 * Need to replace instances of INPUT[WPOS] with temp T
5913 * where T = INPUT[WPOS] is inverted by Y.
5915 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5916 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5917 struct ureg_src
*wpos
=
5918 ctx
->Const
.GLSLFragCoordIsSysVal
?
5919 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5920 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5921 struct ureg_src wpos_input
= *wpos
;
5923 /* First, apply the coordinate shift: */
5924 if (adjX
|| adjY
[0] || adjY
[1]) {
5925 if (adjY
[0] != adjY
[1]) {
5926 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5927 * depending on whether inversion is actually going to be applied
5928 * or not, which is determined by testing against the inversion
5929 * state variable used below, which will be either +1 or -1.
5931 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5933 ureg_CMP(ureg
, adj_temp
,
5934 ureg_scalar(wpostrans
, invert
? 2 : 0),
5935 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5936 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5937 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5939 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5940 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5942 wpos_input
= ureg_src(wpos_temp
);
5944 /* MOV wpos_temp, input[wpos]
5946 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5949 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5950 * inversion/identity, or the other way around if we're drawing to an FBO.
5953 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5956 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5958 ureg_scalar(wpostrans
, 0),
5959 ureg_scalar(wpostrans
, 1));
5961 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5964 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5966 ureg_scalar(wpostrans
, 2),
5967 ureg_scalar(wpostrans
, 3));
5970 /* Use wpos_temp as position input from here on:
5972 *wpos
= ureg_src(wpos_temp
);
5977 * Emit fragment position/ooordinate code.
5980 emit_wpos(struct st_context
*st
,
5981 struct st_translate
*t
,
5982 const struct gl_program
*program
,
5983 struct ureg_program
*ureg
,
5984 int wpos_transform_const
)
5986 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5987 GLfloat adjX
= 0.0f
;
5988 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5989 boolean invert
= FALSE
;
5991 /* Query the pixel center conventions supported by the pipe driver and set
5992 * adjX, adjY to help out if it cannot handle the requested one internally.
5994 * The bias of the y-coordinate depends on whether y-inversion takes place
5995 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5996 * drawing to an FBO (causes additional inversion), and whether the pipe
5997 * driver origin and the requested origin differ (the latter condition is
5998 * stored in the 'invert' variable).
6000 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6002 * center shift only:
6007 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6008 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6009 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6010 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6012 * inversion and center shift:
6013 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6014 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6015 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6016 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6018 if (program
->OriginUpperLeft
) {
6019 /* Fragment shader wants origin in upper-left */
6020 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6021 /* the driver supports upper-left origin */
6023 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6024 /* the driver supports lower-left origin, need to invert Y */
6025 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6026 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6033 /* Fragment shader wants origin in lower-left */
6034 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6035 /* the driver supports lower-left origin */
6036 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6037 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6038 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6039 /* the driver supports upper-left origin, need to invert Y */
6045 if (program
->PixelCenterInteger
) {
6046 /* Fragment shader wants pixel center integer */
6047 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6048 /* the driver supports pixel center integer */
6050 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6051 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6053 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6054 /* the driver supports pixel center half integer, need to bias X,Y */
6063 /* Fragment shader wants pixel center half integer */
6064 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6065 /* the driver supports pixel center half integer */
6067 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6068 /* the driver supports pixel center integer, need to bias X,Y */
6069 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6070 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6071 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6077 /* we invert after adjustment so that we avoid the MOV to temporary,
6078 * and reuse the adjustment ADD instead */
6079 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6083 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6084 * TGSI uses +1 for front, -1 for back.
6085 * This function converts the TGSI value to the GL value. Simply clamping/
6086 * saturating the value to [0,1] does the job.
6089 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6091 struct ureg_program
*ureg
= t
->ureg
;
6092 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6093 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6095 if (ctx
->Const
.NativeIntegers
) {
6096 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6099 /* MOV_SAT face_temp, input[face] */
6100 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6103 /* Use face_temp as face input from here on: */
6104 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6108 emit_compute_block_size(const struct gl_program
*prog
,
6109 struct ureg_program
*ureg
) {
6110 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6111 prog
->info
.cs
.local_size
[0]);
6112 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6113 prog
->info
.cs
.local_size
[1]);
6114 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6115 prog
->info
.cs
.local_size
[2]);
6118 struct sort_inout_decls
{
6119 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6120 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6123 const GLuint
*mapping
;
6126 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6128 * This is for the benefit of older drivers which are broken when the
6129 * declarations aren't sorted in this way.
6132 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6134 const GLuint mapping
[])
6136 sort_inout_decls sorter
;
6137 sorter
.mapping
= mapping
;
6138 std::sort(decls
, decls
+ count
, sorter
);
6142 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6144 switch (glsl_qual
) {
6145 case INTERP_MODE_NONE
:
6146 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6147 return TGSI_INTERPOLATE_COLOR
;
6148 return TGSI_INTERPOLATE_PERSPECTIVE
;
6149 case INTERP_MODE_SMOOTH
:
6150 return TGSI_INTERPOLATE_PERSPECTIVE
;
6151 case INTERP_MODE_FLAT
:
6152 return TGSI_INTERPOLATE_CONSTANT
;
6153 case INTERP_MODE_NOPERSPECTIVE
:
6154 return TGSI_INTERPOLATE_LINEAR
;
6156 assert(0 && "unexpected interp mode in st_translate_interp()");
6157 return TGSI_INTERPOLATE_PERSPECTIVE
;
6162 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6163 * \param program the program to translate
6164 * \param numInputs number of input registers used
6165 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6167 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6168 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6170 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6171 * \param numOutputs number of output registers used
6172 * \param outputMapping maps Mesa fragment program outputs to TGSI
6174 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6175 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6178 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6180 extern "C" enum pipe_error
6181 st_translate_program(
6182 struct gl_context
*ctx
,
6184 struct ureg_program
*ureg
,
6185 glsl_to_tgsi_visitor
*program
,
6186 const struct gl_program
*proginfo
,
6188 const GLuint inputMapping
[],
6189 const GLuint inputSlotToAttr
[],
6190 const ubyte inputSemanticName
[],
6191 const ubyte inputSemanticIndex
[],
6192 const GLuint interpMode
[],
6194 const GLuint outputMapping
[],
6195 const GLuint outputSlotToAttr
[],
6196 const ubyte outputSemanticName
[],
6197 const ubyte outputSemanticIndex
[])
6199 struct st_translate
*t
;
6201 struct gl_program_constants
*frag_const
=
6202 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6203 enum pipe_error ret
= PIPE_OK
;
6205 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6206 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6208 t
= CALLOC_STRUCT(st_translate
);
6210 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6214 t
->procType
= procType
;
6215 t
->inputMapping
= inputMapping
;
6216 t
->outputMapping
= outputMapping
;
6218 t
->num_temp_arrays
= program
->next_array
;
6219 if (t
->num_temp_arrays
)
6220 t
->arrays
= (struct ureg_dst
*)
6221 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6224 * Declare input attributes.
6227 case PIPE_SHADER_FRAGMENT
:
6228 case PIPE_SHADER_GEOMETRY
:
6229 case PIPE_SHADER_TESS_EVAL
:
6230 case PIPE_SHADER_TESS_CTRL
:
6231 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6233 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6234 struct inout_decl
*decl
= &program
->inputs
[i
];
6235 unsigned slot
= inputMapping
[decl
->mesa_index
];
6236 struct ureg_src src
;
6237 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6239 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6240 if (tgsi_usage_mask
== 1)
6241 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6242 else if (tgsi_usage_mask
== 2)
6243 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6245 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6248 unsigned interp_mode
= 0;
6249 unsigned interp_location
= 0;
6250 if (procType
== PIPE_SHADER_FRAGMENT
) {
6252 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6254 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6256 interp_location
= decl
->interp_loc
;
6259 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6260 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6261 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6262 decl
->array_id
, decl
->size
);
6264 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6265 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6266 /* The ArrayID is set up in dst_register */
6267 t
->inputs
[slot
+ j
] = src
;
6268 t
->inputs
[slot
+ j
].ArrayID
= 0;
6269 t
->inputs
[slot
+ j
].Index
+= j
;
6274 case PIPE_SHADER_VERTEX
:
6275 for (i
= 0; i
< numInputs
; i
++) {
6276 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6279 case PIPE_SHADER_COMPUTE
:
6286 * Declare output attributes.
6289 case PIPE_SHADER_FRAGMENT
:
6290 case PIPE_SHADER_COMPUTE
:
6292 case PIPE_SHADER_GEOMETRY
:
6293 case PIPE_SHADER_TESS_EVAL
:
6294 case PIPE_SHADER_TESS_CTRL
:
6295 case PIPE_SHADER_VERTEX
:
6296 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6298 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6299 struct inout_decl
*decl
= &program
->outputs
[i
];
6300 unsigned slot
= outputMapping
[decl
->mesa_index
];
6301 struct ureg_dst dst
;
6302 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6304 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6305 if (tgsi_usage_mask
== 1)
6306 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6307 else if (tgsi_usage_mask
== 2)
6308 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6310 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6313 dst
= ureg_DECL_output_layout(ureg
,
6314 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6315 decl
->gs_out_streams
,
6316 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6318 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6319 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6320 /* The ArrayID is set up in dst_register */
6321 t
->outputs
[slot
+ j
] = dst
;
6322 t
->outputs
[slot
+ j
].ArrayID
= 0;
6323 t
->outputs
[slot
+ j
].Index
+= j
;
6332 if (procType
== PIPE_SHADER_FRAGMENT
) {
6333 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
)
6334 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6336 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6337 /* Must do this after setting up t->inputs. */
6338 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6339 program
->wpos_transform_const
);
6342 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6343 emit_face_var(ctx
, t
);
6345 for (i
= 0; i
< numOutputs
; i
++) {
6346 switch (outputSemanticName
[i
]) {
6347 case TGSI_SEMANTIC_POSITION
:
6348 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6349 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6350 outputSemanticIndex
[i
]);
6351 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6353 case TGSI_SEMANTIC_STENCIL
:
6354 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6355 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6356 outputSemanticIndex
[i
]);
6357 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6359 case TGSI_SEMANTIC_COLOR
:
6360 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6361 TGSI_SEMANTIC_COLOR
,
6362 outputSemanticIndex
[i
]);
6364 case TGSI_SEMANTIC_SAMPLEMASK
:
6365 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6366 TGSI_SEMANTIC_SAMPLEMASK
,
6367 outputSemanticIndex
[i
]);
6368 /* TODO: If we ever support more than 32 samples, this will have
6369 * to become an array.
6371 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6374 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6375 ret
= PIPE_ERROR_BAD_INPUT
;
6380 else if (procType
== PIPE_SHADER_VERTEX
) {
6381 for (i
= 0; i
< numOutputs
; i
++) {
6382 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6383 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6385 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6386 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6387 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6392 if (procType
== PIPE_SHADER_COMPUTE
) {
6393 emit_compute_block_size(proginfo
, ureg
);
6396 /* Declare address register.
6398 if (program
->num_address_regs
> 0) {
6399 assert(program
->num_address_regs
<= 3);
6400 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6401 t
->address
[i
] = ureg_DECL_address(ureg
);
6404 /* Declare misc input registers
6407 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6409 for (i
= 0; sysInputs
; i
++) {
6410 if (sysInputs
& (1 << i
)) {
6411 unsigned semName
= _mesa_sysval_to_semantic(i
);
6413 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6415 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6416 semName
== TGSI_SEMANTIC_VERTEXID
) {
6417 /* From Gallium perspective, these system values are always
6418 * integer, and require native integer support. However, if
6419 * native integer is supported on the vertex stage but not the
6420 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6421 * assumes these system values are floats. To resolve the
6422 * inconsistency, we insert a U2F.
6424 struct st_context
*st
= st_context(ctx
);
6425 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6426 assert(procType
== PIPE_SHADER_VERTEX
);
6427 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6429 if (!ctx
->Const
.NativeIntegers
) {
6430 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6431 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6432 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6436 if (procType
== PIPE_SHADER_FRAGMENT
&&
6437 semName
== TGSI_SEMANTIC_POSITION
)
6438 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6439 program
->wpos_transform_const
);
6441 sysInputs
&= ~(1 << i
);
6446 t
->array_sizes
= program
->array_sizes
;
6447 t
->input_decls
= program
->inputs
;
6448 t
->num_input_decls
= program
->num_inputs
;
6449 t
->output_decls
= program
->outputs
;
6450 t
->num_output_decls
= program
->num_outputs
;
6452 /* Emit constants and uniforms. TGSI uses a single index space for these,
6453 * so we put all the translated regs in t->constants.
6455 if (proginfo
->Parameters
) {
6456 t
->constants
= (struct ureg_src
*)
6457 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6458 if (t
->constants
== NULL
) {
6459 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6462 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6464 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6465 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6466 case PROGRAM_STATE_VAR
:
6467 case PROGRAM_UNIFORM
:
6468 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6471 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6472 * addressing of the const buffer.
6473 * FIXME: Be smarter and recognize param arrays:
6474 * indirect addressing is only valid within the referenced
6477 case PROGRAM_CONSTANT
:
6478 if (program
->indirect_addr_consts
)
6479 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6481 t
->constants
[i
] = emit_immediate(t
,
6482 proginfo
->Parameters
->ParameterValues
[i
],
6483 proginfo
->Parameters
->Parameters
[i
].DataType
,
6492 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6493 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6494 unsigned num_const_vecs
= (size
+ 15) / 16;
6495 unsigned first
, last
;
6496 assert(num_const_vecs
> 0);
6498 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6499 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6502 /* Emit immediate values.
6504 t
->immediates
= (struct ureg_src
*)
6505 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6506 if (t
->immediates
== NULL
) {
6507 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6510 t
->num_immediates
= program
->num_immediates
;
6513 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6514 assert(i
< program
->num_immediates
);
6515 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6517 assert(i
== program
->num_immediates
);
6519 /* texture samplers */
6520 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6521 if (program
->samplers_used
& (1u << i
)) {
6524 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6526 switch (program
->sampler_types
[i
]) {
6528 type
= TGSI_RETURN_TYPE_SINT
;
6530 case GLSL_TYPE_UINT
:
6531 type
= TGSI_RETURN_TYPE_UINT
;
6533 case GLSL_TYPE_FLOAT
:
6534 type
= TGSI_RETURN_TYPE_FLOAT
;
6537 unreachable("not reached");
6540 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6541 type
, type
, type
, type
);
6545 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6546 if (program
->buffers_used
& (1 << i
)) {
6547 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6551 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6553 if (program
->buffers_used
& (1 << i
)) {
6554 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6558 if (program
->use_shared_memory
)
6559 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6561 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6562 if (program
->images_used
& (1 << i
)) {
6563 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6564 program
->image_targets
[i
],
6565 program
->image_formats
[i
],
6570 /* Emit each instruction in turn:
6572 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6573 compile_tgsi_instruction(t
, inst
);
6575 /* Set the next shader stage hint for VS and TES. */
6577 case PIPE_SHADER_VERTEX
:
6578 case PIPE_SHADER_TESS_EVAL
:
6579 if (program
->shader_program
->SeparateShader
)
6582 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6583 if (program
->shader_program
->_LinkedShaders
[i
]) {
6587 case MESA_SHADER_TESS_CTRL
:
6588 next
= PIPE_SHADER_TESS_CTRL
;
6590 case MESA_SHADER_TESS_EVAL
:
6591 next
= PIPE_SHADER_TESS_EVAL
;
6593 case MESA_SHADER_GEOMETRY
:
6594 next
= PIPE_SHADER_GEOMETRY
;
6596 case MESA_SHADER_FRAGMENT
:
6597 next
= PIPE_SHADER_FRAGMENT
;
6604 ureg_set_next_shader_processor(ureg
, next
);
6616 t
->num_constants
= 0;
6617 free(t
->immediates
);
6618 t
->num_immediates
= 0;
6624 /* ----------------------------- End TGSI code ------------------------------ */
6628 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6629 * generating Mesa IR.
6631 static struct gl_program
*
6632 get_mesa_program_tgsi(struct gl_context
*ctx
,
6633 struct gl_shader_program
*shader_program
,
6634 struct gl_linked_shader
*shader
)
6636 glsl_to_tgsi_visitor
* v
;
6637 struct gl_program
*prog
;
6638 struct gl_shader_compiler_options
*options
=
6639 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6640 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6641 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6643 validate_ir_tree(shader
->ir
);
6645 prog
= shader
->Program
;
6647 prog
->Parameters
= _mesa_new_parameter_list();
6648 v
= new glsl_to_tgsi_visitor();
6651 v
->shader_program
= shader_program
;
6653 v
->options
= options
;
6654 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6655 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6657 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6658 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6659 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6660 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6662 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6665 /* Remove reads from output registers. */
6666 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6667 lower_output_reads(shader
->Stage
, shader
->ir
);
6669 /* Emit intermediate IR for main(). */
6670 visit_exec_list(shader
->ir
, v
);
6673 /* Print out some information (for debugging purposes) used by the
6674 * optimization passes. */
6677 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6678 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6679 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6680 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6682 for (i
= 0; i
< v
->next_temp
; i
++) {
6683 first_writes
[i
] = -1;
6684 first_reads
[i
] = -1;
6685 last_writes
[i
] = -1;
6688 v
->get_first_temp_read(first_reads
);
6689 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6690 v
->get_last_temp_write(last_writes
);
6691 for (i
= 0; i
< v
->next_temp
; i
++)
6692 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6696 ralloc_free(first_writes
);
6697 ralloc_free(first_reads
);
6698 ralloc_free(last_writes
);
6699 ralloc_free(last_reads
);
6703 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6706 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6707 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6708 v
->copy_propagate();
6710 while (v
->eliminate_dead_code());
6712 v
->merge_two_dsts();
6713 v
->merge_registers();
6714 v
->renumber_registers();
6716 /* Write the END instruction. */
6717 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6719 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6721 _mesa_log("GLSL IR for linked %s program %d:\n",
6722 _mesa_shader_stage_to_string(shader
->Stage
),
6723 shader_program
->Name
);
6724 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6728 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6729 _mesa_copy_linked_program_data(shader_program
, shader
);
6730 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6731 &prog
->info
.inputs_read
,
6732 prog
->info
.double_inputs_read
,
6733 &prog
->info
.patch_inputs_read
);
6734 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6735 &prog
->info
.outputs_written
, 0ULL,
6736 &prog
->info
.patch_outputs_written
);
6737 count_resources(v
, prog
);
6739 /* The GLSL IR won't be needed anymore. */
6740 ralloc_free(shader
->ir
);
6743 /* This must be done before the uniform storage is associated. */
6744 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6745 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6746 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6747 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6748 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6751 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6752 wposTransformState
);
6755 /* Avoid reallocation of the program parameter list, because the uniform
6756 * storage is only associated with the original parameter list.
6757 * This should be enough for Bitmap and DrawPixels constants.
6759 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6761 /* This has to be done last. Any operation the can cause
6762 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6763 * program constant) has to happen before creating this linkage.
6765 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6766 if (!shader_program
->data
->LinkStatus
) {
6767 free_glsl_to_tgsi_visitor(v
);
6768 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6772 struct st_vertex_program
*stvp
;
6773 struct st_fragment_program
*stfp
;
6774 struct st_geometry_program
*stgp
;
6775 struct st_tessctrl_program
*sttcp
;
6776 struct st_tesseval_program
*sttep
;
6777 struct st_compute_program
*stcp
;
6779 switch (shader
->Stage
) {
6780 case MESA_SHADER_VERTEX
:
6781 stvp
= (struct st_vertex_program
*)prog
;
6782 stvp
->glsl_to_tgsi
= v
;
6784 case MESA_SHADER_FRAGMENT
:
6785 stfp
= (struct st_fragment_program
*)prog
;
6786 stfp
->glsl_to_tgsi
= v
;
6788 case MESA_SHADER_GEOMETRY
:
6789 stgp
= (struct st_geometry_program
*)prog
;
6790 stgp
->glsl_to_tgsi
= v
;
6792 case MESA_SHADER_TESS_CTRL
:
6793 sttcp
= (struct st_tessctrl_program
*)prog
;
6794 sttcp
->glsl_to_tgsi
= v
;
6796 case MESA_SHADER_TESS_EVAL
:
6797 sttep
= (struct st_tesseval_program
*)prog
;
6798 sttep
->glsl_to_tgsi
= v
;
6800 case MESA_SHADER_COMPUTE
:
6801 stcp
= (struct st_compute_program
*)prog
;
6802 stcp
->glsl_to_tgsi
= v
;
6805 assert(!"should not be reached");
6813 set_affected_state_flags(uint64_t *states
,
6814 struct gl_program
*prog
,
6815 uint64_t new_constants
,
6816 uint64_t new_sampler_views
,
6817 uint64_t new_samplers
,
6818 uint64_t new_images
,
6821 uint64_t new_atomics
)
6823 if (prog
->Parameters
->NumParameters
)
6824 *states
|= new_constants
;
6826 if (prog
->info
.num_textures
)
6827 *states
|= new_sampler_views
| new_samplers
;
6829 if (prog
->info
.num_images
)
6830 *states
|= new_images
;
6832 if (prog
->info
.num_ubos
)
6833 *states
|= new_ubos
;
6835 if (prog
->info
.num_ssbos
)
6836 *states
|= new_ssbos
;
6838 if (prog
->info
.num_abos
)
6839 *states
|= new_atomics
;
6843 set_prog_affected_state_flags(struct gl_program
*prog
)
6847 /* This determines which states will be updated when the shader is bound.
6849 switch (prog
->info
.stage
) {
6850 case MESA_SHADER_VERTEX
:
6851 states
= &((struct st_vertex_program
*)prog
)->affected_states
;
6853 *states
= ST_NEW_VS_STATE
|
6855 ST_NEW_VERTEX_ARRAYS
;
6857 set_affected_state_flags(states
, prog
,
6858 ST_NEW_VS_CONSTANTS
,
6859 ST_NEW_VS_SAMPLER_VIEWS
,
6860 ST_NEW_RENDER_SAMPLERS
,
6867 case MESA_SHADER_TESS_CTRL
:
6868 states
= &((struct st_tessctrl_program
*)prog
)->affected_states
;
6870 *states
= ST_NEW_TCS_STATE
;
6872 set_affected_state_flags(states
, prog
,
6873 ST_NEW_TCS_CONSTANTS
,
6874 ST_NEW_TCS_SAMPLER_VIEWS
,
6875 ST_NEW_RENDER_SAMPLERS
,
6879 ST_NEW_TCS_ATOMICS
);
6882 case MESA_SHADER_TESS_EVAL
:
6883 states
= &((struct st_tesseval_program
*)prog
)->affected_states
;
6885 *states
= ST_NEW_TES_STATE
|
6888 set_affected_state_flags(states
, prog
,
6889 ST_NEW_TES_CONSTANTS
,
6890 ST_NEW_TES_SAMPLER_VIEWS
,
6891 ST_NEW_RENDER_SAMPLERS
,
6895 ST_NEW_TES_ATOMICS
);
6898 case MESA_SHADER_GEOMETRY
:
6899 states
= &((struct st_geometry_program
*)prog
)->affected_states
;
6901 *states
= ST_NEW_GS_STATE
|
6904 set_affected_state_flags(states
, prog
,
6905 ST_NEW_GS_CONSTANTS
,
6906 ST_NEW_GS_SAMPLER_VIEWS
,
6907 ST_NEW_RENDER_SAMPLERS
,
6914 case MESA_SHADER_FRAGMENT
:
6915 states
= &((struct st_fragment_program
*)prog
)->affected_states
;
6917 /* gl_FragCoord and glDrawPixels always use constants. */
6918 *states
= ST_NEW_FS_STATE
|
6919 ST_NEW_SAMPLE_SHADING
|
6920 ST_NEW_FS_CONSTANTS
;
6922 set_affected_state_flags(states
, prog
,
6923 ST_NEW_FS_CONSTANTS
,
6924 ST_NEW_FS_SAMPLER_VIEWS
,
6925 ST_NEW_RENDER_SAMPLERS
,
6932 case MESA_SHADER_COMPUTE
:
6933 states
= &((struct st_compute_program
*)prog
)->affected_states
;
6935 *states
= ST_NEW_CS_STATE
;
6937 set_affected_state_flags(states
, prog
,
6938 ST_NEW_CS_CONSTANTS
,
6939 ST_NEW_CS_SAMPLER_VIEWS
,
6948 unreachable("unhandled shader stage");
6952 /* See if there are unsupported control flow statements. */
6953 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6955 const struct gl_shader_compiler_options
*options
;
6957 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6963 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6965 /* Other functions are skipped (same as glsl_to_tgsi). */
6966 if (strcmp(ir
->name
, "main") == 0)
6967 return visit_continue
;
6969 return visit_continue_with_parent
;
6972 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6974 if (!ir
->callee
->is_intrinsic()) {
6975 unsupported
= true; /* it's a function call */
6978 return visit_continue
;
6981 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6983 if (options
->EmitNoMainReturn
) {
6987 return visit_continue
;
6994 has_unsupported_control_flow(exec_list
*ir
,
6995 const struct gl_shader_compiler_options
*options
)
6997 ir_control_flow_info_visitor
visitor(options
);
6998 visit_list_elements(&visitor
, ir
);
6999 return visitor
.unsupported
;
7006 * Called via ctx->Driver.LinkShader()
7007 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7008 * with code lowering and other optimizations.
7011 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7013 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7014 assert(prog
->data
->LinkStatus
);
7016 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7017 if (prog
->_LinkedShaders
[i
] == NULL
)
7020 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7021 exec_list
*ir
= shader
->ir
;
7022 gl_shader_stage stage
= shader
->Stage
;
7023 const struct gl_shader_compiler_options
*options
=
7024 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7025 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
7026 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
7027 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
7028 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7029 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
7030 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7031 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7033 /* If there are forms of indirect addressing that the driver
7034 * cannot handle, perform the lowering pass.
7036 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
7037 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
7038 lower_variable_index_to_cond_assign(stage
, ir
,
7039 options
->EmitNoIndirectInput
,
7040 options
->EmitNoIndirectOutput
,
7041 options
->EmitNoIndirectTemp
,
7042 options
->EmitNoIndirectUniform
);
7045 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
7046 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
7048 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7049 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7050 LOWER_UNPACK_SNORM_2x16
|
7051 LOWER_PACK_UNORM_2x16
|
7052 LOWER_UNPACK_UNORM_2x16
|
7053 LOWER_PACK_SNORM_4x8
|
7054 LOWER_UNPACK_SNORM_4x8
|
7055 LOWER_UNPACK_UNORM_4x8
|
7056 LOWER_PACK_UNORM_4x8
;
7058 if (ctx
->Extensions
.ARB_gpu_shader5
)
7059 lower_inst
|= LOWER_PACK_USE_BFI
|
7061 if (!ctx
->st
->has_half_float_packing
)
7062 lower_inst
|= LOWER_PACK_HALF_2x16
|
7063 LOWER_UNPACK_HALF_2x16
;
7065 lower_packing_builtins(ir
, lower_inst
);
7068 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7069 lower_offset_arrays(ir
);
7070 do_mat_op_to_vec(ir
);
7072 if (stage
== MESA_SHADER_FRAGMENT
)
7073 lower_blend_equation_advanced(shader
);
7075 lower_instructions(ir
,
7081 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7084 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7085 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7086 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7087 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7088 /* Assume that if ARB_gpu_shader5 is not supported
7089 * then all of the extended integer functions need
7090 * lowering. It may be necessary to add some caps
7091 * for individual instructions.
7093 (!ctx
->Extensions
.ARB_gpu_shader5
7094 ? BIT_COUNT_TO_MATH
|
7098 FIND_LSB_TO_FLOAT_CAST
|
7099 FIND_MSB_TO_FLOAT_CAST
|
7103 do_vec_index_to_cond_assign(ir
);
7104 lower_vector_insert(ir
, true);
7105 lower_quadop_vector(ir
, false);
7107 if (options
->MaxIfDepth
== 0) {
7111 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7112 /* Do it once and repeat only if there's unsupported control flow. */
7114 do_common_optimization(ir
, true, true, options
,
7115 ctx
->Const
.NativeIntegers
);
7116 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7117 options
->MaxIfDepth
, if_threshold
);
7118 } while (has_unsupported_control_flow(ir
, options
));
7120 /* Repeat it until it stops making changes. */
7123 progress
= do_common_optimization(ir
, true, true, options
,
7124 ctx
->Const
.NativeIntegers
);
7125 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7126 options
->MaxIfDepth
, if_threshold
);
7130 validate_ir_tree(ir
);
7133 build_program_resource_list(ctx
, prog
);
7135 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7136 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7140 enum pipe_shader_type ptarget
=
7141 st_shader_stage_to_ptarget(shader
->Stage
);
7142 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
7143 pscreen
->get_shader_param(pscreen
, ptarget
,
7144 PIPE_SHADER_CAP_PREFERRED_IR
);
7146 struct gl_program
*linked_prog
= NULL
;
7147 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
7148 /* TODO only for GLSL VS/FS for now: */
7149 switch (shader
->Stage
) {
7150 case MESA_SHADER_VERTEX
:
7151 case MESA_SHADER_FRAGMENT
:
7152 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
7157 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
7161 set_prog_affected_state_flags(linked_prog
);
7162 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7163 _mesa_shader_stage_to_program(i
),
7165 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7175 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7176 const GLuint outputMapping
[],
7177 struct pipe_stream_output_info
*so
)
7179 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7182 struct gl_transform_feedback_info
*info
=
7183 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7184 st_translate_stream_output_info2(info
, outputMapping
, so
);
7188 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7189 const GLuint outputMapping
[],
7190 struct pipe_stream_output_info
*so
)
7194 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7195 so
->output
[i
].register_index
=
7196 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7197 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7198 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7199 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7200 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7201 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7204 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7205 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7207 so
->num_outputs
= info
->NumOutputs
;