2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
57 #include "st_shader_cache.h"
59 #include "util/hash_table.h"
62 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
63 (1 << PROGRAM_CONSTANT) | \
64 (1 << PROGRAM_UNIFORM))
66 #define MAX_GLSL_TEXTURE_OFFSET 4
71 static int swizzle_for_size(int size
);
73 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
75 unsigned num_elements
= 4;
78 type
= type
->without_array();
79 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
80 num_elements
= type
->vector_elements
;
83 int swizzle
= swizzle_for_size(num_elements
);
84 assert(num_elements
+ component
<= 4);
86 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
91 * This struct is a corresponding struct to TGSI ureg_src.
95 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
96 int component
= 0, unsigned array_id
= 0)
98 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
101 this->swizzle
= swizzle_for_type(type
, component
);
105 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
106 this->reladdr
= NULL
;
107 this->reladdr2
= NULL
;
108 this->has_index2
= false;
109 this->double_reg2
= false;
110 this->array_id
= array_id
;
111 this->is_double_vertex_input
= false;
114 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
116 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
121 this->swizzle
= SWIZZLE_XYZW
;
124 this->reladdr
= NULL
;
125 this->reladdr2
= NULL
;
126 this->has_index2
= false;
127 this->double_reg2
= false;
129 this->is_double_vertex_input
= false;
132 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
134 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
138 this->index2D
= index2D
;
139 this->swizzle
= SWIZZLE_XYZW
;
142 this->reladdr
= NULL
;
143 this->reladdr2
= NULL
;
144 this->has_index2
= false;
145 this->double_reg2
= false;
147 this->is_double_vertex_input
= false;
152 this->type
= GLSL_TYPE_ERROR
;
153 this->file
= PROGRAM_UNDEFINED
;
159 this->reladdr
= NULL
;
160 this->reladdr2
= NULL
;
161 this->has_index2
= false;
162 this->double_reg2
= false;
164 this->is_double_vertex_input
= false;
167 explicit st_src_reg(st_dst_reg reg
);
169 int32_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
171 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
172 int negate
:4; /**< NEGATE_XYZW mask from mesa */
174 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
175 unsigned has_index2
:1;
176 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
178 * Is this the second half of a double register pair?
179 * currently used for input mapping only.
181 unsigned double_reg2
:1;
182 unsigned is_double_vertex_input
:1;
183 unsigned array_id
:10;
185 /** Register index should be offset by the integer in this reg. */
187 st_src_reg
*reladdr2
;
191 st_src_reg reg
= *this;
200 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
202 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
206 this->writemask
= writemask
;
207 this->reladdr
= NULL
;
208 this->reladdr2
= NULL
;
209 this->has_index2
= false;
214 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
216 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
220 this->writemask
= writemask
;
221 this->reladdr
= NULL
;
222 this->reladdr2
= NULL
;
223 this->has_index2
= false;
230 this->type
= GLSL_TYPE_ERROR
;
231 this->file
= PROGRAM_UNDEFINED
;
235 this->reladdr
= NULL
;
236 this->reladdr2
= NULL
;
237 this->has_index2
= false;
241 explicit st_dst_reg(st_src_reg reg
);
243 int32_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
245 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
246 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
247 enum glsl_base_type type
:5; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
248 unsigned has_index2
:1;
249 unsigned array_id
:10;
251 /** Register index should be offset by the integer in this reg. */
253 st_src_reg
*reladdr2
;
256 st_src_reg::st_src_reg(st_dst_reg reg
)
258 this->type
= reg
.type
;
259 this->file
= reg
.file
;
260 this->index
= reg
.index
;
261 this->swizzle
= SWIZZLE_XYZW
;
264 this->reladdr
= reg
.reladdr
;
265 this->index2D
= reg
.index2D
;
266 this->reladdr2
= reg
.reladdr2
;
267 this->has_index2
= reg
.has_index2
;
268 this->double_reg2
= false;
269 this->array_id
= reg
.array_id
;
270 this->is_double_vertex_input
= false;
273 st_dst_reg::st_dst_reg(st_src_reg reg
)
275 this->type
= reg
.type
;
276 this->file
= reg
.file
;
277 this->index
= reg
.index
;
278 this->writemask
= WRITEMASK_XYZW
;
279 this->reladdr
= reg
.reladdr
;
280 this->index2D
= reg
.index2D
;
281 this->reladdr2
= reg
.reladdr2
;
282 this->has_index2
= reg
.has_index2
;
283 this->array_id
= reg
.array_id
;
286 class glsl_to_tgsi_instruction
: public exec_node
{
288 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
292 st_src_reg resource
; /**< sampler, image or buffer register */
293 st_src_reg
*tex_offsets
;
295 /** Pointer to the ir source this tree came from for debugging */
298 unsigned op
:8; /**< TGSI opcode */
300 unsigned is_64bit_expanded
:1;
301 unsigned sampler_base
:5;
302 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
303 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
304 glsl_base_type tex_type
:5;
305 unsigned tex_shadow
:1;
306 unsigned image_format
:9;
307 unsigned tex_offset_num_offset
:3;
308 unsigned dead_mask
:4; /**< Used in dead code elimination */
309 unsigned buffer_access
:3; /**< buffer access type */
311 const struct tgsi_opcode_info
*info
;
314 class variable_storage
{
315 DECLARE_RZALLOC_CXX_OPERATORS(variable_storage
)
318 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
319 unsigned array_id
= 0)
320 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
322 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
325 gl_register_file file
;
328 /* Explicit component location. This is given in terms of the GLSL-style
329 * swizzles where each double is a single component, i.e. for 64-bit types
330 * it can only be 0 or 1.
333 ir_variable
*var
; /* variable that maps to this, if any */
337 class immediate_storage
: public exec_node
{
339 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
341 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
342 this->size32
= size32
;
346 /* doubles are stored across 2 gl_constant_values */
347 gl_constant_value values
[4];
348 int size32
; /**< Number of 32-bit components (1-4) */
349 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
352 static const st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
353 static const st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
357 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
360 unsigned gs_out_streams
;
361 enum glsl_interp_mode interp
;
362 enum glsl_base_type base_type
;
363 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
366 static struct inout_decl
*
367 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
369 assert(array_id
!= 0);
371 for (unsigned i
= 0; i
< count
; i
++) {
372 struct inout_decl
*decl
= &decls
[i
];
374 if (array_id
== decl
->array_id
) {
382 static enum glsl_base_type
383 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
386 return GLSL_TYPE_ERROR
;
387 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
389 return decl
->base_type
;
390 return GLSL_TYPE_ERROR
;
393 struct rename_reg_pair
{
398 struct glsl_to_tgsi_visitor
: public ir_visitor
{
400 glsl_to_tgsi_visitor();
401 ~glsl_to_tgsi_visitor();
403 struct gl_context
*ctx
;
404 struct gl_program
*prog
;
405 struct gl_shader_program
*shader_program
;
406 struct gl_linked_shader
*shader
;
407 struct gl_shader_compiler_options
*options
;
411 unsigned *array_sizes
;
412 unsigned max_num_arrays
;
415 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
417 unsigned num_input_arrays
;
418 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
419 unsigned num_outputs
;
420 unsigned num_output_arrays
;
422 int num_address_regs
;
423 uint32_t samplers_used
;
424 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
425 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
427 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
428 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
429 bool indirect_addr_consts
;
430 int wpos_transform_const
;
433 bool native_integers
;
436 bool use_shared_memory
;
439 variable_storage
*find_variable_storage(ir_variable
*var
);
441 int add_constant(gl_register_file file
, gl_constant_value values
[8],
442 int size
, int datatype
, uint16_t *swizzle_out
);
444 st_src_reg
get_temp(const glsl_type
*type
);
445 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
447 st_src_reg
st_src_reg_for_double(double val
);
448 st_src_reg
st_src_reg_for_float(float val
);
449 st_src_reg
st_src_reg_for_int(int val
);
450 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
453 * \name Visit methods
455 * As typical for the visitor pattern, there must be one \c visit method for
456 * each concrete subclass of \c ir_instruction. Virtual base classes within
457 * the hierarchy should not have \c visit methods.
460 virtual void visit(ir_variable
*);
461 virtual void visit(ir_loop
*);
462 virtual void visit(ir_loop_jump
*);
463 virtual void visit(ir_function_signature
*);
464 virtual void visit(ir_function
*);
465 virtual void visit(ir_expression
*);
466 virtual void visit(ir_swizzle
*);
467 virtual void visit(ir_dereference_variable
*);
468 virtual void visit(ir_dereference_array
*);
469 virtual void visit(ir_dereference_record
*);
470 virtual void visit(ir_assignment
*);
471 virtual void visit(ir_constant
*);
472 virtual void visit(ir_call
*);
473 virtual void visit(ir_return
*);
474 virtual void visit(ir_discard
*);
475 virtual void visit(ir_texture
*);
476 virtual void visit(ir_if
*);
477 virtual void visit(ir_emit_vertex
*);
478 virtual void visit(ir_end_primitive
*);
479 virtual void visit(ir_barrier
*);
482 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
484 void visit_atomic_counter_intrinsic(ir_call
*);
485 void visit_ssbo_intrinsic(ir_call
*);
486 void visit_membar_intrinsic(ir_call
*);
487 void visit_shared_intrinsic(ir_call
*);
488 void visit_image_intrinsic(ir_call
*);
489 void visit_generic_intrinsic(ir_call
*, unsigned op
);
493 /** List of variable_storage */
494 struct hash_table
*variables
;
496 /** List of immediate_storage */
497 exec_list immediates
;
498 unsigned num_immediates
;
500 /** List of glsl_to_tgsi_instruction */
501 exec_list instructions
;
503 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
504 st_dst_reg dst
= undef_dst
,
505 st_src_reg src0
= undef_src
,
506 st_src_reg src1
= undef_src
,
507 st_src_reg src2
= undef_src
,
508 st_src_reg src3
= undef_src
);
510 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
511 st_dst_reg dst
, st_dst_reg dst1
,
512 st_src_reg src0
= undef_src
,
513 st_src_reg src1
= undef_src
,
514 st_src_reg src2
= undef_src
,
515 st_src_reg src3
= undef_src
);
517 unsigned get_opcode(unsigned op
,
519 st_src_reg src0
, st_src_reg src1
);
522 * Emit the correct dot-product instruction for the type of arguments
524 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
530 void emit_scalar(ir_instruction
*ir
, unsigned op
,
531 st_dst_reg dst
, st_src_reg src0
);
533 void emit_scalar(ir_instruction
*ir
, unsigned op
,
534 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
536 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
538 void get_deref_offsets(ir_dereference
*ir
,
539 unsigned *array_size
,
544 void calc_deref_offsets(ir_dereference
*tail
,
545 unsigned *array_elements
,
547 st_src_reg
*indirect
,
549 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
551 bool try_emit_mad(ir_expression
*ir
,
553 bool try_emit_mad_for_and_not(ir_expression
*ir
,
556 void emit_swz(ir_expression
*ir
);
558 bool process_move_condition(ir_rvalue
*ir
);
560 void simplify_cmp(void);
562 void rename_temp_registers(struct rename_reg_pair
*renames
);
563 void get_first_temp_read(int *first_reads
);
564 void get_first_temp_write(int *first_writes
);
565 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
566 void get_last_temp_write(int *last_writes
);
568 void copy_propagate(void);
569 int eliminate_dead_code(void);
571 void merge_two_dsts(void);
572 void merge_registers(void);
573 void renumber_registers(void);
575 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
576 st_dst_reg
*l
, st_src_reg
*r
,
577 st_src_reg
*cond
, bool cond_swap
);
582 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
583 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
584 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
587 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
590 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
594 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
597 prog
->data
->LinkStatus
= linking_failure
;
601 swizzle_for_size(int size
)
603 static const int size_swizzles
[4] = {
604 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
605 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
606 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
607 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
610 assert((size
>= 1) && (size
<= 4));
611 return size_swizzles
[size
- 1];
615 is_resource_instruction(unsigned opcode
)
618 case TGSI_OPCODE_RESQ
:
619 case TGSI_OPCODE_LOAD
:
620 case TGSI_OPCODE_ATOMUADD
:
621 case TGSI_OPCODE_ATOMXCHG
:
622 case TGSI_OPCODE_ATOMCAS
:
623 case TGSI_OPCODE_ATOMAND
:
624 case TGSI_OPCODE_ATOMOR
:
625 case TGSI_OPCODE_ATOMXOR
:
626 case TGSI_OPCODE_ATOMUMIN
:
627 case TGSI_OPCODE_ATOMUMAX
:
628 case TGSI_OPCODE_ATOMIMIN
:
629 case TGSI_OPCODE_ATOMIMAX
:
637 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
639 return op
->info
->num_dst
;
643 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
645 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
646 op
->info
->num_src
- 1 : op
->info
->num_src
;
649 glsl_to_tgsi_instruction
*
650 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
651 st_dst_reg dst
, st_dst_reg dst1
,
652 st_src_reg src0
, st_src_reg src1
,
653 st_src_reg src2
, st_src_reg src3
)
655 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
656 int num_reladdr
= 0, i
, j
;
657 bool dst_is_64bit
[2];
659 op
= get_opcode(op
, dst
, src0
, src1
);
661 /* If we have to do relative addressing, we want to load the ARL
662 * reg directly for one of the regs, and preload the other reladdr
663 * sources into temps.
665 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
666 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
667 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
668 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
669 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
670 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
672 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
673 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
674 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
675 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
677 if (dst
.reladdr
|| dst
.reladdr2
) {
679 emit_arl(ir
, address_reg
, *dst
.reladdr
);
681 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
685 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
688 assert(num_reladdr
== 0);
690 /* inst->op has only 8 bits. */
691 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
694 inst
->info
= tgsi_get_opcode_info(op
);
701 inst
->is_64bit_expanded
= false;
704 inst
->tex_offsets
= NULL
;
705 inst
->tex_offset_num_offset
= 0;
707 inst
->tex_shadow
= 0;
708 /* default to float, for paths where this is not initialized
709 * (since 0==UINT which is likely wrong):
711 inst
->tex_type
= GLSL_TYPE_FLOAT
;
713 /* Update indirect addressing status used by TGSI */
714 if (dst
.reladdr
|| dst
.reladdr2
) {
716 case PROGRAM_STATE_VAR
:
717 case PROGRAM_CONSTANT
:
718 case PROGRAM_UNIFORM
:
719 this->indirect_addr_consts
= true;
721 case PROGRAM_IMMEDIATE
:
722 assert(!"immediates should not have indirect addressing");
729 for (i
= 0; i
< 4; i
++) {
730 if(inst
->src
[i
].reladdr
) {
731 switch(inst
->src
[i
].file
) {
732 case PROGRAM_STATE_VAR
:
733 case PROGRAM_CONSTANT
:
734 case PROGRAM_UNIFORM
:
735 this->indirect_addr_consts
= true;
737 case PROGRAM_IMMEDIATE
:
738 assert(!"immediates should not have indirect addressing");
748 * This section contains the double processing.
749 * GLSL just represents doubles as single channel values,
750 * however most HW and TGSI represent doubles as pairs of register channels.
752 * so we have to fixup destination writemask/index and src swizzle/indexes.
753 * dest writemasks need to translate from single channel write mask
754 * to a dual-channel writemask, but also need to modify the index,
755 * if we are touching the Z,W fields in the pre-translated writemask.
757 * src channels have similiar index modifications along with swizzle
758 * changes to we pick the XY, ZW pairs from the correct index.
760 * GLSL [0].x -> TGSI [0].xy
761 * GLSL [0].y -> TGSI [0].zw
762 * GLSL [0].z -> TGSI [1].xy
763 * GLSL [0].w -> TGSI [1].zw
765 for (j
= 0; j
< 2; j
++) {
766 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
767 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
768 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
769 if (glsl_base_type_is_64bit(type
))
770 dst_is_64bit
[j
] = true;
774 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
775 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
776 glsl_to_tgsi_instruction
*dinst
= NULL
;
777 int initial_src_swz
[4], initial_src_idx
[4];
778 int initial_dst_idx
[2], initial_dst_writemask
[2];
779 /* select the writemask for dst0 or dst1 */
780 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
782 /* copy out the writemask, index and swizzles for all src/dsts. */
783 for (j
= 0; j
< 2; j
++) {
784 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
785 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
788 for (j
= 0; j
< 4; j
++) {
789 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
790 initial_src_idx
[j
] = inst
->src
[j
].index
;
794 * scan all the components in the dst writemask
795 * generate an instruction for each of them if required.
800 int i
= u_bit_scan(&writemask
);
802 /* before emitting the instruction, see if we have to adjust load / store
804 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
805 addr
.file
== PROGRAM_UNDEFINED
) {
806 /* We have to advance the buffer address by 16 */
807 addr
= get_temp(glsl_type::uint_type
);
808 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
809 inst
->src
[0], st_src_reg_for_int(16));
812 /* first time use previous instruction */
816 /* create a new instructions for subsequent attempts */
817 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
822 this->instructions
.push_tail(dinst
);
823 dinst
->is_64bit_expanded
= true;
825 /* modify the destination if we are splitting */
826 for (j
= 0; j
< 2; j
++) {
827 if (dst_is_64bit
[j
]) {
828 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
829 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
831 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
832 dinst
->src
[0] = addr
;
833 if (dinst
->op
!= TGSI_OPCODE_STORE
)
834 dinst
->dst
[j
].index
++;
837 /* if we aren't writing to a double, just get the bit of the initial writemask
839 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
843 /* modify the src registers */
844 for (j
= 0; j
< 4; j
++) {
845 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
847 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
848 dinst
->src
[j
].index
= initial_src_idx
[j
];
850 dinst
->src
[j
].double_reg2
= true;
851 dinst
->src
[j
].index
++;
855 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
857 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
860 /* some opcodes are special case in what they use as sources
861 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
862 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
863 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
864 op
== TGSI_OPCODE_DLDEXP
||
865 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
866 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
873 this->instructions
.push_tail(inst
);
880 glsl_to_tgsi_instruction
*
881 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
883 st_src_reg src0
, st_src_reg src1
,
884 st_src_reg src2
, st_src_reg src3
)
886 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
890 * Determines whether to use an integer, unsigned integer, or float opcode
891 * based on the operands and input opcode, then emits the result.
894 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
896 st_src_reg src0
, st_src_reg src1
)
898 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
900 if (op
== TGSI_OPCODE_MOV
)
903 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
904 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
905 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
906 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
908 if (is_resource_instruction(op
))
910 else if (src0
.type
== GLSL_TYPE_INT64
|| src1
.type
== GLSL_TYPE_INT64
)
911 type
= GLSL_TYPE_INT64
;
912 else if (src0
.type
== GLSL_TYPE_UINT64
|| src1
.type
== GLSL_TYPE_UINT64
)
913 type
= GLSL_TYPE_UINT64
;
914 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
915 type
= GLSL_TYPE_DOUBLE
;
916 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
917 type
= GLSL_TYPE_FLOAT
;
918 else if (native_integers
)
919 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
921 #define case7(c, f, i, u, d, i64, ui64) \
922 case TGSI_OPCODE_##c: \
923 if (type == GLSL_TYPE_UINT64) \
924 op = TGSI_OPCODE_##ui64; \
925 else if (type == GLSL_TYPE_INT64) \
926 op = TGSI_OPCODE_##i64; \
927 else if (type == GLSL_TYPE_DOUBLE) \
928 op = TGSI_OPCODE_##d; \
929 else if (type == GLSL_TYPE_INT) \
930 op = TGSI_OPCODE_##i; \
931 else if (type == GLSL_TYPE_UINT) \
932 op = TGSI_OPCODE_##u; \
934 op = TGSI_OPCODE_##f; \
936 #define case5(c, f, i, u, d) \
937 case TGSI_OPCODE_##c: \
938 if (type == GLSL_TYPE_DOUBLE) \
939 op = TGSI_OPCODE_##d; \
940 else if (type == GLSL_TYPE_INT) \
941 op = TGSI_OPCODE_##i; \
942 else if (type == GLSL_TYPE_UINT) \
943 op = TGSI_OPCODE_##u; \
945 op = TGSI_OPCODE_##f; \
948 #define case4(c, f, i, u) \
949 case TGSI_OPCODE_##c: \
950 if (type == GLSL_TYPE_INT) \
951 op = TGSI_OPCODE_##i; \
952 else if (type == GLSL_TYPE_UINT) \
953 op = TGSI_OPCODE_##u; \
955 op = TGSI_OPCODE_##f; \
958 #define case3(f, i, u) case4(f, f, i, u)
959 #define case6d(f, i, u, d, i64, u64) case7(f, f, i, u, d, i64, u64)
960 #define case3fid(f, i, d) case5(f, f, i, i, d)
961 #define case3fid64(f, i, d, i64) case7(f, f, i, i, d, i64, i64)
962 #define case2fi(f, i) case4(f, f, i, i)
963 #define case2iu(i, u) case4(i, LAST, i, u)
965 #define case2iu64(i, i64) case7(i, LAST, i, i, LAST, i64, i64)
966 #define case4iu64(i, u, i64, u64) case7(i, LAST, i, u, LAST, i64, u64)
968 #define casecomp(c, f, i, u, d, i64, ui64) \
969 case TGSI_OPCODE_##c: \
970 if (type == GLSL_TYPE_INT64) \
971 op = TGSI_OPCODE_##i64; \
972 else if (type == GLSL_TYPE_UINT64) \
973 op = TGSI_OPCODE_##ui64; \
974 else if (type == GLSL_TYPE_DOUBLE) \
975 op = TGSI_OPCODE_##d; \
976 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
977 op = TGSI_OPCODE_##i; \
978 else if (type == GLSL_TYPE_UINT) \
979 op = TGSI_OPCODE_##u; \
980 else if (native_integers) \
981 op = TGSI_OPCODE_##f; \
983 op = TGSI_OPCODE_##c; \
987 case3fid64(ADD
, UADD
, DADD
, U64ADD
);
988 case3fid64(MUL
, UMUL
, DMUL
, U64MUL
);
989 case3fid(MAD
, UMAD
, DMAD
);
990 case3fid(FMA
, UMAD
, DFMA
);
991 case6d(DIV
, IDIV
, UDIV
, DDIV
, I64DIV
, U64DIV
);
992 case6d(MAX
, IMAX
, UMAX
, DMAX
, I64MAX
, U64MAX
);
993 case6d(MIN
, IMIN
, UMIN
, DMIN
, I64MIN
, U64MIN
);
994 case4iu64(MOD
, UMOD
, I64MOD
, U64MOD
);
996 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
, U64SEQ
, U64SEQ
);
997 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
, U64SNE
, U64SNE
);
998 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
, I64SGE
, U64SGE
);
999 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
, I64SLT
, U64SLT
);
1001 case2iu64(SHL
, U64SHL
);
1002 case4iu64(ISHR
, USHR
, I64SHR
, U64SHR
);
1004 case3fid64(SSG
, ISSG
, DSSG
, I64SSG
);
1006 case2iu(IBFE
, UBFE
);
1007 case2iu(IMSB
, UMSB
);
1008 case2iu(IMUL_HI
, UMUL_HI
);
1010 case3fid(SQRT
, SQRT
, DSQRT
);
1012 case3fid(RCP
, RCP
, DRCP
);
1013 case3fid(RSQ
, RSQ
, DRSQ
);
1015 case3fid(FRC
, FRC
, DFRAC
);
1016 case3fid(TRUNC
, TRUNC
, DTRUNC
);
1017 case3fid(CEIL
, CEIL
, DCEIL
);
1018 case3fid(FLR
, FLR
, DFLR
);
1019 case3fid(ROUND
, ROUND
, DROUND
);
1021 case2iu(ATOMIMAX
, ATOMUMAX
);
1022 case2iu(ATOMIMIN
, ATOMUMIN
);
1027 assert(op
!= TGSI_OPCODE_LAST
);
1031 glsl_to_tgsi_instruction
*
1032 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
1033 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1036 static const unsigned dot_opcodes
[] = {
1037 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1040 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1044 * Emits TGSI scalar opcodes to produce unique answers across channels.
1046 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1047 * channel determines the result across all channels. So to do a vec4
1048 * of this operation, we want to emit a scalar per source channel used
1049 * to produce dest channels.
1052 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1054 st_src_reg orig_src0
, st_src_reg orig_src1
)
1057 int done_mask
= ~dst
.writemask
;
1059 /* TGSI RCP is a scalar operation splatting results to all channels,
1060 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1063 for (i
= 0; i
< 4; i
++) {
1064 GLuint this_mask
= (1 << i
);
1065 st_src_reg src0
= orig_src0
;
1066 st_src_reg src1
= orig_src1
;
1068 if (done_mask
& this_mask
)
1071 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1072 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1073 for (j
= i
+ 1; j
< 4; j
++) {
1074 /* If there is another enabled component in the destination that is
1075 * derived from the same inputs, generate its value on this pass as
1078 if (!(done_mask
& (1 << j
)) &&
1079 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1080 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1081 this_mask
|= (1 << j
);
1084 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1085 src0_swiz
, src0_swiz
);
1086 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1087 src1_swiz
, src1_swiz
);
1089 dst
.writemask
= this_mask
;
1090 emit_asm(ir
, op
, dst
, src0
, src1
);
1091 done_mask
|= this_mask
;
1096 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1097 st_dst_reg dst
, st_src_reg src0
)
1099 st_src_reg undef
= undef_src
;
1101 undef
.swizzle
= SWIZZLE_XXXX
;
1103 emit_scalar(ir
, op
, dst
, src0
, undef
);
1107 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1108 st_dst_reg dst
, st_src_reg src0
)
1110 int op
= TGSI_OPCODE_ARL
;
1112 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1113 op
= TGSI_OPCODE_UARL
;
1115 assert(dst
.file
== PROGRAM_ADDRESS
);
1116 if (dst
.index
>= this->num_address_regs
)
1117 this->num_address_regs
= dst
.index
+ 1;
1119 emit_asm(NULL
, op
, dst
, src0
);
1123 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1124 gl_constant_value values
[8], int size
, int datatype
,
1125 uint16_t *swizzle_out
)
1127 if (file
== PROGRAM_CONSTANT
) {
1128 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1129 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1130 size
, datatype
, &swizzle
);
1132 *swizzle_out
= swizzle
;
1136 assert(file
== PROGRAM_IMMEDIATE
);
1139 immediate_storage
*entry
;
1140 int size32
= size
* ((datatype
== GL_DOUBLE
||
1141 datatype
== GL_INT64_ARB
||
1142 datatype
== GL_UNSIGNED_INT64_ARB
)? 2 : 1);
1145 /* Search immediate storage to see if we already have an identical
1146 * immediate that we can use instead of adding a duplicate entry.
1148 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1149 immediate_storage
*tmp
= entry
;
1151 for (i
= 0; i
* 4 < size32
; i
++) {
1152 int slot_size
= MIN2(size32
- (i
* 4), 4);
1153 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1155 if (memcmp(tmp
->values
, &values
[i
* 4],
1156 slot_size
* sizeof(gl_constant_value
)))
1159 /* Everything matches, keep going until the full size is matched */
1160 tmp
= (immediate_storage
*)tmp
->next
;
1163 /* The full value matched */
1164 if (i
* 4 >= size32
)
1170 for (i
= 0; i
* 4 < size32
; i
++) {
1171 int slot_size
= MIN2(size32
- (i
* 4), 4);
1172 /* Add this immediate to the list. */
1173 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1174 this->immediates
.push_tail(entry
);
1175 this->num_immediates
++;
1181 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1183 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1184 union gl_constant_value uval
;
1187 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1193 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1195 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1196 union gl_constant_value uval
[2];
1198 memcpy(uval
, &val
, sizeof(uval
));
1199 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1200 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1205 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1207 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1208 union gl_constant_value uval
;
1210 assert(native_integers
);
1213 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1219 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1221 if (native_integers
)
1222 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1223 st_src_reg_for_int(val
);
1225 return st_src_reg_for_float(val
);
1229 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1231 return st_glsl_attrib_type_size(type
, is_vs_input
);
1235 type_size(const struct glsl_type
*type
)
1237 return st_glsl_type_size(type
);
1241 * If the given GLSL type is an array or matrix or a structure containing
1242 * an array/matrix member, return true. Else return false.
1244 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1245 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1246 * we have an array that might be indexed with a variable, we need to use
1247 * the later storage type.
1250 type_has_array_or_matrix(const glsl_type
*type
)
1252 if (type
->is_array() || type
->is_matrix())
1255 if (type
->is_record()) {
1256 for (unsigned i
= 0; i
< type
->length
; i
++) {
1257 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1268 * In the initial pass of codegen, we assign temporary numbers to
1269 * intermediate results. (not SSA -- variable assignments will reuse
1273 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1277 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1282 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1283 if (next_array
>= max_num_arrays
) {
1284 max_num_arrays
+= 32;
1285 array_sizes
= (unsigned*)
1286 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1289 src
.file
= PROGRAM_ARRAY
;
1291 src
.array_id
= next_array
+ 1;
1292 array_sizes
[next_array
] = type_size(type
);
1296 src
.file
= PROGRAM_TEMPORARY
;
1297 src
.index
= next_temp
;
1298 next_temp
+= type_size(type
);
1301 if (type
->is_array() || type
->is_record()) {
1302 src
.swizzle
= SWIZZLE_NOOP
;
1304 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1311 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1313 struct hash_entry
*entry
;
1315 entry
= _mesa_hash_table_search(this->variables
, var
);
1319 return (variable_storage
*)entry
->data
;
1323 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1325 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1326 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1327 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1330 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1332 const ir_state_slot
*const slots
= ir
->get_state_slots();
1333 assert(slots
!= NULL
);
1335 /* Check if this statevar's setup in the STATE file exactly
1336 * matches how we'll want to reference it as a
1337 * struct/array/whatever. If not, then we need to move it into
1338 * temporary storage and hope that it'll get copy-propagated
1341 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1342 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1347 variable_storage
*storage
;
1349 if (i
== ir
->get_num_state_slots()) {
1350 /* We'll set the index later. */
1351 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1353 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1357 /* The variable_storage constructor allocates slots based on the size
1358 * of the type. However, this had better match the number of state
1359 * elements that we're going to copy into the new temporary.
1361 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1363 dst
= st_dst_reg(get_temp(ir
->type
));
1365 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1368 _mesa_hash_table_insert(this->variables
, ir
, storage
);
1372 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1373 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1374 (gl_state_index
*)slots
[i
].tokens
);
1376 if (storage
->file
== PROGRAM_STATE_VAR
) {
1377 if (storage
->index
== -1) {
1378 storage
->index
= index
;
1380 assert(index
== storage
->index
+ (int)i
);
1383 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1384 * the data being moved since MOV does not care about the type of
1385 * data it is moving, and we don't want to declare registers with
1386 * array or struct types.
1388 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1389 src
.swizzle
= slots
[i
].swizzle
;
1390 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1391 /* even a float takes up a whole vec4 reg in a struct/array. */
1396 if (storage
->file
== PROGRAM_TEMPORARY
&&
1397 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1398 fail_link(this->shader_program
,
1399 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1400 ir
->name
, dst
.index
- storage
->index
,
1401 type_size(ir
->type
));
1407 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1409 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1411 visit_exec_list(&ir
->body_instructions
, this);
1413 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1417 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1420 case ir_loop_jump::jump_break
:
1421 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1423 case ir_loop_jump::jump_continue
:
1424 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1431 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1438 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1440 /* Ignore function bodies other than main() -- we shouldn't see calls to
1441 * them since they should all be inlined before we get to glsl_to_tgsi.
1443 if (strcmp(ir
->name
, "main") == 0) {
1444 const ir_function_signature
*sig
;
1447 sig
= ir
->matching_signature(NULL
, &empty
, false);
1451 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1458 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1460 int nonmul_operand
= 1 - mul_operand
;
1462 st_dst_reg result_dst
;
1464 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1465 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1468 expr
->operands
[0]->accept(this);
1470 expr
->operands
[1]->accept(this);
1472 ir
->operands
[nonmul_operand
]->accept(this);
1475 this->result
= get_temp(ir
->type
);
1476 result_dst
= st_dst_reg(this->result
);
1477 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1478 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1484 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1486 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1487 * implemented using multiplication, and logical-or is implemented using
1488 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1489 * As result, the logical expression (a & !b) can be rewritten as:
1493 * - (a * 1) - (a * b)
1497 * This final expression can be implemented as a single MAD(a, -b, a)
1501 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1503 const int other_operand
= 1 - try_operand
;
1506 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1507 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1510 ir
->operands
[other_operand
]->accept(this);
1512 expr
->operands
[0]->accept(this);
1515 b
.negate
= ~b
.negate
;
1517 this->result
= get_temp(ir
->type
);
1518 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1524 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1525 st_src_reg
*reg
, int *num_reladdr
)
1527 if (!reg
->reladdr
&& !reg
->reladdr2
)
1530 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1531 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1533 if (*num_reladdr
!= 1) {
1534 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1536 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1544 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1546 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1548 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1550 if (ir
->operation
== ir_binop_add
) {
1551 if (try_emit_mad(ir
, 1))
1553 if (try_emit_mad(ir
, 0))
1557 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1559 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1560 if (try_emit_mad_for_and_not(ir
, 1))
1562 if (try_emit_mad_for_and_not(ir
, 0))
1566 if (ir
->operation
== ir_quadop_vector
)
1567 assert(!"ir_quadop_vector should have been lowered");
1569 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1570 this->result
.file
= PROGRAM_UNDEFINED
;
1571 ir
->operands
[operand
]->accept(this);
1572 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1573 printf("Failed to get tree for expression operand:\n");
1574 ir
->operands
[operand
]->print();
1578 op
[operand
] = this->result
;
1580 /* Matrix expression operands should have been broken down to vector
1581 * operations already.
1583 assert(!ir
->operands
[operand
]->type
->is_matrix());
1586 visit_expression(ir
, op
);
1589 /* The non-recursive part of the expression visitor lives in a separate
1590 * function and should be prevented from being inlined, to avoid a stack
1591 * explosion when deeply nested expressions are visited.
1594 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1596 st_src_reg result_src
;
1597 st_dst_reg result_dst
;
1599 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1600 if (ir
->operands
[1]) {
1601 vector_elements
= MAX2(vector_elements
,
1602 ir
->operands
[1]->type
->vector_elements
);
1605 this->result
.file
= PROGRAM_UNDEFINED
;
1607 /* Storage for our result. Ideally for an assignment we'd be using
1608 * the actual storage for the result here, instead.
1610 result_src
= get_temp(ir
->type
);
1611 /* convenience for the emit functions below. */
1612 result_dst
= st_dst_reg(result_src
);
1613 /* Limit writes to the channels that will be used by result_src later.
1614 * This does limit this temp's use as a temporary for multi-instruction
1617 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1619 switch (ir
->operation
) {
1620 case ir_unop_logic_not
:
1621 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1622 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1624 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1625 * older GPUs implement SEQ using multiple instructions (i915 uses two
1626 * SGE instructions and a MUL instruction). Since our logic values are
1627 * 0.0 and 1.0, 1-x also implements !x.
1629 op
[0].negate
= ~op
[0].negate
;
1630 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1634 if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1635 emit_asm(ir
, TGSI_OPCODE_I64NEG
, result_dst
, op
[0]);
1636 else if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1637 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1638 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1639 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1641 op
[0].negate
= ~op
[0].negate
;
1645 case ir_unop_subroutine_to_int
:
1646 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1649 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1650 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1651 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1652 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1653 else if (result_dst
.type
== GLSL_TYPE_INT64
|| result_dst
.type
== GLSL_TYPE_UINT64
)
1654 emit_asm(ir
, TGSI_OPCODE_I64ABS
, result_dst
, op
[0]);
1656 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1659 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1662 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1666 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1669 assert(!"not reached: should be handled by exp_to_exp2");
1672 assert(!"not reached: should be handled by log_to_log2");
1675 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1678 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1681 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1683 case ir_unop_saturate
: {
1684 glsl_to_tgsi_instruction
*inst
;
1685 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1686 inst
->saturate
= true;
1691 case ir_unop_dFdx_coarse
:
1692 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1694 case ir_unop_dFdx_fine
:
1695 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1698 case ir_unop_dFdy_coarse
:
1699 case ir_unop_dFdy_fine
:
1701 /* The X component contains 1 or -1 depending on whether the framebuffer
1702 * is a FBO or the window system buffer, respectively.
1703 * It is then multiplied with the source operand of DDY.
1705 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1706 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1708 unsigned transform_y_index
=
1709 _mesa_add_state_reference(this->prog
->Parameters
,
1712 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1714 glsl_type::vec4_type
);
1715 transform_y
.swizzle
= SWIZZLE_XXXX
;
1717 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1719 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1720 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1721 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1725 case ir_unop_frexp_sig
:
1726 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1729 case ir_unop_frexp_exp
:
1730 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1733 case ir_unop_noise
: {
1734 /* At some point, a motivated person could add a better
1735 * implementation of noise. Currently not even the nvidia
1736 * binary drivers do anything more than this. In any case, the
1737 * place to do this is in the GL state tracker, not the poor
1740 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1745 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1748 op
[1].negate
= ~op
[1].negate
;
1749 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1753 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1756 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1759 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1760 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1762 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1766 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1768 case ir_binop_greater
:
1769 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1771 case ir_binop_lequal
:
1772 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1774 case ir_binop_gequal
:
1775 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1777 case ir_binop_equal
:
1778 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1780 case ir_binop_nequal
:
1781 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1783 case ir_binop_all_equal
:
1784 /* "==" operator producing a scalar boolean. */
1785 if (ir
->operands
[0]->type
->is_vector() ||
1786 ir
->operands
[1]->type
->is_vector()) {
1787 st_src_reg temp
= get_temp(native_integers
?
1788 glsl_type::uvec4_type
:
1789 glsl_type::vec4_type
);
1791 if (native_integers
) {
1792 st_dst_reg temp_dst
= st_dst_reg(temp
);
1793 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1795 if (ir
->operands
[0]->type
->is_boolean() &&
1796 ir
->operands
[1]->as_constant() &&
1797 ir
->operands
[1]->as_constant()->is_one()) {
1798 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1800 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1803 /* Emit 1-3 AND operations to combine the SEQ results. */
1804 switch (ir
->operands
[0]->type
->vector_elements
) {
1808 temp_dst
.writemask
= WRITEMASK_Y
;
1809 temp1
.swizzle
= SWIZZLE_YYYY
;
1810 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1811 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1814 temp_dst
.writemask
= WRITEMASK_X
;
1815 temp1
.swizzle
= SWIZZLE_XXXX
;
1816 temp2
.swizzle
= SWIZZLE_YYYY
;
1817 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1818 temp_dst
.writemask
= WRITEMASK_Y
;
1819 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1820 temp2
.swizzle
= SWIZZLE_WWWW
;
1821 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1824 temp1
.swizzle
= SWIZZLE_XXXX
;
1825 temp2
.swizzle
= SWIZZLE_YYYY
;
1826 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1828 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1830 /* After the dot-product, the value will be an integer on the
1831 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1833 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1835 /* Negating the result of the dot-product gives values on the range
1836 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1837 * This is achieved using SGE.
1839 st_src_reg sge_src
= result_src
;
1840 sge_src
.negate
= ~sge_src
.negate
;
1841 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1844 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1847 case ir_binop_any_nequal
:
1848 /* "!=" operator producing a scalar boolean. */
1849 if (ir
->operands
[0]->type
->is_vector() ||
1850 ir
->operands
[1]->type
->is_vector()) {
1851 st_src_reg temp
= get_temp(native_integers
?
1852 glsl_type::uvec4_type
:
1853 glsl_type::vec4_type
);
1854 if (ir
->operands
[0]->type
->is_boolean() &&
1855 ir
->operands
[1]->as_constant() &&
1856 ir
->operands
[1]->as_constant()->is_zero()) {
1857 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1859 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1862 if (native_integers
) {
1863 st_dst_reg temp_dst
= st_dst_reg(temp
);
1864 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1866 /* Emit 1-3 OR operations to combine the SNE results. */
1867 switch (ir
->operands
[0]->type
->vector_elements
) {
1871 temp_dst
.writemask
= WRITEMASK_Y
;
1872 temp1
.swizzle
= SWIZZLE_YYYY
;
1873 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1874 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1877 temp_dst
.writemask
= WRITEMASK_X
;
1878 temp1
.swizzle
= SWIZZLE_XXXX
;
1879 temp2
.swizzle
= SWIZZLE_YYYY
;
1880 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1881 temp_dst
.writemask
= WRITEMASK_Y
;
1882 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1883 temp2
.swizzle
= SWIZZLE_WWWW
;
1884 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1887 temp1
.swizzle
= SWIZZLE_XXXX
;
1888 temp2
.swizzle
= SWIZZLE_YYYY
;
1889 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1891 /* After the dot-product, the value will be an integer on the
1892 * range [0,4]. Zero stays zero, and positive values become 1.0.
1894 glsl_to_tgsi_instruction
*const dp
=
1895 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1896 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1897 /* The clamping to [0,1] can be done for free in the fragment
1898 * shader with a saturate.
1900 dp
->saturate
= true;
1902 /* Negating the result of the dot-product gives values on the range
1903 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1904 * achieved using SLT.
1906 st_src_reg slt_src
= result_src
;
1907 slt_src
.negate
= ~slt_src
.negate
;
1908 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1912 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1916 case ir_binop_logic_xor
:
1917 if (native_integers
)
1918 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1920 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1923 case ir_binop_logic_or
: {
1924 if (native_integers
) {
1925 /* If integers are used as booleans, we can use an actual "or"
1928 assert(native_integers
);
1929 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1931 /* After the addition, the value will be an integer on the
1932 * range [0,2]. Zero stays zero, and positive values become 1.0.
1934 glsl_to_tgsi_instruction
*add
=
1935 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1936 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1937 /* The clamping to [0,1] can be done for free in the fragment
1938 * shader with a saturate if floats are being used as boolean values.
1940 add
->saturate
= true;
1942 /* Negating the result of the addition gives values on the range
1943 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1944 * is achieved using SLT.
1946 st_src_reg slt_src
= result_src
;
1947 slt_src
.negate
= ~slt_src
.negate
;
1948 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1954 case ir_binop_logic_and
:
1955 /* If native integers are disabled, the bool args are stored as float 0.0
1956 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1957 * actual AND opcode.
1959 if (native_integers
)
1960 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1962 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1966 assert(ir
->operands
[0]->type
->is_vector());
1967 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1968 emit_dp(ir
, result_dst
, op
[0], op
[1],
1969 ir
->operands
[0]->type
->vector_elements
);
1974 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1976 /* This is the only instruction sequence that makes the game "Risen"
1977 * render correctly. ABS is not required for the game, but since GLSL
1978 * declares negative values as "undefined", allowing us to do whatever
1979 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1982 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1983 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1987 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1990 if (native_integers
) {
1991 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1994 /* fallthrough to next case otherwise */
1996 if (native_integers
) {
1997 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
2000 /* fallthrough to next case otherwise */
2003 case ir_unop_i642u64
:
2004 case ir_unop_u642i64
:
2005 /* Converting between signed and unsigned integers is a no-op. */
2007 result_src
.type
= result_dst
.type
;
2010 if (native_integers
) {
2011 /* Booleans are stored as integers using ~0 for true and 0 for false.
2012 * GLSL requires that int(bool) return 1 for true and 0 for false.
2013 * This conversion is done with AND, but it could be done with NEG.
2015 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
2017 /* Booleans and integers are both stored as floats when native
2018 * integers are disabled.
2024 if (native_integers
)
2025 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
2027 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2030 if (native_integers
)
2031 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
2033 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2035 case ir_unop_bitcast_f2i
:
2036 case ir_unop_bitcast_f2u
:
2037 /* Make sure we don't propagate the negate modifier to integer opcodes. */
2038 if (op
[0].negate
|| op
[0].abs
)
2039 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2042 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2045 case ir_unop_bitcast_i2f
:
2046 case ir_unop_bitcast_u2f
:
2048 result_src
.type
= GLSL_TYPE_FLOAT
;
2051 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2054 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2057 if (native_integers
)
2058 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2060 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2062 case ir_unop_bitcast_u642d
:
2063 case ir_unop_bitcast_i642d
:
2065 result_src
.type
= GLSL_TYPE_DOUBLE
;
2067 case ir_unop_bitcast_d2i64
:
2069 result_src
.type
= GLSL_TYPE_INT64
;
2071 case ir_unop_bitcast_d2u64
:
2073 result_src
.type
= GLSL_TYPE_UINT64
;
2076 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2079 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2082 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2084 case ir_unop_round_even
:
2085 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2088 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2092 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2095 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2098 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2101 case ir_unop_bit_not
:
2102 if (native_integers
) {
2103 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2107 if (native_integers
) {
2108 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2111 case ir_binop_lshift
:
2112 case ir_binop_rshift
:
2113 if (native_integers
) {
2114 unsigned opcode
= ir
->operation
== ir_binop_lshift
? TGSI_OPCODE_SHL
2118 if (glsl_base_type_is_64bit(op
[0].type
)) {
2119 /* GLSL shift operations have 32-bit shift counts, but TGSI uses
2122 count
= get_temp(glsl_type::u64vec(ir
->operands
[1]->type
->components()));
2123 emit_asm(ir
, TGSI_OPCODE_U2I64
, st_dst_reg(count
), op
[1]);
2128 emit_asm(ir
, opcode
, result_dst
, op
[0], count
);
2131 case ir_binop_bit_and
:
2132 if (native_integers
) {
2133 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2136 case ir_binop_bit_xor
:
2137 if (native_integers
) {
2138 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2141 case ir_binop_bit_or
:
2142 if (native_integers
) {
2143 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2147 assert(!"GLSL 1.30 features unsupported");
2150 case ir_binop_ubo_load
: {
2151 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2152 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2153 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2154 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2155 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2158 cbuf
.type
= ir
->type
->base_type
;
2159 cbuf
.file
= PROGRAM_CONSTANT
;
2161 cbuf
.reladdr
= NULL
;
2165 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2167 if (const_offset_ir
) {
2168 /* Constant index into constant buffer */
2169 cbuf
.reladdr
= NULL
;
2170 cbuf
.index
= const_offset
/ 16;
2173 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2174 st_src_reg offset
= op
[1];
2176 /* The OpenGL spec is written in such a way that accesses with
2177 * non-constant offset are almost always vec4-aligned. The only
2178 * exception to this are members of structs in arrays of structs:
2179 * each struct in an array of structs is at least vec4-aligned,
2180 * but single-element and [ui]vec2 members of the struct may be at
2181 * an offset that is not a multiple of 16 bytes.
2183 * Here, we extract that offset, relying on previous passes to always
2184 * generate offset expressions of the form (+ expr constant_offset).
2186 * Note that the std430 layout, which allows more cases of alignment
2187 * less than vec4 in arrays, is not supported for uniform blocks, so
2188 * we do not have to deal with it here.
2190 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2191 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2192 if (const_offset_ir
) {
2193 const_offset
= const_offset_ir
->value
.u
[0];
2194 cbuf
.index
= const_offset
/ 16;
2195 offset_expr
->operands
[0]->accept(this);
2196 offset
= this->result
;
2200 /* Relative/variable index into constant buffer */
2201 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2202 st_src_reg_for_int(4));
2203 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2204 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2207 if (const_uniform_block
) {
2208 /* Constant constant buffer */
2209 cbuf
.reladdr2
= NULL
;
2210 cbuf
.index2D
= const_block
;
2211 cbuf
.has_index2
= true;
2214 /* Relative/variable constant buffer */
2215 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2217 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2218 cbuf
.has_index2
= true;
2221 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2222 if (glsl_base_type_is_64bit(cbuf
.type
))
2223 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2224 const_offset
% 16 / 8,
2225 const_offset
% 16 / 8,
2226 const_offset
% 16 / 8);
2228 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2229 const_offset
% 16 / 4,
2230 const_offset
% 16 / 4,
2231 const_offset
% 16 / 4);
2233 if (ir
->type
->is_boolean()) {
2234 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2236 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2241 /* note: we have to reorder the three args here */
2242 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2245 if (this->ctx
->Const
.NativeIntegers
)
2246 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2248 op
[0].negate
= ~op
[0].negate
;
2249 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2252 case ir_triop_bitfield_extract
:
2253 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2255 case ir_quadop_bitfield_insert
:
2256 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2258 case ir_unop_bitfield_reverse
:
2259 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2261 case ir_unop_bit_count
:
2262 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2264 case ir_unop_find_msb
:
2265 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2267 case ir_unop_find_lsb
:
2268 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2270 case ir_binop_imul_high
:
2271 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2274 /* In theory, MAD is incorrect here. */
2276 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2278 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2280 case ir_unop_interpolate_at_centroid
:
2281 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2283 case ir_binop_interpolate_at_offset
: {
2284 /* The y coordinate needs to be flipped for the default fb */
2285 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2286 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2288 unsigned transform_y_index
=
2289 _mesa_add_state_reference(this->prog
->Parameters
,
2292 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2294 glsl_type::vec4_type
);
2295 transform_y
.swizzle
= SWIZZLE_XXXX
;
2297 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2298 st_dst_reg temp_dst
= st_dst_reg(temp
);
2300 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2301 temp_dst
.writemask
= WRITEMASK_Y
;
2302 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2303 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2306 case ir_binop_interpolate_at_sample
:
2307 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2311 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2314 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2317 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2320 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2323 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2326 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2328 case ir_unop_unpack_double_2x32
:
2329 case ir_unop_pack_double_2x32
:
2330 case ir_unop_unpack_int_2x32
:
2331 case ir_unop_pack_int_2x32
:
2332 case ir_unop_unpack_uint_2x32
:
2333 case ir_unop_pack_uint_2x32
:
2334 case ir_unop_unpack_sampler_2x32
:
2335 case ir_unop_pack_sampler_2x32
:
2336 case ir_unop_unpack_image_2x32
:
2337 case ir_unop_pack_image_2x32
:
2338 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2341 case ir_binop_ldexp
:
2342 if (ir
->operands
[0]->type
->is_double()) {
2343 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2345 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2349 case ir_unop_pack_half_2x16
:
2350 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2352 case ir_unop_unpack_half_2x16
:
2353 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2356 case ir_unop_get_buffer_size
: {
2357 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2360 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2361 (const_offset
? const_offset
->value
.u
[0] : 0),
2363 if (!const_offset
) {
2364 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2365 *buffer
.reladdr
= op
[0];
2366 emit_arl(ir
, sampler_reladdr
, op
[0]);
2368 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2374 case ir_unop_b2i64
: {
2375 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2376 st_dst_reg temp_dst
= st_dst_reg(temp
);
2377 unsigned orig_swz
= op
[0].swizzle
;
2379 * To convert unsigned to 64-bit:
2380 * zero Y channel, copy X channel.
2382 temp_dst
.writemask
= WRITEMASK_Y
;
2383 if (vector_elements
> 1)
2384 temp_dst
.writemask
|= WRITEMASK_W
;
2385 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2386 temp_dst
.writemask
= WRITEMASK_X
;
2387 if (vector_elements
> 1)
2388 temp_dst
.writemask
|= WRITEMASK_Z
;
2389 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 0), GET_SWZ(orig_swz
, 0),
2390 GET_SWZ(orig_swz
, 1), GET_SWZ(orig_swz
, 1));
2391 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2392 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2394 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2396 result_src
.type
= GLSL_TYPE_UINT64
;
2397 if (vector_elements
> 2) {
2398 /* Subtle: We rely on the fact that get_temp here returns the next
2399 * TGSI temporary register directly after the temp register used for
2400 * the first two components, so that the result gets picked up
2403 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2404 st_dst_reg temp_dst
= st_dst_reg(temp
);
2405 temp_dst
.writemask
= WRITEMASK_Y
;
2406 if (vector_elements
> 3)
2407 temp_dst
.writemask
|= WRITEMASK_W
;
2408 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, st_src_reg_for_int(0));
2410 temp_dst
.writemask
= WRITEMASK_X
;
2411 if (vector_elements
> 3)
2412 temp_dst
.writemask
|= WRITEMASK_Z
;
2413 op
[0].swizzle
= MAKE_SWIZZLE4(GET_SWZ(orig_swz
, 2), GET_SWZ(orig_swz
, 2),
2414 GET_SWZ(orig_swz
, 3), GET_SWZ(orig_swz
, 3));
2415 if (ir
->operation
== ir_unop_u2i64
|| ir
->operation
== ir_unop_u2u64
)
2416 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2418 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, op
[0], st_src_reg_for_int(1));
2425 case ir_unop_i642u
: {
2426 st_src_reg temp
= get_temp(glsl_type::uvec4_type
);
2427 st_dst_reg temp_dst
= st_dst_reg(temp
);
2428 unsigned orig_swz
= op
[0].swizzle
;
2429 unsigned orig_idx
= op
[0].index
;
2431 temp_dst
.writemask
= WRITEMASK_X
;
2433 for (el
= 0; el
< vector_elements
; el
++) {
2434 unsigned swz
= GET_SWZ(orig_swz
, el
);
2436 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
, SWIZZLE_Z
);
2438 op
[0].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
2440 op
[0].index
= orig_idx
+ 1;
2441 op
[0].type
= GLSL_TYPE_UINT
;
2442 temp_dst
.writemask
= WRITEMASK_X
<< el
;
2443 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[0]);
2446 if (ir
->operation
== ir_unop_u642u
|| ir
->operation
== ir_unop_i642u
)
2447 result_src
.type
= GLSL_TYPE_UINT
;
2449 result_src
.type
= GLSL_TYPE_INT
;
2453 emit_asm(ir
, TGSI_OPCODE_U64SNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2456 emit_asm(ir
, TGSI_OPCODE_I642F
, result_dst
, op
[0]);
2459 emit_asm(ir
, TGSI_OPCODE_U642F
, result_dst
, op
[0]);
2462 emit_asm(ir
, TGSI_OPCODE_I642D
, result_dst
, op
[0]);
2465 emit_asm(ir
, TGSI_OPCODE_U642D
, result_dst
, op
[0]);
2468 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2471 emit_asm(ir
, TGSI_OPCODE_F2I64
, result_dst
, op
[0]);
2474 emit_asm(ir
, TGSI_OPCODE_D2I64
, result_dst
, op
[0]);
2477 emit_asm(ir
, TGSI_OPCODE_I2I64
, result_dst
, op
[0]);
2480 emit_asm(ir
, TGSI_OPCODE_F2U64
, result_dst
, op
[0]);
2483 emit_asm(ir
, TGSI_OPCODE_D2U64
, result_dst
, op
[0]);
2485 /* these might be needed */
2486 case ir_unop_pack_snorm_2x16
:
2487 case ir_unop_pack_unorm_2x16
:
2488 case ir_unop_pack_snorm_4x8
:
2489 case ir_unop_pack_unorm_4x8
:
2491 case ir_unop_unpack_snorm_2x16
:
2492 case ir_unop_unpack_unorm_2x16
:
2493 case ir_unop_unpack_snorm_4x8
:
2494 case ir_unop_unpack_unorm_4x8
:
2496 case ir_quadop_vector
:
2497 case ir_binop_vector_extract
:
2498 case ir_triop_vector_insert
:
2499 case ir_binop_carry
:
2500 case ir_binop_borrow
:
2501 case ir_unop_ssbo_unsized_array_length
:
2502 /* This operation is not supported, or should have already been handled.
2504 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2508 this->result
= result_src
;
2513 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2519 /* Note that this is only swizzles in expressions, not those on the left
2520 * hand side of an assignment, which do write masking. See ir_assignment
2524 ir
->val
->accept(this);
2526 assert(src
.file
!= PROGRAM_UNDEFINED
);
2527 assert(ir
->type
->vector_elements
> 0);
2529 for (i
= 0; i
< 4; i
++) {
2530 if (i
< ir
->type
->vector_elements
) {
2533 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2536 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2539 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2542 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2546 /* If the type is smaller than a vec4, replicate the last
2549 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2553 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2558 /* Test if the variable is an array. Note that geometry and
2559 * tessellation shader inputs are outputs are always arrays (except
2560 * for patch inputs), so only the array element type is considered.
2563 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2565 const glsl_type
*type
= var
->type
;
2567 *remove_array
= false;
2569 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2570 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2573 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2574 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2575 stage
== MESA_SHADER_TESS_CTRL
) &&
2577 if (!var
->type
->is_array())
2578 return false; /* a system value probably */
2580 type
= var
->type
->fields
.array
;
2581 *remove_array
= true;
2584 return type
->is_array() || type
->is_matrix();
2588 st_translate_interp_loc(ir_variable
*var
)
2590 if (var
->data
.centroid
)
2591 return TGSI_INTERPOLATE_LOC_CENTROID
;
2592 else if (var
->data
.sample
)
2593 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2595 return TGSI_INTERPOLATE_LOC_CENTER
;
2599 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2601 variable_storage
*entry
= find_variable_storage(ir
->var
);
2602 ir_variable
*var
= ir
->var
;
2606 switch (var
->data
.mode
) {
2607 case ir_var_uniform
:
2608 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2609 var
->data
.param_index
);
2610 _mesa_hash_table_insert(this->variables
, var
, entry
);
2612 case ir_var_shader_in
: {
2613 /* The linker assigns locations for varyings and attributes,
2614 * including deprecated builtins (like gl_Color), user-assign
2615 * generic attributes (glBindVertexLocation), and
2616 * user-defined varyings.
2618 assert(var
->data
.location
!= -1);
2620 const glsl_type
*type_without_array
= var
->type
->without_array();
2621 struct inout_decl
*decl
= &inputs
[num_inputs
];
2622 unsigned component
= var
->data
.location_frac
;
2623 unsigned num_components
;
2626 if (type_without_array
->is_64bit())
2627 component
= component
/ 2;
2628 if (type_without_array
->vector_elements
)
2629 num_components
= type_without_array
->vector_elements
;
2633 decl
->mesa_index
= var
->data
.location
;
2634 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2635 decl
->interp_loc
= st_translate_interp_loc(var
);
2636 decl
->base_type
= type_without_array
->base_type
;
2637 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2639 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2640 decl
->array_id
= num_input_arrays
+ 1;
2647 decl
->size
= type_size(var
->type
->fields
.array
);
2649 decl
->size
= type_size(var
->type
);
2651 entry
= new(mem_ctx
) variable_storage(var
,
2655 entry
->component
= component
;
2657 _mesa_hash_table_insert(this->variables
, var
, entry
);
2661 case ir_var_shader_out
: {
2662 assert(var
->data
.location
!= -1);
2664 const glsl_type
*type_without_array
= var
->type
->without_array();
2665 struct inout_decl
*decl
= &outputs
[num_outputs
];
2666 unsigned component
= var
->data
.location_frac
;
2667 unsigned num_components
;
2670 if (type_without_array
->is_64bit())
2671 component
= component
/ 2;
2672 if (type_without_array
->vector_elements
)
2673 num_components
= type_without_array
->vector_elements
;
2677 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2678 decl
->base_type
= type_without_array
->base_type
;
2679 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2680 if (var
->data
.stream
& (1u << 31)) {
2681 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2683 assert(var
->data
.stream
< 4);
2684 decl
->gs_out_streams
= 0;
2685 for (unsigned i
= 0; i
< num_components
; ++i
)
2686 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2689 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2690 decl
->array_id
= num_output_arrays
+ 1;
2691 num_output_arrays
++;
2697 decl
->size
= type_size(var
->type
->fields
.array
);
2699 decl
->size
= type_size(var
->type
);
2701 if (var
->data
.fb_fetch_output
) {
2702 st_dst_reg dst
= st_dst_reg(get_temp(var
->type
));
2703 st_src_reg src
= st_src_reg(PROGRAM_OUTPUT
, decl
->mesa_index
,
2704 var
->type
, component
, decl
->array_id
);
2705 emit_asm(NULL
, TGSI_OPCODE_FBFETCH
, dst
, src
);
2706 entry
= new(mem_ctx
) variable_storage(var
, dst
.file
, dst
.index
,
2709 entry
= new(mem_ctx
) variable_storage(var
,
2714 entry
->component
= component
;
2716 _mesa_hash_table_insert(this->variables
, var
, entry
);
2720 case ir_var_system_value
:
2721 entry
= new(mem_ctx
) variable_storage(var
,
2722 PROGRAM_SYSTEM_VALUE
,
2723 var
->data
.location
);
2726 case ir_var_temporary
:
2727 st_src_reg src
= get_temp(var
->type
);
2729 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2731 _mesa_hash_table_insert(this->variables
, var
, entry
);
2737 printf("Failed to make storage for %s\n", var
->name
);
2742 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2743 entry
->component
, entry
->array_id
);
2744 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2745 this->result
.is_double_vertex_input
= true;
2746 if (!native_integers
)
2747 this->result
.type
= GLSL_TYPE_FLOAT
;
2751 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2752 GLbitfield64
* usage_mask
,
2753 GLbitfield64 double_usage_mask
,
2754 GLbitfield
* patch_usage_mask
)
2759 /* Fix array declarations by removing unused array elements at both ends
2760 * of the arrays. For example, mat4[3] where only mat[1] is used.
2762 for (i
= 0; i
< count
; i
++) {
2763 struct inout_decl
*decl
= &decls
[i
];
2764 if (!decl
->array_id
)
2767 /* Shrink the beginning. */
2768 for (j
= 0; j
< (int)decl
->size
; j
++) {
2769 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2770 if (*patch_usage_mask
&
2771 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2775 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2777 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2786 /* Shrink the end. */
2787 for (j
= decl
->size
-1; j
>= 0; j
--) {
2788 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2789 if (*patch_usage_mask
&
2790 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2794 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2796 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2803 /* When not all entries of an array are accessed, we mark them as used
2804 * here anyway, to ensure that the input/output mapping logic doesn't get
2807 * TODO This happens when an array isn't used via indirect access, which
2808 * some game ports do (at least eON-based). There is an optimization
2809 * opportunity here by replacing the array declaration with non-array
2810 * declarations of those slots that are actually used.
2812 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2813 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2814 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2816 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2822 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2826 int element_size
= type_size(ir
->type
);
2829 index
= ir
->array_index
->constant_expression_value();
2831 ir
->array
->accept(this);
2834 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2835 switch (this->prog
->Target
) {
2836 case GL_TESS_CONTROL_PROGRAM_NV
:
2837 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2838 !ir
->variable_referenced()->data
.patch
;
2840 case GL_TESS_EVALUATION_PROGRAM_NV
:
2841 is_2D
= src
.file
== PROGRAM_INPUT
&&
2842 !ir
->variable_referenced()->data
.patch
;
2844 case GL_GEOMETRY_PROGRAM_NV
:
2845 is_2D
= src
.file
== PROGRAM_INPUT
;
2855 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2856 src
.file
== PROGRAM_INPUT
)
2857 element_size
= attrib_type_size(ir
->type
, true);
2859 src
.index2D
= index
->value
.i
[0];
2860 src
.has_index2
= true;
2862 src
.index
+= index
->value
.i
[0] * element_size
;
2864 /* Variable index array dereference. It eats the "vec4" of the
2865 * base of the array and an index that offsets the TGSI register
2868 ir
->array_index
->accept(this);
2870 st_src_reg index_reg
;
2872 if (element_size
== 1) {
2873 index_reg
= this->result
;
2875 index_reg
= get_temp(native_integers
?
2876 glsl_type::int_type
: glsl_type::float_type
);
2878 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2879 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2882 /* If there was already a relative address register involved, add the
2883 * new and the old together to get the new offset.
2885 if (!is_2D
&& src
.reladdr
!= NULL
) {
2886 st_src_reg accum_reg
= get_temp(native_integers
?
2887 glsl_type::int_type
: glsl_type::float_type
);
2889 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2890 index_reg
, *src
.reladdr
);
2892 index_reg
= accum_reg
;
2896 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2897 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2899 src
.has_index2
= true;
2901 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2902 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2906 /* Change the register type to the element type of the array. */
2907 src
.type
= ir
->type
->base_type
;
2913 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2916 const glsl_type
*struct_type
= ir
->record
->type
;
2919 ir
->record
->accept(this);
2921 for (i
= 0; i
< struct_type
->length
; i
++) {
2922 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2924 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2927 /* If the type is smaller than a vec4, replicate the last channel out. */
2928 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2929 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2931 this->result
.swizzle
= SWIZZLE_NOOP
;
2933 this->result
.index
+= offset
;
2934 this->result
.type
= ir
->type
->base_type
;
2938 * We want to be careful in assignment setup to hit the actual storage
2939 * instead of potentially using a temporary like we might with the
2940 * ir_dereference handler.
2943 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2945 /* The LHS must be a dereference. If the LHS is a variable indexed array
2946 * access of a vector, it must be separated into a series conditional moves
2947 * before reaching this point (see ir_vec_index_to_cond_assign).
2949 assert(ir
->as_dereference());
2950 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2952 assert(!deref_array
->array
->type
->is_vector());
2955 /* Use the rvalue deref handler for the most part. We write swizzles using
2956 * the writemask, but we do extract the base component for enhanced layouts
2957 * from the source swizzle.
2960 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2961 return st_dst_reg(v
->result
);
2965 * Process the condition of a conditional assignment
2967 * Examines the condition of a conditional assignment to generate the optimal
2968 * first operand of a \c CMP instruction. If the condition is a relational
2969 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2970 * used as the source for the \c CMP instruction. Otherwise the comparison
2971 * is processed to a boolean result, and the boolean result is used as the
2972 * operand to the CMP instruction.
2975 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2977 ir_rvalue
*src_ir
= ir
;
2979 bool switch_order
= false;
2981 ir_expression
*const expr
= ir
->as_expression();
2983 if (native_integers
) {
2984 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2985 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2986 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2987 type
== GLSL_TYPE_BOOL
) {
2988 if (expr
->operation
== ir_binop_equal
) {
2989 if (expr
->operands
[0]->is_zero()) {
2990 src_ir
= expr
->operands
[1];
2991 switch_order
= true;
2993 else if (expr
->operands
[1]->is_zero()) {
2994 src_ir
= expr
->operands
[0];
2995 switch_order
= true;
2998 else if (expr
->operation
== ir_binop_nequal
) {
2999 if (expr
->operands
[0]->is_zero()) {
3000 src_ir
= expr
->operands
[1];
3002 else if (expr
->operands
[1]->is_zero()) {
3003 src_ir
= expr
->operands
[0];
3009 src_ir
->accept(this);
3010 return switch_order
;
3013 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
3014 bool zero_on_left
= false;
3016 if (expr
->operands
[0]->is_zero()) {
3017 src_ir
= expr
->operands
[1];
3018 zero_on_left
= true;
3019 } else if (expr
->operands
[1]->is_zero()) {
3020 src_ir
= expr
->operands
[0];
3021 zero_on_left
= false;
3025 * (a < 0) T F F ( a < 0) T F F
3026 * (0 < a) F F T (-a < 0) F F T
3027 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
3028 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
3029 * (a > 0) F F T (-a < 0) F F T
3030 * (0 > a) T F F ( a < 0) T F F
3031 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
3032 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
3034 * Note that exchanging the order of 0 and 'a' in the comparison simply
3035 * means that the value of 'a' should be negated.
3038 switch (expr
->operation
) {
3040 switch_order
= false;
3041 negate
= zero_on_left
;
3044 case ir_binop_greater
:
3045 switch_order
= false;
3046 negate
= !zero_on_left
;
3049 case ir_binop_lequal
:
3050 switch_order
= true;
3051 negate
= !zero_on_left
;
3054 case ir_binop_gequal
:
3055 switch_order
= true;
3056 negate
= zero_on_left
;
3060 /* This isn't the right kind of comparison afterall, so make sure
3061 * the whole condition is visited.
3069 src_ir
->accept(this);
3071 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
3072 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
3073 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
3074 * computing the condition.
3077 this->result
.negate
= ~this->result
.negate
;
3079 return switch_order
;
3083 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
3084 st_dst_reg
*l
, st_src_reg
*r
,
3085 st_src_reg
*cond
, bool cond_swap
)
3087 if (type
->is_record()) {
3088 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3089 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
3095 if (type
->is_array()) {
3096 for (unsigned int i
= 0; i
< type
->length
; i
++) {
3097 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
3102 if (type
->is_matrix()) {
3103 const struct glsl_type
*vec_type
;
3105 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
3106 type
->vector_elements
, 1);
3108 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
3109 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
3114 assert(type
->is_scalar() || type
->is_vector());
3116 l
->type
= type
->base_type
;
3117 r
->type
= type
->base_type
;
3119 st_src_reg l_src
= st_src_reg(*l
);
3120 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
3122 if (native_integers
) {
3123 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
3124 cond_swap
? l_src
: *r
,
3125 cond_swap
? *r
: l_src
);
3127 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
3128 cond_swap
? l_src
: *r
,
3129 cond_swap
? *r
: l_src
);
3132 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
3136 if (type
->is_dual_slot()) {
3138 if (r
->is_double_vertex_input
== false)
3144 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
3150 ir
->rhs
->accept(this);
3153 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
3157 int first_enabled_chan
= 0;
3159 ir_variable
*variable
= ir
->lhs
->variable_referenced();
3161 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
3162 variable
->data
.mode
== ir_var_shader_out
&&
3163 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
3164 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
3165 assert(ir
->lhs
->type
->is_scalar());
3166 assert(ir
->write_mask
== WRITEMASK_X
);
3168 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
3169 l
.writemask
= WRITEMASK_Z
;
3171 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
3172 l
.writemask
= WRITEMASK_Y
;
3174 } else if (ir
->write_mask
== 0) {
3175 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
3177 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
3180 l
.writemask
= u_bit_consecutive(0, num_elements
);
3182 /* The type is a struct or an array of (array of) structs. */
3183 l
.writemask
= WRITEMASK_XYZW
;
3186 l
.writemask
= ir
->write_mask
;
3189 for (int i
= 0; i
< 4; i
++) {
3190 if (l
.writemask
& (1 << i
)) {
3191 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3196 l
.writemask
= l
.writemask
<< dst_component
;
3198 /* Swizzle a small RHS vector into the channels being written.
3200 * glsl ir treats write_mask as dictating how many channels are
3201 * present on the RHS while TGSI treats write_mask as just
3202 * showing which channels of the vec4 RHS get written.
3204 for (int i
= 0; i
< 4; i
++) {
3205 if (l
.writemask
& (1 << i
))
3206 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3208 swizzles
[i
] = first_enabled_chan
;
3210 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3211 swizzles
[2], swizzles
[3]);
3214 assert(l
.file
!= PROGRAM_UNDEFINED
);
3215 assert(r
.file
!= PROGRAM_UNDEFINED
);
3217 if (ir
->condition
) {
3218 const bool switch_order
= this->process_move_condition(ir
->condition
);
3219 st_src_reg condition
= this->result
;
3221 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3222 } else if (ir
->rhs
->as_expression() &&
3223 this->instructions
.get_tail() &&
3224 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3225 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3226 type_size(ir
->lhs
->type
) == 1 &&
3227 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3228 /* To avoid emitting an extra MOV when assigning an expression to a
3229 * variable, emit the last instruction of the expression again, but
3230 * replace the destination register with the target of the assignment.
3231 * Dead code elimination will remove the original instruction.
3233 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3234 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3235 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3236 new_inst
->saturate
= inst
->saturate
;
3237 inst
->dead_mask
= inst
->dst
[0].writemask
;
3239 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3245 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3248 GLdouble stack_vals
[4] = { 0 };
3249 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3250 GLenum gl_type
= GL_NONE
;
3252 static int in_array
= 0;
3253 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3255 /* Unfortunately, 4 floats is all we can get into
3256 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3257 * aggregate constant and move each constant value into it. If we
3258 * get lucky, copy propagation will eliminate the extra moves.
3260 if (ir
->type
->is_record()) {
3261 st_src_reg temp_base
= get_temp(ir
->type
);
3262 st_dst_reg temp
= st_dst_reg(temp_base
);
3264 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3265 int size
= type_size(field_value
->type
);
3269 field_value
->accept(this);
3272 for (i
= 0; i
< (unsigned int)size
; i
++) {
3273 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3279 this->result
= temp_base
;
3283 if (ir
->type
->is_array()) {
3284 st_src_reg temp_base
= get_temp(ir
->type
);
3285 st_dst_reg temp
= st_dst_reg(temp_base
);
3286 int size
= type_size(ir
->type
->fields
.array
);
3291 for (i
= 0; i
< ir
->type
->length
; i
++) {
3292 ir
->array_elements
[i
]->accept(this);
3294 for (int j
= 0; j
< size
; j
++) {
3295 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3301 this->result
= temp_base
;
3306 if (ir
->type
->is_matrix()) {
3307 st_src_reg mat
= get_temp(ir
->type
);
3308 st_dst_reg mat_column
= st_dst_reg(mat
);
3310 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3311 switch (ir
->type
->base_type
) {
3312 case GLSL_TYPE_FLOAT
:
3313 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3315 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3316 src
.index
= add_constant(file
,
3318 ir
->type
->vector_elements
,
3321 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3323 case GLSL_TYPE_DOUBLE
:
3324 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3325 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3326 src
.index
= add_constant(file
,
3328 ir
->type
->vector_elements
,
3331 if (ir
->type
->vector_elements
>= 2) {
3332 mat_column
.writemask
= WRITEMASK_XY
;
3333 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3334 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3336 mat_column
.writemask
= WRITEMASK_X
;
3337 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3338 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3341 if (ir
->type
->vector_elements
> 2) {
3342 if (ir
->type
->vector_elements
== 4) {
3343 mat_column
.writemask
= WRITEMASK_ZW
;
3344 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3345 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3347 mat_column
.writemask
= WRITEMASK_Z
;
3348 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3349 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3350 mat_column
.writemask
= WRITEMASK_XYZW
;
3351 src
.swizzle
= SWIZZLE_XYZW
;
3357 unreachable("Illegal matrix constant type.\n");
3366 switch (ir
->type
->base_type
) {
3367 case GLSL_TYPE_FLOAT
:
3369 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3370 values
[i
].f
= ir
->value
.f
[i
];
3373 case GLSL_TYPE_DOUBLE
:
3374 gl_type
= GL_DOUBLE
;
3375 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3376 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3379 case GLSL_TYPE_INT64
:
3380 gl_type
= GL_INT64_ARB
;
3381 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3382 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(int64_t));
3385 case GLSL_TYPE_UINT64
:
3386 gl_type
= GL_UNSIGNED_INT64_ARB
;
3387 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3388 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(uint64_t));
3391 case GLSL_TYPE_UINT
:
3392 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3393 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3394 if (native_integers
)
3395 values
[i
].u
= ir
->value
.u
[i
];
3397 values
[i
].f
= ir
->value
.u
[i
];
3401 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3402 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3403 if (native_integers
)
3404 values
[i
].i
= ir
->value
.i
[i
];
3406 values
[i
].f
= ir
->value
.i
[i
];
3409 case GLSL_TYPE_BOOL
:
3410 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3411 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3412 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3416 assert(!"Non-float/uint/int/bool constant");
3419 this->result
= st_src_reg(file
, -1, ir
->type
);
3420 this->result
.index
= add_constant(file
,
3422 ir
->type
->vector_elements
,
3424 &this->result
.swizzle
);
3428 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3430 exec_node
*param
= ir
->actual_parameters
.get_head();
3431 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3432 ir_variable
*location
= deref
->variable_referenced();
3435 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3437 /* Calculate the surface offset */
3439 unsigned array_size
= 0, base
= 0;
3442 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3444 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3445 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3446 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3447 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3448 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3450 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3453 ir
->return_deref
->accept(this);
3454 st_dst_reg
dst(this->result
);
3455 dst
.writemask
= WRITEMASK_X
;
3457 glsl_to_tgsi_instruction
*inst
;
3459 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3460 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3461 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3462 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3463 st_src_reg_for_int(1));
3464 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3465 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3466 st_src_reg_for_int(-1));
3467 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3469 param
= param
->get_next();
3470 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3473 st_src_reg data
= this->result
, data2
= undef_src
;
3475 switch (ir
->callee
->intrinsic_id
) {
3476 case ir_intrinsic_atomic_counter_add
:
3477 opcode
= TGSI_OPCODE_ATOMUADD
;
3479 case ir_intrinsic_atomic_counter_min
:
3480 opcode
= TGSI_OPCODE_ATOMIMIN
;
3482 case ir_intrinsic_atomic_counter_max
:
3483 opcode
= TGSI_OPCODE_ATOMIMAX
;
3485 case ir_intrinsic_atomic_counter_and
:
3486 opcode
= TGSI_OPCODE_ATOMAND
;
3488 case ir_intrinsic_atomic_counter_or
:
3489 opcode
= TGSI_OPCODE_ATOMOR
;
3491 case ir_intrinsic_atomic_counter_xor
:
3492 opcode
= TGSI_OPCODE_ATOMXOR
;
3494 case ir_intrinsic_atomic_counter_exchange
:
3495 opcode
= TGSI_OPCODE_ATOMXCHG
;
3497 case ir_intrinsic_atomic_counter_comp_swap
: {
3498 opcode
= TGSI_OPCODE_ATOMCAS
;
3499 param
= param
->get_next();
3500 val
= ((ir_instruction
*)param
)->as_rvalue();
3502 data2
= this->result
;
3506 assert(!"Unexpected intrinsic");
3510 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3513 inst
->resource
= buffer
;
3517 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3519 exec_node
*param
= ir
->actual_parameters
.get_head();
3521 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3523 param
= param
->get_next();
3524 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3526 ir_constant
*const_block
= block
->as_constant();
3530 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3531 (const_block
? const_block
->value
.u
[0] : 0),
3535 block
->accept(this);
3536 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3537 *buffer
.reladdr
= this->result
;
3538 emit_arl(ir
, sampler_reladdr
, this->result
);
3541 /* Calculate the surface offset */
3542 offset
->accept(this);
3543 st_src_reg off
= this->result
;
3545 st_dst_reg dst
= undef_dst
;
3546 if (ir
->return_deref
) {
3547 ir
->return_deref
->accept(this);
3548 dst
= st_dst_reg(this->result
);
3549 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3552 glsl_to_tgsi_instruction
*inst
;
3554 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3555 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3556 if (dst
.type
== GLSL_TYPE_BOOL
)
3557 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3558 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3559 param
= param
->get_next();
3560 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3563 param
= param
->get_next();
3564 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3566 dst
.writemask
= write_mask
->value
.u
[0];
3568 dst
.type
= this->result
.type
;
3569 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3571 param
= param
->get_next();
3572 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3575 st_src_reg data
= this->result
, data2
= undef_src
;
3577 switch (ir
->callee
->intrinsic_id
) {
3578 case ir_intrinsic_ssbo_atomic_add
:
3579 opcode
= TGSI_OPCODE_ATOMUADD
;
3581 case ir_intrinsic_ssbo_atomic_min
:
3582 opcode
= TGSI_OPCODE_ATOMIMIN
;
3584 case ir_intrinsic_ssbo_atomic_max
:
3585 opcode
= TGSI_OPCODE_ATOMIMAX
;
3587 case ir_intrinsic_ssbo_atomic_and
:
3588 opcode
= TGSI_OPCODE_ATOMAND
;
3590 case ir_intrinsic_ssbo_atomic_or
:
3591 opcode
= TGSI_OPCODE_ATOMOR
;
3593 case ir_intrinsic_ssbo_atomic_xor
:
3594 opcode
= TGSI_OPCODE_ATOMXOR
;
3596 case ir_intrinsic_ssbo_atomic_exchange
:
3597 opcode
= TGSI_OPCODE_ATOMXCHG
;
3599 case ir_intrinsic_ssbo_atomic_comp_swap
:
3600 opcode
= TGSI_OPCODE_ATOMCAS
;
3601 param
= param
->get_next();
3602 val
= ((ir_instruction
*)param
)->as_rvalue();
3604 data2
= this->result
;
3607 assert(!"Unexpected intrinsic");
3611 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3614 param
= param
->get_next();
3615 ir_constant
*access
= NULL
;
3616 if (!param
->is_tail_sentinel()) {
3617 access
= ((ir_instruction
*)param
)->as_constant();
3621 /* The emit_asm() might have actually split the op into pieces, e.g. for
3622 * double stores. We have to go back and fix up all the generated ops.
3624 unsigned op
= inst
->op
;
3626 inst
->resource
= buffer
;
3628 inst
->buffer_access
= access
->value
.u
[0];
3630 if (inst
== this->instructions
.get_head_raw())
3632 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3634 if (inst
->op
== TGSI_OPCODE_UADD
) {
3635 if (inst
== this->instructions
.get_head_raw())
3637 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3639 } while (inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3643 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3645 switch (ir
->callee
->intrinsic_id
) {
3646 case ir_intrinsic_memory_barrier
:
3647 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3648 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3649 TGSI_MEMBAR_ATOMIC_BUFFER
|
3650 TGSI_MEMBAR_SHADER_IMAGE
|
3651 TGSI_MEMBAR_SHARED
));
3653 case ir_intrinsic_memory_barrier_atomic_counter
:
3654 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3655 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3657 case ir_intrinsic_memory_barrier_buffer
:
3658 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3659 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3661 case ir_intrinsic_memory_barrier_image
:
3662 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3663 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3665 case ir_intrinsic_memory_barrier_shared
:
3666 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3667 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3669 case ir_intrinsic_group_memory_barrier
:
3670 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3671 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3672 TGSI_MEMBAR_ATOMIC_BUFFER
|
3673 TGSI_MEMBAR_SHADER_IMAGE
|
3674 TGSI_MEMBAR_SHARED
|
3675 TGSI_MEMBAR_THREAD_GROUP
));
3678 assert(!"Unexpected memory barrier intrinsic");
3683 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3685 exec_node
*param
= ir
->actual_parameters
.get_head();
3687 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3689 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3691 /* Calculate the surface offset */
3692 offset
->accept(this);
3693 st_src_reg off
= this->result
;
3695 st_dst_reg dst
= undef_dst
;
3696 if (ir
->return_deref
) {
3697 ir
->return_deref
->accept(this);
3698 dst
= st_dst_reg(this->result
);
3699 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3702 glsl_to_tgsi_instruction
*inst
;
3704 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3705 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3706 inst
->resource
= buffer
;
3707 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3708 param
= param
->get_next();
3709 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3712 param
= param
->get_next();
3713 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3715 dst
.writemask
= write_mask
->value
.u
[0];
3717 dst
.type
= this->result
.type
;
3718 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3719 inst
->resource
= buffer
;
3721 param
= param
->get_next();
3722 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3725 st_src_reg data
= this->result
, data2
= undef_src
;
3727 switch (ir
->callee
->intrinsic_id
) {
3728 case ir_intrinsic_shared_atomic_add
:
3729 opcode
= TGSI_OPCODE_ATOMUADD
;
3731 case ir_intrinsic_shared_atomic_min
:
3732 opcode
= TGSI_OPCODE_ATOMIMIN
;
3734 case ir_intrinsic_shared_atomic_max
:
3735 opcode
= TGSI_OPCODE_ATOMIMAX
;
3737 case ir_intrinsic_shared_atomic_and
:
3738 opcode
= TGSI_OPCODE_ATOMAND
;
3740 case ir_intrinsic_shared_atomic_or
:
3741 opcode
= TGSI_OPCODE_ATOMOR
;
3743 case ir_intrinsic_shared_atomic_xor
:
3744 opcode
= TGSI_OPCODE_ATOMXOR
;
3746 case ir_intrinsic_shared_atomic_exchange
:
3747 opcode
= TGSI_OPCODE_ATOMXCHG
;
3749 case ir_intrinsic_shared_atomic_comp_swap
:
3750 opcode
= TGSI_OPCODE_ATOMCAS
;
3751 param
= param
->get_next();
3752 val
= ((ir_instruction
*)param
)->as_rvalue();
3754 data2
= this->result
;
3757 assert(!"Unexpected intrinsic");
3761 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3762 inst
->resource
= buffer
;
3767 get_image_qualifiers(ir_dereference
*ir
, const glsl_type
**type
,
3768 bool *memory_coherent
, bool *memory_volatile
,
3769 bool *memory_restrict
, unsigned *image_format
)
3772 switch (ir
->ir_type
) {
3773 case ir_type_dereference_record
: {
3774 ir_dereference_record
*deref_record
= ir
->as_dereference_record();
3775 const glsl_type
*struct_type
= deref_record
->record
->type
;
3777 for (unsigned i
= 0; i
< struct_type
->length
; i
++) {
3778 if (!strcmp(struct_type
->fields
.structure
[i
].name
,
3779 deref_record
->field
)) {
3780 *type
= struct_type
->fields
.structure
[i
].type
;
3782 struct_type
->fields
.structure
[i
].memory_coherent
;
3784 struct_type
->fields
.structure
[i
].memory_volatile
;
3786 struct_type
->fields
.structure
[i
].memory_restrict
;
3788 struct_type
->fields
.structure
[i
].image_format
;
3795 case ir_type_dereference_array
: {
3796 ir_dereference_array
*deref_arr
= ir
->as_dereference_array();
3797 get_image_qualifiers((ir_dereference
*)deref_arr
->array
, type
,
3798 memory_coherent
, memory_volatile
, memory_restrict
,
3803 case ir_type_dereference_variable
: {
3804 ir_variable
*var
= ir
->variable_referenced();
3806 *type
= var
->type
->without_array();
3807 *memory_coherent
= var
->data
.memory_coherent
;
3808 *memory_volatile
= var
->data
.memory_volatile
;
3809 *memory_restrict
= var
->data
.memory_restrict
;
3810 *image_format
= var
->data
.image_format
;
3820 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3822 exec_node
*param
= ir
->actual_parameters
.get_head();
3824 ir_dereference
*img
= (ir_dereference
*)param
;
3825 const ir_variable
*imgvar
= img
->variable_referenced();
3826 unsigned sampler_array_size
= 1, sampler_base
= 0;
3827 bool memory_coherent
= false, memory_volatile
= false, memory_restrict
= false;
3828 unsigned image_format
= 0;
3829 const glsl_type
*type
= NULL
;
3831 get_image_qualifiers(img
, &type
, &memory_coherent
, &memory_volatile
,
3832 &memory_restrict
, &image_format
);
3835 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3837 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3838 &index
, &reladdr
, !imgvar
->contains_bindless());
3840 image
.index
= index
;
3841 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3842 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3843 *image
.reladdr
= reladdr
;
3844 emit_arl(ir
, sampler_reladdr
, reladdr
);
3847 st_dst_reg dst
= undef_dst
;
3848 if (ir
->return_deref
) {
3849 ir
->return_deref
->accept(this);
3850 dst
= st_dst_reg(this->result
);
3851 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3854 glsl_to_tgsi_instruction
*inst
;
3856 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3857 dst
.writemask
= WRITEMASK_XYZ
;
3858 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3859 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3860 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3861 st_dst_reg dstres
= st_dst_reg(res
);
3862 dstres
.writemask
= WRITEMASK_W
;
3863 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3864 res
.swizzle
= SWIZZLE_WWWW
;
3865 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3867 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3869 st_dst_reg coord_dst
;
3870 coord
= get_temp(glsl_type::ivec4_type
);
3871 coord_dst
= st_dst_reg(coord
);
3872 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3873 param
= param
->get_next();
3874 ((ir_dereference
*)param
)->accept(this);
3875 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3876 coord
.swizzle
= SWIZZLE_XXXX
;
3877 switch (type
->coordinate_components()) {
3878 case 4: assert(!"unexpected coord count");
3880 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3882 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3885 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3886 param
= param
->get_next();
3887 ((ir_dereference
*)param
)->accept(this);
3888 st_src_reg sample
= this->result
;
3889 sample
.swizzle
= SWIZZLE_XXXX
;
3890 coord_dst
.writemask
= WRITEMASK_W
;
3891 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3892 coord
.swizzle
|= SWIZZLE_W
<< 9;
3895 param
= param
->get_next();
3896 if (!param
->is_tail_sentinel()) {
3897 ((ir_dereference
*)param
)->accept(this);
3898 arg1
= this->result
;
3899 param
= param
->get_next();
3902 if (!param
->is_tail_sentinel()) {
3903 ((ir_dereference
*)param
)->accept(this);
3904 arg2
= this->result
;
3905 param
= param
->get_next();
3908 assert(param
->is_tail_sentinel());
3911 switch (ir
->callee
->intrinsic_id
) {
3912 case ir_intrinsic_image_load
:
3913 opcode
= TGSI_OPCODE_LOAD
;
3915 case ir_intrinsic_image_store
:
3916 opcode
= TGSI_OPCODE_STORE
;
3918 case ir_intrinsic_image_atomic_add
:
3919 opcode
= TGSI_OPCODE_ATOMUADD
;
3921 case ir_intrinsic_image_atomic_min
:
3922 opcode
= TGSI_OPCODE_ATOMIMIN
;
3924 case ir_intrinsic_image_atomic_max
:
3925 opcode
= TGSI_OPCODE_ATOMIMAX
;
3927 case ir_intrinsic_image_atomic_and
:
3928 opcode
= TGSI_OPCODE_ATOMAND
;
3930 case ir_intrinsic_image_atomic_or
:
3931 opcode
= TGSI_OPCODE_ATOMOR
;
3933 case ir_intrinsic_image_atomic_xor
:
3934 opcode
= TGSI_OPCODE_ATOMXOR
;
3936 case ir_intrinsic_image_atomic_exchange
:
3937 opcode
= TGSI_OPCODE_ATOMXCHG
;
3939 case ir_intrinsic_image_atomic_comp_swap
:
3940 opcode
= TGSI_OPCODE_ATOMCAS
;
3943 assert(!"Unexpected intrinsic");
3947 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3948 if (opcode
== TGSI_OPCODE_STORE
)
3949 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3952 if (imgvar
->contains_bindless()) {
3954 inst
->resource
= this->result
;
3955 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
3956 SWIZZLE_X
, SWIZZLE_Y
);
3958 inst
->resource
= image
;
3959 inst
->sampler_array_size
= sampler_array_size
;
3960 inst
->sampler_base
= sampler_base
;
3963 inst
->tex_target
= type
->sampler_index();
3964 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3965 _mesa_get_shader_image_format(image_format
));
3967 if (memory_coherent
)
3968 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3969 if (memory_restrict
)
3970 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3971 if (memory_volatile
)
3972 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3976 glsl_to_tgsi_visitor::visit_generic_intrinsic(ir_call
*ir
, unsigned op
)
3978 ir
->return_deref
->accept(this);
3979 st_dst_reg dst
= st_dst_reg(this->result
);
3981 dst
.writemask
= u_bit_consecutive(0, ir
->return_deref
->var
->type
->vector_elements
);
3983 st_src_reg src
[4] = { undef_src
, undef_src
, undef_src
, undef_src
};
3984 unsigned num_src
= 0;
3985 foreach_in_list(ir_rvalue
, param
, &ir
->actual_parameters
) {
3986 assert(num_src
< ARRAY_SIZE(src
));
3988 this->result
.file
= PROGRAM_UNDEFINED
;
3989 param
->accept(this);
3990 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
3992 src
[num_src
] = this->result
;
3996 emit_asm(ir
, op
, dst
, src
[0], src
[1], src
[2], src
[3]);
4000 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
4002 ir_function_signature
*sig
= ir
->callee
;
4004 /* Filter out intrinsics */
4005 switch (sig
->intrinsic_id
) {
4006 case ir_intrinsic_atomic_counter_read
:
4007 case ir_intrinsic_atomic_counter_increment
:
4008 case ir_intrinsic_atomic_counter_predecrement
:
4009 case ir_intrinsic_atomic_counter_add
:
4010 case ir_intrinsic_atomic_counter_min
:
4011 case ir_intrinsic_atomic_counter_max
:
4012 case ir_intrinsic_atomic_counter_and
:
4013 case ir_intrinsic_atomic_counter_or
:
4014 case ir_intrinsic_atomic_counter_xor
:
4015 case ir_intrinsic_atomic_counter_exchange
:
4016 case ir_intrinsic_atomic_counter_comp_swap
:
4017 visit_atomic_counter_intrinsic(ir
);
4020 case ir_intrinsic_ssbo_load
:
4021 case ir_intrinsic_ssbo_store
:
4022 case ir_intrinsic_ssbo_atomic_add
:
4023 case ir_intrinsic_ssbo_atomic_min
:
4024 case ir_intrinsic_ssbo_atomic_max
:
4025 case ir_intrinsic_ssbo_atomic_and
:
4026 case ir_intrinsic_ssbo_atomic_or
:
4027 case ir_intrinsic_ssbo_atomic_xor
:
4028 case ir_intrinsic_ssbo_atomic_exchange
:
4029 case ir_intrinsic_ssbo_atomic_comp_swap
:
4030 visit_ssbo_intrinsic(ir
);
4033 case ir_intrinsic_memory_barrier
:
4034 case ir_intrinsic_memory_barrier_atomic_counter
:
4035 case ir_intrinsic_memory_barrier_buffer
:
4036 case ir_intrinsic_memory_barrier_image
:
4037 case ir_intrinsic_memory_barrier_shared
:
4038 case ir_intrinsic_group_memory_barrier
:
4039 visit_membar_intrinsic(ir
);
4042 case ir_intrinsic_shared_load
:
4043 case ir_intrinsic_shared_store
:
4044 case ir_intrinsic_shared_atomic_add
:
4045 case ir_intrinsic_shared_atomic_min
:
4046 case ir_intrinsic_shared_atomic_max
:
4047 case ir_intrinsic_shared_atomic_and
:
4048 case ir_intrinsic_shared_atomic_or
:
4049 case ir_intrinsic_shared_atomic_xor
:
4050 case ir_intrinsic_shared_atomic_exchange
:
4051 case ir_intrinsic_shared_atomic_comp_swap
:
4052 visit_shared_intrinsic(ir
);
4055 case ir_intrinsic_image_load
:
4056 case ir_intrinsic_image_store
:
4057 case ir_intrinsic_image_atomic_add
:
4058 case ir_intrinsic_image_atomic_min
:
4059 case ir_intrinsic_image_atomic_max
:
4060 case ir_intrinsic_image_atomic_and
:
4061 case ir_intrinsic_image_atomic_or
:
4062 case ir_intrinsic_image_atomic_xor
:
4063 case ir_intrinsic_image_atomic_exchange
:
4064 case ir_intrinsic_image_atomic_comp_swap
:
4065 case ir_intrinsic_image_size
:
4066 case ir_intrinsic_image_samples
:
4067 visit_image_intrinsic(ir
);
4070 case ir_intrinsic_shader_clock
:
4071 visit_generic_intrinsic(ir
, TGSI_OPCODE_CLOCK
);
4074 case ir_intrinsic_vote_all
:
4075 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ALL
);
4077 case ir_intrinsic_vote_any
:
4078 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_ANY
);
4080 case ir_intrinsic_vote_eq
:
4081 visit_generic_intrinsic(ir
, TGSI_OPCODE_VOTE_EQ
);
4083 case ir_intrinsic_ballot
:
4084 visit_generic_intrinsic(ir
, TGSI_OPCODE_BALLOT
);
4086 case ir_intrinsic_read_first_invocation
:
4087 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_FIRST
);
4089 case ir_intrinsic_read_invocation
:
4090 visit_generic_intrinsic(ir
, TGSI_OPCODE_READ_INVOC
);
4093 case ir_intrinsic_invalid
:
4094 case ir_intrinsic_generic_load
:
4095 case ir_intrinsic_generic_store
:
4096 case ir_intrinsic_generic_atomic_add
:
4097 case ir_intrinsic_generic_atomic_and
:
4098 case ir_intrinsic_generic_atomic_or
:
4099 case ir_intrinsic_generic_atomic_xor
:
4100 case ir_intrinsic_generic_atomic_min
:
4101 case ir_intrinsic_generic_atomic_max
:
4102 case ir_intrinsic_generic_atomic_exchange
:
4103 case ir_intrinsic_generic_atomic_comp_swap
:
4104 unreachable("Invalid intrinsic");
4109 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
4110 unsigned *array_elements
,
4112 st_src_reg
*indirect
,
4115 switch (tail
->ir_type
) {
4116 case ir_type_dereference_record
: {
4117 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
4118 const glsl_type
*struct_type
= deref_record
->record
->type
;
4119 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
4121 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
4123 assert(field_index
>= 0);
4124 *location
+= struct_type
->record_location_offset(field_index
);
4128 case ir_type_dereference_array
: {
4129 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
4130 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
4133 st_src_reg temp_reg
;
4134 st_dst_reg temp_dst
;
4136 temp_reg
= get_temp(glsl_type::uint_type
);
4137 temp_dst
= st_dst_reg(temp_reg
);
4138 temp_dst
.writemask
= 1;
4140 deref_arr
->array_index
->accept(this);
4141 if (*array_elements
!= 1)
4142 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
4144 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
4146 if (indirect
->file
== PROGRAM_UNDEFINED
)
4147 *indirect
= temp_reg
;
4149 temp_dst
= st_dst_reg(*indirect
);
4150 temp_dst
.writemask
= 1;
4151 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
4154 *index
+= array_index
->value
.u
[0] * *array_elements
;
4156 *array_elements
*= deref_arr
->array
->type
->length
;
4158 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
4167 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
4168 unsigned *array_size
,
4171 st_src_reg
*reladdr
,
4174 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
4175 unsigned location
= 0;
4176 ir_variable
*var
= ir
->variable_referenced();
4178 memset(reladdr
, 0, sizeof(*reladdr
));
4179 reladdr
->file
= PROGRAM_UNDEFINED
;
4185 location
= var
->data
.location
;
4186 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
4189 * If we end up with no indirect then adjust the base to the index,
4190 * and set the array size to 1.
4192 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
4198 assert(location
!= 0xffffffff);
4199 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4200 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
4205 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
4207 if (offset
.reladdr
|| offset
.reladdr2
) {
4208 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
4209 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
4210 tmp_dst
.writemask
= WRITEMASK_XY
;
4211 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
4219 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
4221 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
4222 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
4223 st_src_reg levels_src
, reladdr
;
4224 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
4225 glsl_to_tgsi_instruction
*inst
= NULL
;
4226 unsigned opcode
= TGSI_OPCODE_NOP
;
4227 const glsl_type
*sampler_type
= ir
->sampler
->type
;
4228 unsigned sampler_array_size
= 1, sampler_base
= 0;
4229 bool is_cube_array
= false, is_cube_shadow
= false;
4230 ir_variable
*var
= ir
->sampler
->variable_referenced();
4233 /* if we are a cube array sampler or a cube shadow */
4234 if (sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4235 is_cube_array
= sampler_type
->sampler_array
;
4236 is_cube_shadow
= sampler_type
->sampler_shadow
;
4239 if (ir
->coordinate
) {
4240 ir
->coordinate
->accept(this);
4242 /* Put our coords in a temp. We'll need to modify them for shadow,
4243 * projection, or LOD, so the only case we'd use it as-is is if
4244 * we're doing plain old texturing. The optimization passes on
4245 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
4247 coord
= get_temp(glsl_type::vec4_type
);
4248 coord_dst
= st_dst_reg(coord
);
4249 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
4250 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4253 if (ir
->projector
) {
4254 ir
->projector
->accept(this);
4255 projector
= this->result
;
4258 /* Storage for our result. Ideally for an assignment we'd be using
4259 * the actual storage for the result here, instead.
4261 result_src
= get_temp(ir
->type
);
4262 result_dst
= st_dst_reg(result_src
);
4263 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
4267 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
4269 ir
->offset
->accept(this);
4270 offset
[0] = this->result
;
4274 if (is_cube_array
|| is_cube_shadow
) {
4275 opcode
= TGSI_OPCODE_TXB2
;
4278 opcode
= TGSI_OPCODE_TXB
;
4280 ir
->lod_info
.bias
->accept(this);
4281 lod_info
= this->result
;
4283 ir
->offset
->accept(this);
4284 offset
[0] = this->result
;
4288 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4289 opcode
= TGSI_OPCODE_TEX_LZ
;
4291 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4292 ir
->lod_info
.lod
->accept(this);
4293 lod_info
= this->result
;
4296 ir
->offset
->accept(this);
4297 offset
[0] = this->result
;
4301 opcode
= TGSI_OPCODE_TXD
;
4302 ir
->lod_info
.grad
.dPdx
->accept(this);
4304 ir
->lod_info
.grad
.dPdy
->accept(this);
4307 ir
->offset
->accept(this);
4308 offset
[0] = this->result
;
4312 opcode
= TGSI_OPCODE_TXQ
;
4313 ir
->lod_info
.lod
->accept(this);
4314 lod_info
= this->result
;
4316 case ir_query_levels
:
4317 opcode
= TGSI_OPCODE_TXQ
;
4318 lod_info
= undef_src
;
4319 levels_src
= get_temp(ir
->type
);
4322 if (this->has_tex_txf_lz
&& ir
->lod_info
.lod
->is_zero()) {
4323 opcode
= TGSI_OPCODE_TXF_LZ
;
4325 opcode
= TGSI_OPCODE_TXF
;
4326 ir
->lod_info
.lod
->accept(this);
4327 lod_info
= this->result
;
4330 ir
->offset
->accept(this);
4331 offset
[0] = this->result
;
4335 opcode
= TGSI_OPCODE_TXF
;
4336 ir
->lod_info
.sample_index
->accept(this);
4337 sample_index
= this->result
;
4340 opcode
= TGSI_OPCODE_TG4
;
4341 ir
->lod_info
.component
->accept(this);
4342 component
= this->result
;
4344 ir
->offset
->accept(this);
4345 if (ir
->offset
->type
->is_array()) {
4346 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4347 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4348 offset
[i
] = this->result
;
4349 offset
[i
].index
+= i
* type_size(elt_type
);
4350 offset
[i
].type
= elt_type
->base_type
;
4351 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4352 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4355 offset
[0] = canonicalize_gather_offset(this->result
);
4360 opcode
= TGSI_OPCODE_LODQ
;
4362 case ir_texture_samples
:
4363 opcode
= TGSI_OPCODE_TXQS
;
4365 case ir_samples_identical
:
4366 unreachable("Unexpected ir_samples_identical opcode");
4369 if (ir
->projector
) {
4370 if (opcode
== TGSI_OPCODE_TEX
) {
4371 /* Slot the projector in as the last component of the coord. */
4372 coord_dst
.writemask
= WRITEMASK_W
;
4373 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4374 coord_dst
.writemask
= WRITEMASK_XYZW
;
4375 opcode
= TGSI_OPCODE_TXP
;
4377 st_src_reg coord_w
= coord
;
4378 coord_w
.swizzle
= SWIZZLE_WWWW
;
4380 /* For the other TEX opcodes there's no projective version
4381 * since the last slot is taken up by LOD info. Do the
4382 * projective divide now.
4384 coord_dst
.writemask
= WRITEMASK_W
;
4385 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4387 /* In the case where we have to project the coordinates "by hand,"
4388 * the shadow comparator value must also be projected.
4390 st_src_reg tmp_src
= coord
;
4391 if (ir
->shadow_comparator
) {
4392 /* Slot the shadow value in as the second to last component of the
4395 ir
->shadow_comparator
->accept(this);
4397 tmp_src
= get_temp(glsl_type::vec4_type
);
4398 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4400 /* Projective division not allowed for array samplers. */
4401 assert(!sampler_type
->sampler_array
);
4403 tmp_dst
.writemask
= WRITEMASK_Z
;
4404 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4406 tmp_dst
.writemask
= WRITEMASK_XY
;
4407 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4410 coord_dst
.writemask
= WRITEMASK_XYZ
;
4411 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4413 coord_dst
.writemask
= WRITEMASK_XYZW
;
4414 coord
.swizzle
= SWIZZLE_XYZW
;
4418 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4419 * comparator was put in the correct place (and projected) by the code,
4420 * above, that handles by-hand projection.
4422 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4423 /* Slot the shadow value in as the second to last component of the
4426 ir
->shadow_comparator
->accept(this);
4428 if (is_cube_array
) {
4429 cube_sc
= get_temp(glsl_type::float_type
);
4430 cube_sc_dst
= st_dst_reg(cube_sc
);
4431 cube_sc_dst
.writemask
= WRITEMASK_X
;
4432 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4433 cube_sc_dst
.writemask
= WRITEMASK_X
;
4436 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4437 sampler_type
->sampler_array
) ||
4438 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4439 coord_dst
.writemask
= WRITEMASK_W
;
4441 coord_dst
.writemask
= WRITEMASK_Z
;
4443 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4444 coord_dst
.writemask
= WRITEMASK_XYZW
;
4448 if (ir
->op
== ir_txf_ms
) {
4449 coord_dst
.writemask
= WRITEMASK_W
;
4450 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4451 coord_dst
.writemask
= WRITEMASK_XYZW
;
4452 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4453 opcode
== TGSI_OPCODE_TXF
) {
4454 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4455 coord_dst
.writemask
= WRITEMASK_W
;
4456 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4457 coord_dst
.writemask
= WRITEMASK_XYZW
;
4460 st_src_reg
sampler(PROGRAM_SAMPLER
, 0, GLSL_TYPE_UINT
);
4463 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4464 &index
, &reladdr
, !var
->contains_bindless());
4466 sampler
.index
= index
;
4467 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4468 sampler
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4469 *sampler
.reladdr
= reladdr
;
4470 emit_arl(ir
, sampler_reladdr
, reladdr
);
4473 if (opcode
== TGSI_OPCODE_TXD
)
4474 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4475 else if (opcode
== TGSI_OPCODE_TXQ
) {
4476 if (ir
->op
== ir_query_levels
) {
4477 /* the level is stored in W */
4478 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4479 result_dst
.writemask
= WRITEMASK_X
;
4480 levels_src
.swizzle
= SWIZZLE_WWWW
;
4481 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4483 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4484 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4485 inst
= emit_asm(ir
, opcode
, result_dst
);
4486 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4487 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4488 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4489 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4490 } else if (opcode
== TGSI_OPCODE_TG4
) {
4491 if (is_cube_array
&& ir
->shadow_comparator
) {
4492 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4494 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4497 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4499 if (ir
->shadow_comparator
)
4500 inst
->tex_shadow
= GL_TRUE
;
4502 if (var
->contains_bindless()) {
4503 ir
->sampler
->accept(this);
4504 inst
->resource
= this->result
;
4505 inst
->resource
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
,
4506 SWIZZLE_X
, SWIZZLE_Y
);
4508 inst
->resource
= sampler
;
4509 inst
->sampler_array_size
= sampler_array_size
;
4510 inst
->sampler_base
= sampler_base
;
4514 if (!inst
->tex_offsets
)
4515 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4517 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4518 inst
->tex_offsets
[i
] = offset
[i
];
4519 inst
->tex_offset_num_offset
= i
;
4522 inst
->tex_target
= sampler_type
->sampler_index();
4523 inst
->tex_type
= ir
->type
->base_type
;
4525 this->result
= result_src
;
4529 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4531 assert(!ir
->get_value());
4533 emit_asm(ir
, TGSI_OPCODE_RET
);
4537 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4539 if (ir
->condition
) {
4540 ir
->condition
->accept(this);
4541 st_src_reg condition
= this->result
;
4543 /* Convert the bool condition to a float so we can negate. */
4544 if (native_integers
) {
4545 st_src_reg temp
= get_temp(ir
->condition
->type
);
4546 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4547 condition
, st_src_reg_for_float(1.0));
4551 condition
.negate
= ~condition
.negate
;
4552 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4554 /* unconditional kil */
4555 emit_asm(ir
, TGSI_OPCODE_KILL
);
4560 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4563 glsl_to_tgsi_instruction
*if_inst
;
4565 ir
->condition
->accept(this);
4566 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4568 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4570 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4572 this->instructions
.push_tail(if_inst
);
4574 visit_exec_list(&ir
->then_instructions
, this);
4576 if (!ir
->else_instructions
.is_empty()) {
4577 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4578 visit_exec_list(&ir
->else_instructions
, this);
4581 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4586 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4588 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4590 ir
->stream
->accept(this);
4591 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4595 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4597 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4599 ir
->stream
->accept(this);
4600 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4604 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4606 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4607 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4609 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4612 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4614 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4616 result
.file
= PROGRAM_UNDEFINED
;
4623 num_input_arrays
= 0;
4624 num_output_arrays
= 0;
4626 num_address_regs
= 0;
4629 indirect_addr_consts
= false;
4630 wpos_transform_const
= -1;
4632 native_integers
= false;
4633 mem_ctx
= ralloc_context(NULL
);
4636 shader_program
= NULL
;
4641 use_shared_memory
= false;
4642 has_tex_txf_lz
= false;
4646 static void var_destroy(struct hash_entry
*entry
)
4648 variable_storage
*storage
= (variable_storage
*)entry
->data
;
4653 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4655 _mesa_hash_table_destroy(variables
, var_destroy
);
4657 ralloc_free(mem_ctx
);
4660 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4667 * Count resources used by the given gpu program (number of texture
4671 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4673 v
->samplers_used
= 0;
4676 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4677 if (inst
->info
->is_tex
) {
4678 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4679 unsigned idx
= inst
->sampler_base
+ i
;
4680 v
->samplers_used
|= 1u << idx
;
4682 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4683 v
->sampler_types
[idx
] = inst
->tex_type
;
4684 v
->sampler_targets
[idx
] =
4685 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4687 if (inst
->tex_shadow
) {
4688 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4693 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4694 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4696 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4697 is_resource_instruction(inst
->op
) ||
4698 inst
->op
== TGSI_OPCODE_STORE
)) {
4699 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4700 v
->use_shared_memory
= true;
4701 } else if (inst
->resource
.file
== PROGRAM_IMAGE
) {
4702 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4703 unsigned idx
= inst
->sampler_base
+ i
;
4704 v
->images_used
|= 1 << idx
;
4705 v
->image_targets
[idx
] =
4706 st_translate_texture_target(inst
->tex_target
, false);
4707 v
->image_formats
[idx
] = inst
->image_format
;
4712 prog
->SamplersUsed
= v
->samplers_used
;
4714 if (v
->shader_program
!= NULL
)
4715 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4719 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4720 * are read from the given src in this instruction
4723 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4725 int read_mask
= 0, comp
;
4727 /* Now, given the src swizzle and the written channels, find which
4728 * components are actually read
4730 for (comp
= 0; comp
< 4; ++comp
) {
4731 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4733 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4734 read_mask
|= 1 << coord
;
4741 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4742 * instruction is the first instruction to write to register T0. There are
4743 * several lowering passes done in GLSL IR (e.g. branches and
4744 * relative addressing) that create a large number of conditional assignments
4745 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4747 * Here is why this conversion is safe:
4748 * CMP T0, T1 T2 T0 can be expanded to:
4754 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4755 * as the original program. If (T1 < 0.0) evaluates to false, executing
4756 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4757 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4758 * because any instruction that was going to read from T0 after this was going
4759 * to read a garbage value anyway.
4762 glsl_to_tgsi_visitor::simplify_cmp(void)
4764 int tempWritesSize
= 0;
4765 unsigned *tempWrites
= NULL
;
4766 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4768 memset(outputWrites
, 0, sizeof(outputWrites
));
4770 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4771 unsigned prevWriteMask
= 0;
4773 /* Give up if we encounter relative addressing or flow control. */
4774 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4775 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4776 inst
->info
->is_branch
||
4777 inst
->op
== TGSI_OPCODE_CONT
||
4778 inst
->op
== TGSI_OPCODE_END
||
4779 inst
->op
== TGSI_OPCODE_RET
) {
4783 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4784 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4785 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4786 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4787 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4788 if (inst
->dst
[0].index
>= tempWritesSize
) {
4789 const int inc
= 4096;
4791 tempWrites
= (unsigned*)
4793 (tempWritesSize
+ inc
) * sizeof(unsigned));
4797 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4798 tempWritesSize
+= inc
;
4801 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4802 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4806 /* For a CMP to be considered a conditional write, the destination
4807 * register and source register two must be the same. */
4808 if (inst
->op
== TGSI_OPCODE_CMP
4809 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4810 && inst
->src
[2].file
== inst
->dst
[0].file
4811 && inst
->src
[2].index
== inst
->dst
[0].index
4812 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4814 inst
->op
= TGSI_OPCODE_MOV
;
4815 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4816 inst
->src
[0] = inst
->src
[1];
4823 /* Replaces all references to a temporary register index with another index. */
4825 glsl_to_tgsi_visitor::rename_temp_registers(struct rename_reg_pair
*renames
)
4827 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4829 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4830 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4831 int old_idx
= inst
->src
[j
].index
;
4832 if (renames
[old_idx
].valid
)
4833 inst
->src
[j
].index
= renames
[old_idx
].new_reg
;
4837 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4838 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4839 int old_idx
= inst
->tex_offsets
[j
].index
;
4840 if (renames
[old_idx
].valid
)
4841 inst
->tex_offsets
[j
].index
= renames
[old_idx
].new_reg
;
4845 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
4846 int old_idx
= inst
->resource
.index
;
4847 if (renames
[old_idx
].valid
)
4848 inst
->resource
.index
= renames
[old_idx
].new_reg
;
4851 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4852 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4853 int old_idx
= inst
->dst
[j
].index
;
4854 if (renames
[old_idx
].valid
)
4855 inst
->dst
[j
].index
= renames
[old_idx
].new_reg
;}
4861 glsl_to_tgsi_visitor::get_first_temp_write(int *first_writes
)
4863 int depth
= 0; /* loop depth */
4864 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4867 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4868 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4869 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4870 if (first_writes
[inst
->dst
[j
].index
] == -1)
4871 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4875 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4878 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4888 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4890 int depth
= 0; /* loop depth */
4891 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4894 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4895 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4896 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4897 if (first_reads
[inst
->src
[j
].index
] == -1)
4898 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4901 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4902 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4903 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4904 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4907 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4910 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4920 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4922 int depth
= 0; /* loop depth */
4923 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4926 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4927 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4928 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4929 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4931 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4932 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4933 if (first_writes
[inst
->dst
[j
].index
] == -1)
4934 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4935 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4938 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4939 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4940 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4942 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4945 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4948 for (k
= 0; k
< this->next_temp
; k
++) {
4949 if (last_reads
[k
] == -2) {
4961 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4963 int depth
= 0; /* loop depth */
4967 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4968 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4969 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4970 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4973 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4975 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4977 for (k
= 0; k
< this->next_temp
; k
++) {
4978 if (last_writes
[k
] == -2) {
4989 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4990 * channels for copy propagation and updates following instructions to
4991 * use the original versions.
4993 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4994 * will occur. As an example, a TXP production before this pass:
4996 * 0: MOV TEMP[1], INPUT[4].xyyy;
4997 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4998 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
5002 * 0: MOV TEMP[1], INPUT[4].xyyy;
5003 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5004 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5006 * which allows for dead code elimination on TEMP[1]'s writes.
5009 glsl_to_tgsi_visitor::copy_propagate(void)
5011 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
5012 glsl_to_tgsi_instruction
*,
5013 this->next_temp
* 4);
5014 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5017 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5018 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5019 || inst
->dst
[0].index
< this->next_temp
);
5021 /* First, do any copy propagation possible into the src regs. */
5022 for (int r
= 0; r
< 3; r
++) {
5023 glsl_to_tgsi_instruction
*first
= NULL
;
5025 int acp_base
= inst
->src
[r
].index
* 4;
5027 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
5028 inst
->src
[r
].reladdr
||
5029 inst
->src
[r
].reladdr2
)
5032 /* See if we can find entries in the ACP consisting of MOVs
5033 * from the same src register for all the swizzled channels
5034 * of this src register reference.
5036 for (int i
= 0; i
< 4; i
++) {
5037 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5038 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
5045 assert(acp_level
[acp_base
+ src_chan
] <= level
);
5050 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
5051 first
->src
[0].index
!= copy_chan
->src
[0].index
||
5052 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
5053 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
5061 /* We've now validated that we can copy-propagate to
5062 * replace this src register reference. Do it.
5064 inst
->src
[r
].file
= first
->src
[0].file
;
5065 inst
->src
[r
].index
= first
->src
[0].index
;
5066 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
5067 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
5068 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
5069 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
5072 for (int i
= 0; i
< 4; i
++) {
5073 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
5074 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
5075 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
5077 inst
->src
[r
].swizzle
= swizzle
;
5082 case TGSI_OPCODE_BGNLOOP
:
5083 case TGSI_OPCODE_ENDLOOP
:
5084 /* End of a basic block, clear the ACP entirely. */
5085 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5088 case TGSI_OPCODE_IF
:
5089 case TGSI_OPCODE_UIF
:
5093 case TGSI_OPCODE_ENDIF
:
5094 case TGSI_OPCODE_ELSE
:
5095 /* Clear all channels written inside the block from the ACP, but
5096 * leaving those that were not touched.
5098 for (int r
= 0; r
< this->next_temp
; r
++) {
5099 for (int c
= 0; c
< 4; c
++) {
5100 if (!acp
[4 * r
+ c
])
5103 if (acp_level
[4 * r
+ c
] >= level
)
5104 acp
[4 * r
+ c
] = NULL
;
5107 if (inst
->op
== TGSI_OPCODE_ENDIF
)
5112 /* Continuing the block, clear any written channels from
5115 for (int d
= 0; d
< 2; d
++) {
5116 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
5117 /* Any temporary might be written, so no copy propagation
5118 * across this instruction.
5120 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
5121 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
5122 inst
->dst
[d
].reladdr
) {
5123 /* Any output might be written, so no copy propagation
5124 * from outputs across this instruction.
5126 for (int r
= 0; r
< this->next_temp
; r
++) {
5127 for (int c
= 0; c
< 4; c
++) {
5128 if (!acp
[4 * r
+ c
])
5131 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
5132 acp
[4 * r
+ c
] = NULL
;
5135 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
5136 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
5137 /* Clear where it's used as dst. */
5138 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
5139 for (int c
= 0; c
< 4; c
++) {
5140 if (inst
->dst
[d
].writemask
& (1 << c
))
5141 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
5145 /* Clear where it's used as src. */
5146 for (int r
= 0; r
< this->next_temp
; r
++) {
5147 for (int c
= 0; c
< 4; c
++) {
5148 if (!acp
[4 * r
+ c
])
5151 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
5153 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
5154 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
5155 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
5156 acp
[4 * r
+ c
] = NULL
;
5165 /* If this is a copy, add it to the ACP. */
5166 if (inst
->op
== TGSI_OPCODE_MOV
&&
5167 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
5168 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
5169 inst
->dst
[0].index
== inst
->src
[0].index
) &&
5170 !inst
->dst
[0].reladdr
&&
5171 !inst
->dst
[0].reladdr2
&&
5173 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
5174 !inst
->src
[0].reladdr
&&
5175 !inst
->src
[0].reladdr2
&&
5176 !inst
->src
[0].negate
&&
5177 !inst
->src
[0].abs
) {
5178 for (int i
= 0; i
< 4; i
++) {
5179 if (inst
->dst
[0].writemask
& (1 << i
)) {
5180 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
5181 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
5187 ralloc_free(acp_level
);
5192 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
5195 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
5196 * will occur. As an example, a TXP production after copy propagation but
5199 * 0: MOV TEMP[1], INPUT[4].xyyy;
5200 * 1: MOV TEMP[1].w, INPUT[4].wwww;
5201 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5203 * and after this pass:
5205 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
5208 glsl_to_tgsi_visitor::eliminate_dead_code(void)
5210 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
5211 glsl_to_tgsi_instruction
*,
5212 this->next_temp
* 4);
5213 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
5217 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5218 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
5219 || inst
->dst
[0].index
< this->next_temp
);
5222 case TGSI_OPCODE_BGNLOOP
:
5223 case TGSI_OPCODE_ENDLOOP
:
5224 case TGSI_OPCODE_CONT
:
5225 case TGSI_OPCODE_BRK
:
5226 /* End of a basic block, clear the write array entirely.
5228 * This keeps us from killing dead code when the writes are
5229 * on either side of a loop, even when the register isn't touched
5230 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
5231 * dead code of this type, so it shouldn't make a difference as long as
5232 * the dead code elimination pass in the GLSL compiler does its job.
5234 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5237 case TGSI_OPCODE_ENDIF
:
5238 case TGSI_OPCODE_ELSE
:
5239 /* Promote the recorded level of all channels written inside the
5240 * preceding if or else block to the level above the if/else block.
5242 for (int r
= 0; r
< this->next_temp
; r
++) {
5243 for (int c
= 0; c
< 4; c
++) {
5244 if (!writes
[4 * r
+ c
])
5247 if (write_level
[4 * r
+ c
] == level
)
5248 write_level
[4 * r
+ c
] = level
-1;
5251 if(inst
->op
== TGSI_OPCODE_ENDIF
)
5255 case TGSI_OPCODE_IF
:
5256 case TGSI_OPCODE_UIF
:
5258 /* fallthrough to default case to mark the condition as read */
5260 /* Continuing the block, clear any channels from the write array that
5261 * are read by this instruction.
5263 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
5264 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
5265 /* Any temporary might be read, so no dead code elimination
5266 * across this instruction.
5268 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5269 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
5270 /* Clear where it's used as src. */
5271 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
5272 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
5273 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
5274 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
5276 for (int c
= 0; c
< 4; c
++) {
5277 if (src_chans
& (1 << c
))
5278 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
5282 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
5283 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
5284 /* Any temporary might be read, so no dead code elimination
5285 * across this instruction.
5287 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
5288 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
5289 /* Clear where it's used as src. */
5290 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
5291 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
5292 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
5293 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
5295 for (int c
= 0; c
< 4; c
++) {
5296 if (src_chans
& (1 << c
))
5297 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
5302 if (inst
->resource
.file
== PROGRAM_TEMPORARY
) {
5305 src_chans
= 1 << GET_SWZ(inst
->resource
.swizzle
, 0);
5306 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 1);
5307 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 2);
5308 src_chans
|= 1 << GET_SWZ(inst
->resource
.swizzle
, 3);
5310 for (int c
= 0; c
< 4; c
++) {
5311 if (src_chans
& (1 << c
))
5312 writes
[4 * inst
->resource
.index
+ c
] = NULL
;
5319 /* If this instruction writes to a temporary, add it to the write array.
5320 * If there is already an instruction in the write array for one or more
5321 * of the channels, flag that channel write as dead.
5323 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
5324 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5325 !inst
->dst
[i
].reladdr
) {
5326 for (int c
= 0; c
< 4; c
++) {
5327 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5328 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5329 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5332 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5334 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5335 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5342 /* Anything still in the write array at this point is dead code. */
5343 for (int r
= 0; r
< this->next_temp
; r
++) {
5344 for (int c
= 0; c
< 4; c
++) {
5345 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5347 inst
->dead_mask
|= (1 << c
);
5351 /* Now actually remove the instructions that are completely dead and update
5352 * the writemask of other instructions with dead channels.
5354 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5355 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5357 /* No amount of dead masks should remove memory stores */
5358 if (inst
->info
->is_store
)
5361 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5366 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5367 if (inst
->dead_mask
== WRITEMASK_XY
||
5368 inst
->dead_mask
== WRITEMASK_ZW
)
5369 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5371 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5375 ralloc_free(write_level
);
5376 ralloc_free(writes
);
5381 /* merge DFRACEXP instructions into one. */
5383 glsl_to_tgsi_visitor::merge_two_dsts(void)
5385 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5386 glsl_to_tgsi_instruction
*inst2
;
5388 if (num_inst_dst_regs(inst
) != 2)
5391 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5392 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5395 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5398 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5399 inst
->src
[0].index
== inst2
->src
[0].index
&&
5400 inst
->src
[0].type
== inst2
->src
[0].type
&&
5401 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5403 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5409 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5411 inst
->dst
[0] = inst2
->dst
[0];
5412 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5413 inst
->dst
[1] = inst2
->dst
[1];
5424 /* Merges temporary registers together where possible to reduce the number of
5425 * registers needed to run a program.
5427 * Produces optimal code only after copy propagation and dead code elimination
5430 glsl_to_tgsi_visitor::merge_registers(void)
5432 int *last_reads
= ralloc_array(mem_ctx
, int, this->next_temp
);
5433 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5434 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5437 /* Read the indices of the last read and first write to each temp register
5438 * into an array so that we don't have to traverse the instruction list as
5440 for (i
= 0; i
< this->next_temp
; i
++) {
5442 first_writes
[i
] = -1;
5444 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5446 /* Start looking for registers with non-overlapping usages that can be
5447 * merged together. */
5448 for (i
= 0; i
< this->next_temp
; i
++) {
5449 /* Don't touch unused registers. */
5450 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5452 for (j
= 0; j
< this->next_temp
; j
++) {
5453 /* Don't touch unused registers. */
5454 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5456 /* We can merge the two registers if the first write to j is after or
5457 * in the same instruction as the last read from i. Note that the
5458 * register at index i will always be used earlier or at the same time
5459 * as the register at index j. */
5460 if (first_writes
[i
] <= first_writes
[j
] &&
5461 last_reads
[i
] <= first_writes
[j
]) {
5462 renames
[j
].new_reg
= i
;
5463 renames
[j
].valid
= true;
5465 /* Update the first_writes and last_reads arrays with the new
5466 * values for the merged register index, and mark the newly unused
5467 * register index as such. */
5468 assert(last_reads
[j
] >= last_reads
[i
]);
5469 last_reads
[i
] = last_reads
[j
];
5470 first_writes
[j
] = -1;
5476 rename_temp_registers(renames
);
5477 ralloc_free(renames
);
5478 ralloc_free(last_reads
);
5479 ralloc_free(first_writes
);
5482 /* Reassign indices to temporary registers by reusing unused indices created
5483 * by optimization passes. */
5485 glsl_to_tgsi_visitor::renumber_registers(void)
5489 int *first_writes
= ralloc_array(mem_ctx
, int, this->next_temp
);
5490 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5492 for (i
= 0; i
< this->next_temp
; i
++) {
5493 first_writes
[i
] = -1;
5495 get_first_temp_write(first_writes
);
5497 for (i
= 0; i
< this->next_temp
; i
++) {
5498 if (first_writes
[i
] < 0) continue;
5499 if (i
!= new_index
) {
5500 renames
[i
].new_reg
= new_index
;
5501 renames
[i
].valid
= true;
5506 rename_temp_registers(renames
);
5507 this->next_temp
= new_index
;
5508 ralloc_free(renames
);
5509 ralloc_free(first_writes
);
5512 /* ------------------------- TGSI conversion stuff -------------------------- */
5515 * Intermediate state used during shader translation.
5517 struct st_translate
{
5518 struct ureg_program
*ureg
;
5520 unsigned temps_size
;
5521 struct ureg_dst
*temps
;
5523 struct ureg_dst
*arrays
;
5524 unsigned num_temp_arrays
;
5525 struct ureg_src
*constants
;
5527 struct ureg_src
*immediates
;
5529 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5530 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5531 struct ureg_dst address
[3];
5532 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5533 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5534 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5535 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5536 struct ureg_src shared_memory
;
5537 unsigned *array_sizes
;
5538 struct inout_decl
*input_decls
;
5539 unsigned num_input_decls
;
5540 struct inout_decl
*output_decls
;
5541 unsigned num_output_decls
;
5543 const ubyte
*inputMapping
;
5544 const ubyte
*outputMapping
;
5546 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5549 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5551 _mesa_sysval_to_semantic(unsigned sysval
)
5555 case SYSTEM_VALUE_VERTEX_ID
:
5556 return TGSI_SEMANTIC_VERTEXID
;
5557 case SYSTEM_VALUE_INSTANCE_ID
:
5558 return TGSI_SEMANTIC_INSTANCEID
;
5559 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5560 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5561 case SYSTEM_VALUE_BASE_VERTEX
:
5562 return TGSI_SEMANTIC_BASEVERTEX
;
5563 case SYSTEM_VALUE_BASE_INSTANCE
:
5564 return TGSI_SEMANTIC_BASEINSTANCE
;
5565 case SYSTEM_VALUE_DRAW_ID
:
5566 return TGSI_SEMANTIC_DRAWID
;
5568 /* Geometry shader */
5569 case SYSTEM_VALUE_INVOCATION_ID
:
5570 return TGSI_SEMANTIC_INVOCATIONID
;
5572 /* Fragment shader */
5573 case SYSTEM_VALUE_FRAG_COORD
:
5574 return TGSI_SEMANTIC_POSITION
;
5575 case SYSTEM_VALUE_FRONT_FACE
:
5576 return TGSI_SEMANTIC_FACE
;
5577 case SYSTEM_VALUE_SAMPLE_ID
:
5578 return TGSI_SEMANTIC_SAMPLEID
;
5579 case SYSTEM_VALUE_SAMPLE_POS
:
5580 return TGSI_SEMANTIC_SAMPLEPOS
;
5581 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5582 return TGSI_SEMANTIC_SAMPLEMASK
;
5583 case SYSTEM_VALUE_HELPER_INVOCATION
:
5584 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5586 /* Tessellation shader */
5587 case SYSTEM_VALUE_TESS_COORD
:
5588 return TGSI_SEMANTIC_TESSCOORD
;
5589 case SYSTEM_VALUE_VERTICES_IN
:
5590 return TGSI_SEMANTIC_VERTICESIN
;
5591 case SYSTEM_VALUE_PRIMITIVE_ID
:
5592 return TGSI_SEMANTIC_PRIMID
;
5593 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5594 return TGSI_SEMANTIC_TESSOUTER
;
5595 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5596 return TGSI_SEMANTIC_TESSINNER
;
5598 /* Compute shader */
5599 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5600 return TGSI_SEMANTIC_THREAD_ID
;
5601 case SYSTEM_VALUE_WORK_GROUP_ID
:
5602 return TGSI_SEMANTIC_BLOCK_ID
;
5603 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5604 return TGSI_SEMANTIC_GRID_SIZE
;
5605 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5606 return TGSI_SEMANTIC_BLOCK_SIZE
;
5608 /* ARB_shader_ballot */
5609 case SYSTEM_VALUE_SUBGROUP_SIZE
:
5610 return TGSI_SEMANTIC_SUBGROUP_SIZE
;
5611 case SYSTEM_VALUE_SUBGROUP_INVOCATION
:
5612 return TGSI_SEMANTIC_SUBGROUP_INVOCATION
;
5613 case SYSTEM_VALUE_SUBGROUP_EQ_MASK
:
5614 return TGSI_SEMANTIC_SUBGROUP_EQ_MASK
;
5615 case SYSTEM_VALUE_SUBGROUP_GE_MASK
:
5616 return TGSI_SEMANTIC_SUBGROUP_GE_MASK
;
5617 case SYSTEM_VALUE_SUBGROUP_GT_MASK
:
5618 return TGSI_SEMANTIC_SUBGROUP_GT_MASK
;
5619 case SYSTEM_VALUE_SUBGROUP_LE_MASK
:
5620 return TGSI_SEMANTIC_SUBGROUP_LE_MASK
;
5621 case SYSTEM_VALUE_SUBGROUP_LT_MASK
:
5622 return TGSI_SEMANTIC_SUBGROUP_LT_MASK
;
5625 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5626 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5627 case SYSTEM_VALUE_VERTEX_CNT
:
5629 assert(!"Unexpected SYSTEM_VALUE_ enum");
5630 return TGSI_SEMANTIC_COUNT
;
5635 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5637 static struct ureg_src
5638 emit_immediate(struct st_translate
*t
,
5639 gl_constant_value values
[4],
5642 struct ureg_program
*ureg
= t
->ureg
;
5647 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5649 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5651 return ureg_DECL_immediate_int64(ureg
, (int64_t *)&values
[0].f
, size
);
5652 case GL_UNSIGNED_INT64_ARB
:
5653 return ureg_DECL_immediate_uint64(ureg
, (uint64_t *)&values
[0].f
, size
);
5655 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5656 case GL_UNSIGNED_INT
:
5658 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5660 assert(!"should not get here - type must be float, int, uint, or bool");
5661 return ureg_src_undef();
5666 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5668 static struct ureg_dst
5669 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5675 case PROGRAM_UNDEFINED
:
5676 return ureg_dst_undef();
5678 case PROGRAM_TEMPORARY
:
5679 /* Allocate space for temporaries on demand. */
5680 if (index
>= t
->temps_size
) {
5681 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5683 t
->temps
= (struct ureg_dst
*)
5685 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5687 return ureg_dst_undef();
5689 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5690 t
->temps_size
+= inc
;
5693 if (ureg_dst_is_undef(t
->temps
[index
]))
5694 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5696 return t
->temps
[index
];
5699 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5700 array
= array_id
- 1;
5702 if (ureg_dst_is_undef(t
->arrays
[array
]))
5703 t
->arrays
[array
] = ureg_DECL_array_temporary(
5704 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5706 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5708 case PROGRAM_OUTPUT
:
5710 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5711 assert(index
< 2 * FRAG_RESULT_MAX
);
5712 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5713 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5714 assert(index
< VARYING_SLOT_TESS_MAX
);
5716 assert(index
< VARYING_SLOT_MAX
);
5718 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5719 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5720 return t
->outputs
[t
->outputMapping
[index
]];
5723 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5724 unsigned mesa_index
= decl
->mesa_index
;
5725 int slot
= t
->outputMapping
[mesa_index
];
5727 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5729 struct ureg_dst dst
= t
->outputs
[slot
];
5730 dst
.ArrayID
= array_id
;
5731 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5734 case PROGRAM_ADDRESS
:
5735 return t
->address
[index
];
5738 assert(!"unknown dst register file");
5739 return ureg_dst_undef();
5744 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5746 static struct ureg_src
5747 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5749 int index
= reg
->index
;
5750 int double_reg2
= reg
->double_reg2
? 1 : 0;
5753 case PROGRAM_UNDEFINED
:
5754 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5756 case PROGRAM_TEMPORARY
:
5758 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5760 case PROGRAM_OUTPUT
: {
5761 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5762 assert(dst
.WriteMask
!= 0);
5763 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5764 return ureg_swizzle(ureg_src(dst
),
5768 MIN2(shift
+ 3, 3));
5771 case PROGRAM_UNIFORM
:
5772 assert(reg
->index
>= 0);
5773 return reg
->index
< t
->num_constants
?
5774 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5775 case PROGRAM_STATE_VAR
:
5776 case PROGRAM_CONSTANT
: /* ie, immediate */
5777 if (reg
->has_index2
)
5778 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5780 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5781 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5783 case PROGRAM_IMMEDIATE
:
5784 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5785 return t
->immediates
[reg
->index
];
5788 /* GLSL inputs are 64-bit containers, so we have to
5789 * map back to the original index and add the offset after
5791 index
-= double_reg2
;
5792 if (!reg
->array_id
) {
5793 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5794 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5795 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5798 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5799 unsigned mesa_index
= decl
->mesa_index
;
5800 int slot
= t
->inputMapping
[mesa_index
];
5802 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5804 struct ureg_src src
= t
->inputs
[slot
];
5805 src
.ArrayID
= reg
->array_id
;
5806 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5809 case PROGRAM_ADDRESS
:
5810 return ureg_src(t
->address
[reg
->index
]);
5812 case PROGRAM_SYSTEM_VALUE
:
5813 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5814 return t
->systemValues
[reg
->index
];
5817 assert(!"unknown src register file");
5818 return ureg_src_undef();
5823 * Create a TGSI ureg_dst register from an st_dst_reg.
5825 static struct ureg_dst
5826 translate_dst(struct st_translate
*t
,
5827 const st_dst_reg
*dst_reg
,
5830 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5833 if (dst
.File
== TGSI_FILE_NULL
)
5836 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5839 dst
= ureg_saturate(dst
);
5841 if (dst_reg
->reladdr
!= NULL
) {
5842 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5843 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5846 if (dst_reg
->has_index2
) {
5847 if (dst_reg
->reladdr2
)
5848 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5851 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5858 * Create a TGSI ureg_src register from an st_src_reg.
5860 static struct ureg_src
5861 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5863 struct ureg_src src
= src_register(t
, src_reg
);
5865 if (src_reg
->has_index2
) {
5866 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5867 * and UBO constant buffers (buffer, position).
5869 if (src_reg
->reladdr2
)
5870 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5873 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5876 src
= ureg_swizzle(src
,
5877 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5878 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5879 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5880 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5883 src
= ureg_abs(src
);
5885 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5886 src
= ureg_negate(src
);
5888 if (src_reg
->reladdr
!= NULL
) {
5889 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5890 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5896 static struct tgsi_texture_offset
5897 translate_tex_offset(struct st_translate
*t
,
5898 const st_src_reg
*in_offset
)
5900 struct tgsi_texture_offset offset
;
5901 struct ureg_src src
= translate_src(t
, in_offset
);
5903 offset
.File
= src
.File
;
5904 offset
.Index
= src
.Index
;
5905 offset
.SwizzleX
= src
.SwizzleX
;
5906 offset
.SwizzleY
= src
.SwizzleY
;
5907 offset
.SwizzleZ
= src
.SwizzleZ
;
5910 assert(!src
.Indirect
);
5911 assert(!src
.DimIndirect
);
5912 assert(!src
.Dimension
);
5913 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5914 assert(!src
.Negate
);
5920 compile_tgsi_instruction(struct st_translate
*t
,
5921 const glsl_to_tgsi_instruction
*inst
)
5923 struct ureg_program
*ureg
= t
->ureg
;
5925 struct ureg_dst dst
[2];
5926 struct ureg_src src
[4];
5927 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5931 unsigned tex_target
= 0;
5933 num_dst
= num_inst_dst_regs(inst
);
5934 num_src
= num_inst_src_regs(inst
);
5936 for (i
= 0; i
< num_dst
; i
++)
5937 dst
[i
] = translate_dst(t
,
5941 for (i
= 0; i
< num_src
; i
++)
5942 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5945 case TGSI_OPCODE_BGNLOOP
:
5946 case TGSI_OPCODE_ELSE
:
5947 case TGSI_OPCODE_ENDLOOP
:
5948 case TGSI_OPCODE_IF
:
5949 case TGSI_OPCODE_UIF
:
5950 assert(num_dst
== 0);
5951 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
);
5954 case TGSI_OPCODE_TEX
:
5955 case TGSI_OPCODE_TEX_LZ
:
5956 case TGSI_OPCODE_TXB
:
5957 case TGSI_OPCODE_TXD
:
5958 case TGSI_OPCODE_TXL
:
5959 case TGSI_OPCODE_TXP
:
5960 case TGSI_OPCODE_TXQ
:
5961 case TGSI_OPCODE_TXQS
:
5962 case TGSI_OPCODE_TXF
:
5963 case TGSI_OPCODE_TXF_LZ
:
5964 case TGSI_OPCODE_TEX2
:
5965 case TGSI_OPCODE_TXB2
:
5966 case TGSI_OPCODE_TXL2
:
5967 case TGSI_OPCODE_TG4
:
5968 case TGSI_OPCODE_LODQ
:
5969 if (inst
->resource
.file
== PROGRAM_SAMPLER
) {
5970 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5972 /* Bindless samplers. */
5973 src
[num_src
] = translate_src(t
, &inst
->resource
);
5975 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5976 if (inst
->resource
.reladdr
)
5978 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5980 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5981 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5983 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5989 st_translate_texture_type(inst
->tex_type
),
5990 texoffsets
, inst
->tex_offset_num_offset
,
5994 case TGSI_OPCODE_RESQ
:
5995 case TGSI_OPCODE_LOAD
:
5996 case TGSI_OPCODE_ATOMUADD
:
5997 case TGSI_OPCODE_ATOMXCHG
:
5998 case TGSI_OPCODE_ATOMCAS
:
5999 case TGSI_OPCODE_ATOMAND
:
6000 case TGSI_OPCODE_ATOMOR
:
6001 case TGSI_OPCODE_ATOMXOR
:
6002 case TGSI_OPCODE_ATOMUMIN
:
6003 case TGSI_OPCODE_ATOMUMAX
:
6004 case TGSI_OPCODE_ATOMIMIN
:
6005 case TGSI_OPCODE_ATOMIMAX
:
6006 for (i
= num_src
- 1; i
>= 0; i
--)
6007 src
[i
+ 1] = src
[i
];
6009 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6010 src
[0] = t
->shared_memory
;
6011 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6012 src
[0] = t
->buffers
[inst
->resource
.index
];
6014 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6015 src
[0] = t
->images
[inst
->resource
.index
];
6017 /* Bindless images. */
6018 src
[0] = translate_src(t
, &inst
->resource
);
6020 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6022 if (inst
->resource
.reladdr
)
6023 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
6024 assert(src
[0].File
!= TGSI_FILE_NULL
);
6025 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6026 inst
->buffer_access
,
6027 tex_target
, inst
->image_format
);
6030 case TGSI_OPCODE_STORE
:
6031 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
6032 dst
[0] = ureg_dst(t
->shared_memory
);
6033 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
6034 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
6036 if (inst
->resource
.file
== PROGRAM_IMAGE
) {
6037 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
6039 /* Bindless images. */
6040 dst
[0] = ureg_dst(translate_src(t
, &inst
->resource
));
6042 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
6044 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
6045 if (inst
->resource
.reladdr
)
6046 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
6047 assert(dst
[0].File
!= TGSI_FILE_NULL
);
6048 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
6049 inst
->buffer_access
,
6050 tex_target
, inst
->image_format
);
6053 case TGSI_OPCODE_SCS
:
6054 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
6055 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
6068 * Emit the TGSI instructions for inverting and adjusting WPOS.
6069 * This code is unavoidable because it also depends on whether
6070 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
6073 emit_wpos_adjustment(struct gl_context
*ctx
,
6074 struct st_translate
*t
,
6075 int wpos_transform_const
,
6077 GLfloat adjX
, GLfloat adjY
[2])
6079 struct ureg_program
*ureg
= t
->ureg
;
6081 assert(wpos_transform_const
>= 0);
6083 /* Fragment program uses fragment position input.
6084 * Need to replace instances of INPUT[WPOS] with temp T
6085 * where T = INPUT[WPOS] is inverted by Y.
6087 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
6088 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
6089 struct ureg_src
*wpos
=
6090 ctx
->Const
.GLSLFragCoordIsSysVal
?
6091 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
6092 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
6093 struct ureg_src wpos_input
= *wpos
;
6095 /* First, apply the coordinate shift: */
6096 if (adjX
|| adjY
[0] || adjY
[1]) {
6097 if (adjY
[0] != adjY
[1]) {
6098 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
6099 * depending on whether inversion is actually going to be applied
6100 * or not, which is determined by testing against the inversion
6101 * state variable used below, which will be either +1 or -1.
6103 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
6105 ureg_CMP(ureg
, adj_temp
,
6106 ureg_scalar(wpostrans
, invert
? 2 : 0),
6107 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
6108 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
6109 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
6111 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
6112 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
6114 wpos_input
= ureg_src(wpos_temp
);
6116 /* MOV wpos_temp, input[wpos]
6118 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
6121 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
6122 * inversion/identity, or the other way around if we're drawing to an FBO.
6125 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
6128 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6130 ureg_scalar(wpostrans
, 0),
6131 ureg_scalar(wpostrans
, 1));
6133 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
6136 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
6138 ureg_scalar(wpostrans
, 2),
6139 ureg_scalar(wpostrans
, 3));
6142 /* Use wpos_temp as position input from here on:
6144 *wpos
= ureg_src(wpos_temp
);
6149 * Emit fragment position/ooordinate code.
6152 emit_wpos(struct st_context
*st
,
6153 struct st_translate
*t
,
6154 const struct gl_program
*program
,
6155 struct ureg_program
*ureg
,
6156 int wpos_transform_const
)
6158 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6159 GLfloat adjX
= 0.0f
;
6160 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
6161 boolean invert
= FALSE
;
6163 /* Query the pixel center conventions supported by the pipe driver and set
6164 * adjX, adjY to help out if it cannot handle the requested one internally.
6166 * The bias of the y-coordinate depends on whether y-inversion takes place
6167 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
6168 * drawing to an FBO (causes additional inversion), and whether the pipe
6169 * driver origin and the requested origin differ (the latter condition is
6170 * stored in the 'invert' variable).
6172 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
6174 * center shift only:
6179 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
6180 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
6181 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
6182 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
6184 * inversion and center shift:
6185 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
6186 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
6187 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
6188 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
6190 if (program
->OriginUpperLeft
) {
6191 /* Fragment shader wants origin in upper-left */
6192 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
6193 /* the driver supports upper-left origin */
6195 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
6196 /* the driver supports lower-left origin, need to invert Y */
6197 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6198 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6205 /* Fragment shader wants origin in lower-left */
6206 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
6207 /* the driver supports lower-left origin */
6208 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
6209 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
6210 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
6211 /* the driver supports upper-left origin, need to invert Y */
6217 if (program
->PixelCenterInteger
) {
6218 /* Fragment shader wants pixel center integer */
6219 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6220 /* the driver supports pixel center integer */
6222 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6223 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6225 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6226 /* the driver supports pixel center half integer, need to bias X,Y */
6235 /* Fragment shader wants pixel center half integer */
6236 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
6237 /* the driver supports pixel center half integer */
6239 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
6240 /* the driver supports pixel center integer, need to bias X,Y */
6241 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
6242 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
6243 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
6249 /* we invert after adjustment so that we avoid the MOV to temporary,
6250 * and reuse the adjustment ADD instead */
6251 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
6255 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
6256 * TGSI uses +1 for front, -1 for back.
6257 * This function converts the TGSI value to the GL value. Simply clamping/
6258 * saturating the value to [0,1] does the job.
6261 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
6263 struct ureg_program
*ureg
= t
->ureg
;
6264 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
6265 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
6267 if (ctx
->Const
.NativeIntegers
) {
6268 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
6271 /* MOV_SAT face_temp, input[face] */
6272 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
6275 /* Use face_temp as face input from here on: */
6276 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
6280 emit_compute_block_size(const struct gl_program
*prog
,
6281 struct ureg_program
*ureg
) {
6282 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
6283 prog
->info
.cs
.local_size
[0]);
6284 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
6285 prog
->info
.cs
.local_size
[1]);
6286 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
6287 prog
->info
.cs
.local_size
[2]);
6290 struct sort_inout_decls
{
6291 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
6292 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
6295 const ubyte
*mapping
;
6298 /* Sort the given array of decls by the corresponding slot (TGSI file index).
6300 * This is for the benefit of older drivers which are broken when the
6301 * declarations aren't sorted in this way.
6304 sort_inout_decls_by_slot(struct inout_decl
*decls
,
6306 const ubyte mapping
[])
6308 sort_inout_decls sorter
;
6309 sorter
.mapping
= mapping
;
6310 std::sort(decls
, decls
+ count
, sorter
);
6314 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
6316 switch (glsl_qual
) {
6317 case INTERP_MODE_NONE
:
6318 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
6319 return TGSI_INTERPOLATE_COLOR
;
6320 return TGSI_INTERPOLATE_PERSPECTIVE
;
6321 case INTERP_MODE_SMOOTH
:
6322 return TGSI_INTERPOLATE_PERSPECTIVE
;
6323 case INTERP_MODE_FLAT
:
6324 return TGSI_INTERPOLATE_CONSTANT
;
6325 case INTERP_MODE_NOPERSPECTIVE
:
6326 return TGSI_INTERPOLATE_LINEAR
;
6328 assert(0 && "unexpected interp mode in st_translate_interp()");
6329 return TGSI_INTERPOLATE_PERSPECTIVE
;
6334 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
6335 * \param program the program to translate
6336 * \param numInputs number of input registers used
6337 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
6339 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
6340 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
6342 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
6343 * \param numOutputs number of output registers used
6344 * \param outputMapping maps Mesa fragment program outputs to TGSI
6346 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
6347 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
6350 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
6352 extern "C" enum pipe_error
6353 st_translate_program(
6354 struct gl_context
*ctx
,
6356 struct ureg_program
*ureg
,
6357 glsl_to_tgsi_visitor
*program
,
6358 const struct gl_program
*proginfo
,
6360 const ubyte inputMapping
[],
6361 const ubyte inputSlotToAttr
[],
6362 const ubyte inputSemanticName
[],
6363 const ubyte inputSemanticIndex
[],
6364 const ubyte interpMode
[],
6366 const ubyte outputMapping
[],
6367 const ubyte outputSemanticName
[],
6368 const ubyte outputSemanticIndex
[])
6370 struct st_translate
*t
;
6372 struct gl_program_constants
*frag_const
=
6373 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6374 enum pipe_error ret
= PIPE_OK
;
6376 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6377 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6379 t
= CALLOC_STRUCT(st_translate
);
6381 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6385 t
->procType
= procType
;
6386 t
->inputMapping
= inputMapping
;
6387 t
->outputMapping
= outputMapping
;
6389 t
->num_temp_arrays
= program
->next_array
;
6390 if (t
->num_temp_arrays
)
6391 t
->arrays
= (struct ureg_dst
*)
6392 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6395 * Declare input attributes.
6398 case PIPE_SHADER_FRAGMENT
:
6399 case PIPE_SHADER_GEOMETRY
:
6400 case PIPE_SHADER_TESS_EVAL
:
6401 case PIPE_SHADER_TESS_CTRL
:
6402 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6404 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6405 struct inout_decl
*decl
= &program
->inputs
[i
];
6406 unsigned slot
= inputMapping
[decl
->mesa_index
];
6407 struct ureg_src src
;
6408 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6410 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6411 if (tgsi_usage_mask
== 1)
6412 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6413 else if (tgsi_usage_mask
== 2)
6414 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6416 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6419 unsigned interp_mode
= 0;
6420 unsigned interp_location
= 0;
6421 if (procType
== PIPE_SHADER_FRAGMENT
) {
6423 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6425 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6427 interp_location
= decl
->interp_loc
;
6430 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6431 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6432 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6433 decl
->array_id
, decl
->size
);
6435 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6436 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6437 /* The ArrayID is set up in dst_register */
6438 t
->inputs
[slot
+ j
] = src
;
6439 t
->inputs
[slot
+ j
].ArrayID
= 0;
6440 t
->inputs
[slot
+ j
].Index
+= j
;
6445 case PIPE_SHADER_VERTEX
:
6446 for (i
= 0; i
< numInputs
; i
++) {
6447 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6450 case PIPE_SHADER_COMPUTE
:
6457 * Declare output attributes.
6460 case PIPE_SHADER_FRAGMENT
:
6461 case PIPE_SHADER_COMPUTE
:
6463 case PIPE_SHADER_GEOMETRY
:
6464 case PIPE_SHADER_TESS_EVAL
:
6465 case PIPE_SHADER_TESS_CTRL
:
6466 case PIPE_SHADER_VERTEX
:
6467 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6469 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6470 struct inout_decl
*decl
= &program
->outputs
[i
];
6471 unsigned slot
= outputMapping
[decl
->mesa_index
];
6472 struct ureg_dst dst
;
6473 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6475 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6476 if (tgsi_usage_mask
== 1)
6477 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6478 else if (tgsi_usage_mask
== 2)
6479 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6481 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6484 dst
= ureg_DECL_output_layout(ureg
,
6485 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6486 decl
->gs_out_streams
,
6487 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6489 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6490 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6491 /* The ArrayID is set up in dst_register */
6492 t
->outputs
[slot
+ j
] = dst
;
6493 t
->outputs
[slot
+ j
].ArrayID
= 0;
6494 t
->outputs
[slot
+ j
].Index
+= j
;
6503 if (procType
== PIPE_SHADER_FRAGMENT
) {
6504 if (program
->shader
->Program
->info
.fs
.early_fragment_tests
||
6505 program
->shader
->Program
->info
.fs
.post_depth_coverage
) {
6506 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6508 if (program
->shader
->Program
->info
.fs
.post_depth_coverage
)
6509 ureg_property(ureg
, TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
, 1);
6512 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6513 /* Must do this after setting up t->inputs. */
6514 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6515 program
->wpos_transform_const
);
6518 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6519 emit_face_var(ctx
, t
);
6521 for (i
= 0; i
< numOutputs
; i
++) {
6522 switch (outputSemanticName
[i
]) {
6523 case TGSI_SEMANTIC_POSITION
:
6524 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6525 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6526 outputSemanticIndex
[i
]);
6527 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6529 case TGSI_SEMANTIC_STENCIL
:
6530 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6531 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6532 outputSemanticIndex
[i
]);
6533 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6535 case TGSI_SEMANTIC_COLOR
:
6536 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6537 TGSI_SEMANTIC_COLOR
,
6538 outputSemanticIndex
[i
]);
6540 case TGSI_SEMANTIC_SAMPLEMASK
:
6541 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6542 TGSI_SEMANTIC_SAMPLEMASK
,
6543 outputSemanticIndex
[i
]);
6544 /* TODO: If we ever support more than 32 samples, this will have
6545 * to become an array.
6547 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6550 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6551 ret
= PIPE_ERROR_BAD_INPUT
;
6556 else if (procType
== PIPE_SHADER_VERTEX
) {
6557 for (i
= 0; i
< numOutputs
; i
++) {
6558 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6559 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6561 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6562 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6563 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6568 if (procType
== PIPE_SHADER_COMPUTE
) {
6569 emit_compute_block_size(proginfo
, ureg
);
6572 /* Declare address register.
6574 if (program
->num_address_regs
> 0) {
6575 assert(program
->num_address_regs
<= 3);
6576 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6577 t
->address
[i
] = ureg_DECL_address(ureg
);
6580 /* Declare misc input registers
6583 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6585 for (i
= 0; sysInputs
; i
++) {
6586 if (sysInputs
& (1 << i
)) {
6587 unsigned semName
= _mesa_sysval_to_semantic(i
);
6589 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6591 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6592 semName
== TGSI_SEMANTIC_VERTEXID
) {
6593 /* From Gallium perspective, these system values are always
6594 * integer, and require native integer support. However, if
6595 * native integer is supported on the vertex stage but not the
6596 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6597 * assumes these system values are floats. To resolve the
6598 * inconsistency, we insert a U2F.
6600 struct st_context
*st
= st_context(ctx
);
6601 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6602 assert(procType
== PIPE_SHADER_VERTEX
);
6603 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6605 if (!ctx
->Const
.NativeIntegers
) {
6606 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6607 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6608 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6612 if (procType
== PIPE_SHADER_FRAGMENT
&&
6613 semName
== TGSI_SEMANTIC_POSITION
)
6614 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6615 program
->wpos_transform_const
);
6617 sysInputs
&= ~(1 << i
);
6622 t
->array_sizes
= program
->array_sizes
;
6623 t
->input_decls
= program
->inputs
;
6624 t
->num_input_decls
= program
->num_inputs
;
6625 t
->output_decls
= program
->outputs
;
6626 t
->num_output_decls
= program
->num_outputs
;
6628 /* Emit constants and uniforms. TGSI uses a single index space for these,
6629 * so we put all the translated regs in t->constants.
6631 if (proginfo
->Parameters
) {
6632 t
->constants
= (struct ureg_src
*)
6633 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6634 if (t
->constants
== NULL
) {
6635 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6638 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6640 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6641 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6642 case PROGRAM_STATE_VAR
:
6643 case PROGRAM_UNIFORM
:
6644 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6647 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6648 * addressing of the const buffer.
6649 * FIXME: Be smarter and recognize param arrays:
6650 * indirect addressing is only valid within the referenced
6653 case PROGRAM_CONSTANT
:
6654 if (program
->indirect_addr_consts
)
6655 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6657 t
->constants
[i
] = emit_immediate(t
,
6658 proginfo
->Parameters
->ParameterValues
[i
],
6659 proginfo
->Parameters
->Parameters
[i
].DataType
,
6668 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6669 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6670 unsigned num_const_vecs
= (size
+ 15) / 16;
6671 unsigned first
, last
;
6672 assert(num_const_vecs
> 0);
6674 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6675 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6678 /* Emit immediate values.
6680 t
->immediates
= (struct ureg_src
*)
6681 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6682 if (t
->immediates
== NULL
) {
6683 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6686 t
->num_immediates
= program
->num_immediates
;
6689 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6690 assert(i
< program
->num_immediates
);
6691 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6693 assert(i
== program
->num_immediates
);
6695 /* texture samplers */
6696 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6697 if (program
->samplers_used
& (1u << i
)) {
6698 unsigned type
= st_translate_texture_type(program
->sampler_types
[i
]);
6700 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6702 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6703 type
, type
, type
, type
);
6707 /* Declare atomic and shader storage buffers. */
6709 struct gl_program
*prog
= program
->prog
;
6711 for (i
= 0; i
< prog
->info
.num_abos
; i
++) {
6712 unsigned index
= prog
->sh
.AtomicBuffers
[i
]->Binding
;
6713 assert(index
< frag_const
->MaxAtomicBuffers
);
6714 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, true);
6717 assert(prog
->info
.num_ssbos
<= frag_const
->MaxShaderStorageBlocks
);
6718 for (i
= 0; i
< prog
->info
.num_ssbos
; i
++) {
6719 unsigned index
= frag_const
->MaxAtomicBuffers
+ i
;
6720 t
->buffers
[index
] = ureg_DECL_buffer(ureg
, index
, false);
6724 if (program
->use_shared_memory
)
6725 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6727 for (i
= 0; i
< program
->shader
->Program
->info
.num_images
; i
++) {
6728 if (program
->images_used
& (1 << i
)) {
6729 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6730 program
->image_targets
[i
],
6731 program
->image_formats
[i
],
6736 /* Emit each instruction in turn:
6738 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6739 compile_tgsi_instruction(t
, inst
);
6741 /* Set the next shader stage hint for VS and TES. */
6743 case PIPE_SHADER_VERTEX
:
6744 case PIPE_SHADER_TESS_EVAL
:
6745 if (program
->shader_program
->SeparateShader
)
6748 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6749 if (program
->shader_program
->_LinkedShaders
[i
]) {
6753 case MESA_SHADER_TESS_CTRL
:
6754 next
= PIPE_SHADER_TESS_CTRL
;
6756 case MESA_SHADER_TESS_EVAL
:
6757 next
= PIPE_SHADER_TESS_EVAL
;
6759 case MESA_SHADER_GEOMETRY
:
6760 next
= PIPE_SHADER_GEOMETRY
;
6762 case MESA_SHADER_FRAGMENT
:
6763 next
= PIPE_SHADER_FRAGMENT
;
6770 ureg_set_next_shader_processor(ureg
, next
);
6782 t
->num_constants
= 0;
6783 free(t
->immediates
);
6784 t
->num_immediates
= 0;
6790 /* ----------------------------- End TGSI code ------------------------------ */
6794 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6795 * generating Mesa IR.
6797 static struct gl_program
*
6798 get_mesa_program_tgsi(struct gl_context
*ctx
,
6799 struct gl_shader_program
*shader_program
,
6800 struct gl_linked_shader
*shader
)
6802 glsl_to_tgsi_visitor
* v
;
6803 struct gl_program
*prog
;
6804 struct gl_shader_compiler_options
*options
=
6805 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6806 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6807 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6808 unsigned skip_merge_registers
;
6810 validate_ir_tree(shader
->ir
);
6812 prog
= shader
->Program
;
6814 prog
->Parameters
= _mesa_new_parameter_list();
6815 v
= new glsl_to_tgsi_visitor();
6818 v
->shader_program
= shader_program
;
6820 v
->options
= options
;
6821 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6822 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6824 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6825 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6826 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6827 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6828 v
->has_tex_txf_lz
= pscreen
->get_param(pscreen
,
6829 PIPE_CAP_TGSI_TEX_TXF_LZ
);
6831 v
->variables
= _mesa_hash_table_create(v
->mem_ctx
, _mesa_hash_pointer
,
6832 _mesa_key_pointer_equal
);
6833 skip_merge_registers
=
6834 pscreen
->get_shader_param(pscreen
, ptarget
,
6835 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
);
6837 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6840 /* Remove reads from output registers. */
6841 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6842 lower_output_reads(shader
->Stage
, shader
->ir
);
6844 /* Emit intermediate IR for main(). */
6845 visit_exec_list(shader
->ir
, v
);
6848 /* Print out some information (for debugging purposes) used by the
6849 * optimization passes. */
6852 int *first_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6853 int *first_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6854 int *last_writes
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6855 int *last_reads
= ralloc_array(v
->mem_ctx
, int, v
->next_temp
);
6857 for (i
= 0; i
< v
->next_temp
; i
++) {
6858 first_writes
[i
] = -1;
6859 first_reads
[i
] = -1;
6860 last_writes
[i
] = -1;
6863 v
->get_first_temp_read(first_reads
);
6864 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6865 v
->get_last_temp_write(last_writes
);
6866 for (i
= 0; i
< v
->next_temp
; i
++)
6867 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6871 ralloc_free(first_writes
);
6872 ralloc_free(first_reads
);
6873 ralloc_free(last_writes
);
6874 ralloc_free(last_reads
);
6878 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6881 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6882 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6883 v
->copy_propagate();
6885 while (v
->eliminate_dead_code());
6887 v
->merge_two_dsts();
6888 if (!skip_merge_registers
)
6889 v
->merge_registers();
6890 v
->renumber_registers();
6892 /* Write the END instruction. */
6893 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6895 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6897 _mesa_log("GLSL IR for linked %s program %d:\n",
6898 _mesa_shader_stage_to_string(shader
->Stage
),
6899 shader_program
->Name
);
6900 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6904 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6905 _mesa_copy_linked_program_data(shader_program
, shader
);
6906 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6907 &prog
->info
.inputs_read
,
6908 prog
->info
.double_inputs_read
,
6909 &prog
->info
.patch_inputs_read
);
6910 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6911 &prog
->info
.outputs_written
, 0ULL,
6912 &prog
->info
.patch_outputs_written
);
6913 count_resources(v
, prog
);
6915 /* The GLSL IR won't be needed anymore. */
6916 ralloc_free(shader
->ir
);
6919 /* This must be done before the uniform storage is associated. */
6920 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6921 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6922 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6923 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6924 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6927 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6928 wposTransformState
);
6931 /* Avoid reallocation of the program parameter list, because the uniform
6932 * storage is only associated with the original parameter list.
6933 * This should be enough for Bitmap and DrawPixels constants.
6935 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6937 /* This has to be done last. Any operation the can cause
6938 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6939 * program constant) has to happen before creating this linkage.
6941 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
, true);
6942 if (!shader_program
->data
->LinkStatus
) {
6943 free_glsl_to_tgsi_visitor(v
);
6944 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6948 struct st_vertex_program
*stvp
;
6949 struct st_fragment_program
*stfp
;
6950 struct st_common_program
*stp
;
6951 struct st_compute_program
*stcp
;
6953 switch (shader
->Stage
) {
6954 case MESA_SHADER_VERTEX
:
6955 stvp
= (struct st_vertex_program
*)prog
;
6956 stvp
->glsl_to_tgsi
= v
;
6958 case MESA_SHADER_FRAGMENT
:
6959 stfp
= (struct st_fragment_program
*)prog
;
6960 stfp
->glsl_to_tgsi
= v
;
6962 case MESA_SHADER_TESS_CTRL
:
6963 case MESA_SHADER_TESS_EVAL
:
6964 case MESA_SHADER_GEOMETRY
:
6965 stp
= st_common_program(prog
);
6966 stp
->glsl_to_tgsi
= v
;
6968 case MESA_SHADER_COMPUTE
:
6969 stcp
= (struct st_compute_program
*)prog
;
6970 stcp
->glsl_to_tgsi
= v
;
6973 assert(!"should not be reached");
6980 /* See if there are unsupported control flow statements. */
6981 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6983 const struct gl_shader_compiler_options
*options
;
6985 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6991 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6993 /* Other functions are skipped (same as glsl_to_tgsi). */
6994 if (strcmp(ir
->name
, "main") == 0)
6995 return visit_continue
;
6997 return visit_continue_with_parent
;
7000 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
7002 if (!ir
->callee
->is_intrinsic()) {
7003 unsupported
= true; /* it's a function call */
7006 return visit_continue
;
7009 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
7011 if (options
->EmitNoMainReturn
) {
7015 return visit_continue
;
7022 has_unsupported_control_flow(exec_list
*ir
,
7023 const struct gl_shader_compiler_options
*options
)
7025 ir_control_flow_info_visitor
visitor(options
);
7026 visit_list_elements(&visitor
, ir
);
7027 return visitor
.unsupported
;
7034 * Called via ctx->Driver.LinkShader()
7035 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
7036 * with code lowering and other optimizations.
7039 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
7041 /* Return early if we are loading the shader from on-disk cache */
7042 if (st_load_tgsi_from_disk_cache(ctx
, prog
)) {
7046 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
7047 assert(prog
->data
->LinkStatus
);
7049 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7050 if (prog
->_LinkedShaders
[i
] == NULL
)
7053 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7054 exec_list
*ir
= shader
->ir
;
7055 gl_shader_stage stage
= shader
->Stage
;
7056 const struct gl_shader_compiler_options
*options
=
7057 &ctx
->Const
.ShaderCompilerOptions
[stage
];
7058 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
7059 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
7060 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
7061 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
7062 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
7063 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
7064 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
7066 /* If there are forms of indirect addressing that the driver
7067 * cannot handle, perform the lowering pass.
7069 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
7070 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
7071 lower_variable_index_to_cond_assign(stage
, ir
,
7072 options
->EmitNoIndirectInput
,
7073 options
->EmitNoIndirectOutput
,
7074 options
->EmitNoIndirectTemp
,
7075 options
->EmitNoIndirectUniform
);
7078 if (!pscreen
->get_param(pscreen
, PIPE_CAP_INT64_DIVMOD
))
7079 lower_64bit_integer_instructions(ir
, DIV64
| MOD64
);
7081 if (ctx
->Extensions
.ARB_shading_language_packing
) {
7082 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
7083 LOWER_UNPACK_SNORM_2x16
|
7084 LOWER_PACK_UNORM_2x16
|
7085 LOWER_UNPACK_UNORM_2x16
|
7086 LOWER_PACK_SNORM_4x8
|
7087 LOWER_UNPACK_SNORM_4x8
|
7088 LOWER_UNPACK_UNORM_4x8
|
7089 LOWER_PACK_UNORM_4x8
;
7091 if (ctx
->Extensions
.ARB_gpu_shader5
)
7092 lower_inst
|= LOWER_PACK_USE_BFI
|
7094 if (!ctx
->st
->has_half_float_packing
)
7095 lower_inst
|= LOWER_PACK_HALF_2x16
|
7096 LOWER_UNPACK_HALF_2x16
;
7098 lower_packing_builtins(ir
, lower_inst
);
7101 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
7102 lower_offset_arrays(ir
);
7103 do_mat_op_to_vec(ir
);
7105 if (stage
== MESA_SHADER_FRAGMENT
)
7106 lower_blend_equation_advanced(shader
);
7108 lower_instructions(ir
,
7114 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
7117 (have_dround
? 0 : DOPS_TO_DFRAC
) |
7118 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
7119 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
7120 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
7121 (ctx
->Const
.ForceGLSLAbsSqrt
? SQRT_TO_ABS_SQRT
: 0) |
7122 /* Assume that if ARB_gpu_shader5 is not supported
7123 * then all of the extended integer functions need
7124 * lowering. It may be necessary to add some caps
7125 * for individual instructions.
7127 (!ctx
->Extensions
.ARB_gpu_shader5
7128 ? BIT_COUNT_TO_MATH
|
7132 FIND_LSB_TO_FLOAT_CAST
|
7133 FIND_MSB_TO_FLOAT_CAST
|
7137 do_vec_index_to_cond_assign(ir
);
7138 lower_vector_insert(ir
, true);
7139 lower_quadop_vector(ir
, false);
7141 if (options
->MaxIfDepth
== 0) {
7145 if (ctx
->Const
.GLSLOptimizeConservatively
) {
7146 /* Do it once and repeat only if there's unsupported control flow. */
7148 do_common_optimization(ir
, true, true, options
,
7149 ctx
->Const
.NativeIntegers
);
7150 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7151 options
->MaxIfDepth
, if_threshold
);
7152 } while (has_unsupported_control_flow(ir
, options
));
7154 /* Repeat it until it stops making changes. */
7157 progress
= do_common_optimization(ir
, true, true, options
,
7158 ctx
->Const
.NativeIntegers
);
7159 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
7160 options
->MaxIfDepth
, if_threshold
);
7164 validate_ir_tree(ir
);
7167 build_program_resource_list(ctx
, prog
);
7169 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
7170 struct gl_linked_shader
*shader
= prog
->_LinkedShaders
[i
];
7174 enum pipe_shader_type ptarget
=
7175 st_shader_stage_to_ptarget(shader
->Stage
);
7176 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
7177 pscreen
->get_shader_param(pscreen
, ptarget
,
7178 PIPE_SHADER_CAP_PREFERRED_IR
);
7180 struct gl_program
*linked_prog
= NULL
;
7181 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
7182 /* TODO only for GLSL VS/FS/CS for now: */
7183 switch (shader
->Stage
) {
7184 case MESA_SHADER_VERTEX
:
7185 case MESA_SHADER_FRAGMENT
:
7186 case MESA_SHADER_COMPUTE
:
7187 linked_prog
= st_nir_get_mesa_program(ctx
, prog
, shader
);
7192 linked_prog
= get_mesa_program_tgsi(ctx
, prog
, shader
);
7196 st_set_prog_affected_state_flags(linked_prog
);
7197 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
7198 _mesa_shader_stage_to_program(i
),
7200 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
7210 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
7211 const ubyte outputMapping
[],
7212 struct pipe_stream_output_info
*so
)
7214 if (!glsl_to_tgsi
->shader_program
->last_vert_prog
)
7217 struct gl_transform_feedback_info
*info
=
7218 glsl_to_tgsi
->shader_program
->last_vert_prog
->sh
.LinkedTransformFeedback
;
7219 st_translate_stream_output_info2(info
, outputMapping
, so
);
7223 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7224 const ubyte outputMapping
[],
7225 struct pipe_stream_output_info
*so
)
7229 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7230 so
->output
[i
].register_index
=
7231 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7232 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7233 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7234 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7235 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7236 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7239 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7240 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7242 so
->num_outputs
= info
->NumOutputs
;