2 * Copyright (C) 2005-2007 Brian Paul All Rights Reserved.
3 * Copyright (C) 2008 VMware, Inc. All Rights Reserved.
4 * Copyright © 2010 Intel Corporation
5 * Copyright © 2011 Bryan Cain
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8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
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18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * \file glsl_to_tgsi.cpp
30 * Translate GLSL IR to TGSI.
33 #include "st_glsl_to_tgsi.h"
35 #include "compiler/glsl/glsl_parser_extras.h"
36 #include "compiler/glsl/ir_optimization.h"
37 #include "compiler/glsl/program.h"
39 #include "main/errors.h"
40 #include "main/shaderobj.h"
41 #include "main/uniforms.h"
42 #include "main/shaderapi.h"
43 #include "main/shaderimage.h"
44 #include "program/prog_instruction.h"
46 #include "pipe/p_context.h"
47 #include "pipe/p_screen.h"
48 #include "tgsi/tgsi_ureg.h"
49 #include "tgsi/tgsi_info.h"
50 #include "util/u_math.h"
51 #include "util/u_memory.h"
52 #include "st_program.h"
53 #include "st_mesa_to_tgsi.h"
54 #include "st_format.h"
55 #include "st_glsl_types.h"
60 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
61 (1 << PROGRAM_CONSTANT) | \
62 (1 << PROGRAM_UNIFORM))
64 #define MAX_GLSL_TEXTURE_OFFSET 4
69 static int swizzle_for_size(int size
);
71 static int swizzle_for_type(const glsl_type
*type
, int component
= 0)
73 unsigned num_elements
= 4;
76 type
= type
->without_array();
77 if (type
->is_scalar() || type
->is_vector() || type
->is_matrix())
78 num_elements
= type
->vector_elements
;
81 int swizzle
= swizzle_for_size(num_elements
);
82 assert(num_elements
+ component
<= 4);
84 swizzle
+= component
* MAKE_SWIZZLE4(1, 1, 1, 1);
89 * This struct is a corresponding struct to TGSI ureg_src.
93 st_src_reg(gl_register_file file
, int index
, const glsl_type
*type
,
94 int component
= 0, unsigned array_id
= 0)
96 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
99 this->swizzle
= swizzle_for_type(type
, component
);
103 this->type
= type
? type
->base_type
: GLSL_TYPE_ERROR
;
104 this->reladdr
= NULL
;
105 this->reladdr2
= NULL
;
106 this->has_index2
= false;
107 this->double_reg2
= false;
108 this->array_id
= array_id
;
109 this->is_double_vertex_input
= false;
112 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
)
114 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
119 this->swizzle
= SWIZZLE_XYZW
;
122 this->reladdr
= NULL
;
123 this->reladdr2
= NULL
;
124 this->has_index2
= false;
125 this->double_reg2
= false;
127 this->is_double_vertex_input
= false;
130 st_src_reg(gl_register_file file
, int index
, enum glsl_base_type type
, int index2D
)
132 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
136 this->index2D
= index2D
;
137 this->swizzle
= SWIZZLE_XYZW
;
140 this->reladdr
= NULL
;
141 this->reladdr2
= NULL
;
142 this->has_index2
= false;
143 this->double_reg2
= false;
145 this->is_double_vertex_input
= false;
150 this->type
= GLSL_TYPE_ERROR
;
151 this->file
= PROGRAM_UNDEFINED
;
157 this->reladdr
= NULL
;
158 this->reladdr2
= NULL
;
159 this->has_index2
= false;
160 this->double_reg2
= false;
162 this->is_double_vertex_input
= false;
165 explicit st_src_reg(st_dst_reg reg
);
167 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
169 uint16_t swizzle
; /**< SWIZZLE_XYZWONEZERO swizzles from Mesa. */
170 int negate
:4; /**< NEGATE_XYZW mask from mesa */
172 enum glsl_base_type type
:4; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
173 unsigned has_index2
:1;
174 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
176 * Is this the second half of a double register pair?
177 * currently used for input mapping only.
179 unsigned double_reg2
:1;
180 unsigned is_double_vertex_input
:1;
181 unsigned array_id
:10;
183 /** Register index should be offset by the integer in this reg. */
185 st_src_reg
*reladdr2
;
189 st_src_reg reg
= *this;
198 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
, int index
)
200 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
204 this->writemask
= writemask
;
205 this->reladdr
= NULL
;
206 this->reladdr2
= NULL
;
207 this->has_index2
= false;
212 st_dst_reg(gl_register_file file
, int writemask
, enum glsl_base_type type
)
214 assert(file
!= PROGRAM_ARRAY
); /* need array_id > 0 */
218 this->writemask
= writemask
;
219 this->reladdr
= NULL
;
220 this->reladdr2
= NULL
;
221 this->has_index2
= false;
228 this->type
= GLSL_TYPE_ERROR
;
229 this->file
= PROGRAM_UNDEFINED
;
233 this->reladdr
= NULL
;
234 this->reladdr2
= NULL
;
235 this->has_index2
= false;
239 explicit st_dst_reg(st_src_reg reg
);
241 int16_t index
; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
243 gl_register_file file
:5; /**< PROGRAM_* from Mesa */
244 unsigned writemask
:4; /**< Bitfield of WRITEMASK_[XYZW] */
245 enum glsl_base_type type
:4; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
246 unsigned has_index2
:1;
247 unsigned array_id
:10;
249 /** Register index should be offset by the integer in this reg. */
251 st_src_reg
*reladdr2
;
254 st_src_reg::st_src_reg(st_dst_reg reg
)
256 this->type
= reg
.type
;
257 this->file
= reg
.file
;
258 this->index
= reg
.index
;
259 this->swizzle
= SWIZZLE_XYZW
;
262 this->reladdr
= reg
.reladdr
;
263 this->index2D
= reg
.index2D
;
264 this->reladdr2
= reg
.reladdr2
;
265 this->has_index2
= reg
.has_index2
;
266 this->double_reg2
= false;
267 this->array_id
= reg
.array_id
;
268 this->is_double_vertex_input
= false;
271 st_dst_reg::st_dst_reg(st_src_reg reg
)
273 this->type
= reg
.type
;
274 this->file
= reg
.file
;
275 this->index
= reg
.index
;
276 this->writemask
= WRITEMASK_XYZW
;
277 this->reladdr
= reg
.reladdr
;
278 this->index2D
= reg
.index2D
;
279 this->reladdr2
= reg
.reladdr2
;
280 this->has_index2
= reg
.has_index2
;
281 this->array_id
= reg
.array_id
;
284 class glsl_to_tgsi_instruction
: public exec_node
{
286 DECLARE_RALLOC_CXX_OPERATORS(glsl_to_tgsi_instruction
)
290 st_src_reg resource
; /**< sampler or buffer register */
291 st_src_reg
*tex_offsets
;
293 /** Pointer to the ir source this tree came from for debugging */
296 unsigned op
:8; /**< TGSI opcode */
298 unsigned is_64bit_expanded
:1;
299 unsigned sampler_base
:5;
300 unsigned sampler_array_size
:6; /**< 1-based size of sampler array, 1 if not array */
301 unsigned tex_target
:4; /**< One of TEXTURE_*_INDEX */
302 glsl_base_type tex_type
:4;
303 unsigned tex_shadow
:1;
304 unsigned image_format
:9;
305 unsigned tex_offset_num_offset
:3;
306 unsigned dead_mask
:4; /**< Used in dead code elimination */
307 unsigned buffer_access
:3; /**< buffer access type */
309 const struct tgsi_opcode_info
*info
;
312 class variable_storage
: public exec_node
{
314 variable_storage(ir_variable
*var
, gl_register_file file
, int index
,
315 unsigned array_id
= 0)
316 : file(file
), index(index
), component(0), var(var
), array_id(array_id
)
318 assert(file
!= PROGRAM_ARRAY
|| array_id
!= 0);
321 gl_register_file file
;
324 /* Explicit component location. This is given in terms of the GLSL-style
325 * swizzles where each double is a single component, i.e. for 64-bit types
326 * it can only be 0 or 1.
329 ir_variable
*var
; /* variable that maps to this, if any */
333 class immediate_storage
: public exec_node
{
335 immediate_storage(gl_constant_value
*values
, int size32
, int type
)
337 memcpy(this->values
, values
, size32
* sizeof(gl_constant_value
));
338 this->size32
= size32
;
342 /* doubles are stored across 2 gl_constant_values */
343 gl_constant_value values
[4];
344 int size32
; /**< Number of 32-bit components (1-4) */
345 int type
; /**< GL_DOUBLE, GL_FLOAT, GL_INT, GL_BOOL, or GL_UNSIGNED_INT */
348 static st_src_reg undef_src
= st_src_reg(PROGRAM_UNDEFINED
, 0, GLSL_TYPE_ERROR
);
349 static st_dst_reg undef_dst
= st_dst_reg(PROGRAM_UNDEFINED
, SWIZZLE_NOOP
, GLSL_TYPE_ERROR
);
353 unsigned array_id
; /* TGSI ArrayID; 1-based: 0 means not an array */
356 unsigned gs_out_streams
;
357 enum glsl_interp_mode interp
;
358 enum glsl_base_type base_type
;
359 ubyte usage_mask
; /* GLSL-style usage-mask, i.e. single bit per double */
362 static struct inout_decl
*
363 find_inout_array(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
365 assert(array_id
!= 0);
367 for (unsigned i
= 0; i
< count
; i
++) {
368 struct inout_decl
*decl
= &decls
[i
];
370 if (array_id
== decl
->array_id
) {
378 static enum glsl_base_type
379 find_array_type(struct inout_decl
*decls
, unsigned count
, unsigned array_id
)
382 return GLSL_TYPE_ERROR
;
383 struct inout_decl
*decl
= find_inout_array(decls
, count
, array_id
);
385 return decl
->base_type
;
386 return GLSL_TYPE_ERROR
;
389 struct rename_reg_pair
{
394 struct glsl_to_tgsi_visitor
: public ir_visitor
{
396 glsl_to_tgsi_visitor();
397 ~glsl_to_tgsi_visitor();
399 struct gl_context
*ctx
;
400 struct gl_program
*prog
;
401 struct gl_shader_program
*shader_program
;
402 struct gl_linked_shader
*shader
;
403 struct gl_shader_compiler_options
*options
;
407 unsigned *array_sizes
;
408 unsigned max_num_arrays
;
411 struct inout_decl inputs
[4 * PIPE_MAX_SHADER_INPUTS
];
413 unsigned num_input_arrays
;
414 struct inout_decl outputs
[4 * PIPE_MAX_SHADER_OUTPUTS
];
415 unsigned num_outputs
;
416 unsigned num_output_arrays
;
418 int num_address_regs
;
419 uint32_t samplers_used
;
420 glsl_base_type sampler_types
[PIPE_MAX_SAMPLERS
];
421 int sampler_targets
[PIPE_MAX_SAMPLERS
]; /**< One of TGSI_TEXTURE_* */
424 int image_targets
[PIPE_MAX_SHADER_IMAGES
];
425 unsigned image_formats
[PIPE_MAX_SHADER_IMAGES
];
426 bool indirect_addr_consts
;
427 int wpos_transform_const
;
430 bool native_integers
;
433 bool use_shared_memory
;
435 variable_storage
*find_variable_storage(ir_variable
*var
);
437 int add_constant(gl_register_file file
, gl_constant_value values
[8],
438 int size
, int datatype
, uint16_t *swizzle_out
);
440 st_src_reg
get_temp(const glsl_type
*type
);
441 void reladdr_to_temp(ir_instruction
*ir
, st_src_reg
*reg
, int *num_reladdr
);
443 st_src_reg
st_src_reg_for_double(double val
);
444 st_src_reg
st_src_reg_for_float(float val
);
445 st_src_reg
st_src_reg_for_int(int val
);
446 st_src_reg
st_src_reg_for_type(enum glsl_base_type type
, int val
);
449 * \name Visit methods
451 * As typical for the visitor pattern, there must be one \c visit method for
452 * each concrete subclass of \c ir_instruction. Virtual base classes within
453 * the hierarchy should not have \c visit methods.
456 virtual void visit(ir_variable
*);
457 virtual void visit(ir_loop
*);
458 virtual void visit(ir_loop_jump
*);
459 virtual void visit(ir_function_signature
*);
460 virtual void visit(ir_function
*);
461 virtual void visit(ir_expression
*);
462 virtual void visit(ir_swizzle
*);
463 virtual void visit(ir_dereference_variable
*);
464 virtual void visit(ir_dereference_array
*);
465 virtual void visit(ir_dereference_record
*);
466 virtual void visit(ir_assignment
*);
467 virtual void visit(ir_constant
*);
468 virtual void visit(ir_call
*);
469 virtual void visit(ir_return
*);
470 virtual void visit(ir_discard
*);
471 virtual void visit(ir_texture
*);
472 virtual void visit(ir_if
*);
473 virtual void visit(ir_emit_vertex
*);
474 virtual void visit(ir_end_primitive
*);
475 virtual void visit(ir_barrier
*);
478 void visit_expression(ir_expression
*, st_src_reg
*) ATTRIBUTE_NOINLINE
;
480 void visit_atomic_counter_intrinsic(ir_call
*);
481 void visit_ssbo_intrinsic(ir_call
*);
482 void visit_membar_intrinsic(ir_call
*);
483 void visit_shared_intrinsic(ir_call
*);
484 void visit_image_intrinsic(ir_call
*);
488 /** List of variable_storage */
491 /** List of immediate_storage */
492 exec_list immediates
;
493 unsigned num_immediates
;
495 /** List of glsl_to_tgsi_instruction */
496 exec_list instructions
;
498 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
499 st_dst_reg dst
= undef_dst
,
500 st_src_reg src0
= undef_src
,
501 st_src_reg src1
= undef_src
,
502 st_src_reg src2
= undef_src
,
503 st_src_reg src3
= undef_src
);
505 glsl_to_tgsi_instruction
*emit_asm(ir_instruction
*ir
, unsigned op
,
506 st_dst_reg dst
, st_dst_reg dst1
,
507 st_src_reg src0
= undef_src
,
508 st_src_reg src1
= undef_src
,
509 st_src_reg src2
= undef_src
,
510 st_src_reg src3
= undef_src
);
512 unsigned get_opcode(unsigned op
,
514 st_src_reg src0
, st_src_reg src1
);
517 * Emit the correct dot-product instruction for the type of arguments
519 glsl_to_tgsi_instruction
*emit_dp(ir_instruction
*ir
,
525 void emit_scalar(ir_instruction
*ir
, unsigned op
,
526 st_dst_reg dst
, st_src_reg src0
);
528 void emit_scalar(ir_instruction
*ir
, unsigned op
,
529 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
);
531 void emit_arl(ir_instruction
*ir
, st_dst_reg dst
, st_src_reg src0
);
533 void get_deref_offsets(ir_dereference
*ir
,
534 unsigned *array_size
,
539 void calc_deref_offsets(ir_dereference
*tail
,
540 unsigned *array_elements
,
542 st_src_reg
*indirect
,
544 st_src_reg
canonicalize_gather_offset(st_src_reg offset
);
546 bool try_emit_mad(ir_expression
*ir
,
548 bool try_emit_mad_for_and_not(ir_expression
*ir
,
551 void emit_swz(ir_expression
*ir
);
553 bool process_move_condition(ir_rvalue
*ir
);
555 void simplify_cmp(void);
557 void rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
);
558 void get_first_temp_read(int *first_reads
);
559 void get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
);
560 void get_last_temp_write(int *last_writes
);
562 void copy_propagate(void);
563 int eliminate_dead_code(void);
565 void merge_two_dsts(void);
566 void merge_registers(void);
567 void renumber_registers(void);
569 void emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
570 st_dst_reg
*l
, st_src_reg
*r
,
571 st_src_reg
*cond
, bool cond_swap
);
576 static st_dst_reg address_reg
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 0);
577 static st_dst_reg address_reg2
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 1);
578 static st_dst_reg sampler_reladdr
= st_dst_reg(PROGRAM_ADDRESS
, WRITEMASK_X
, GLSL_TYPE_FLOAT
, 2);
581 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...) PRINTFLIKE(2, 3);
584 fail_link(struct gl_shader_program
*prog
, const char *fmt
, ...)
588 ralloc_vasprintf_append(&prog
->data
->InfoLog
, fmt
, args
);
591 prog
->data
->LinkStatus
= GL_FALSE
;
595 swizzle_for_size(int size
)
597 static const int size_swizzles
[4] = {
598 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
599 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
600 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
601 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
604 assert((size
>= 1) && (size
<= 4));
605 return size_swizzles
[size
- 1];
609 is_resource_instruction(unsigned opcode
)
612 case TGSI_OPCODE_RESQ
:
613 case TGSI_OPCODE_LOAD
:
614 case TGSI_OPCODE_ATOMUADD
:
615 case TGSI_OPCODE_ATOMXCHG
:
616 case TGSI_OPCODE_ATOMCAS
:
617 case TGSI_OPCODE_ATOMAND
:
618 case TGSI_OPCODE_ATOMOR
:
619 case TGSI_OPCODE_ATOMXOR
:
620 case TGSI_OPCODE_ATOMUMIN
:
621 case TGSI_OPCODE_ATOMUMAX
:
622 case TGSI_OPCODE_ATOMIMIN
:
623 case TGSI_OPCODE_ATOMIMAX
:
631 num_inst_dst_regs(const glsl_to_tgsi_instruction
*op
)
633 return op
->info
->num_dst
;
637 num_inst_src_regs(const glsl_to_tgsi_instruction
*op
)
639 return op
->info
->is_tex
|| is_resource_instruction(op
->op
) ?
640 op
->info
->num_src
- 1 : op
->info
->num_src
;
643 glsl_to_tgsi_instruction
*
644 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
645 st_dst_reg dst
, st_dst_reg dst1
,
646 st_src_reg src0
, st_src_reg src1
,
647 st_src_reg src2
, st_src_reg src3
)
649 glsl_to_tgsi_instruction
*inst
= new(mem_ctx
) glsl_to_tgsi_instruction();
650 int num_reladdr
= 0, i
, j
;
651 bool dst_is_64bit
[2];
653 op
= get_opcode(op
, dst
, src0
, src1
);
655 /* If we have to do relative addressing, we want to load the ARL
656 * reg directly for one of the regs, and preload the other reladdr
657 * sources into temps.
659 num_reladdr
+= dst
.reladdr
!= NULL
|| dst
.reladdr2
;
660 num_reladdr
+= dst1
.reladdr
!= NULL
|| dst1
.reladdr2
;
661 num_reladdr
+= src0
.reladdr
!= NULL
|| src0
.reladdr2
!= NULL
;
662 num_reladdr
+= src1
.reladdr
!= NULL
|| src1
.reladdr2
!= NULL
;
663 num_reladdr
+= src2
.reladdr
!= NULL
|| src2
.reladdr2
!= NULL
;
664 num_reladdr
+= src3
.reladdr
!= NULL
|| src3
.reladdr2
!= NULL
;
666 reladdr_to_temp(ir
, &src3
, &num_reladdr
);
667 reladdr_to_temp(ir
, &src2
, &num_reladdr
);
668 reladdr_to_temp(ir
, &src1
, &num_reladdr
);
669 reladdr_to_temp(ir
, &src0
, &num_reladdr
);
671 if (dst
.reladdr
|| dst
.reladdr2
) {
673 emit_arl(ir
, address_reg
, *dst
.reladdr
);
675 emit_arl(ir
, address_reg2
, *dst
.reladdr2
);
679 emit_arl(ir
, address_reg
, *dst1
.reladdr
);
682 assert(num_reladdr
== 0);
684 /* inst->op has only 8 bits. */
685 STATIC_ASSERT(TGSI_OPCODE_LAST
<= 255);
688 inst
->info
= tgsi_get_opcode_info(op
);
695 inst
->is_64bit_expanded
= false;
698 inst
->tex_offsets
= NULL
;
699 inst
->tex_offset_num_offset
= 0;
701 inst
->tex_shadow
= 0;
702 /* default to float, for paths where this is not initialized
703 * (since 0==UINT which is likely wrong):
705 inst
->tex_type
= GLSL_TYPE_FLOAT
;
707 /* Update indirect addressing status used by TGSI */
708 if (dst
.reladdr
|| dst
.reladdr2
) {
710 case PROGRAM_STATE_VAR
:
711 case PROGRAM_CONSTANT
:
712 case PROGRAM_UNIFORM
:
713 this->indirect_addr_consts
= true;
715 case PROGRAM_IMMEDIATE
:
716 assert(!"immediates should not have indirect addressing");
723 for (i
= 0; i
< 4; i
++) {
724 if(inst
->src
[i
].reladdr
) {
725 switch(inst
->src
[i
].file
) {
726 case PROGRAM_STATE_VAR
:
727 case PROGRAM_CONSTANT
:
728 case PROGRAM_UNIFORM
:
729 this->indirect_addr_consts
= true;
731 case PROGRAM_IMMEDIATE
:
732 assert(!"immediates should not have indirect addressing");
742 * This section contains the double processing.
743 * GLSL just represents doubles as single channel values,
744 * however most HW and TGSI represent doubles as pairs of register channels.
746 * so we have to fixup destination writemask/index and src swizzle/indexes.
747 * dest writemasks need to translate from single channel write mask
748 * to a dual-channel writemask, but also need to modify the index,
749 * if we are touching the Z,W fields in the pre-translated writemask.
751 * src channels have similiar index modifications along with swizzle
752 * changes to we pick the XY, ZW pairs from the correct index.
754 * GLSL [0].x -> TGSI [0].xy
755 * GLSL [0].y -> TGSI [0].zw
756 * GLSL [0].z -> TGSI [1].xy
757 * GLSL [0].w -> TGSI [1].zw
759 for (j
= 0; j
< 2; j
++) {
760 dst_is_64bit
[j
] = glsl_base_type_is_64bit(inst
->dst
[j
].type
);
761 if (!dst_is_64bit
[j
] && inst
->dst
[j
].file
== PROGRAM_OUTPUT
&& inst
->dst
[j
].type
== GLSL_TYPE_ARRAY
) {
762 enum glsl_base_type type
= find_array_type(this->outputs
, this->num_outputs
, inst
->dst
[j
].array_id
);
763 if (glsl_base_type_is_64bit(type
))
764 dst_is_64bit
[j
] = true;
768 if (dst_is_64bit
[0] || dst_is_64bit
[1] ||
769 glsl_base_type_is_64bit(inst
->src
[0].type
)) {
770 glsl_to_tgsi_instruction
*dinst
= NULL
;
771 int initial_src_swz
[4], initial_src_idx
[4];
772 int initial_dst_idx
[2], initial_dst_writemask
[2];
773 /* select the writemask for dst0 or dst1 */
774 unsigned writemask
= inst
->dst
[1].file
== PROGRAM_UNDEFINED
? inst
->dst
[0].writemask
: inst
->dst
[1].writemask
;
776 /* copy out the writemask, index and swizzles for all src/dsts. */
777 for (j
= 0; j
< 2; j
++) {
778 initial_dst_writemask
[j
] = inst
->dst
[j
].writemask
;
779 initial_dst_idx
[j
] = inst
->dst
[j
].index
;
782 for (j
= 0; j
< 4; j
++) {
783 initial_src_swz
[j
] = inst
->src
[j
].swizzle
;
784 initial_src_idx
[j
] = inst
->src
[j
].index
;
788 * scan all the components in the dst writemask
789 * generate an instruction for each of them if required.
794 int i
= u_bit_scan(&writemask
);
796 /* before emitting the instruction, see if we have to adjust load / store
798 if (i
> 1 && (inst
->op
== TGSI_OPCODE_LOAD
|| inst
->op
== TGSI_OPCODE_STORE
) &&
799 addr
.file
== PROGRAM_UNDEFINED
) {
800 /* We have to advance the buffer address by 16 */
801 addr
= get_temp(glsl_type::uint_type
);
802 emit_asm(ir
, TGSI_OPCODE_UADD
, st_dst_reg(addr
),
803 inst
->src
[0], st_src_reg_for_int(16));
806 /* first time use previous instruction */
810 /* create a new instructions for subsequent attempts */
811 dinst
= new(mem_ctx
) glsl_to_tgsi_instruction();
816 this->instructions
.push_tail(dinst
);
817 dinst
->is_64bit_expanded
= true;
819 /* modify the destination if we are splitting */
820 for (j
= 0; j
< 2; j
++) {
821 if (dst_is_64bit
[j
]) {
822 dinst
->dst
[j
].writemask
= (i
& 1) ? WRITEMASK_ZW
: WRITEMASK_XY
;
823 dinst
->dst
[j
].index
= initial_dst_idx
[j
];
825 if (dinst
->op
== TGSI_OPCODE_LOAD
|| dinst
->op
== TGSI_OPCODE_STORE
)
826 dinst
->src
[0] = addr
;
827 if (dinst
->op
!= TGSI_OPCODE_STORE
)
828 dinst
->dst
[j
].index
++;
831 /* if we aren't writing to a double, just get the bit of the initial writemask
833 dinst
->dst
[j
].writemask
= initial_dst_writemask
[j
] & (1 << i
);
837 /* modify the src registers */
838 for (j
= 0; j
< 4; j
++) {
839 int swz
= GET_SWZ(initial_src_swz
[j
], i
);
841 if (glsl_base_type_is_64bit(dinst
->src
[j
].type
)) {
842 dinst
->src
[j
].index
= initial_src_idx
[j
];
844 dinst
->src
[j
].double_reg2
= true;
845 dinst
->src
[j
].index
++;
849 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_Z
, SWIZZLE_W
, SWIZZLE_Z
, SWIZZLE_W
);
851 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
854 /* some opcodes are special case in what they use as sources
855 - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer src1 */
856 if (op
== TGSI_OPCODE_F2D
|| op
== TGSI_OPCODE_U2D
|| op
== TGSI_OPCODE_I2D
||
857 op
== TGSI_OPCODE_I2I64
|| op
== TGSI_OPCODE_U2I64
||
858 op
== TGSI_OPCODE_DLDEXP
||
859 (op
== TGSI_OPCODE_UCMP
&& dst_is_64bit
[0])) {
860 dinst
->src
[j
].swizzle
= MAKE_SWIZZLE4(swz
, swz
, swz
, swz
);
867 this->instructions
.push_tail(inst
);
874 glsl_to_tgsi_instruction
*
875 glsl_to_tgsi_visitor::emit_asm(ir_instruction
*ir
, unsigned op
,
877 st_src_reg src0
, st_src_reg src1
,
878 st_src_reg src2
, st_src_reg src3
)
880 return emit_asm(ir
, op
, dst
, undef_dst
, src0
, src1
, src2
, src3
);
884 * Determines whether to use an integer, unsigned integer, or float opcode
885 * based on the operands and input opcode, then emits the result.
888 glsl_to_tgsi_visitor::get_opcode(unsigned op
,
890 st_src_reg src0
, st_src_reg src1
)
892 enum glsl_base_type type
= GLSL_TYPE_FLOAT
;
894 if (op
== TGSI_OPCODE_MOV
)
897 assert(src0
.type
!= GLSL_TYPE_ARRAY
);
898 assert(src0
.type
!= GLSL_TYPE_STRUCT
);
899 assert(src1
.type
!= GLSL_TYPE_ARRAY
);
900 assert(src1
.type
!= GLSL_TYPE_STRUCT
);
902 if (is_resource_instruction(op
))
904 else if (src0
.type
== GLSL_TYPE_DOUBLE
|| src1
.type
== GLSL_TYPE_DOUBLE
)
905 type
= GLSL_TYPE_DOUBLE
;
906 else if (src0
.type
== GLSL_TYPE_FLOAT
|| src1
.type
== GLSL_TYPE_FLOAT
)
907 type
= GLSL_TYPE_FLOAT
;
908 else if (native_integers
)
909 type
= src0
.type
== GLSL_TYPE_BOOL
? GLSL_TYPE_INT
: src0
.type
;
911 #define case5(c, f, i, u, d) \
912 case TGSI_OPCODE_##c: \
913 if (type == GLSL_TYPE_DOUBLE) \
914 op = TGSI_OPCODE_##d; \
915 else if (type == GLSL_TYPE_INT) \
916 op = TGSI_OPCODE_##i; \
917 else if (type == GLSL_TYPE_UINT) \
918 op = TGSI_OPCODE_##u; \
920 op = TGSI_OPCODE_##f; \
923 #define case4(c, f, i, u) \
924 case TGSI_OPCODE_##c: \
925 if (type == GLSL_TYPE_INT) \
926 op = TGSI_OPCODE_##i; \
927 else if (type == GLSL_TYPE_UINT) \
928 op = TGSI_OPCODE_##u; \
930 op = TGSI_OPCODE_##f; \
933 #define case3(f, i, u) case4(f, f, i, u)
934 #define case4d(f, i, u, d) case5(f, f, i, u, d)
935 #define case3fid(f, i, d) case5(f, f, i, i, d)
936 #define case2fi(f, i) case4(f, f, i, i)
937 #define case2iu(i, u) case4(i, LAST, i, u)
939 #define casecomp(c, f, i, u, d) \
940 case TGSI_OPCODE_##c: \
941 if (type == GLSL_TYPE_DOUBLE) \
942 op = TGSI_OPCODE_##d; \
943 else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \
944 op = TGSI_OPCODE_##i; \
945 else if (type == GLSL_TYPE_UINT) \
946 op = TGSI_OPCODE_##u; \
947 else if (native_integers) \
948 op = TGSI_OPCODE_##f; \
950 op = TGSI_OPCODE_##c; \
954 case3fid(ADD
, UADD
, DADD
);
955 case3fid(MUL
, UMUL
, DMUL
);
956 case3fid(MAD
, UMAD
, DMAD
);
957 case3fid(FMA
, UMAD
, DFMA
);
958 case3(DIV
, IDIV
, UDIV
);
959 case4d(MAX
, IMAX
, UMAX
, DMAX
);
960 case4d(MIN
, IMIN
, UMIN
, DMIN
);
963 casecomp(SEQ
, FSEQ
, USEQ
, USEQ
, DSEQ
);
964 casecomp(SNE
, FSNE
, USNE
, USNE
, DSNE
);
965 casecomp(SGE
, FSGE
, ISGE
, USGE
, DSGE
);
966 casecomp(SLT
, FSLT
, ISLT
, USLT
, DSLT
);
970 case3fid(SSG
, ISSG
, DSSG
);
974 case2iu(IMUL_HI
, UMUL_HI
);
976 case3fid(SQRT
, SQRT
, DSQRT
);
978 case3fid(RCP
, RCP
, DRCP
);
979 case3fid(RSQ
, RSQ
, DRSQ
);
981 case3fid(FRC
, FRC
, DFRAC
);
982 case3fid(TRUNC
, TRUNC
, DTRUNC
);
983 case3fid(CEIL
, CEIL
, DCEIL
);
984 case3fid(FLR
, FLR
, DFLR
);
985 case3fid(ROUND
, ROUND
, DROUND
);
987 case2iu(ATOMIMAX
, ATOMUMAX
);
988 case2iu(ATOMIMIN
, ATOMUMIN
);
993 assert(op
!= TGSI_OPCODE_LAST
);
997 glsl_to_tgsi_instruction
*
998 glsl_to_tgsi_visitor::emit_dp(ir_instruction
*ir
,
999 st_dst_reg dst
, st_src_reg src0
, st_src_reg src1
,
1002 static const unsigned dot_opcodes
[] = {
1003 TGSI_OPCODE_DP2
, TGSI_OPCODE_DP3
, TGSI_OPCODE_DP4
1006 return emit_asm(ir
, dot_opcodes
[elements
- 2], dst
, src0
, src1
);
1010 * Emits TGSI scalar opcodes to produce unique answers across channels.
1012 * Some TGSI opcodes are scalar-only, like ARB_fp/vp. The src X
1013 * channel determines the result across all channels. So to do a vec4
1014 * of this operation, we want to emit a scalar per source channel used
1015 * to produce dest channels.
1018 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1020 st_src_reg orig_src0
, st_src_reg orig_src1
)
1023 int done_mask
= ~dst
.writemask
;
1025 /* TGSI RCP is a scalar operation splatting results to all channels,
1026 * like ARB_fp/vp. So emit as many RCPs as necessary to cover our
1029 for (i
= 0; i
< 4; i
++) {
1030 GLuint this_mask
= (1 << i
);
1031 st_src_reg src0
= orig_src0
;
1032 st_src_reg src1
= orig_src1
;
1034 if (done_mask
& this_mask
)
1037 GLuint src0_swiz
= GET_SWZ(src0
.swizzle
, i
);
1038 GLuint src1_swiz
= GET_SWZ(src1
.swizzle
, i
);
1039 for (j
= i
+ 1; j
< 4; j
++) {
1040 /* If there is another enabled component in the destination that is
1041 * derived from the same inputs, generate its value on this pass as
1044 if (!(done_mask
& (1 << j
)) &&
1045 GET_SWZ(src0
.swizzle
, j
) == src0_swiz
&&
1046 GET_SWZ(src1
.swizzle
, j
) == src1_swiz
) {
1047 this_mask
|= (1 << j
);
1050 src0
.swizzle
= MAKE_SWIZZLE4(src0_swiz
, src0_swiz
,
1051 src0_swiz
, src0_swiz
);
1052 src1
.swizzle
= MAKE_SWIZZLE4(src1_swiz
, src1_swiz
,
1053 src1_swiz
, src1_swiz
);
1055 dst
.writemask
= this_mask
;
1056 emit_asm(ir
, op
, dst
, src0
, src1
);
1057 done_mask
|= this_mask
;
1062 glsl_to_tgsi_visitor::emit_scalar(ir_instruction
*ir
, unsigned op
,
1063 st_dst_reg dst
, st_src_reg src0
)
1065 st_src_reg undef
= undef_src
;
1067 undef
.swizzle
= SWIZZLE_XXXX
;
1069 emit_scalar(ir
, op
, dst
, src0
, undef
);
1073 glsl_to_tgsi_visitor::emit_arl(ir_instruction
*ir
,
1074 st_dst_reg dst
, st_src_reg src0
)
1076 int op
= TGSI_OPCODE_ARL
;
1078 if (src0
.type
== GLSL_TYPE_INT
|| src0
.type
== GLSL_TYPE_UINT
)
1079 op
= TGSI_OPCODE_UARL
;
1081 assert(dst
.file
== PROGRAM_ADDRESS
);
1082 if (dst
.index
>= this->num_address_regs
)
1083 this->num_address_regs
= dst
.index
+ 1;
1085 emit_asm(NULL
, op
, dst
, src0
);
1089 glsl_to_tgsi_visitor::add_constant(gl_register_file file
,
1090 gl_constant_value values
[8], int size
, int datatype
,
1091 uint16_t *swizzle_out
)
1093 if (file
== PROGRAM_CONSTANT
) {
1094 GLuint swizzle
= swizzle_out
? *swizzle_out
: 0;
1095 int result
= _mesa_add_typed_unnamed_constant(this->prog
->Parameters
, values
,
1096 size
, datatype
, &swizzle
);
1098 *swizzle_out
= swizzle
;
1102 assert(file
== PROGRAM_IMMEDIATE
);
1105 immediate_storage
*entry
;
1106 int size32
= size
* (datatype
== GL_DOUBLE
? 2 : 1);
1109 /* Search immediate storage to see if we already have an identical
1110 * immediate that we can use instead of adding a duplicate entry.
1112 foreach_in_list(immediate_storage
, entry
, &this->immediates
) {
1113 immediate_storage
*tmp
= entry
;
1115 for (i
= 0; i
* 4 < size32
; i
++) {
1116 int slot_size
= MIN2(size32
- (i
* 4), 4);
1117 if (tmp
->type
!= datatype
|| tmp
->size32
!= slot_size
)
1119 if (memcmp(tmp
->values
, &values
[i
* 4],
1120 slot_size
* sizeof(gl_constant_value
)))
1123 /* Everything matches, keep going until the full size is matched */
1124 tmp
= (immediate_storage
*)tmp
->next
;
1127 /* The full value matched */
1128 if (i
* 4 >= size32
)
1134 for (i
= 0; i
* 4 < size32
; i
++) {
1135 int slot_size
= MIN2(size32
- (i
* 4), 4);
1136 /* Add this immediate to the list. */
1137 entry
= new(mem_ctx
) immediate_storage(&values
[i
* 4], slot_size
, datatype
);
1138 this->immediates
.push_tail(entry
);
1139 this->num_immediates
++;
1145 glsl_to_tgsi_visitor::st_src_reg_for_float(float val
)
1147 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_FLOAT
);
1148 union gl_constant_value uval
;
1151 src
.index
= add_constant(src
.file
, &uval
, 1, GL_FLOAT
, &src
.swizzle
);
1157 glsl_to_tgsi_visitor::st_src_reg_for_double(double val
)
1159 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_DOUBLE
);
1160 union gl_constant_value uval
[2];
1162 memcpy(uval
, &val
, sizeof(uval
));
1163 src
.index
= add_constant(src
.file
, uval
, 1, GL_DOUBLE
, &src
.swizzle
);
1164 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
1169 glsl_to_tgsi_visitor::st_src_reg_for_int(int val
)
1171 st_src_reg
src(PROGRAM_IMMEDIATE
, -1, GLSL_TYPE_INT
);
1172 union gl_constant_value uval
;
1174 assert(native_integers
);
1177 src
.index
= add_constant(src
.file
, &uval
, 1, GL_INT
, &src
.swizzle
);
1183 glsl_to_tgsi_visitor::st_src_reg_for_type(enum glsl_base_type type
, int val
)
1185 if (native_integers
)
1186 return type
== GLSL_TYPE_FLOAT
? st_src_reg_for_float(val
) :
1187 st_src_reg_for_int(val
);
1189 return st_src_reg_for_float(val
);
1193 attrib_type_size(const struct glsl_type
*type
, bool is_vs_input
)
1195 return st_glsl_attrib_type_size(type
, is_vs_input
);
1199 type_size(const struct glsl_type
*type
)
1201 return st_glsl_type_size(type
);
1205 * If the given GLSL type is an array or matrix or a structure containing
1206 * an array/matrix member, return true. Else return false.
1208 * This is used to determine which kind of temp storage (PROGRAM_TEMPORARY
1209 * or PROGRAM_ARRAY) should be used for variables of this type. Anytime
1210 * we have an array that might be indexed with a variable, we need to use
1211 * the later storage type.
1214 type_has_array_or_matrix(const glsl_type
*type
)
1216 if (type
->is_array() || type
->is_matrix())
1219 if (type
->is_record()) {
1220 for (unsigned i
= 0; i
< type
->length
; i
++) {
1221 if (type_has_array_or_matrix(type
->fields
.structure
[i
].type
)) {
1232 * In the initial pass of codegen, we assign temporary numbers to
1233 * intermediate results. (not SSA -- variable assignments will reuse
1237 glsl_to_tgsi_visitor::get_temp(const glsl_type
*type
)
1241 src
.type
= native_integers
? type
->base_type
: GLSL_TYPE_FLOAT
;
1246 if (!options
->EmitNoIndirectTemp
&& type_has_array_or_matrix(type
)) {
1247 if (next_array
>= max_num_arrays
) {
1248 max_num_arrays
+= 32;
1249 array_sizes
= (unsigned*)
1250 realloc(array_sizes
, sizeof(array_sizes
[0]) * max_num_arrays
);
1253 src
.file
= PROGRAM_ARRAY
;
1255 src
.array_id
= next_array
+ 1;
1256 array_sizes
[next_array
] = type_size(type
);
1260 src
.file
= PROGRAM_TEMPORARY
;
1261 src
.index
= next_temp
;
1262 next_temp
+= type_size(type
);
1265 if (type
->is_array() || type
->is_record()) {
1266 src
.swizzle
= SWIZZLE_NOOP
;
1268 src
.swizzle
= swizzle_for_size(type
->vector_elements
);
1275 glsl_to_tgsi_visitor::find_variable_storage(ir_variable
*var
)
1278 foreach_in_list(variable_storage
, entry
, &this->variables
) {
1279 if (entry
->var
== var
)
1287 glsl_to_tgsi_visitor::visit(ir_variable
*ir
)
1289 if (strcmp(ir
->name
, "gl_FragCoord") == 0) {
1290 this->prog
->OriginUpperLeft
= ir
->data
.origin_upper_left
;
1291 this->prog
->PixelCenterInteger
= ir
->data
.pixel_center_integer
;
1294 if (ir
->data
.mode
== ir_var_uniform
&& strncmp(ir
->name
, "gl_", 3) == 0) {
1296 const ir_state_slot
*const slots
= ir
->get_state_slots();
1297 assert(slots
!= NULL
);
1299 /* Check if this statevar's setup in the STATE file exactly
1300 * matches how we'll want to reference it as a
1301 * struct/array/whatever. If not, then we need to move it into
1302 * temporary storage and hope that it'll get copy-propagated
1305 for (i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1306 if (slots
[i
].swizzle
!= SWIZZLE_XYZW
) {
1311 variable_storage
*storage
;
1313 if (i
== ir
->get_num_state_slots()) {
1314 /* We'll set the index later. */
1315 storage
= new(mem_ctx
) variable_storage(ir
, PROGRAM_STATE_VAR
, -1);
1316 this->variables
.push_tail(storage
);
1320 /* The variable_storage constructor allocates slots based on the size
1321 * of the type. However, this had better match the number of state
1322 * elements that we're going to copy into the new temporary.
1324 assert((int) ir
->get_num_state_slots() == type_size(ir
->type
));
1326 dst
= st_dst_reg(get_temp(ir
->type
));
1328 storage
= new(mem_ctx
) variable_storage(ir
, dst
.file
, dst
.index
,
1331 this->variables
.push_tail(storage
);
1335 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1336 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1337 (gl_state_index
*)slots
[i
].tokens
);
1339 if (storage
->file
== PROGRAM_STATE_VAR
) {
1340 if (storage
->index
== -1) {
1341 storage
->index
= index
;
1343 assert(index
== storage
->index
+ (int)i
);
1346 /* We use GLSL_TYPE_FLOAT here regardless of the actual type of
1347 * the data being moved since MOV does not care about the type of
1348 * data it is moving, and we don't want to declare registers with
1349 * array or struct types.
1351 st_src_reg
src(PROGRAM_STATE_VAR
, index
, GLSL_TYPE_FLOAT
);
1352 src
.swizzle
= slots
[i
].swizzle
;
1353 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, src
);
1354 /* even a float takes up a whole vec4 reg in a struct/array. */
1359 if (storage
->file
== PROGRAM_TEMPORARY
&&
1360 dst
.index
!= storage
->index
+ (int) ir
->get_num_state_slots()) {
1361 fail_link(this->shader_program
,
1362 "failed to load builtin uniform `%s' (%d/%d regs loaded)\n",
1363 ir
->name
, dst
.index
- storage
->index
,
1364 type_size(ir
->type
));
1370 glsl_to_tgsi_visitor::visit(ir_loop
*ir
)
1372 emit_asm(NULL
, TGSI_OPCODE_BGNLOOP
);
1374 visit_exec_list(&ir
->body_instructions
, this);
1376 emit_asm(NULL
, TGSI_OPCODE_ENDLOOP
);
1380 glsl_to_tgsi_visitor::visit(ir_loop_jump
*ir
)
1383 case ir_loop_jump::jump_break
:
1384 emit_asm(NULL
, TGSI_OPCODE_BRK
);
1386 case ir_loop_jump::jump_continue
:
1387 emit_asm(NULL
, TGSI_OPCODE_CONT
);
1394 glsl_to_tgsi_visitor::visit(ir_function_signature
*ir
)
1401 glsl_to_tgsi_visitor::visit(ir_function
*ir
)
1403 /* Ignore function bodies other than main() -- we shouldn't see calls to
1404 * them since they should all be inlined before we get to glsl_to_tgsi.
1406 if (strcmp(ir
->name
, "main") == 0) {
1407 const ir_function_signature
*sig
;
1410 sig
= ir
->matching_signature(NULL
, &empty
, false);
1414 foreach_in_list(ir_instruction
, ir
, &sig
->body
) {
1421 glsl_to_tgsi_visitor::try_emit_mad(ir_expression
*ir
, int mul_operand
)
1423 int nonmul_operand
= 1 - mul_operand
;
1425 st_dst_reg result_dst
;
1427 ir_expression
*expr
= ir
->operands
[mul_operand
]->as_expression();
1428 if (!expr
|| expr
->operation
!= ir_binop_mul
)
1431 expr
->operands
[0]->accept(this);
1433 expr
->operands
[1]->accept(this);
1435 ir
->operands
[nonmul_operand
]->accept(this);
1438 this->result
= get_temp(ir
->type
);
1439 result_dst
= st_dst_reg(this->result
);
1440 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1441 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, a
, b
, c
);
1447 * Emit MAD(a, -b, a) instead of AND(a, NOT(b))
1449 * The logic values are 1.0 for true and 0.0 for false. Logical-and is
1450 * implemented using multiplication, and logical-or is implemented using
1451 * addition. Logical-not can be implemented as (true - x), or (1.0 - x).
1452 * As result, the logical expression (a & !b) can be rewritten as:
1456 * - (a * 1) - (a * b)
1460 * This final expression can be implemented as a single MAD(a, -b, a)
1464 glsl_to_tgsi_visitor::try_emit_mad_for_and_not(ir_expression
*ir
, int try_operand
)
1466 const int other_operand
= 1 - try_operand
;
1469 ir_expression
*expr
= ir
->operands
[try_operand
]->as_expression();
1470 if (!expr
|| expr
->operation
!= ir_unop_logic_not
)
1473 ir
->operands
[other_operand
]->accept(this);
1475 expr
->operands
[0]->accept(this);
1478 b
.negate
= ~b
.negate
;
1480 this->result
= get_temp(ir
->type
);
1481 emit_asm(ir
, TGSI_OPCODE_MAD
, st_dst_reg(this->result
), a
, b
, a
);
1487 glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction
*ir
,
1488 st_src_reg
*reg
, int *num_reladdr
)
1490 if (!reg
->reladdr
&& !reg
->reladdr2
)
1493 if (reg
->reladdr
) emit_arl(ir
, address_reg
, *reg
->reladdr
);
1494 if (reg
->reladdr2
) emit_arl(ir
, address_reg2
, *reg
->reladdr2
);
1496 if (*num_reladdr
!= 1) {
1497 st_src_reg temp
= get_temp(reg
->type
== GLSL_TYPE_DOUBLE
? glsl_type::dvec4_type
: glsl_type::vec4_type
);
1499 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), *reg
);
1507 glsl_to_tgsi_visitor::visit(ir_expression
*ir
)
1509 st_src_reg op
[ARRAY_SIZE(ir
->operands
)];
1511 /* Quick peephole: Emit MAD(a, b, c) instead of ADD(MUL(a, b), c)
1513 if (ir
->operation
== ir_binop_add
) {
1514 if (try_emit_mad(ir
, 1))
1516 if (try_emit_mad(ir
, 0))
1520 /* Quick peephole: Emit OPCODE_MAD(-a, -b, a) instead of AND(a, NOT(b))
1522 if (!native_integers
&& ir
->operation
== ir_binop_logic_and
) {
1523 if (try_emit_mad_for_and_not(ir
, 1))
1525 if (try_emit_mad_for_and_not(ir
, 0))
1529 if (ir
->operation
== ir_quadop_vector
)
1530 assert(!"ir_quadop_vector should have been lowered");
1532 for (unsigned int operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
1533 this->result
.file
= PROGRAM_UNDEFINED
;
1534 ir
->operands
[operand
]->accept(this);
1535 if (this->result
.file
== PROGRAM_UNDEFINED
) {
1536 printf("Failed to get tree for expression operand:\n");
1537 ir
->operands
[operand
]->print();
1541 op
[operand
] = this->result
;
1543 /* Matrix expression operands should have been broken down to vector
1544 * operations already.
1546 assert(!ir
->operands
[operand
]->type
->is_matrix());
1549 visit_expression(ir
, op
);
1552 /* The non-recursive part of the expression visitor lives in a separate
1553 * function and should be prevented from being inlined, to avoid a stack
1554 * explosion when deeply nested expressions are visited.
1557 glsl_to_tgsi_visitor::visit_expression(ir_expression
* ir
, st_src_reg
*op
)
1559 st_src_reg result_src
;
1560 st_dst_reg result_dst
;
1562 int vector_elements
= ir
->operands
[0]->type
->vector_elements
;
1563 if (ir
->operands
[1]) {
1564 vector_elements
= MAX2(vector_elements
,
1565 ir
->operands
[1]->type
->vector_elements
);
1568 this->result
.file
= PROGRAM_UNDEFINED
;
1570 /* Storage for our result. Ideally for an assignment we'd be using
1571 * the actual storage for the result here, instead.
1573 result_src
= get_temp(ir
->type
);
1574 /* convenience for the emit functions below. */
1575 result_dst
= st_dst_reg(result_src
);
1576 /* Limit writes to the channels that will be used by result_src later.
1577 * This does limit this temp's use as a temporary for multi-instruction
1580 result_dst
.writemask
= (1 << ir
->type
->vector_elements
) - 1;
1582 switch (ir
->operation
) {
1583 case ir_unop_logic_not
:
1584 if (result_dst
.type
!= GLSL_TYPE_FLOAT
)
1585 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
1587 /* Previously 'SEQ dst, src, 0.0' was used for this. However, many
1588 * older GPUs implement SEQ using multiple instructions (i915 uses two
1589 * SGE instructions and a MUL instruction). Since our logic values are
1590 * 0.0 and 1.0, 1-x also implements !x.
1592 op
[0].negate
= ~op
[0].negate
;
1593 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1597 if (result_dst
.type
== GLSL_TYPE_INT
|| result_dst
.type
== GLSL_TYPE_UINT
)
1598 emit_asm(ir
, TGSI_OPCODE_INEG
, result_dst
, op
[0]);
1599 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1600 emit_asm(ir
, TGSI_OPCODE_DNEG
, result_dst
, op
[0]);
1602 op
[0].negate
= ~op
[0].negate
;
1606 case ir_unop_subroutine_to_int
:
1607 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1610 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1611 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0].get_abs());
1612 else if (result_dst
.type
== GLSL_TYPE_DOUBLE
)
1613 emit_asm(ir
, TGSI_OPCODE_DABS
, result_dst
, op
[0]);
1615 emit_asm(ir
, TGSI_OPCODE_IABS
, result_dst
, op
[0]);
1618 emit_asm(ir
, TGSI_OPCODE_SSG
, result_dst
, op
[0]);
1621 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, op
[0]);
1625 emit_scalar(ir
, TGSI_OPCODE_EX2
, result_dst
, op
[0]);
1629 assert(!"not reached: should be handled by ir_explog_to_explog2");
1632 emit_scalar(ir
, TGSI_OPCODE_LG2
, result_dst
, op
[0]);
1635 emit_scalar(ir
, TGSI_OPCODE_SIN
, result_dst
, op
[0]);
1638 emit_scalar(ir
, TGSI_OPCODE_COS
, result_dst
, op
[0]);
1640 case ir_unop_saturate
: {
1641 glsl_to_tgsi_instruction
*inst
;
1642 inst
= emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
1643 inst
->saturate
= true;
1648 case ir_unop_dFdx_coarse
:
1649 emit_asm(ir
, TGSI_OPCODE_DDX
, result_dst
, op
[0]);
1651 case ir_unop_dFdx_fine
:
1652 emit_asm(ir
, TGSI_OPCODE_DDX_FINE
, result_dst
, op
[0]);
1655 case ir_unop_dFdy_coarse
:
1656 case ir_unop_dFdy_fine
:
1658 /* The X component contains 1 or -1 depending on whether the framebuffer
1659 * is a FBO or the window system buffer, respectively.
1660 * It is then multiplied with the source operand of DDY.
1662 static const gl_state_index transform_y_state
[STATE_LENGTH
]
1663 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
1665 unsigned transform_y_index
=
1666 _mesa_add_state_reference(this->prog
->Parameters
,
1669 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
1671 glsl_type::vec4_type
);
1672 transform_y
.swizzle
= SWIZZLE_XXXX
;
1674 st_src_reg temp
= get_temp(glsl_type::vec4_type
);
1676 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(temp
), transform_y
, op
[0]);
1677 emit_asm(ir
, ir
->operation
== ir_unop_dFdy_fine
?
1678 TGSI_OPCODE_DDY_FINE
: TGSI_OPCODE_DDY
, result_dst
, temp
);
1682 case ir_unop_frexp_sig
:
1683 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, result_dst
, undef_dst
, op
[0]);
1686 case ir_unop_frexp_exp
:
1687 emit_asm(ir
, TGSI_OPCODE_DFRACEXP
, undef_dst
, result_dst
, op
[0]);
1690 case ir_unop_noise
: {
1691 /* At some point, a motivated person could add a better
1692 * implementation of noise. Currently not even the nvidia
1693 * binary drivers do anything more than this. In any case, the
1694 * place to do this is in the GL state tracker, not the poor
1697 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, st_src_reg_for_float(0.5));
1702 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1705 op
[1].negate
= ~op
[1].negate
;
1706 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1710 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1713 if (result_dst
.type
== GLSL_TYPE_FLOAT
|| result_dst
.type
== GLSL_TYPE_DOUBLE
)
1714 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1716 emit_asm(ir
, TGSI_OPCODE_DIV
, result_dst
, op
[0], op
[1]);
1719 if (result_dst
.type
== GLSL_TYPE_FLOAT
)
1720 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1722 emit_asm(ir
, TGSI_OPCODE_MOD
, result_dst
, op
[0], op
[1]);
1726 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[0], op
[1]);
1728 case ir_binop_greater
:
1729 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, op
[1], op
[0]);
1731 case ir_binop_lequal
:
1732 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[1], op
[0]);
1734 case ir_binop_gequal
:
1735 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, op
[0], op
[1]);
1737 case ir_binop_equal
:
1738 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1740 case ir_binop_nequal
:
1741 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1743 case ir_binop_all_equal
:
1744 /* "==" operator producing a scalar boolean. */
1745 if (ir
->operands
[0]->type
->is_vector() ||
1746 ir
->operands
[1]->type
->is_vector()) {
1747 st_src_reg temp
= get_temp(native_integers
?
1748 glsl_type::uvec4_type
:
1749 glsl_type::vec4_type
);
1751 if (native_integers
) {
1752 st_dst_reg temp_dst
= st_dst_reg(temp
);
1753 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1755 if (ir
->operands
[0]->type
->is_boolean() &&
1756 ir
->operands
[1]->as_constant() &&
1757 ir
->operands
[1]->as_constant()->is_one()) {
1758 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1760 emit_asm(ir
, TGSI_OPCODE_SEQ
, st_dst_reg(temp
), op
[0], op
[1]);
1763 /* Emit 1-3 AND operations to combine the SEQ results. */
1764 switch (ir
->operands
[0]->type
->vector_elements
) {
1768 temp_dst
.writemask
= WRITEMASK_Y
;
1769 temp1
.swizzle
= SWIZZLE_YYYY
;
1770 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1771 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1774 temp_dst
.writemask
= WRITEMASK_X
;
1775 temp1
.swizzle
= SWIZZLE_XXXX
;
1776 temp2
.swizzle
= SWIZZLE_YYYY
;
1777 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1778 temp_dst
.writemask
= WRITEMASK_Y
;
1779 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1780 temp2
.swizzle
= SWIZZLE_WWWW
;
1781 emit_asm(ir
, TGSI_OPCODE_AND
, temp_dst
, temp1
, temp2
);
1784 temp1
.swizzle
= SWIZZLE_XXXX
;
1785 temp2
.swizzle
= SWIZZLE_YYYY
;
1786 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, temp1
, temp2
);
1788 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1790 /* After the dot-product, the value will be an integer on the
1791 * range [0,4]. Zero becomes 1.0, and positive values become zero.
1793 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1795 /* Negating the result of the dot-product gives values on the range
1796 * [-4, 0]. Zero becomes 1.0, and negative values become zero.
1797 * This is achieved using SGE.
1799 st_src_reg sge_src
= result_src
;
1800 sge_src
.negate
= ~sge_src
.negate
;
1801 emit_asm(ir
, TGSI_OPCODE_SGE
, result_dst
, sge_src
, st_src_reg_for_float(0.0));
1804 emit_asm(ir
, TGSI_OPCODE_SEQ
, result_dst
, op
[0], op
[1]);
1807 case ir_binop_any_nequal
:
1808 /* "!=" operator producing a scalar boolean. */
1809 if (ir
->operands
[0]->type
->is_vector() ||
1810 ir
->operands
[1]->type
->is_vector()) {
1811 st_src_reg temp
= get_temp(native_integers
?
1812 glsl_type::uvec4_type
:
1813 glsl_type::vec4_type
);
1814 if (ir
->operands
[0]->type
->is_boolean() &&
1815 ir
->operands
[1]->as_constant() &&
1816 ir
->operands
[1]->as_constant()->is_zero()) {
1817 emit_asm(ir
, TGSI_OPCODE_MOV
, st_dst_reg(temp
), op
[0]);
1819 emit_asm(ir
, TGSI_OPCODE_SNE
, st_dst_reg(temp
), op
[0], op
[1]);
1822 if (native_integers
) {
1823 st_dst_reg temp_dst
= st_dst_reg(temp
);
1824 st_src_reg temp1
= st_src_reg(temp
), temp2
= st_src_reg(temp
);
1826 /* Emit 1-3 OR operations to combine the SNE results. */
1827 switch (ir
->operands
[0]->type
->vector_elements
) {
1831 temp_dst
.writemask
= WRITEMASK_Y
;
1832 temp1
.swizzle
= SWIZZLE_YYYY
;
1833 temp2
.swizzle
= SWIZZLE_ZZZZ
;
1834 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1837 temp_dst
.writemask
= WRITEMASK_X
;
1838 temp1
.swizzle
= SWIZZLE_XXXX
;
1839 temp2
.swizzle
= SWIZZLE_YYYY
;
1840 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1841 temp_dst
.writemask
= WRITEMASK_Y
;
1842 temp1
.swizzle
= SWIZZLE_ZZZZ
;
1843 temp2
.swizzle
= SWIZZLE_WWWW
;
1844 emit_asm(ir
, TGSI_OPCODE_OR
, temp_dst
, temp1
, temp2
);
1847 temp1
.swizzle
= SWIZZLE_XXXX
;
1848 temp2
.swizzle
= SWIZZLE_YYYY
;
1849 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, temp1
, temp2
);
1851 /* After the dot-product, the value will be an integer on the
1852 * range [0,4]. Zero stays zero, and positive values become 1.0.
1854 glsl_to_tgsi_instruction
*const dp
=
1855 emit_dp(ir
, result_dst
, temp
, temp
, vector_elements
);
1856 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1857 /* The clamping to [0,1] can be done for free in the fragment
1858 * shader with a saturate.
1860 dp
->saturate
= true;
1862 /* Negating the result of the dot-product gives values on the range
1863 * [-4, 0]. Zero stays zero, and negative values become 1.0. This
1864 * achieved using SLT.
1866 st_src_reg slt_src
= result_src
;
1867 slt_src
.negate
= ~slt_src
.negate
;
1868 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1872 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1876 case ir_binop_logic_xor
:
1877 if (native_integers
)
1878 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
1880 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], op
[1]);
1883 case ir_binop_logic_or
: {
1884 if (native_integers
) {
1885 /* If integers are used as booleans, we can use an actual "or"
1888 assert(native_integers
);
1889 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
1891 /* After the addition, the value will be an integer on the
1892 * range [0,2]. Zero stays zero, and positive values become 1.0.
1894 glsl_to_tgsi_instruction
*add
=
1895 emit_asm(ir
, TGSI_OPCODE_ADD
, result_dst
, op
[0], op
[1]);
1896 if (this->prog
->Target
== GL_FRAGMENT_PROGRAM_ARB
) {
1897 /* The clamping to [0,1] can be done for free in the fragment
1898 * shader with a saturate if floats are being used as boolean values.
1900 add
->saturate
= true;
1902 /* Negating the result of the addition gives values on the range
1903 * [-2, 0]. Zero stays zero, and negative values become 1.0. This
1904 * is achieved using SLT.
1906 st_src_reg slt_src
= result_src
;
1907 slt_src
.negate
= ~slt_src
.negate
;
1908 emit_asm(ir
, TGSI_OPCODE_SLT
, result_dst
, slt_src
, st_src_reg_for_float(0.0));
1914 case ir_binop_logic_and
:
1915 /* If native integers are disabled, the bool args are stored as float 0.0
1916 * or 1.0, so "mul" gives us "and". If they're enabled, just use the
1917 * actual AND opcode.
1919 if (native_integers
)
1920 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
1922 emit_asm(ir
, TGSI_OPCODE_MUL
, result_dst
, op
[0], op
[1]);
1926 assert(ir
->operands
[0]->type
->is_vector());
1927 assert(ir
->operands
[0]->type
== ir
->operands
[1]->type
);
1928 emit_dp(ir
, result_dst
, op
[0], op
[1],
1929 ir
->operands
[0]->type
->vector_elements
);
1934 emit_scalar(ir
, TGSI_OPCODE_SQRT
, result_dst
, op
[0]);
1936 /* This is the only instruction sequence that makes the game "Risen"
1937 * render correctly. ABS is not required for the game, but since GLSL
1938 * declares negative values as "undefined", allowing us to do whatever
1939 * we want, I choose to use ABS to match DX9 and pre-GLSL RSQ
1942 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0].get_abs());
1943 emit_scalar(ir
, TGSI_OPCODE_RCP
, result_dst
, result_src
);
1947 emit_scalar(ir
, TGSI_OPCODE_RSQ
, result_dst
, op
[0]);
1950 if (native_integers
) {
1951 emit_asm(ir
, TGSI_OPCODE_I2F
, result_dst
, op
[0]);
1954 /* fallthrough to next case otherwise */
1956 if (native_integers
) {
1957 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_float(1.0));
1960 /* fallthrough to next case otherwise */
1963 /* Converting between signed and unsigned integers is a no-op. */
1965 result_src
.type
= result_dst
.type
;
1968 if (native_integers
) {
1969 /* Booleans are stored as integers using ~0 for true and 0 for false.
1970 * GLSL requires that int(bool) return 1 for true and 0 for false.
1971 * This conversion is done with AND, but it could be done with NEG.
1973 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], st_src_reg_for_int(1));
1975 /* Booleans and integers are both stored as floats when native
1976 * integers are disabled.
1982 if (native_integers
)
1983 emit_asm(ir
, TGSI_OPCODE_F2I
, result_dst
, op
[0]);
1985 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1988 if (native_integers
)
1989 emit_asm(ir
, TGSI_OPCODE_F2U
, result_dst
, op
[0]);
1991 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
1993 case ir_unop_bitcast_f2i
:
1994 case ir_unop_bitcast_f2u
:
1995 /* Make sure we don't propagate the negate modifier to integer opcodes. */
1996 if (op
[0].negate
|| op
[0].abs
)
1997 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2000 result_src
.type
= ir
->operation
== ir_unop_bitcast_f2i
? GLSL_TYPE_INT
:
2003 case ir_unop_bitcast_i2f
:
2004 case ir_unop_bitcast_u2f
:
2006 result_src
.type
= GLSL_TYPE_FLOAT
;
2009 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2012 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_double(0.0));
2015 if (native_integers
)
2016 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, op
[0], st_src_reg_for_int(0));
2018 emit_asm(ir
, TGSI_OPCODE_SNE
, result_dst
, op
[0], st_src_reg_for_float(0.0));
2021 emit_asm(ir
, TGSI_OPCODE_TRUNC
, result_dst
, op
[0]);
2024 emit_asm(ir
, TGSI_OPCODE_CEIL
, result_dst
, op
[0]);
2027 emit_asm(ir
, TGSI_OPCODE_FLR
, result_dst
, op
[0]);
2029 case ir_unop_round_even
:
2030 emit_asm(ir
, TGSI_OPCODE_ROUND
, result_dst
, op
[0]);
2033 emit_asm(ir
, TGSI_OPCODE_FRC
, result_dst
, op
[0]);
2037 emit_asm(ir
, TGSI_OPCODE_MIN
, result_dst
, op
[0], op
[1]);
2040 emit_asm(ir
, TGSI_OPCODE_MAX
, result_dst
, op
[0], op
[1]);
2043 emit_scalar(ir
, TGSI_OPCODE_POW
, result_dst
, op
[0], op
[1]);
2046 case ir_unop_bit_not
:
2047 if (native_integers
) {
2048 emit_asm(ir
, TGSI_OPCODE_NOT
, result_dst
, op
[0]);
2052 if (native_integers
) {
2053 emit_asm(ir
, TGSI_OPCODE_U2F
, result_dst
, op
[0]);
2056 case ir_binop_lshift
:
2057 if (native_integers
) {
2058 emit_asm(ir
, TGSI_OPCODE_SHL
, result_dst
, op
[0], op
[1]);
2061 case ir_binop_rshift
:
2062 if (native_integers
) {
2063 emit_asm(ir
, TGSI_OPCODE_ISHR
, result_dst
, op
[0], op
[1]);
2066 case ir_binop_bit_and
:
2067 if (native_integers
) {
2068 emit_asm(ir
, TGSI_OPCODE_AND
, result_dst
, op
[0], op
[1]);
2071 case ir_binop_bit_xor
:
2072 if (native_integers
) {
2073 emit_asm(ir
, TGSI_OPCODE_XOR
, result_dst
, op
[0], op
[1]);
2076 case ir_binop_bit_or
:
2077 if (native_integers
) {
2078 emit_asm(ir
, TGSI_OPCODE_OR
, result_dst
, op
[0], op
[1]);
2082 assert(!"GLSL 1.30 features unsupported");
2085 case ir_binop_ubo_load
: {
2086 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
2087 ir_constant
*const_offset_ir
= ir
->operands
[1]->as_constant();
2088 unsigned const_offset
= const_offset_ir
? const_offset_ir
->value
.u
[0] : 0;
2089 unsigned const_block
= const_uniform_block
? const_uniform_block
->value
.u
[0] + 1 : 0;
2090 st_src_reg index_reg
= get_temp(glsl_type::uint_type
);
2093 cbuf
.type
= ir
->type
->base_type
;
2094 cbuf
.file
= PROGRAM_CONSTANT
;
2096 cbuf
.reladdr
= NULL
;
2100 assert(ir
->type
->is_vector() || ir
->type
->is_scalar());
2102 if (const_offset_ir
) {
2103 /* Constant index into constant buffer */
2104 cbuf
.reladdr
= NULL
;
2105 cbuf
.index
= const_offset
/ 16;
2108 ir_expression
*offset_expr
= ir
->operands
[1]->as_expression();
2109 st_src_reg offset
= op
[1];
2111 /* The OpenGL spec is written in such a way that accesses with
2112 * non-constant offset are almost always vec4-aligned. The only
2113 * exception to this are members of structs in arrays of structs:
2114 * each struct in an array of structs is at least vec4-aligned,
2115 * but single-element and [ui]vec2 members of the struct may be at
2116 * an offset that is not a multiple of 16 bytes.
2118 * Here, we extract that offset, relying on previous passes to always
2119 * generate offset expressions of the form (+ expr constant_offset).
2121 * Note that the std430 layout, which allows more cases of alignment
2122 * less than vec4 in arrays, is not supported for uniform blocks, so
2123 * we do not have to deal with it here.
2125 if (offset_expr
&& offset_expr
->operation
== ir_binop_add
) {
2126 const_offset_ir
= offset_expr
->operands
[1]->as_constant();
2127 if (const_offset_ir
) {
2128 const_offset
= const_offset_ir
->value
.u
[0];
2129 cbuf
.index
= const_offset
/ 16;
2130 offset_expr
->operands
[0]->accept(this);
2131 offset
= this->result
;
2135 /* Relative/variable index into constant buffer */
2136 emit_asm(ir
, TGSI_OPCODE_USHR
, st_dst_reg(index_reg
), offset
,
2137 st_src_reg_for_int(4));
2138 cbuf
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2139 memcpy(cbuf
.reladdr
, &index_reg
, sizeof(index_reg
));
2142 if (const_uniform_block
) {
2143 /* Constant constant buffer */
2144 cbuf
.reladdr2
= NULL
;
2145 cbuf
.index2D
= const_block
;
2146 cbuf
.has_index2
= true;
2149 /* Relative/variable constant buffer */
2150 cbuf
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2152 memcpy(cbuf
.reladdr2
, &op
[0], sizeof(st_src_reg
));
2153 cbuf
.has_index2
= true;
2156 cbuf
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2157 if (glsl_base_type_is_64bit(cbuf
.type
))
2158 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 8,
2159 const_offset
% 16 / 8,
2160 const_offset
% 16 / 8,
2161 const_offset
% 16 / 8);
2163 cbuf
.swizzle
+= MAKE_SWIZZLE4(const_offset
% 16 / 4,
2164 const_offset
% 16 / 4,
2165 const_offset
% 16 / 4,
2166 const_offset
% 16 / 4);
2168 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
2169 emit_asm(ir
, TGSI_OPCODE_USNE
, result_dst
, cbuf
, st_src_reg_for_int(0));
2171 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, cbuf
);
2176 /* note: we have to reorder the three args here */
2177 emit_asm(ir
, TGSI_OPCODE_LRP
, result_dst
, op
[2], op
[1], op
[0]);
2180 if (this->ctx
->Const
.NativeIntegers
)
2181 emit_asm(ir
, TGSI_OPCODE_UCMP
, result_dst
, op
[0], op
[1], op
[2]);
2183 op
[0].negate
= ~op
[0].negate
;
2184 emit_asm(ir
, TGSI_OPCODE_CMP
, result_dst
, op
[0], op
[1], op
[2]);
2187 case ir_triop_bitfield_extract
:
2188 emit_asm(ir
, TGSI_OPCODE_IBFE
, result_dst
, op
[0], op
[1], op
[2]);
2190 case ir_quadop_bitfield_insert
:
2191 emit_asm(ir
, TGSI_OPCODE_BFI
, result_dst
, op
[0], op
[1], op
[2], op
[3]);
2193 case ir_unop_bitfield_reverse
:
2194 emit_asm(ir
, TGSI_OPCODE_BREV
, result_dst
, op
[0]);
2196 case ir_unop_bit_count
:
2197 emit_asm(ir
, TGSI_OPCODE_POPC
, result_dst
, op
[0]);
2199 case ir_unop_find_msb
:
2200 emit_asm(ir
, TGSI_OPCODE_IMSB
, result_dst
, op
[0]);
2202 case ir_unop_find_lsb
:
2203 emit_asm(ir
, TGSI_OPCODE_LSB
, result_dst
, op
[0]);
2205 case ir_binop_imul_high
:
2206 emit_asm(ir
, TGSI_OPCODE_IMUL_HI
, result_dst
, op
[0], op
[1]);
2209 /* In theory, MAD is incorrect here. */
2211 emit_asm(ir
, TGSI_OPCODE_FMA
, result_dst
, op
[0], op
[1], op
[2]);
2213 emit_asm(ir
, TGSI_OPCODE_MAD
, result_dst
, op
[0], op
[1], op
[2]);
2215 case ir_unop_interpolate_at_centroid
:
2216 emit_asm(ir
, TGSI_OPCODE_INTERP_CENTROID
, result_dst
, op
[0]);
2218 case ir_binop_interpolate_at_offset
: {
2219 /* The y coordinate needs to be flipped for the default fb */
2220 static const gl_state_index transform_y_state
[STATE_LENGTH
]
2221 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
};
2223 unsigned transform_y_index
=
2224 _mesa_add_state_reference(this->prog
->Parameters
,
2227 st_src_reg transform_y
= st_src_reg(PROGRAM_STATE_VAR
,
2229 glsl_type::vec4_type
);
2230 transform_y
.swizzle
= SWIZZLE_XXXX
;
2232 st_src_reg temp
= get_temp(glsl_type::vec2_type
);
2233 st_dst_reg temp_dst
= st_dst_reg(temp
);
2235 emit_asm(ir
, TGSI_OPCODE_MOV
, temp_dst
, op
[1]);
2236 temp_dst
.writemask
= WRITEMASK_Y
;
2237 emit_asm(ir
, TGSI_OPCODE_MUL
, temp_dst
, transform_y
, op
[1]);
2238 emit_asm(ir
, TGSI_OPCODE_INTERP_OFFSET
, result_dst
, op
[0], temp
);
2241 case ir_binop_interpolate_at_sample
:
2242 emit_asm(ir
, TGSI_OPCODE_INTERP_SAMPLE
, result_dst
, op
[0], op
[1]);
2246 emit_asm(ir
, TGSI_OPCODE_D2F
, result_dst
, op
[0]);
2249 emit_asm(ir
, TGSI_OPCODE_F2D
, result_dst
, op
[0]);
2252 emit_asm(ir
, TGSI_OPCODE_D2I
, result_dst
, op
[0]);
2255 emit_asm(ir
, TGSI_OPCODE_I2D
, result_dst
, op
[0]);
2258 emit_asm(ir
, TGSI_OPCODE_D2U
, result_dst
, op
[0]);
2261 emit_asm(ir
, TGSI_OPCODE_U2D
, result_dst
, op
[0]);
2263 case ir_unop_unpack_double_2x32
:
2264 case ir_unop_pack_double_2x32
:
2265 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, op
[0]);
2268 case ir_binop_ldexp
:
2269 if (ir
->operands
[0]->type
->base_type
== GLSL_TYPE_DOUBLE
) {
2270 emit_asm(ir
, TGSI_OPCODE_DLDEXP
, result_dst
, op
[0], op
[1]);
2272 assert(!"Invalid ldexp for non-double opcode in glsl_to_tgsi_visitor::visit()");
2276 case ir_unop_pack_half_2x16
:
2277 emit_asm(ir
, TGSI_OPCODE_PK2H
, result_dst
, op
[0]);
2279 case ir_unop_unpack_half_2x16
:
2280 emit_asm(ir
, TGSI_OPCODE_UP2H
, result_dst
, op
[0]);
2283 case ir_unop_get_buffer_size
: {
2284 ir_constant
*const_offset
= ir
->operands
[0]->as_constant();
2287 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
2288 (const_offset
? const_offset
->value
.u
[0] : 0),
2290 if (!const_offset
) {
2291 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2292 *buffer
.reladdr
= op
[0];
2293 emit_arl(ir
, sampler_reladdr
, op
[0]);
2295 emit_asm(ir
, TGSI_OPCODE_RESQ
, result_dst
)->resource
= buffer
;
2299 case ir_unop_vote_any
:
2300 emit_asm(ir
, TGSI_OPCODE_VOTE_ANY
, result_dst
, op
[0]);
2302 case ir_unop_vote_all
:
2303 emit_asm(ir
, TGSI_OPCODE_VOTE_ALL
, result_dst
, op
[0]);
2305 case ir_unop_vote_eq
:
2306 emit_asm(ir
, TGSI_OPCODE_VOTE_EQ
, result_dst
, op
[0]);
2309 case ir_unop_pack_snorm_2x16
:
2310 case ir_unop_pack_unorm_2x16
:
2311 case ir_unop_pack_snorm_4x8
:
2312 case ir_unop_pack_unorm_4x8
:
2314 case ir_unop_unpack_snorm_2x16
:
2315 case ir_unop_unpack_unorm_2x16
:
2316 case ir_unop_unpack_snorm_4x8
:
2317 case ir_unop_unpack_unorm_4x8
:
2319 case ir_quadop_vector
:
2320 case ir_binop_vector_extract
:
2321 case ir_triop_vector_insert
:
2322 case ir_binop_carry
:
2323 case ir_binop_borrow
:
2324 case ir_unop_ssbo_unsized_array_length
:
2325 /* This operation is not supported, or should have already been handled.
2327 assert(!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()");
2331 this->result
= result_src
;
2336 glsl_to_tgsi_visitor::visit(ir_swizzle
*ir
)
2342 /* Note that this is only swizzles in expressions, not those on the left
2343 * hand side of an assignment, which do write masking. See ir_assignment
2347 ir
->val
->accept(this);
2349 assert(src
.file
!= PROGRAM_UNDEFINED
);
2350 assert(ir
->type
->vector_elements
> 0);
2352 for (i
= 0; i
< 4; i
++) {
2353 if (i
< ir
->type
->vector_elements
) {
2356 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.x
);
2359 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.y
);
2362 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.z
);
2365 swizzle
[i
] = GET_SWZ(src
.swizzle
, ir
->mask
.w
);
2369 /* If the type is smaller than a vec4, replicate the last
2372 swizzle
[i
] = swizzle
[ir
->type
->vector_elements
- 1];
2376 src
.swizzle
= MAKE_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2381 /* Test if the variable is an array. Note that geometry and
2382 * tessellation shader inputs are outputs are always arrays (except
2383 * for patch inputs), so only the array element type is considered.
2386 is_inout_array(unsigned stage
, ir_variable
*var
, bool *remove_array
)
2388 const glsl_type
*type
= var
->type
;
2390 *remove_array
= false;
2392 if ((stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
) ||
2393 (stage
== MESA_SHADER_FRAGMENT
&& var
->data
.mode
== ir_var_shader_out
))
2396 if (((stage
== MESA_SHADER_GEOMETRY
&& var
->data
.mode
== ir_var_shader_in
) ||
2397 (stage
== MESA_SHADER_TESS_EVAL
&& var
->data
.mode
== ir_var_shader_in
) ||
2398 stage
== MESA_SHADER_TESS_CTRL
) &&
2400 if (!var
->type
->is_array())
2401 return false; /* a system value probably */
2403 type
= var
->type
->fields
.array
;
2404 *remove_array
= true;
2407 return type
->is_array() || type
->is_matrix();
2411 st_translate_interp_loc(ir_variable
*var
)
2413 if (var
->data
.centroid
)
2414 return TGSI_INTERPOLATE_LOC_CENTROID
;
2415 else if (var
->data
.sample
)
2416 return TGSI_INTERPOLATE_LOC_SAMPLE
;
2418 return TGSI_INTERPOLATE_LOC_CENTER
;
2422 glsl_to_tgsi_visitor::visit(ir_dereference_variable
*ir
)
2424 variable_storage
*entry
= find_variable_storage(ir
->var
);
2425 ir_variable
*var
= ir
->var
;
2429 switch (var
->data
.mode
) {
2430 case ir_var_uniform
:
2431 entry
= new(mem_ctx
) variable_storage(var
, PROGRAM_UNIFORM
,
2432 var
->data
.param_index
);
2433 this->variables
.push_tail(entry
);
2435 case ir_var_shader_in
: {
2436 /* The linker assigns locations for varyings and attributes,
2437 * including deprecated builtins (like gl_Color), user-assign
2438 * generic attributes (glBindVertexLocation), and
2439 * user-defined varyings.
2441 assert(var
->data
.location
!= -1);
2443 const glsl_type
*type_without_array
= var
->type
->without_array();
2444 struct inout_decl
*decl
= &inputs
[num_inputs
];
2445 unsigned component
= var
->data
.location_frac
;
2446 unsigned num_components
;
2449 if (type_without_array
->is_64bit())
2450 component
= component
/ 2;
2451 if (type_without_array
->vector_elements
)
2452 num_components
= type_without_array
->vector_elements
;
2456 decl
->mesa_index
= var
->data
.location
;
2457 decl
->interp
= (glsl_interp_mode
) var
->data
.interpolation
;
2458 decl
->interp_loc
= st_translate_interp_loc(var
);
2459 decl
->base_type
= type_without_array
->base_type
;
2460 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2462 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2463 decl
->array_id
= num_input_arrays
+ 1;
2470 decl
->size
= type_size(var
->type
->fields
.array
);
2472 decl
->size
= type_size(var
->type
);
2474 entry
= new(mem_ctx
) variable_storage(var
,
2478 entry
->component
= component
;
2480 this->variables
.push_tail(entry
);
2483 case ir_var_shader_out
: {
2484 assert(var
->data
.location
!= -1);
2486 const glsl_type
*type_without_array
= var
->type
->without_array();
2487 struct inout_decl
*decl
= &outputs
[num_outputs
];
2488 unsigned component
= var
->data
.location_frac
;
2489 unsigned num_components
;
2492 if (type_without_array
->is_64bit())
2493 component
= component
/ 2;
2494 if (type_without_array
->vector_elements
)
2495 num_components
= type_without_array
->vector_elements
;
2499 decl
->mesa_index
= var
->data
.location
+ FRAG_RESULT_MAX
* var
->data
.index
;
2500 decl
->base_type
= type_without_array
->base_type
;
2501 decl
->usage_mask
= u_bit_consecutive(component
, num_components
);
2502 if (var
->data
.stream
& (1u << 31)) {
2503 decl
->gs_out_streams
= var
->data
.stream
& ~(1u << 31);
2505 assert(var
->data
.stream
< 4);
2506 decl
->gs_out_streams
= 0;
2507 for (unsigned i
= 0; i
< num_components
; ++i
)
2508 decl
->gs_out_streams
|= var
->data
.stream
<< (2 * (component
+ i
));
2511 if (is_inout_array(shader
->Stage
, var
, &remove_array
)) {
2512 decl
->array_id
= num_output_arrays
+ 1;
2513 num_output_arrays
++;
2519 decl
->size
= type_size(var
->type
->fields
.array
);
2521 decl
->size
= type_size(var
->type
);
2523 entry
= new(mem_ctx
) variable_storage(var
,
2527 entry
->component
= component
;
2529 this->variables
.push_tail(entry
);
2532 case ir_var_system_value
:
2533 entry
= new(mem_ctx
) variable_storage(var
,
2534 PROGRAM_SYSTEM_VALUE
,
2535 var
->data
.location
);
2538 case ir_var_temporary
:
2539 st_src_reg src
= get_temp(var
->type
);
2541 entry
= new(mem_ctx
) variable_storage(var
, src
.file
, src
.index
,
2543 this->variables
.push_tail(entry
);
2549 printf("Failed to make storage for %s\n", var
->name
);
2554 this->result
= st_src_reg(entry
->file
, entry
->index
, var
->type
,
2555 entry
->component
, entry
->array_id
);
2556 if (this->shader
->Stage
== MESA_SHADER_VERTEX
&& var
->data
.mode
== ir_var_shader_in
&& var
->type
->is_double())
2557 this->result
.is_double_vertex_input
= true;
2558 if (!native_integers
)
2559 this->result
.type
= GLSL_TYPE_FLOAT
;
2563 shrink_array_declarations(struct inout_decl
*decls
, unsigned count
,
2564 GLbitfield64
* usage_mask
,
2565 GLbitfield64 double_usage_mask
,
2566 GLbitfield
* patch_usage_mask
)
2571 /* Fix array declarations by removing unused array elements at both ends
2572 * of the arrays. For example, mat4[3] where only mat[1] is used.
2574 for (i
= 0; i
< count
; i
++) {
2575 struct inout_decl
*decl
= &decls
[i
];
2576 if (!decl
->array_id
)
2579 /* Shrink the beginning. */
2580 for (j
= 0; j
< (int)decl
->size
; j
++) {
2581 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2582 if (*patch_usage_mask
&
2583 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2587 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2589 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2598 /* Shrink the end. */
2599 for (j
= decl
->size
-1; j
>= 0; j
--) {
2600 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
) {
2601 if (*patch_usage_mask
&
2602 BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
))
2606 if (*usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
))
2608 if (double_usage_mask
& BITFIELD64_BIT(decl
->mesa_index
+j
-1))
2615 /* When not all entries of an array are accessed, we mark them as used
2616 * here anyway, to ensure that the input/output mapping logic doesn't get
2619 * TODO This happens when an array isn't used via indirect access, which
2620 * some game ports do (at least eON-based). There is an optimization
2621 * opportunity here by replacing the array declaration with non-array
2622 * declarations of those slots that are actually used.
2624 for (j
= 1; j
< (int)decl
->size
; ++j
) {
2625 if (decl
->mesa_index
>= VARYING_SLOT_PATCH0
)
2626 *patch_usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
- VARYING_SLOT_PATCH0
+ j
);
2628 *usage_mask
|= BITFIELD64_BIT(decl
->mesa_index
+ j
);
2634 glsl_to_tgsi_visitor::visit(ir_dereference_array
*ir
)
2638 int element_size
= type_size(ir
->type
);
2641 index
= ir
->array_index
->constant_expression_value();
2643 ir
->array
->accept(this);
2646 if (ir
->array
->ir_type
!= ir_type_dereference_array
) {
2647 switch (this->prog
->Target
) {
2648 case GL_TESS_CONTROL_PROGRAM_NV
:
2649 is_2D
= (src
.file
== PROGRAM_INPUT
|| src
.file
== PROGRAM_OUTPUT
) &&
2650 !ir
->variable_referenced()->data
.patch
;
2652 case GL_TESS_EVALUATION_PROGRAM_NV
:
2653 is_2D
= src
.file
== PROGRAM_INPUT
&&
2654 !ir
->variable_referenced()->data
.patch
;
2656 case GL_GEOMETRY_PROGRAM_NV
:
2657 is_2D
= src
.file
== PROGRAM_INPUT
;
2667 if (this->prog
->Target
== GL_VERTEX_PROGRAM_ARB
&&
2668 src
.file
== PROGRAM_INPUT
)
2669 element_size
= attrib_type_size(ir
->type
, true);
2671 src
.index2D
= index
->value
.i
[0];
2672 src
.has_index2
= true;
2674 src
.index
+= index
->value
.i
[0] * element_size
;
2676 /* Variable index array dereference. It eats the "vec4" of the
2677 * base of the array and an index that offsets the TGSI register
2680 ir
->array_index
->accept(this);
2682 st_src_reg index_reg
;
2684 if (element_size
== 1) {
2685 index_reg
= this->result
;
2687 index_reg
= get_temp(native_integers
?
2688 glsl_type::int_type
: glsl_type::float_type
);
2690 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(index_reg
),
2691 this->result
, st_src_reg_for_type(index_reg
.type
, element_size
));
2694 /* If there was already a relative address register involved, add the
2695 * new and the old together to get the new offset.
2697 if (!is_2D
&& src
.reladdr
!= NULL
) {
2698 st_src_reg accum_reg
= get_temp(native_integers
?
2699 glsl_type::int_type
: glsl_type::float_type
);
2701 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(accum_reg
),
2702 index_reg
, *src
.reladdr
);
2704 index_reg
= accum_reg
;
2708 src
.reladdr2
= ralloc(mem_ctx
, st_src_reg
);
2709 memcpy(src
.reladdr2
, &index_reg
, sizeof(index_reg
));
2711 src
.has_index2
= true;
2713 src
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
2714 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
2718 /* Change the register type to the element type of the array. */
2719 src
.type
= ir
->type
->base_type
;
2725 glsl_to_tgsi_visitor::visit(ir_dereference_record
*ir
)
2728 const glsl_type
*struct_type
= ir
->record
->type
;
2731 ir
->record
->accept(this);
2733 for (i
= 0; i
< struct_type
->length
; i
++) {
2734 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
2736 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
2739 /* If the type is smaller than a vec4, replicate the last channel out. */
2740 if (ir
->type
->is_scalar() || ir
->type
->is_vector())
2741 this->result
.swizzle
= swizzle_for_size(ir
->type
->vector_elements
);
2743 this->result
.swizzle
= SWIZZLE_NOOP
;
2745 this->result
.index
+= offset
;
2746 this->result
.type
= ir
->type
->base_type
;
2750 * We want to be careful in assignment setup to hit the actual storage
2751 * instead of potentially using a temporary like we might with the
2752 * ir_dereference handler.
2755 get_assignment_lhs(ir_dereference
*ir
, glsl_to_tgsi_visitor
*v
, int *component
)
2757 /* The LHS must be a dereference. If the LHS is a variable indexed array
2758 * access of a vector, it must be separated into a series conditional moves
2759 * before reaching this point (see ir_vec_index_to_cond_assign).
2761 assert(ir
->as_dereference());
2762 ir_dereference_array
*deref_array
= ir
->as_dereference_array();
2764 assert(!deref_array
->array
->type
->is_vector());
2767 /* Use the rvalue deref handler for the most part. We write swizzles using
2768 * the writemask, but we do extract the base component for enhanced layouts
2769 * from the source swizzle.
2772 *component
= GET_SWZ(v
->result
.swizzle
, 0);
2773 return st_dst_reg(v
->result
);
2777 * Process the condition of a conditional assignment
2779 * Examines the condition of a conditional assignment to generate the optimal
2780 * first operand of a \c CMP instruction. If the condition is a relational
2781 * operator with 0 (e.g., \c ir_binop_less), the value being compared will be
2782 * used as the source for the \c CMP instruction. Otherwise the comparison
2783 * is processed to a boolean result, and the boolean result is used as the
2784 * operand to the CMP instruction.
2787 glsl_to_tgsi_visitor::process_move_condition(ir_rvalue
*ir
)
2789 ir_rvalue
*src_ir
= ir
;
2791 bool switch_order
= false;
2793 ir_expression
*const expr
= ir
->as_expression();
2795 if (native_integers
) {
2796 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2797 enum glsl_base_type type
= expr
->operands
[0]->type
->base_type
;
2798 if (type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
||
2799 type
== GLSL_TYPE_BOOL
) {
2800 if (expr
->operation
== ir_binop_equal
) {
2801 if (expr
->operands
[0]->is_zero()) {
2802 src_ir
= expr
->operands
[1];
2803 switch_order
= true;
2805 else if (expr
->operands
[1]->is_zero()) {
2806 src_ir
= expr
->operands
[0];
2807 switch_order
= true;
2810 else if (expr
->operation
== ir_binop_nequal
) {
2811 if (expr
->operands
[0]->is_zero()) {
2812 src_ir
= expr
->operands
[1];
2814 else if (expr
->operands
[1]->is_zero()) {
2815 src_ir
= expr
->operands
[0];
2821 src_ir
->accept(this);
2822 return switch_order
;
2825 if ((expr
!= NULL
) && (expr
->get_num_operands() == 2)) {
2826 bool zero_on_left
= false;
2828 if (expr
->operands
[0]->is_zero()) {
2829 src_ir
= expr
->operands
[1];
2830 zero_on_left
= true;
2831 } else if (expr
->operands
[1]->is_zero()) {
2832 src_ir
= expr
->operands
[0];
2833 zero_on_left
= false;
2837 * (a < 0) T F F ( a < 0) T F F
2838 * (0 < a) F F T (-a < 0) F F T
2839 * (a <= 0) T T F (-a < 0) F F T (swap order of other operands)
2840 * (0 <= a) F T T ( a < 0) T F F (swap order of other operands)
2841 * (a > 0) F F T (-a < 0) F F T
2842 * (0 > a) T F F ( a < 0) T F F
2843 * (a >= 0) F T T ( a < 0) T F F (swap order of other operands)
2844 * (0 >= a) T T F (-a < 0) F F T (swap order of other operands)
2846 * Note that exchanging the order of 0 and 'a' in the comparison simply
2847 * means that the value of 'a' should be negated.
2850 switch (expr
->operation
) {
2852 switch_order
= false;
2853 negate
= zero_on_left
;
2856 case ir_binop_greater
:
2857 switch_order
= false;
2858 negate
= !zero_on_left
;
2861 case ir_binop_lequal
:
2862 switch_order
= true;
2863 negate
= !zero_on_left
;
2866 case ir_binop_gequal
:
2867 switch_order
= true;
2868 negate
= zero_on_left
;
2872 /* This isn't the right kind of comparison afterall, so make sure
2873 * the whole condition is visited.
2881 src_ir
->accept(this);
2883 /* We use the TGSI_OPCODE_CMP (a < 0 ? b : c) for conditional moves, and the
2884 * condition we produced is 0.0 or 1.0. By flipping the sign, we can
2885 * choose which value TGSI_OPCODE_CMP produces without an extra instruction
2886 * computing the condition.
2889 this->result
.negate
= ~this->result
.negate
;
2891 return switch_order
;
2895 glsl_to_tgsi_visitor::emit_block_mov(ir_assignment
*ir
, const struct glsl_type
*type
,
2896 st_dst_reg
*l
, st_src_reg
*r
,
2897 st_src_reg
*cond
, bool cond_swap
)
2899 if (type
->base_type
== GLSL_TYPE_STRUCT
) {
2900 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2901 emit_block_mov(ir
, type
->fields
.structure
[i
].type
, l
, r
,
2907 if (type
->is_array()) {
2908 for (unsigned int i
= 0; i
< type
->length
; i
++) {
2909 emit_block_mov(ir
, type
->fields
.array
, l
, r
, cond
, cond_swap
);
2914 if (type
->is_matrix()) {
2915 const struct glsl_type
*vec_type
;
2917 vec_type
= glsl_type::get_instance(type
->is_double() ? GLSL_TYPE_DOUBLE
: GLSL_TYPE_FLOAT
,
2918 type
->vector_elements
, 1);
2920 for (int i
= 0; i
< type
->matrix_columns
; i
++) {
2921 emit_block_mov(ir
, vec_type
, l
, r
, cond
, cond_swap
);
2926 assert(type
->is_scalar() || type
->is_vector());
2928 l
->type
= type
->base_type
;
2929 r
->type
= type
->base_type
;
2931 st_src_reg l_src
= st_src_reg(*l
);
2932 l_src
.swizzle
= swizzle_for_size(type
->vector_elements
);
2934 if (native_integers
) {
2935 emit_asm(ir
, TGSI_OPCODE_UCMP
, *l
, *cond
,
2936 cond_swap
? l_src
: *r
,
2937 cond_swap
? *r
: l_src
);
2939 emit_asm(ir
, TGSI_OPCODE_CMP
, *l
, *cond
,
2940 cond_swap
? l_src
: *r
,
2941 cond_swap
? *r
: l_src
);
2944 emit_asm(ir
, TGSI_OPCODE_MOV
, *l
, *r
);
2948 if (type
->is_dual_slot()) {
2950 if (r
->is_double_vertex_input
== false)
2956 glsl_to_tgsi_visitor::visit(ir_assignment
*ir
)
2962 ir
->rhs
->accept(this);
2965 l
= get_assignment_lhs(ir
->lhs
, this, &dst_component
);
2969 int first_enabled_chan
= 0;
2971 ir_variable
*variable
= ir
->lhs
->variable_referenced();
2973 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
2974 variable
->data
.mode
== ir_var_shader_out
&&
2975 (variable
->data
.location
== FRAG_RESULT_DEPTH
||
2976 variable
->data
.location
== FRAG_RESULT_STENCIL
)) {
2977 assert(ir
->lhs
->type
->is_scalar());
2978 assert(ir
->write_mask
== WRITEMASK_X
);
2980 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
2981 l
.writemask
= WRITEMASK_Z
;
2983 assert(variable
->data
.location
== FRAG_RESULT_STENCIL
);
2984 l
.writemask
= WRITEMASK_Y
;
2986 } else if (ir
->write_mask
== 0) {
2987 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
2989 unsigned num_elements
= ir
->lhs
->type
->without_array()->vector_elements
;
2992 l
.writemask
= u_bit_consecutive(0, num_elements
);
2994 /* The type is a struct or an array of (array of) structs. */
2995 l
.writemask
= WRITEMASK_XYZW
;
2998 l
.writemask
= ir
->write_mask
;
3001 for (int i
= 0; i
< 4; i
++) {
3002 if (l
.writemask
& (1 << i
)) {
3003 first_enabled_chan
= GET_SWZ(r
.swizzle
, i
);
3008 l
.writemask
= l
.writemask
<< dst_component
;
3010 /* Swizzle a small RHS vector into the channels being written.
3012 * glsl ir treats write_mask as dictating how many channels are
3013 * present on the RHS while TGSI treats write_mask as just
3014 * showing which channels of the vec4 RHS get written.
3016 for (int i
= 0; i
< 4; i
++) {
3017 if (l
.writemask
& (1 << i
))
3018 swizzles
[i
] = GET_SWZ(r
.swizzle
, rhs_chan
++);
3020 swizzles
[i
] = first_enabled_chan
;
3022 r
.swizzle
= MAKE_SWIZZLE4(swizzles
[0], swizzles
[1],
3023 swizzles
[2], swizzles
[3]);
3026 assert(l
.file
!= PROGRAM_UNDEFINED
);
3027 assert(r
.file
!= PROGRAM_UNDEFINED
);
3029 if (ir
->condition
) {
3030 const bool switch_order
= this->process_move_condition(ir
->condition
);
3031 st_src_reg condition
= this->result
;
3033 emit_block_mov(ir
, ir
->lhs
->type
, &l
, &r
, &condition
, switch_order
);
3034 } else if (ir
->rhs
->as_expression() &&
3035 this->instructions
.get_tail() &&
3036 ir
->rhs
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->ir
&&
3037 !((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->is_64bit_expanded
&&
3038 type_size(ir
->lhs
->type
) == 1 &&
3039 l
.writemask
== ((glsl_to_tgsi_instruction
*)this->instructions
.get_tail())->dst
[0].writemask
) {
3040 /* To avoid emitting an extra MOV when assigning an expression to a
3041 * variable, emit the last instruction of the expression again, but
3042 * replace the destination register with the target of the assignment.
3043 * Dead code elimination will remove the original instruction.
3045 glsl_to_tgsi_instruction
*inst
, *new_inst
;
3046 inst
= (glsl_to_tgsi_instruction
*)this->instructions
.get_tail();
3047 new_inst
= emit_asm(ir
, inst
->op
, l
, inst
->src
[0], inst
->src
[1], inst
->src
[2], inst
->src
[3]);
3048 new_inst
->saturate
= inst
->saturate
;
3049 inst
->dead_mask
= inst
->dst
[0].writemask
;
3051 emit_block_mov(ir
, ir
->rhs
->type
, &l
, &r
, NULL
, false);
3057 glsl_to_tgsi_visitor::visit(ir_constant
*ir
)
3060 GLdouble stack_vals
[4] = { 0 };
3061 gl_constant_value
*values
= (gl_constant_value
*) stack_vals
;
3062 GLenum gl_type
= GL_NONE
;
3064 static int in_array
= 0;
3065 gl_register_file file
= in_array
? PROGRAM_CONSTANT
: PROGRAM_IMMEDIATE
;
3067 /* Unfortunately, 4 floats is all we can get into
3068 * _mesa_add_typed_unnamed_constant. So, make a temp to store an
3069 * aggregate constant and move each constant value into it. If we
3070 * get lucky, copy propagation will eliminate the extra moves.
3072 if (ir
->type
->base_type
== GLSL_TYPE_STRUCT
) {
3073 st_src_reg temp_base
= get_temp(ir
->type
);
3074 st_dst_reg temp
= st_dst_reg(temp_base
);
3076 foreach_in_list(ir_constant
, field_value
, &ir
->components
) {
3077 int size
= type_size(field_value
->type
);
3081 field_value
->accept(this);
3084 for (i
= 0; i
< (unsigned int)size
; i
++) {
3085 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3091 this->result
= temp_base
;
3095 if (ir
->type
->is_array()) {
3096 st_src_reg temp_base
= get_temp(ir
->type
);
3097 st_dst_reg temp
= st_dst_reg(temp_base
);
3098 int size
= type_size(ir
->type
->fields
.array
);
3103 for (i
= 0; i
< ir
->type
->length
; i
++) {
3104 ir
->array_elements
[i
]->accept(this);
3106 for (int j
= 0; j
< size
; j
++) {
3107 emit_asm(ir
, TGSI_OPCODE_MOV
, temp
, src
);
3113 this->result
= temp_base
;
3118 if (ir
->type
->is_matrix()) {
3119 st_src_reg mat
= get_temp(ir
->type
);
3120 st_dst_reg mat_column
= st_dst_reg(mat
);
3122 for (i
= 0; i
< ir
->type
->matrix_columns
; i
++) {
3123 switch (ir
->type
->base_type
) {
3124 case GLSL_TYPE_FLOAT
:
3125 values
= (gl_constant_value
*) &ir
->value
.f
[i
* ir
->type
->vector_elements
];
3127 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3128 src
.index
= add_constant(file
,
3130 ir
->type
->vector_elements
,
3133 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3135 case GLSL_TYPE_DOUBLE
:
3136 values
= (gl_constant_value
*) &ir
->value
.d
[i
* ir
->type
->vector_elements
];
3137 src
= st_src_reg(file
, -1, ir
->type
->base_type
);
3138 src
.index
= add_constant(file
,
3140 ir
->type
->vector_elements
,
3143 if (ir
->type
->vector_elements
>= 2) {
3144 mat_column
.writemask
= WRITEMASK_XY
;
3145 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3146 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3148 mat_column
.writemask
= WRITEMASK_X
;
3149 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
);
3150 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3153 if (ir
->type
->vector_elements
> 2) {
3154 if (ir
->type
->vector_elements
== 4) {
3155 mat_column
.writemask
= WRITEMASK_ZW
;
3156 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_X
, SWIZZLE_Y
);
3157 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3159 mat_column
.writemask
= WRITEMASK_Z
;
3160 src
.swizzle
= MAKE_SWIZZLE4(SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
);
3161 emit_asm(ir
, TGSI_OPCODE_MOV
, mat_column
, src
);
3162 mat_column
.writemask
= WRITEMASK_XYZW
;
3163 src
.swizzle
= SWIZZLE_XYZW
;
3169 unreachable("Illegal matrix constant type.\n");
3178 switch (ir
->type
->base_type
) {
3179 case GLSL_TYPE_FLOAT
:
3181 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3182 values
[i
].f
= ir
->value
.f
[i
];
3185 case GLSL_TYPE_DOUBLE
:
3186 gl_type
= GL_DOUBLE
;
3187 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3188 memcpy(&values
[i
* 2], &ir
->value
.d
[i
], sizeof(double));
3191 case GLSL_TYPE_UINT
:
3192 gl_type
= native_integers
? GL_UNSIGNED_INT
: GL_FLOAT
;
3193 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3194 if (native_integers
)
3195 values
[i
].u
= ir
->value
.u
[i
];
3197 values
[i
].f
= ir
->value
.u
[i
];
3201 gl_type
= native_integers
? GL_INT
: GL_FLOAT
;
3202 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3203 if (native_integers
)
3204 values
[i
].i
= ir
->value
.i
[i
];
3206 values
[i
].f
= ir
->value
.i
[i
];
3209 case GLSL_TYPE_BOOL
:
3210 gl_type
= native_integers
? GL_BOOL
: GL_FLOAT
;
3211 for (i
= 0; i
< ir
->type
->vector_elements
; i
++) {
3212 values
[i
].u
= ir
->value
.b
[i
] ? ctx
->Const
.UniformBooleanTrue
: 0;
3216 assert(!"Non-float/uint/int/bool constant");
3219 this->result
= st_src_reg(file
, -1, ir
->type
);
3220 this->result
.index
= add_constant(file
,
3222 ir
->type
->vector_elements
,
3224 &this->result
.swizzle
);
3228 glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
3230 exec_node
*param
= ir
->actual_parameters
.get_head();
3231 ir_dereference
*deref
= static_cast<ir_dereference
*>(param
);
3232 ir_variable
*location
= deref
->variable_referenced();
3235 PROGRAM_BUFFER
, location
->data
.binding
, GLSL_TYPE_ATOMIC_UINT
);
3237 /* Calculate the surface offset */
3239 unsigned array_size
= 0, base
= 0;
3242 get_deref_offsets(deref
, &array_size
, &base
, &index
, &offset
, false);
3244 if (offset
.file
!= PROGRAM_UNDEFINED
) {
3245 emit_asm(ir
, TGSI_OPCODE_MUL
, st_dst_reg(offset
),
3246 offset
, st_src_reg_for_int(ATOMIC_COUNTER_SIZE
));
3247 emit_asm(ir
, TGSI_OPCODE_ADD
, st_dst_reg(offset
),
3248 offset
, st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
));
3250 offset
= st_src_reg_for_int(location
->data
.offset
+ index
* ATOMIC_COUNTER_SIZE
);
3253 ir
->return_deref
->accept(this);
3254 st_dst_reg
dst(this->result
);
3255 dst
.writemask
= WRITEMASK_X
;
3257 glsl_to_tgsi_instruction
*inst
;
3259 if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_read
) {
3260 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, offset
);
3261 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_increment
) {
3262 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3263 st_src_reg_for_int(1));
3264 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_atomic_counter_predecrement
) {
3265 inst
= emit_asm(ir
, TGSI_OPCODE_ATOMUADD
, dst
, offset
,
3266 st_src_reg_for_int(-1));
3267 emit_asm(ir
, TGSI_OPCODE_ADD
, dst
, this->result
, st_src_reg_for_int(-1));
3269 param
= param
->get_next();
3270 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3273 st_src_reg data
= this->result
, data2
= undef_src
;
3275 switch (ir
->callee
->intrinsic_id
) {
3276 case ir_intrinsic_atomic_counter_add
:
3277 opcode
= TGSI_OPCODE_ATOMUADD
;
3279 case ir_intrinsic_atomic_counter_min
:
3280 opcode
= TGSI_OPCODE_ATOMIMIN
;
3282 case ir_intrinsic_atomic_counter_max
:
3283 opcode
= TGSI_OPCODE_ATOMIMAX
;
3285 case ir_intrinsic_atomic_counter_and
:
3286 opcode
= TGSI_OPCODE_ATOMAND
;
3288 case ir_intrinsic_atomic_counter_or
:
3289 opcode
= TGSI_OPCODE_ATOMOR
;
3291 case ir_intrinsic_atomic_counter_xor
:
3292 opcode
= TGSI_OPCODE_ATOMXOR
;
3294 case ir_intrinsic_atomic_counter_exchange
:
3295 opcode
= TGSI_OPCODE_ATOMXCHG
;
3297 case ir_intrinsic_atomic_counter_comp_swap
: {
3298 opcode
= TGSI_OPCODE_ATOMCAS
;
3299 param
= param
->get_next();
3300 val
= ((ir_instruction
*)param
)->as_rvalue();
3302 data2
= this->result
;
3306 assert(!"Unexpected intrinsic");
3310 inst
= emit_asm(ir
, opcode
, dst
, offset
, data
, data2
);
3313 inst
->resource
= buffer
;
3317 glsl_to_tgsi_visitor::visit_ssbo_intrinsic(ir_call
*ir
)
3319 exec_node
*param
= ir
->actual_parameters
.get_head();
3321 ir_rvalue
*block
= ((ir_instruction
*)param
)->as_rvalue();
3323 param
= param
->get_next();
3324 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3326 ir_constant
*const_block
= block
->as_constant();
3330 ctx
->Const
.Program
[shader
->Stage
].MaxAtomicBuffers
+
3331 (const_block
? const_block
->value
.u
[0] : 0),
3335 block
->accept(this);
3336 buffer
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3337 *buffer
.reladdr
= this->result
;
3338 emit_arl(ir
, sampler_reladdr
, this->result
);
3341 /* Calculate the surface offset */
3342 offset
->accept(this);
3343 st_src_reg off
= this->result
;
3345 st_dst_reg dst
= undef_dst
;
3346 if (ir
->return_deref
) {
3347 ir
->return_deref
->accept(this);
3348 dst
= st_dst_reg(this->result
);
3349 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3352 glsl_to_tgsi_instruction
*inst
;
3354 if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_load
) {
3355 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3356 if (dst
.type
== GLSL_TYPE_BOOL
)
3357 emit_asm(ir
, TGSI_OPCODE_USNE
, dst
, st_src_reg(dst
), st_src_reg_for_int(0));
3358 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_ssbo_store
) {
3359 param
= param
->get_next();
3360 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3363 param
= param
->get_next();
3364 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3366 dst
.writemask
= write_mask
->value
.u
[0];
3368 dst
.type
= this->result
.type
;
3369 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3371 param
= param
->get_next();
3372 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3375 st_src_reg data
= this->result
, data2
= undef_src
;
3377 switch (ir
->callee
->intrinsic_id
) {
3378 case ir_intrinsic_ssbo_atomic_add
:
3379 opcode
= TGSI_OPCODE_ATOMUADD
;
3381 case ir_intrinsic_ssbo_atomic_min
:
3382 opcode
= TGSI_OPCODE_ATOMIMIN
;
3384 case ir_intrinsic_ssbo_atomic_max
:
3385 opcode
= TGSI_OPCODE_ATOMIMAX
;
3387 case ir_intrinsic_ssbo_atomic_and
:
3388 opcode
= TGSI_OPCODE_ATOMAND
;
3390 case ir_intrinsic_ssbo_atomic_or
:
3391 opcode
= TGSI_OPCODE_ATOMOR
;
3393 case ir_intrinsic_ssbo_atomic_xor
:
3394 opcode
= TGSI_OPCODE_ATOMXOR
;
3396 case ir_intrinsic_ssbo_atomic_exchange
:
3397 opcode
= TGSI_OPCODE_ATOMXCHG
;
3399 case ir_intrinsic_ssbo_atomic_comp_swap
:
3400 opcode
= TGSI_OPCODE_ATOMCAS
;
3401 param
= param
->get_next();
3402 val
= ((ir_instruction
*)param
)->as_rvalue();
3404 data2
= this->result
;
3407 assert(!"Unexpected intrinsic");
3411 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3414 param
= param
->get_next();
3415 ir_constant
*access
= NULL
;
3416 if (!param
->is_tail_sentinel()) {
3417 access
= ((ir_instruction
*)param
)->as_constant();
3421 /* The emit_asm() might have actually split the op into pieces, e.g. for
3422 * double stores. We have to go back and fix up all the generated ops.
3424 unsigned op
= inst
->op
;
3426 inst
->resource
= buffer
;
3428 inst
->buffer_access
= access
->value
.u
[0];
3429 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3430 if (inst
->op
== TGSI_OPCODE_UADD
)
3431 inst
= (glsl_to_tgsi_instruction
*)inst
->get_prev();
3432 } while (inst
&& inst
->op
== op
&& inst
->resource
.file
== PROGRAM_UNDEFINED
);
3436 glsl_to_tgsi_visitor::visit_membar_intrinsic(ir_call
*ir
)
3438 switch (ir
->callee
->intrinsic_id
) {
3439 case ir_intrinsic_memory_barrier
:
3440 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3441 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3442 TGSI_MEMBAR_ATOMIC_BUFFER
|
3443 TGSI_MEMBAR_SHADER_IMAGE
|
3444 TGSI_MEMBAR_SHARED
));
3446 case ir_intrinsic_memory_barrier_atomic_counter
:
3447 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3448 st_src_reg_for_int(TGSI_MEMBAR_ATOMIC_BUFFER
));
3450 case ir_intrinsic_memory_barrier_buffer
:
3451 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3452 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
));
3454 case ir_intrinsic_memory_barrier_image
:
3455 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3456 st_src_reg_for_int(TGSI_MEMBAR_SHADER_IMAGE
));
3458 case ir_intrinsic_memory_barrier_shared
:
3459 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3460 st_src_reg_for_int(TGSI_MEMBAR_SHARED
));
3462 case ir_intrinsic_group_memory_barrier
:
3463 emit_asm(ir
, TGSI_OPCODE_MEMBAR
, undef_dst
,
3464 st_src_reg_for_int(TGSI_MEMBAR_SHADER_BUFFER
|
3465 TGSI_MEMBAR_ATOMIC_BUFFER
|
3466 TGSI_MEMBAR_SHADER_IMAGE
|
3467 TGSI_MEMBAR_SHARED
|
3468 TGSI_MEMBAR_THREAD_GROUP
));
3471 assert(!"Unexpected memory barrier intrinsic");
3476 glsl_to_tgsi_visitor::visit_shared_intrinsic(ir_call
*ir
)
3478 exec_node
*param
= ir
->actual_parameters
.get_head();
3480 ir_rvalue
*offset
= ((ir_instruction
*)param
)->as_rvalue();
3482 st_src_reg
buffer(PROGRAM_MEMORY
, 0, GLSL_TYPE_UINT
);
3484 /* Calculate the surface offset */
3485 offset
->accept(this);
3486 st_src_reg off
= this->result
;
3488 st_dst_reg dst
= undef_dst
;
3489 if (ir
->return_deref
) {
3490 ir
->return_deref
->accept(this);
3491 dst
= st_dst_reg(this->result
);
3492 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3495 glsl_to_tgsi_instruction
*inst
;
3497 if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_load
) {
3498 inst
= emit_asm(ir
, TGSI_OPCODE_LOAD
, dst
, off
);
3499 inst
->resource
= buffer
;
3500 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_shared_store
) {
3501 param
= param
->get_next();
3502 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3505 param
= param
->get_next();
3506 ir_constant
*write_mask
= ((ir_instruction
*)param
)->as_constant();
3508 dst
.writemask
= write_mask
->value
.u
[0];
3510 dst
.type
= this->result
.type
;
3511 inst
= emit_asm(ir
, TGSI_OPCODE_STORE
, dst
, off
, this->result
);
3512 inst
->resource
= buffer
;
3514 param
= param
->get_next();
3515 ir_rvalue
*val
= ((ir_instruction
*)param
)->as_rvalue();
3518 st_src_reg data
= this->result
, data2
= undef_src
;
3520 switch (ir
->callee
->intrinsic_id
) {
3521 case ir_intrinsic_shared_atomic_add
:
3522 opcode
= TGSI_OPCODE_ATOMUADD
;
3524 case ir_intrinsic_shared_atomic_min
:
3525 opcode
= TGSI_OPCODE_ATOMIMIN
;
3527 case ir_intrinsic_shared_atomic_max
:
3528 opcode
= TGSI_OPCODE_ATOMIMAX
;
3530 case ir_intrinsic_shared_atomic_and
:
3531 opcode
= TGSI_OPCODE_ATOMAND
;
3533 case ir_intrinsic_shared_atomic_or
:
3534 opcode
= TGSI_OPCODE_ATOMOR
;
3536 case ir_intrinsic_shared_atomic_xor
:
3537 opcode
= TGSI_OPCODE_ATOMXOR
;
3539 case ir_intrinsic_shared_atomic_exchange
:
3540 opcode
= TGSI_OPCODE_ATOMXCHG
;
3542 case ir_intrinsic_shared_atomic_comp_swap
:
3543 opcode
= TGSI_OPCODE_ATOMCAS
;
3544 param
= param
->get_next();
3545 val
= ((ir_instruction
*)param
)->as_rvalue();
3547 data2
= this->result
;
3550 assert(!"Unexpected intrinsic");
3554 inst
= emit_asm(ir
, opcode
, dst
, off
, data
, data2
);
3555 inst
->resource
= buffer
;
3560 glsl_to_tgsi_visitor::visit_image_intrinsic(ir_call
*ir
)
3562 exec_node
*param
= ir
->actual_parameters
.get_head();
3564 ir_dereference
*img
= (ir_dereference
*)param
;
3565 const ir_variable
*imgvar
= img
->variable_referenced();
3566 const glsl_type
*type
= imgvar
->type
->without_array();
3567 unsigned sampler_array_size
= 1, sampler_base
= 0;
3570 st_src_reg
image(PROGRAM_IMAGE
, 0, GLSL_TYPE_UINT
);
3572 get_deref_offsets(img
, &sampler_array_size
, &sampler_base
,
3573 (uint16_t*)&image
.index
, &reladdr
, true);
3575 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
3576 image
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
3577 *image
.reladdr
= reladdr
;
3578 emit_arl(ir
, sampler_reladdr
, reladdr
);
3581 st_dst_reg dst
= undef_dst
;
3582 if (ir
->return_deref
) {
3583 ir
->return_deref
->accept(this);
3584 dst
= st_dst_reg(this->result
);
3585 dst
.writemask
= (1 << ir
->return_deref
->type
->vector_elements
) - 1;
3588 glsl_to_tgsi_instruction
*inst
;
3590 if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_size
) {
3591 dst
.writemask
= WRITEMASK_XYZ
;
3592 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dst
);
3593 } else if (ir
->callee
->intrinsic_id
== ir_intrinsic_image_samples
) {
3594 st_src_reg res
= get_temp(glsl_type::ivec4_type
);
3595 st_dst_reg dstres
= st_dst_reg(res
);
3596 dstres
.writemask
= WRITEMASK_W
;
3597 inst
= emit_asm(ir
, TGSI_OPCODE_RESQ
, dstres
);
3598 res
.swizzle
= SWIZZLE_WWWW
;
3599 emit_asm(ir
, TGSI_OPCODE_MOV
, dst
, res
);
3601 st_src_reg arg1
= undef_src
, arg2
= undef_src
;
3603 st_dst_reg coord_dst
;
3604 coord
= get_temp(glsl_type::ivec4_type
);
3605 coord_dst
= st_dst_reg(coord
);
3606 coord_dst
.writemask
= (1 << type
->coordinate_components()) - 1;
3607 param
= param
->get_next();
3608 ((ir_dereference
*)param
)->accept(this);
3609 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3610 coord
.swizzle
= SWIZZLE_XXXX
;
3611 switch (type
->coordinate_components()) {
3612 case 4: assert(!"unexpected coord count");
3614 case 3: coord
.swizzle
|= SWIZZLE_Z
<< 6;
3616 case 2: coord
.swizzle
|= SWIZZLE_Y
<< 3;
3619 if (type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_MS
) {
3620 param
= param
->get_next();
3621 ((ir_dereference
*)param
)->accept(this);
3622 st_src_reg sample
= this->result
;
3623 sample
.swizzle
= SWIZZLE_XXXX
;
3624 coord_dst
.writemask
= WRITEMASK_W
;
3625 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample
);
3626 coord
.swizzle
|= SWIZZLE_W
<< 9;
3629 param
= param
->get_next();
3630 if (!param
->is_tail_sentinel()) {
3631 ((ir_dereference
*)param
)->accept(this);
3632 arg1
= this->result
;
3633 param
= param
->get_next();
3636 if (!param
->is_tail_sentinel()) {
3637 ((ir_dereference
*)param
)->accept(this);
3638 arg2
= this->result
;
3639 param
= param
->get_next();
3642 assert(param
->is_tail_sentinel());
3645 switch (ir
->callee
->intrinsic_id
) {
3646 case ir_intrinsic_image_load
:
3647 opcode
= TGSI_OPCODE_LOAD
;
3649 case ir_intrinsic_image_store
:
3650 opcode
= TGSI_OPCODE_STORE
;
3652 case ir_intrinsic_image_atomic_add
:
3653 opcode
= TGSI_OPCODE_ATOMUADD
;
3655 case ir_intrinsic_image_atomic_min
:
3656 opcode
= TGSI_OPCODE_ATOMIMIN
;
3658 case ir_intrinsic_image_atomic_max
:
3659 opcode
= TGSI_OPCODE_ATOMIMAX
;
3661 case ir_intrinsic_image_atomic_and
:
3662 opcode
= TGSI_OPCODE_ATOMAND
;
3664 case ir_intrinsic_image_atomic_or
:
3665 opcode
= TGSI_OPCODE_ATOMOR
;
3667 case ir_intrinsic_image_atomic_xor
:
3668 opcode
= TGSI_OPCODE_ATOMXOR
;
3670 case ir_intrinsic_image_atomic_exchange
:
3671 opcode
= TGSI_OPCODE_ATOMXCHG
;
3673 case ir_intrinsic_image_atomic_comp_swap
:
3674 opcode
= TGSI_OPCODE_ATOMCAS
;
3677 assert(!"Unexpected intrinsic");
3681 inst
= emit_asm(ir
, opcode
, dst
, coord
, arg1
, arg2
);
3682 if (opcode
== TGSI_OPCODE_STORE
)
3683 inst
->dst
[0].writemask
= WRITEMASK_XYZW
;
3686 inst
->resource
= image
;
3687 inst
->sampler_array_size
= sampler_array_size
;
3688 inst
->sampler_base
= sampler_base
;
3690 switch (type
->sampler_dimensionality
) {
3691 case GLSL_SAMPLER_DIM_1D
:
3692 inst
->tex_target
= (type
->sampler_array
)
3693 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
3695 case GLSL_SAMPLER_DIM_2D
:
3696 inst
->tex_target
= (type
->sampler_array
)
3697 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
3699 case GLSL_SAMPLER_DIM_3D
:
3700 inst
->tex_target
= TEXTURE_3D_INDEX
;
3702 case GLSL_SAMPLER_DIM_CUBE
:
3703 inst
->tex_target
= (type
->sampler_array
)
3704 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
3706 case GLSL_SAMPLER_DIM_RECT
:
3707 inst
->tex_target
= TEXTURE_RECT_INDEX
;
3709 case GLSL_SAMPLER_DIM_BUF
:
3710 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
3712 case GLSL_SAMPLER_DIM_EXTERNAL
:
3713 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
3715 case GLSL_SAMPLER_DIM_MS
:
3716 inst
->tex_target
= (type
->sampler_array
)
3717 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
3720 assert(!"Should not get here.");
3723 inst
->image_format
= st_mesa_format_to_pipe_format(st_context(ctx
),
3724 _mesa_get_shader_image_format(imgvar
->data
.image_format
));
3726 if (imgvar
->data
.image_coherent
)
3727 inst
->buffer_access
|= TGSI_MEMORY_COHERENT
;
3728 if (imgvar
->data
.image_restrict
)
3729 inst
->buffer_access
|= TGSI_MEMORY_RESTRICT
;
3730 if (imgvar
->data
.image_volatile
)
3731 inst
->buffer_access
|= TGSI_MEMORY_VOLATILE
;
3735 glsl_to_tgsi_visitor::visit(ir_call
*ir
)
3737 ir_function_signature
*sig
= ir
->callee
;
3739 /* Filter out intrinsics */
3740 switch (sig
->intrinsic_id
) {
3741 case ir_intrinsic_atomic_counter_read
:
3742 case ir_intrinsic_atomic_counter_increment
:
3743 case ir_intrinsic_atomic_counter_predecrement
:
3744 case ir_intrinsic_atomic_counter_add
:
3745 case ir_intrinsic_atomic_counter_min
:
3746 case ir_intrinsic_atomic_counter_max
:
3747 case ir_intrinsic_atomic_counter_and
:
3748 case ir_intrinsic_atomic_counter_or
:
3749 case ir_intrinsic_atomic_counter_xor
:
3750 case ir_intrinsic_atomic_counter_exchange
:
3751 case ir_intrinsic_atomic_counter_comp_swap
:
3752 visit_atomic_counter_intrinsic(ir
);
3755 case ir_intrinsic_ssbo_load
:
3756 case ir_intrinsic_ssbo_store
:
3757 case ir_intrinsic_ssbo_atomic_add
:
3758 case ir_intrinsic_ssbo_atomic_min
:
3759 case ir_intrinsic_ssbo_atomic_max
:
3760 case ir_intrinsic_ssbo_atomic_and
:
3761 case ir_intrinsic_ssbo_atomic_or
:
3762 case ir_intrinsic_ssbo_atomic_xor
:
3763 case ir_intrinsic_ssbo_atomic_exchange
:
3764 case ir_intrinsic_ssbo_atomic_comp_swap
:
3765 visit_ssbo_intrinsic(ir
);
3768 case ir_intrinsic_memory_barrier
:
3769 case ir_intrinsic_memory_barrier_atomic_counter
:
3770 case ir_intrinsic_memory_barrier_buffer
:
3771 case ir_intrinsic_memory_barrier_image
:
3772 case ir_intrinsic_memory_barrier_shared
:
3773 case ir_intrinsic_group_memory_barrier
:
3774 visit_membar_intrinsic(ir
);
3777 case ir_intrinsic_shared_load
:
3778 case ir_intrinsic_shared_store
:
3779 case ir_intrinsic_shared_atomic_add
:
3780 case ir_intrinsic_shared_atomic_min
:
3781 case ir_intrinsic_shared_atomic_max
:
3782 case ir_intrinsic_shared_atomic_and
:
3783 case ir_intrinsic_shared_atomic_or
:
3784 case ir_intrinsic_shared_atomic_xor
:
3785 case ir_intrinsic_shared_atomic_exchange
:
3786 case ir_intrinsic_shared_atomic_comp_swap
:
3787 visit_shared_intrinsic(ir
);
3790 case ir_intrinsic_image_load
:
3791 case ir_intrinsic_image_store
:
3792 case ir_intrinsic_image_atomic_add
:
3793 case ir_intrinsic_image_atomic_min
:
3794 case ir_intrinsic_image_atomic_max
:
3795 case ir_intrinsic_image_atomic_and
:
3796 case ir_intrinsic_image_atomic_or
:
3797 case ir_intrinsic_image_atomic_xor
:
3798 case ir_intrinsic_image_atomic_exchange
:
3799 case ir_intrinsic_image_atomic_comp_swap
:
3800 case ir_intrinsic_image_size
:
3801 case ir_intrinsic_image_samples
:
3802 visit_image_intrinsic(ir
);
3805 case ir_intrinsic_invalid
:
3806 case ir_intrinsic_generic_load
:
3807 case ir_intrinsic_generic_store
:
3808 case ir_intrinsic_generic_atomic_add
:
3809 case ir_intrinsic_generic_atomic_and
:
3810 case ir_intrinsic_generic_atomic_or
:
3811 case ir_intrinsic_generic_atomic_xor
:
3812 case ir_intrinsic_generic_atomic_min
:
3813 case ir_intrinsic_generic_atomic_max
:
3814 case ir_intrinsic_generic_atomic_exchange
:
3815 case ir_intrinsic_generic_atomic_comp_swap
:
3816 case ir_intrinsic_shader_clock
:
3817 unreachable("Invalid intrinsic");
3822 glsl_to_tgsi_visitor::calc_deref_offsets(ir_dereference
*tail
,
3823 unsigned *array_elements
,
3825 st_src_reg
*indirect
,
3828 switch (tail
->ir_type
) {
3829 case ir_type_dereference_record
: {
3830 ir_dereference_record
*deref_record
= tail
->as_dereference_record();
3831 const glsl_type
*struct_type
= deref_record
->record
->type
;
3832 int field_index
= deref_record
->record
->type
->field_index(deref_record
->field
);
3834 calc_deref_offsets(deref_record
->record
->as_dereference(), array_elements
, index
, indirect
, location
);
3836 assert(field_index
>= 0);
3837 *location
+= struct_type
->record_location_offset(field_index
);
3841 case ir_type_dereference_array
: {
3842 ir_dereference_array
*deref_arr
= tail
->as_dereference_array();
3843 ir_constant
*array_index
= deref_arr
->array_index
->constant_expression_value();
3846 st_src_reg temp_reg
;
3847 st_dst_reg temp_dst
;
3849 temp_reg
= get_temp(glsl_type::uint_type
);
3850 temp_dst
= st_dst_reg(temp_reg
);
3851 temp_dst
.writemask
= 1;
3853 deref_arr
->array_index
->accept(this);
3854 if (*array_elements
!= 1)
3855 emit_asm(NULL
, TGSI_OPCODE_MUL
, temp_dst
, this->result
, st_src_reg_for_int(*array_elements
));
3857 emit_asm(NULL
, TGSI_OPCODE_MOV
, temp_dst
, this->result
);
3859 if (indirect
->file
== PROGRAM_UNDEFINED
)
3860 *indirect
= temp_reg
;
3862 temp_dst
= st_dst_reg(*indirect
);
3863 temp_dst
.writemask
= 1;
3864 emit_asm(NULL
, TGSI_OPCODE_ADD
, temp_dst
, *indirect
, temp_reg
);
3867 *index
+= array_index
->value
.u
[0] * *array_elements
;
3869 *array_elements
*= deref_arr
->array
->type
->length
;
3871 calc_deref_offsets(deref_arr
->array
->as_dereference(), array_elements
, index
, indirect
, location
);
3880 glsl_to_tgsi_visitor::get_deref_offsets(ir_dereference
*ir
,
3881 unsigned *array_size
,
3884 st_src_reg
*reladdr
,
3887 GLuint shader
= _mesa_program_enum_to_shader_stage(this->prog
->Target
);
3888 unsigned location
= 0;
3889 ir_variable
*var
= ir
->variable_referenced();
3891 memset(reladdr
, 0, sizeof(*reladdr
));
3892 reladdr
->file
= PROGRAM_UNDEFINED
;
3898 location
= var
->data
.location
;
3899 calc_deref_offsets(ir
, array_size
, index
, reladdr
, &location
);
3902 * If we end up with no indirect then adjust the base to the index,
3903 * and set the array size to 1.
3905 if (reladdr
->file
== PROGRAM_UNDEFINED
) {
3911 assert(location
!= 0xffffffff);
3912 *base
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3913 *index
+= this->shader_program
->data
->UniformStorage
[location
].opaque
[shader
].index
;
3918 glsl_to_tgsi_visitor::canonicalize_gather_offset(st_src_reg offset
)
3920 if (offset
.reladdr
|| offset
.reladdr2
) {
3921 st_src_reg tmp
= get_temp(glsl_type::ivec2_type
);
3922 st_dst_reg tmp_dst
= st_dst_reg(tmp
);
3923 tmp_dst
.writemask
= WRITEMASK_XY
;
3924 emit_asm(NULL
, TGSI_OPCODE_MOV
, tmp_dst
, offset
);
3932 glsl_to_tgsi_visitor::visit(ir_texture
*ir
)
3934 st_src_reg result_src
, coord
, cube_sc
, lod_info
, projector
, dx
, dy
;
3935 st_src_reg offset
[MAX_GLSL_TEXTURE_OFFSET
], sample_index
, component
;
3936 st_src_reg levels_src
, reladdr
;
3937 st_dst_reg result_dst
, coord_dst
, cube_sc_dst
;
3938 glsl_to_tgsi_instruction
*inst
= NULL
;
3939 unsigned opcode
= TGSI_OPCODE_NOP
;
3940 const glsl_type
*sampler_type
= ir
->sampler
->type
;
3941 unsigned sampler_array_size
= 1, sampler_base
= 0;
3942 uint16_t sampler_index
= 0;
3943 bool is_cube_array
= false;
3946 /* if we are a cube array sampler */
3947 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3948 sampler_type
->sampler_array
)) {
3949 is_cube_array
= true;
3952 if (ir
->coordinate
) {
3953 ir
->coordinate
->accept(this);
3955 /* Put our coords in a temp. We'll need to modify them for shadow,
3956 * projection, or LOD, so the only case we'd use it as-is is if
3957 * we're doing plain old texturing. The optimization passes on
3958 * glsl_to_tgsi_visitor should handle cleaning up our mess in that case.
3960 coord
= get_temp(glsl_type::vec4_type
);
3961 coord_dst
= st_dst_reg(coord
);
3962 coord_dst
.writemask
= (1 << ir
->coordinate
->type
->vector_elements
) - 1;
3963 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
3966 if (ir
->projector
) {
3967 ir
->projector
->accept(this);
3968 projector
= this->result
;
3971 /* Storage for our result. Ideally for an assignment we'd be using
3972 * the actual storage for the result here, instead.
3974 result_src
= get_temp(ir
->type
);
3975 result_dst
= st_dst_reg(result_src
);
3979 opcode
= (is_cube_array
&& ir
->shadow_comparator
) ? TGSI_OPCODE_TEX2
: TGSI_OPCODE_TEX
;
3981 ir
->offset
->accept(this);
3982 offset
[0] = this->result
;
3986 if (is_cube_array
||
3987 sampler_type
== glsl_type::samplerCubeShadow_type
) {
3988 opcode
= TGSI_OPCODE_TXB2
;
3991 opcode
= TGSI_OPCODE_TXB
;
3993 ir
->lod_info
.bias
->accept(this);
3994 lod_info
= this->result
;
3996 ir
->offset
->accept(this);
3997 offset
[0] = this->result
;
4001 opcode
= is_cube_array
? TGSI_OPCODE_TXL2
: TGSI_OPCODE_TXL
;
4002 ir
->lod_info
.lod
->accept(this);
4003 lod_info
= this->result
;
4005 ir
->offset
->accept(this);
4006 offset
[0] = this->result
;
4010 opcode
= TGSI_OPCODE_TXD
;
4011 ir
->lod_info
.grad
.dPdx
->accept(this);
4013 ir
->lod_info
.grad
.dPdy
->accept(this);
4016 ir
->offset
->accept(this);
4017 offset
[0] = this->result
;
4021 opcode
= TGSI_OPCODE_TXQ
;
4022 ir
->lod_info
.lod
->accept(this);
4023 lod_info
= this->result
;
4025 case ir_query_levels
:
4026 opcode
= TGSI_OPCODE_TXQ
;
4027 lod_info
= undef_src
;
4028 levels_src
= get_temp(ir
->type
);
4031 opcode
= TGSI_OPCODE_TXF
;
4032 ir
->lod_info
.lod
->accept(this);
4033 lod_info
= this->result
;
4035 ir
->offset
->accept(this);
4036 offset
[0] = this->result
;
4040 opcode
= TGSI_OPCODE_TXF
;
4041 ir
->lod_info
.sample_index
->accept(this);
4042 sample_index
= this->result
;
4045 opcode
= TGSI_OPCODE_TG4
;
4046 ir
->lod_info
.component
->accept(this);
4047 component
= this->result
;
4049 ir
->offset
->accept(this);
4050 if (ir
->offset
->type
->base_type
== GLSL_TYPE_ARRAY
) {
4051 const glsl_type
*elt_type
= ir
->offset
->type
->fields
.array
;
4052 for (i
= 0; i
< ir
->offset
->type
->length
; i
++) {
4053 offset
[i
] = this->result
;
4054 offset
[i
].index
+= i
* type_size(elt_type
);
4055 offset
[i
].type
= elt_type
->base_type
;
4056 offset
[i
].swizzle
= swizzle_for_size(elt_type
->vector_elements
);
4057 offset
[i
] = canonicalize_gather_offset(offset
[i
]);
4060 offset
[0] = canonicalize_gather_offset(this->result
);
4065 opcode
= TGSI_OPCODE_LODQ
;
4067 case ir_texture_samples
:
4068 opcode
= TGSI_OPCODE_TXQS
;
4070 case ir_samples_identical
:
4071 unreachable("Unexpected ir_samples_identical opcode");
4074 if (ir
->projector
) {
4075 if (opcode
== TGSI_OPCODE_TEX
) {
4076 /* Slot the projector in as the last component of the coord. */
4077 coord_dst
.writemask
= WRITEMASK_W
;
4078 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, projector
);
4079 coord_dst
.writemask
= WRITEMASK_XYZW
;
4080 opcode
= TGSI_OPCODE_TXP
;
4082 st_src_reg coord_w
= coord
;
4083 coord_w
.swizzle
= SWIZZLE_WWWW
;
4085 /* For the other TEX opcodes there's no projective version
4086 * since the last slot is taken up by LOD info. Do the
4087 * projective divide now.
4089 coord_dst
.writemask
= WRITEMASK_W
;
4090 emit_asm(ir
, TGSI_OPCODE_RCP
, coord_dst
, projector
);
4092 /* In the case where we have to project the coordinates "by hand,"
4093 * the shadow comparator value must also be projected.
4095 st_src_reg tmp_src
= coord
;
4096 if (ir
->shadow_comparator
) {
4097 /* Slot the shadow value in as the second to last component of the
4100 ir
->shadow_comparator
->accept(this);
4102 tmp_src
= get_temp(glsl_type::vec4_type
);
4103 st_dst_reg tmp_dst
= st_dst_reg(tmp_src
);
4105 /* Projective division not allowed for array samplers. */
4106 assert(!sampler_type
->sampler_array
);
4108 tmp_dst
.writemask
= WRITEMASK_Z
;
4109 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, this->result
);
4111 tmp_dst
.writemask
= WRITEMASK_XY
;
4112 emit_asm(ir
, TGSI_OPCODE_MOV
, tmp_dst
, coord
);
4115 coord_dst
.writemask
= WRITEMASK_XYZ
;
4116 emit_asm(ir
, TGSI_OPCODE_MUL
, coord_dst
, tmp_src
, coord_w
);
4118 coord_dst
.writemask
= WRITEMASK_XYZW
;
4119 coord
.swizzle
= SWIZZLE_XYZW
;
4123 /* If projection is done and the opcode is not TGSI_OPCODE_TXP, then the shadow
4124 * comparator was put in the correct place (and projected) by the code,
4125 * above, that handles by-hand projection.
4127 if (ir
->shadow_comparator
&& (!ir
->projector
|| opcode
== TGSI_OPCODE_TXP
)) {
4128 /* Slot the shadow value in as the second to last component of the
4131 ir
->shadow_comparator
->accept(this);
4133 if (is_cube_array
) {
4134 cube_sc
= get_temp(glsl_type::float_type
);
4135 cube_sc_dst
= st_dst_reg(cube_sc
);
4136 cube_sc_dst
.writemask
= WRITEMASK_X
;
4137 emit_asm(ir
, TGSI_OPCODE_MOV
, cube_sc_dst
, this->result
);
4138 cube_sc_dst
.writemask
= WRITEMASK_X
;
4141 if ((sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_2D
&&
4142 sampler_type
->sampler_array
) ||
4143 sampler_type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
) {
4144 coord_dst
.writemask
= WRITEMASK_W
;
4146 coord_dst
.writemask
= WRITEMASK_Z
;
4148 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, this->result
);
4149 coord_dst
.writemask
= WRITEMASK_XYZW
;
4153 if (ir
->op
== ir_txf_ms
) {
4154 coord_dst
.writemask
= WRITEMASK_W
;
4155 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, sample_index
);
4156 coord_dst
.writemask
= WRITEMASK_XYZW
;
4157 } else if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXB
||
4158 opcode
== TGSI_OPCODE_TXF
) {
4159 /* TGSI stores LOD or LOD bias in the last channel of the coords. */
4160 coord_dst
.writemask
= WRITEMASK_W
;
4161 emit_asm(ir
, TGSI_OPCODE_MOV
, coord_dst
, lod_info
);
4162 coord_dst
.writemask
= WRITEMASK_XYZW
;
4165 get_deref_offsets(ir
->sampler
, &sampler_array_size
, &sampler_base
,
4166 &sampler_index
, &reladdr
, true);
4167 if (reladdr
.file
!= PROGRAM_UNDEFINED
)
4168 emit_arl(ir
, sampler_reladdr
, reladdr
);
4170 if (opcode
== TGSI_OPCODE_TXD
)
4171 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, dx
, dy
);
4172 else if (opcode
== TGSI_OPCODE_TXQ
) {
4173 if (ir
->op
== ir_query_levels
) {
4174 /* the level is stored in W */
4175 inst
= emit_asm(ir
, opcode
, st_dst_reg(levels_src
), lod_info
);
4176 result_dst
.writemask
= WRITEMASK_X
;
4177 levels_src
.swizzle
= SWIZZLE_WWWW
;
4178 emit_asm(ir
, TGSI_OPCODE_MOV
, result_dst
, levels_src
);
4180 inst
= emit_asm(ir
, opcode
, result_dst
, lod_info
);
4181 } else if (opcode
== TGSI_OPCODE_TXQS
) {
4182 inst
= emit_asm(ir
, opcode
, result_dst
);
4183 } else if (opcode
== TGSI_OPCODE_TXF
) {
4184 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4185 } else if (opcode
== TGSI_OPCODE_TXL2
|| opcode
== TGSI_OPCODE_TXB2
) {
4186 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, lod_info
);
4187 } else if (opcode
== TGSI_OPCODE_TEX2
) {
4188 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4189 } else if (opcode
== TGSI_OPCODE_TG4
) {
4190 if (is_cube_array
&& ir
->shadow_comparator
) {
4191 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, cube_sc
);
4193 inst
= emit_asm(ir
, opcode
, result_dst
, coord
, component
);
4196 inst
= emit_asm(ir
, opcode
, result_dst
, coord
);
4198 if (ir
->shadow_comparator
)
4199 inst
->tex_shadow
= GL_TRUE
;
4201 inst
->resource
.index
= sampler_index
;
4202 inst
->sampler_array_size
= sampler_array_size
;
4203 inst
->sampler_base
= sampler_base
;
4205 if (reladdr
.file
!= PROGRAM_UNDEFINED
) {
4206 inst
->resource
.reladdr
= ralloc(mem_ctx
, st_src_reg
);
4207 memcpy(inst
->resource
.reladdr
, &reladdr
, sizeof(reladdr
));
4211 if (!inst
->tex_offsets
)
4212 inst
->tex_offsets
= rzalloc_array(inst
, st_src_reg
, MAX_GLSL_TEXTURE_OFFSET
);
4214 for (i
= 0; i
< MAX_GLSL_TEXTURE_OFFSET
&& offset
[i
].file
!= PROGRAM_UNDEFINED
; i
++)
4215 inst
->tex_offsets
[i
] = offset
[i
];
4216 inst
->tex_offset_num_offset
= i
;
4219 switch (sampler_type
->sampler_dimensionality
) {
4220 case GLSL_SAMPLER_DIM_1D
:
4221 inst
->tex_target
= (sampler_type
->sampler_array
)
4222 ? TEXTURE_1D_ARRAY_INDEX
: TEXTURE_1D_INDEX
;
4224 case GLSL_SAMPLER_DIM_2D
:
4225 inst
->tex_target
= (sampler_type
->sampler_array
)
4226 ? TEXTURE_2D_ARRAY_INDEX
: TEXTURE_2D_INDEX
;
4228 case GLSL_SAMPLER_DIM_3D
:
4229 inst
->tex_target
= TEXTURE_3D_INDEX
;
4231 case GLSL_SAMPLER_DIM_CUBE
:
4232 inst
->tex_target
= (sampler_type
->sampler_array
)
4233 ? TEXTURE_CUBE_ARRAY_INDEX
: TEXTURE_CUBE_INDEX
;
4235 case GLSL_SAMPLER_DIM_RECT
:
4236 inst
->tex_target
= TEXTURE_RECT_INDEX
;
4238 case GLSL_SAMPLER_DIM_BUF
:
4239 inst
->tex_target
= TEXTURE_BUFFER_INDEX
;
4241 case GLSL_SAMPLER_DIM_EXTERNAL
:
4242 inst
->tex_target
= TEXTURE_EXTERNAL_INDEX
;
4244 case GLSL_SAMPLER_DIM_MS
:
4245 inst
->tex_target
= (sampler_type
->sampler_array
)
4246 ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: TEXTURE_2D_MULTISAMPLE_INDEX
;
4249 assert(!"Should not get here.");
4252 inst
->tex_type
= ir
->type
->base_type
;
4254 this->result
= result_src
;
4258 glsl_to_tgsi_visitor::visit(ir_return
*ir
)
4260 assert(!ir
->get_value());
4262 emit_asm(ir
, TGSI_OPCODE_RET
);
4266 glsl_to_tgsi_visitor::visit(ir_discard
*ir
)
4268 if (ir
->condition
) {
4269 ir
->condition
->accept(this);
4270 st_src_reg condition
= this->result
;
4272 /* Convert the bool condition to a float so we can negate. */
4273 if (native_integers
) {
4274 st_src_reg temp
= get_temp(ir
->condition
->type
);
4275 emit_asm(ir
, TGSI_OPCODE_AND
, st_dst_reg(temp
),
4276 condition
, st_src_reg_for_float(1.0));
4280 condition
.negate
= ~condition
.negate
;
4281 emit_asm(ir
, TGSI_OPCODE_KILL_IF
, undef_dst
, condition
);
4283 /* unconditional kil */
4284 emit_asm(ir
, TGSI_OPCODE_KILL
);
4289 glsl_to_tgsi_visitor::visit(ir_if
*ir
)
4292 glsl_to_tgsi_instruction
*if_inst
;
4294 ir
->condition
->accept(this);
4295 assert(this->result
.file
!= PROGRAM_UNDEFINED
);
4297 if_opcode
= native_integers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
;
4299 if_inst
= emit_asm(ir
->condition
, if_opcode
, undef_dst
, this->result
);
4301 this->instructions
.push_tail(if_inst
);
4303 visit_exec_list(&ir
->then_instructions
, this);
4305 if (!ir
->else_instructions
.is_empty()) {
4306 emit_asm(ir
->condition
, TGSI_OPCODE_ELSE
);
4307 visit_exec_list(&ir
->else_instructions
, this);
4310 if_inst
= emit_asm(ir
->condition
, TGSI_OPCODE_ENDIF
);
4315 glsl_to_tgsi_visitor::visit(ir_emit_vertex
*ir
)
4317 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4319 ir
->stream
->accept(this);
4320 emit_asm(ir
, TGSI_OPCODE_EMIT
, undef_dst
, this->result
);
4324 glsl_to_tgsi_visitor::visit(ir_end_primitive
*ir
)
4326 assert(this->prog
->Target
== GL_GEOMETRY_PROGRAM_NV
);
4328 ir
->stream
->accept(this);
4329 emit_asm(ir
, TGSI_OPCODE_ENDPRIM
, undef_dst
, this->result
);
4333 glsl_to_tgsi_visitor::visit(ir_barrier
*ir
)
4335 assert(this->prog
->Target
== GL_TESS_CONTROL_PROGRAM_NV
||
4336 this->prog
->Target
== GL_COMPUTE_PROGRAM_NV
);
4338 emit_asm(ir
, TGSI_OPCODE_BARRIER
);
4341 glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
4343 STATIC_ASSERT(sizeof(samplers_used
) * 8 >= PIPE_MAX_SAMPLERS
);
4345 result
.file
= PROGRAM_UNDEFINED
;
4352 num_input_arrays
= 0;
4353 num_output_arrays
= 0;
4355 num_address_regs
= 0;
4359 indirect_addr_consts
= false;
4360 wpos_transform_const
= -1;
4362 native_integers
= false;
4363 mem_ctx
= ralloc_context(NULL
);
4366 shader_program
= NULL
;
4371 use_shared_memory
= false;
4374 glsl_to_tgsi_visitor::~glsl_to_tgsi_visitor()
4377 ralloc_free(mem_ctx
);
4380 extern "C" void free_glsl_to_tgsi_visitor(glsl_to_tgsi_visitor
*v
)
4387 * Count resources used by the given gpu program (number of texture
4391 count_resources(glsl_to_tgsi_visitor
*v
, gl_program
*prog
)
4393 v
->samplers_used
= 0;
4394 v
->buffers_used
= 0;
4397 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &v
->instructions
) {
4398 if (inst
->info
->is_tex
) {
4399 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4400 unsigned idx
= inst
->sampler_base
+ i
;
4401 v
->samplers_used
|= 1u << idx
;
4403 debug_assert(idx
< (int)ARRAY_SIZE(v
->sampler_types
));
4404 v
->sampler_types
[idx
] = inst
->tex_type
;
4405 v
->sampler_targets
[idx
] =
4406 st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
4408 if (inst
->tex_shadow
) {
4409 prog
->ShadowSamplers
|= 1 << (inst
->resource
.index
+ i
);
4414 if (inst
->tex_target
== TEXTURE_EXTERNAL_INDEX
)
4415 prog
->ExternalSamplersUsed
|= 1 << inst
->resource
.index
;
4417 if (inst
->resource
.file
!= PROGRAM_UNDEFINED
&& (
4418 is_resource_instruction(inst
->op
) ||
4419 inst
->op
== TGSI_OPCODE_STORE
)) {
4420 if (inst
->resource
.file
== PROGRAM_BUFFER
) {
4421 v
->buffers_used
|= 1 << inst
->resource
.index
;
4422 } else if (inst
->resource
.file
== PROGRAM_MEMORY
) {
4423 v
->use_shared_memory
= true;
4425 assert(inst
->resource
.file
== PROGRAM_IMAGE
);
4426 for (int i
= 0; i
< inst
->sampler_array_size
; i
++) {
4427 unsigned idx
= inst
->sampler_base
+ i
;
4428 v
->images_used
|= 1 << idx
;
4429 v
->image_targets
[idx
] =
4430 st_translate_texture_target(inst
->tex_target
, false);
4431 v
->image_formats
[idx
] = inst
->image_format
;
4436 prog
->SamplersUsed
= v
->samplers_used
;
4438 if (v
->shader_program
!= NULL
)
4439 _mesa_update_shader_textures_used(v
->shader_program
, prog
);
4443 * Returns the mask of channels (bitmask of WRITEMASK_X,Y,Z,W) which
4444 * are read from the given src in this instruction
4447 get_src_arg_mask(st_dst_reg dst
, st_src_reg src
)
4449 int read_mask
= 0, comp
;
4451 /* Now, given the src swizzle and the written channels, find which
4452 * components are actually read
4454 for (comp
= 0; comp
< 4; ++comp
) {
4455 const unsigned coord
= GET_SWZ(src
.swizzle
, comp
);
4457 if (dst
.writemask
& (1 << comp
) && coord
<= SWIZZLE_W
)
4458 read_mask
|= 1 << coord
;
4465 * This pass replaces CMP T0, T1 T2 T0 with MOV T0, T2 when the CMP
4466 * instruction is the first instruction to write to register T0. There are
4467 * several lowering passes done in GLSL IR (e.g. branches and
4468 * relative addressing) that create a large number of conditional assignments
4469 * that ir_to_mesa converts to CMP instructions like the one mentioned above.
4471 * Here is why this conversion is safe:
4472 * CMP T0, T1 T2 T0 can be expanded to:
4478 * If (T1 < 0.0) evaluates to true then our replacement MOV T0, T2 is the same
4479 * as the original program. If (T1 < 0.0) evaluates to false, executing
4480 * MOV T0, T0 will store a garbage value in T0 since T0 is uninitialized.
4481 * Therefore, it doesn't matter that we are replacing MOV T0, T0 with MOV T0, T2
4482 * because any instruction that was going to read from T0 after this was going
4483 * to read a garbage value anyway.
4486 glsl_to_tgsi_visitor::simplify_cmp(void)
4488 int tempWritesSize
= 0;
4489 unsigned *tempWrites
= NULL
;
4490 unsigned outputWrites
[VARYING_SLOT_TESS_MAX
];
4492 memset(outputWrites
, 0, sizeof(outputWrites
));
4494 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4495 unsigned prevWriteMask
= 0;
4497 /* Give up if we encounter relative addressing or flow control. */
4498 if (inst
->dst
[0].reladdr
|| inst
->dst
[0].reladdr2
||
4499 inst
->dst
[1].reladdr
|| inst
->dst
[1].reladdr2
||
4500 tgsi_get_opcode_info(inst
->op
)->is_branch
||
4501 inst
->op
== TGSI_OPCODE_CONT
||
4502 inst
->op
== TGSI_OPCODE_END
||
4503 inst
->op
== TGSI_OPCODE_RET
) {
4507 if (inst
->dst
[0].file
== PROGRAM_OUTPUT
) {
4508 assert(inst
->dst
[0].index
< (signed)ARRAY_SIZE(outputWrites
));
4509 prevWriteMask
= outputWrites
[inst
->dst
[0].index
];
4510 outputWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4511 } else if (inst
->dst
[0].file
== PROGRAM_TEMPORARY
) {
4512 if (inst
->dst
[0].index
>= tempWritesSize
) {
4513 const int inc
= 4096;
4515 tempWrites
= (unsigned*)
4517 (tempWritesSize
+ inc
) * sizeof(unsigned));
4521 memset(tempWrites
+ tempWritesSize
, 0, inc
* sizeof(unsigned));
4522 tempWritesSize
+= inc
;
4525 prevWriteMask
= tempWrites
[inst
->dst
[0].index
];
4526 tempWrites
[inst
->dst
[0].index
] |= inst
->dst
[0].writemask
;
4530 /* For a CMP to be considered a conditional write, the destination
4531 * register and source register two must be the same. */
4532 if (inst
->op
== TGSI_OPCODE_CMP
4533 && !(inst
->dst
[0].writemask
& prevWriteMask
)
4534 && inst
->src
[2].file
== inst
->dst
[0].file
4535 && inst
->src
[2].index
== inst
->dst
[0].index
4536 && inst
->dst
[0].writemask
== get_src_arg_mask(inst
->dst
[0], inst
->src
[2])) {
4538 inst
->op
= TGSI_OPCODE_MOV
;
4539 inst
->info
= tgsi_get_opcode_info(inst
->op
);
4540 inst
->src
[0] = inst
->src
[1];
4547 /* Replaces all references to a temporary register index with another index. */
4549 glsl_to_tgsi_visitor::rename_temp_registers(int num_renames
, struct rename_reg_pair
*renames
)
4551 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4554 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4555 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4556 for (k
= 0; k
< num_renames
; k
++)
4557 if (inst
->src
[j
].index
== renames
[k
].old_reg
)
4558 inst
->src
[j
].index
= renames
[k
].new_reg
;
4561 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4562 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4563 for (k
= 0; k
< num_renames
; k
++)
4564 if (inst
->tex_offsets
[j
].index
== renames
[k
].old_reg
)
4565 inst
->tex_offsets
[j
].index
= renames
[k
].new_reg
;
4568 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4569 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4570 for (k
= 0; k
< num_renames
; k
++)
4571 if (inst
->dst
[j
].index
== renames
[k
].old_reg
)
4572 inst
->dst
[j
].index
= renames
[k
].new_reg
;
4578 glsl_to_tgsi_visitor::get_first_temp_read(int *first_reads
)
4580 int depth
= 0; /* loop depth */
4581 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4584 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4585 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4586 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
) {
4587 if (first_reads
[inst
->src
[j
].index
] == -1)
4588 first_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4591 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4592 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
) {
4593 if (first_reads
[inst
->tex_offsets
[j
].index
] == -1)
4594 first_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4597 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4600 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4610 glsl_to_tgsi_visitor::get_last_temp_read_first_temp_write(int *last_reads
, int *first_writes
)
4612 int depth
= 0; /* loop depth */
4613 int loop_start
= -1; /* index of the first active BGNLOOP (if any) */
4616 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4617 for (j
= 0; j
< num_inst_src_regs(inst
); j
++) {
4618 if (inst
->src
[j
].file
== PROGRAM_TEMPORARY
)
4619 last_reads
[inst
->src
[j
].index
] = (depth
== 0) ? i
: -2;
4621 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4622 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
) {
4623 if (first_writes
[inst
->dst
[j
].index
] == -1)
4624 first_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: loop_start
;
4625 last_reads
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4628 for (j
= 0; j
< inst
->tex_offset_num_offset
; j
++) {
4629 if (inst
->tex_offsets
[j
].file
== PROGRAM_TEMPORARY
)
4630 last_reads
[inst
->tex_offsets
[j
].index
] = (depth
== 0) ? i
: -2;
4632 if (inst
->op
== TGSI_OPCODE_BGNLOOP
) {
4635 } else if (inst
->op
== TGSI_OPCODE_ENDLOOP
) {
4638 for (k
= 0; k
< this->next_temp
; k
++) {
4639 if (last_reads
[k
] == -2) {
4651 glsl_to_tgsi_visitor::get_last_temp_write(int *last_writes
)
4653 int depth
= 0; /* loop depth */
4657 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4658 for (j
= 0; j
< num_inst_dst_regs(inst
); j
++) {
4659 if (inst
->dst
[j
].file
== PROGRAM_TEMPORARY
)
4660 last_writes
[inst
->dst
[j
].index
] = (depth
== 0) ? i
: -2;
4663 if (inst
->op
== TGSI_OPCODE_BGNLOOP
)
4665 else if (inst
->op
== TGSI_OPCODE_ENDLOOP
)
4667 for (k
= 0; k
< this->next_temp
; k
++) {
4668 if (last_writes
[k
] == -2) {
4679 * On a basic block basis, tracks available PROGRAM_TEMPORARY register
4680 * channels for copy propagation and updates following instructions to
4681 * use the original versions.
4683 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4684 * will occur. As an example, a TXP production before this pass:
4686 * 0: MOV TEMP[1], INPUT[4].xyyy;
4687 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4688 * 2: TXP TEMP[2], TEMP[1], texture[0], 2D;
4692 * 0: MOV TEMP[1], INPUT[4].xyyy;
4693 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4694 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4696 * which allows for dead code elimination on TEMP[1]'s writes.
4699 glsl_to_tgsi_visitor::copy_propagate(void)
4701 glsl_to_tgsi_instruction
**acp
= rzalloc_array(mem_ctx
,
4702 glsl_to_tgsi_instruction
*,
4703 this->next_temp
* 4);
4704 int *acp_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4707 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4708 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4709 || inst
->dst
[0].index
< this->next_temp
);
4711 /* First, do any copy propagation possible into the src regs. */
4712 for (int r
= 0; r
< 3; r
++) {
4713 glsl_to_tgsi_instruction
*first
= NULL
;
4715 int acp_base
= inst
->src
[r
].index
* 4;
4717 if (inst
->src
[r
].file
!= PROGRAM_TEMPORARY
||
4718 inst
->src
[r
].reladdr
||
4719 inst
->src
[r
].reladdr2
)
4722 /* See if we can find entries in the ACP consisting of MOVs
4723 * from the same src register for all the swizzled channels
4724 * of this src register reference.
4726 for (int i
= 0; i
< 4; i
++) {
4727 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4728 glsl_to_tgsi_instruction
*copy_chan
= acp
[acp_base
+ src_chan
];
4735 assert(acp_level
[acp_base
+ src_chan
] <= level
);
4740 if (first
->src
[0].file
!= copy_chan
->src
[0].file
||
4741 first
->src
[0].index
!= copy_chan
->src
[0].index
||
4742 first
->src
[0].double_reg2
!= copy_chan
->src
[0].double_reg2
||
4743 first
->src
[0].index2D
!= copy_chan
->src
[0].index2D
) {
4751 /* We've now validated that we can copy-propagate to
4752 * replace this src register reference. Do it.
4754 inst
->src
[r
].file
= first
->src
[0].file
;
4755 inst
->src
[r
].index
= first
->src
[0].index
;
4756 inst
->src
[r
].index2D
= first
->src
[0].index2D
;
4757 inst
->src
[r
].has_index2
= first
->src
[0].has_index2
;
4758 inst
->src
[r
].double_reg2
= first
->src
[0].double_reg2
;
4759 inst
->src
[r
].array_id
= first
->src
[0].array_id
;
4762 for (int i
= 0; i
< 4; i
++) {
4763 int src_chan
= GET_SWZ(inst
->src
[r
].swizzle
, i
);
4764 glsl_to_tgsi_instruction
*copy_inst
= acp
[acp_base
+ src_chan
];
4765 swizzle
|= (GET_SWZ(copy_inst
->src
[0].swizzle
, src_chan
) << (3 * i
));
4767 inst
->src
[r
].swizzle
= swizzle
;
4772 case TGSI_OPCODE_BGNLOOP
:
4773 case TGSI_OPCODE_ENDLOOP
:
4774 /* End of a basic block, clear the ACP entirely. */
4775 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4778 case TGSI_OPCODE_IF
:
4779 case TGSI_OPCODE_UIF
:
4783 case TGSI_OPCODE_ENDIF
:
4784 case TGSI_OPCODE_ELSE
:
4785 /* Clear all channels written inside the block from the ACP, but
4786 * leaving those that were not touched.
4788 for (int r
= 0; r
< this->next_temp
; r
++) {
4789 for (int c
= 0; c
< 4; c
++) {
4790 if (!acp
[4 * r
+ c
])
4793 if (acp_level
[4 * r
+ c
] >= level
)
4794 acp
[4 * r
+ c
] = NULL
;
4797 if (inst
->op
== TGSI_OPCODE_ENDIF
)
4802 /* Continuing the block, clear any written channels from
4805 for (int d
= 0; d
< 2; d
++) {
4806 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
&& inst
->dst
[d
].reladdr
) {
4807 /* Any temporary might be written, so no copy propagation
4808 * across this instruction.
4810 memset(acp
, 0, sizeof(*acp
) * this->next_temp
* 4);
4811 } else if (inst
->dst
[d
].file
== PROGRAM_OUTPUT
&&
4812 inst
->dst
[d
].reladdr
) {
4813 /* Any output might be written, so no copy propagation
4814 * from outputs across this instruction.
4816 for (int r
= 0; r
< this->next_temp
; r
++) {
4817 for (int c
= 0; c
< 4; c
++) {
4818 if (!acp
[4 * r
+ c
])
4821 if (acp
[4 * r
+ c
]->src
[0].file
== PROGRAM_OUTPUT
)
4822 acp
[4 * r
+ c
] = NULL
;
4825 } else if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
||
4826 inst
->dst
[d
].file
== PROGRAM_OUTPUT
) {
4827 /* Clear where it's used as dst. */
4828 if (inst
->dst
[d
].file
== PROGRAM_TEMPORARY
) {
4829 for (int c
= 0; c
< 4; c
++) {
4830 if (inst
->dst
[d
].writemask
& (1 << c
))
4831 acp
[4 * inst
->dst
[d
].index
+ c
] = NULL
;
4835 /* Clear where it's used as src. */
4836 for (int r
= 0; r
< this->next_temp
; r
++) {
4837 for (int c
= 0; c
< 4; c
++) {
4838 if (!acp
[4 * r
+ c
])
4841 int src_chan
= GET_SWZ(acp
[4 * r
+ c
]->src
[0].swizzle
, c
);
4843 if (acp
[4 * r
+ c
]->src
[0].file
== inst
->dst
[d
].file
&&
4844 acp
[4 * r
+ c
]->src
[0].index
== inst
->dst
[d
].index
&&
4845 inst
->dst
[d
].writemask
& (1 << src_chan
)) {
4846 acp
[4 * r
+ c
] = NULL
;
4855 /* If this is a copy, add it to the ACP. */
4856 if (inst
->op
== TGSI_OPCODE_MOV
&&
4857 inst
->dst
[0].file
== PROGRAM_TEMPORARY
&&
4858 !(inst
->dst
[0].file
== inst
->src
[0].file
&&
4859 inst
->dst
[0].index
== inst
->src
[0].index
) &&
4860 !inst
->dst
[0].reladdr
&&
4861 !inst
->dst
[0].reladdr2
&&
4863 inst
->src
[0].file
!= PROGRAM_ARRAY
&&
4864 !inst
->src
[0].reladdr
&&
4865 !inst
->src
[0].reladdr2
&&
4866 !inst
->src
[0].negate
&&
4867 !inst
->src
[0].abs
) {
4868 for (int i
= 0; i
< 4; i
++) {
4869 if (inst
->dst
[0].writemask
& (1 << i
)) {
4870 acp
[4 * inst
->dst
[0].index
+ i
] = inst
;
4871 acp_level
[4 * inst
->dst
[0].index
+ i
] = level
;
4877 ralloc_free(acp_level
);
4882 * On a basic block basis, tracks available PROGRAM_TEMPORARY registers for dead
4885 * The glsl_to_tgsi_visitor lazily produces code assuming that this pass
4886 * will occur. As an example, a TXP production after copy propagation but
4889 * 0: MOV TEMP[1], INPUT[4].xyyy;
4890 * 1: MOV TEMP[1].w, INPUT[4].wwww;
4891 * 2: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4893 * and after this pass:
4895 * 0: TXP TEMP[2], INPUT[4].xyyw, texture[0], 2D;
4898 glsl_to_tgsi_visitor::eliminate_dead_code(void)
4900 glsl_to_tgsi_instruction
**writes
= rzalloc_array(mem_ctx
,
4901 glsl_to_tgsi_instruction
*,
4902 this->next_temp
* 4);
4903 int *write_level
= rzalloc_array(mem_ctx
, int, this->next_temp
* 4);
4907 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
4908 assert(inst
->dst
[0].file
!= PROGRAM_TEMPORARY
4909 || inst
->dst
[0].index
< this->next_temp
);
4912 case TGSI_OPCODE_BGNLOOP
:
4913 case TGSI_OPCODE_ENDLOOP
:
4914 case TGSI_OPCODE_CONT
:
4915 case TGSI_OPCODE_BRK
:
4916 /* End of a basic block, clear the write array entirely.
4918 * This keeps us from killing dead code when the writes are
4919 * on either side of a loop, even when the register isn't touched
4920 * inside the loop. However, glsl_to_tgsi_visitor doesn't seem to emit
4921 * dead code of this type, so it shouldn't make a difference as long as
4922 * the dead code elimination pass in the GLSL compiler does its job.
4924 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4927 case TGSI_OPCODE_ENDIF
:
4928 case TGSI_OPCODE_ELSE
:
4929 /* Promote the recorded level of all channels written inside the
4930 * preceding if or else block to the level above the if/else block.
4932 for (int r
= 0; r
< this->next_temp
; r
++) {
4933 for (int c
= 0; c
< 4; c
++) {
4934 if (!writes
[4 * r
+ c
])
4937 if (write_level
[4 * r
+ c
] == level
)
4938 write_level
[4 * r
+ c
] = level
-1;
4941 if(inst
->op
== TGSI_OPCODE_ENDIF
)
4945 case TGSI_OPCODE_IF
:
4946 case TGSI_OPCODE_UIF
:
4948 /* fallthrough to default case to mark the condition as read */
4950 /* Continuing the block, clear any channels from the write array that
4951 * are read by this instruction.
4953 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->src
); i
++) {
4954 if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
&& inst
->src
[i
].reladdr
){
4955 /* Any temporary might be read, so no dead code elimination
4956 * across this instruction.
4958 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4959 } else if (inst
->src
[i
].file
== PROGRAM_TEMPORARY
) {
4960 /* Clear where it's used as src. */
4961 int src_chans
= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 0);
4962 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 1);
4963 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 2);
4964 src_chans
|= 1 << GET_SWZ(inst
->src
[i
].swizzle
, 3);
4966 for (int c
= 0; c
< 4; c
++) {
4967 if (src_chans
& (1 << c
))
4968 writes
[4 * inst
->src
[i
].index
+ c
] = NULL
;
4972 for (unsigned i
= 0; i
< inst
->tex_offset_num_offset
; i
++) {
4973 if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
&& inst
->tex_offsets
[i
].reladdr
){
4974 /* Any temporary might be read, so no dead code elimination
4975 * across this instruction.
4977 memset(writes
, 0, sizeof(*writes
) * this->next_temp
* 4);
4978 } else if (inst
->tex_offsets
[i
].file
== PROGRAM_TEMPORARY
) {
4979 /* Clear where it's used as src. */
4980 int src_chans
= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 0);
4981 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 1);
4982 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 2);
4983 src_chans
|= 1 << GET_SWZ(inst
->tex_offsets
[i
].swizzle
, 3);
4985 for (int c
= 0; c
< 4; c
++) {
4986 if (src_chans
& (1 << c
))
4987 writes
[4 * inst
->tex_offsets
[i
].index
+ c
] = NULL
;
4994 /* If this instruction writes to a temporary, add it to the write array.
4995 * If there is already an instruction in the write array for one or more
4996 * of the channels, flag that channel write as dead.
4998 for (unsigned i
= 0; i
< ARRAY_SIZE(inst
->dst
); i
++) {
4999 if (inst
->dst
[i
].file
== PROGRAM_TEMPORARY
&&
5000 !inst
->dst
[i
].reladdr
) {
5001 for (int c
= 0; c
< 4; c
++) {
5002 if (inst
->dst
[i
].writemask
& (1 << c
)) {
5003 if (writes
[4 * inst
->dst
[i
].index
+ c
]) {
5004 if (write_level
[4 * inst
->dst
[i
].index
+ c
] < level
)
5007 writes
[4 * inst
->dst
[i
].index
+ c
]->dead_mask
|= (1 << c
);
5009 writes
[4 * inst
->dst
[i
].index
+ c
] = inst
;
5010 write_level
[4 * inst
->dst
[i
].index
+ c
] = level
;
5017 /* Anything still in the write array at this point is dead code. */
5018 for (int r
= 0; r
< this->next_temp
; r
++) {
5019 for (int c
= 0; c
< 4; c
++) {
5020 glsl_to_tgsi_instruction
*inst
= writes
[4 * r
+ c
];
5022 inst
->dead_mask
|= (1 << c
);
5026 /* Now actually remove the instructions that are completely dead and update
5027 * the writemask of other instructions with dead channels.
5029 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5030 if (!inst
->dead_mask
|| !inst
->dst
[0].writemask
)
5032 /* No amount of dead masks should remove memory stores */
5033 if (inst
->info
->is_store
)
5036 if ((inst
->dst
[0].writemask
& ~inst
->dead_mask
) == 0) {
5041 if (glsl_base_type_is_64bit(inst
->dst
[0].type
)) {
5042 if (inst
->dead_mask
== WRITEMASK_XY
||
5043 inst
->dead_mask
== WRITEMASK_ZW
)
5044 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5046 inst
->dst
[0].writemask
&= ~(inst
->dead_mask
);
5050 ralloc_free(write_level
);
5051 ralloc_free(writes
);
5056 /* merge DFRACEXP instructions into one. */
5058 glsl_to_tgsi_visitor::merge_two_dsts(void)
5060 foreach_in_list_safe(glsl_to_tgsi_instruction
, inst
, &this->instructions
) {
5061 glsl_to_tgsi_instruction
*inst2
;
5063 if (num_inst_dst_regs(inst
) != 2)
5066 if (inst
->dst
[0].file
!= PROGRAM_UNDEFINED
&&
5067 inst
->dst
[1].file
!= PROGRAM_UNDEFINED
)
5070 inst2
= (glsl_to_tgsi_instruction
*) inst
->next
;
5073 if (inst
->src
[0].file
== inst2
->src
[0].file
&&
5074 inst
->src
[0].index
== inst2
->src
[0].index
&&
5075 inst
->src
[0].type
== inst2
->src
[0].type
&&
5076 inst
->src
[0].swizzle
== inst2
->src
[0].swizzle
)
5078 inst2
= (glsl_to_tgsi_instruction
*) inst2
->next
;
5084 if (inst
->dst
[0].file
== PROGRAM_UNDEFINED
) {
5086 inst
->dst
[0] = inst2
->dst
[0];
5087 } else if (inst
->dst
[1].file
== PROGRAM_UNDEFINED
) {
5088 inst
->dst
[1] = inst2
->dst
[1];
5099 /* Merges temporary registers together where possible to reduce the number of
5100 * registers needed to run a program.
5102 * Produces optimal code only after copy propagation and dead code elimination
5105 glsl_to_tgsi_visitor::merge_registers(void)
5107 int *last_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5108 int *first_writes
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5109 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5111 int num_renames
= 0;
5113 /* Read the indices of the last read and first write to each temp register
5114 * into an array so that we don't have to traverse the instruction list as
5116 for (i
= 0; i
< this->next_temp
; i
++) {
5118 first_writes
[i
] = -1;
5120 get_last_temp_read_first_temp_write(last_reads
, first_writes
);
5122 /* Start looking for registers with non-overlapping usages that can be
5123 * merged together. */
5124 for (i
= 0; i
< this->next_temp
; i
++) {
5125 /* Don't touch unused registers. */
5126 if (last_reads
[i
] < 0 || first_writes
[i
] < 0) continue;
5128 for (j
= 0; j
< this->next_temp
; j
++) {
5129 /* Don't touch unused registers. */
5130 if (last_reads
[j
] < 0 || first_writes
[j
] < 0) continue;
5132 /* We can merge the two registers if the first write to j is after or
5133 * in the same instruction as the last read from i. Note that the
5134 * register at index i will always be used earlier or at the same time
5135 * as the register at index j. */
5136 if (first_writes
[i
] <= first_writes
[j
] &&
5137 last_reads
[i
] <= first_writes
[j
]) {
5138 renames
[num_renames
].old_reg
= j
;
5139 renames
[num_renames
].new_reg
= i
;
5142 /* Update the first_writes and last_reads arrays with the new
5143 * values for the merged register index, and mark the newly unused
5144 * register index as such. */
5145 assert(last_reads
[j
] >= last_reads
[i
]);
5146 last_reads
[i
] = last_reads
[j
];
5147 first_writes
[j
] = -1;
5153 rename_temp_registers(num_renames
, renames
);
5154 ralloc_free(renames
);
5155 ralloc_free(last_reads
);
5156 ralloc_free(first_writes
);
5159 /* Reassign indices to temporary registers by reusing unused indices created
5160 * by optimization passes. */
5162 glsl_to_tgsi_visitor::renumber_registers(void)
5166 int *first_reads
= rzalloc_array(mem_ctx
, int, this->next_temp
);
5167 struct rename_reg_pair
*renames
= rzalloc_array(mem_ctx
, struct rename_reg_pair
, this->next_temp
);
5168 int num_renames
= 0;
5169 for (i
= 0; i
< this->next_temp
; i
++) {
5170 first_reads
[i
] = -1;
5172 get_first_temp_read(first_reads
);
5174 for (i
= 0; i
< this->next_temp
; i
++) {
5175 if (first_reads
[i
] < 0) continue;
5176 if (i
!= new_index
) {
5177 renames
[num_renames
].old_reg
= i
;
5178 renames
[num_renames
].new_reg
= new_index
;
5184 rename_temp_registers(num_renames
, renames
);
5185 this->next_temp
= new_index
;
5186 ralloc_free(renames
);
5187 ralloc_free(first_reads
);
5190 /* ------------------------- TGSI conversion stuff -------------------------- */
5193 * Intermediate state used during shader translation.
5195 struct st_translate
{
5196 struct ureg_program
*ureg
;
5198 unsigned temps_size
;
5199 struct ureg_dst
*temps
;
5201 struct ureg_dst
*arrays
;
5202 unsigned num_temp_arrays
;
5203 struct ureg_src
*constants
;
5205 struct ureg_src
*immediates
;
5207 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
5208 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
5209 struct ureg_dst address
[3];
5210 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
5211 struct ureg_src buffers
[PIPE_MAX_SHADER_BUFFERS
];
5212 struct ureg_src images
[PIPE_MAX_SHADER_IMAGES
];
5213 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
5214 struct ureg_src shared_memory
;
5215 unsigned *array_sizes
;
5216 struct inout_decl
*input_decls
;
5217 unsigned num_input_decls
;
5218 struct inout_decl
*output_decls
;
5219 unsigned num_output_decls
;
5221 const GLuint
*inputMapping
;
5222 const GLuint
*outputMapping
;
5224 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
5227 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
5229 _mesa_sysval_to_semantic(unsigned sysval
)
5233 case SYSTEM_VALUE_VERTEX_ID
:
5234 return TGSI_SEMANTIC_VERTEXID
;
5235 case SYSTEM_VALUE_INSTANCE_ID
:
5236 return TGSI_SEMANTIC_INSTANCEID
;
5237 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
5238 return TGSI_SEMANTIC_VERTEXID_NOBASE
;
5239 case SYSTEM_VALUE_BASE_VERTEX
:
5240 return TGSI_SEMANTIC_BASEVERTEX
;
5241 case SYSTEM_VALUE_BASE_INSTANCE
:
5242 return TGSI_SEMANTIC_BASEINSTANCE
;
5243 case SYSTEM_VALUE_DRAW_ID
:
5244 return TGSI_SEMANTIC_DRAWID
;
5246 /* Geometry shader */
5247 case SYSTEM_VALUE_INVOCATION_ID
:
5248 return TGSI_SEMANTIC_INVOCATIONID
;
5250 /* Fragment shader */
5251 case SYSTEM_VALUE_FRAG_COORD
:
5252 return TGSI_SEMANTIC_POSITION
;
5253 case SYSTEM_VALUE_FRONT_FACE
:
5254 return TGSI_SEMANTIC_FACE
;
5255 case SYSTEM_VALUE_SAMPLE_ID
:
5256 return TGSI_SEMANTIC_SAMPLEID
;
5257 case SYSTEM_VALUE_SAMPLE_POS
:
5258 return TGSI_SEMANTIC_SAMPLEPOS
;
5259 case SYSTEM_VALUE_SAMPLE_MASK_IN
:
5260 return TGSI_SEMANTIC_SAMPLEMASK
;
5261 case SYSTEM_VALUE_HELPER_INVOCATION
:
5262 return TGSI_SEMANTIC_HELPER_INVOCATION
;
5264 /* Tessellation shader */
5265 case SYSTEM_VALUE_TESS_COORD
:
5266 return TGSI_SEMANTIC_TESSCOORD
;
5267 case SYSTEM_VALUE_VERTICES_IN
:
5268 return TGSI_SEMANTIC_VERTICESIN
;
5269 case SYSTEM_VALUE_PRIMITIVE_ID
:
5270 return TGSI_SEMANTIC_PRIMID
;
5271 case SYSTEM_VALUE_TESS_LEVEL_OUTER
:
5272 return TGSI_SEMANTIC_TESSOUTER
;
5273 case SYSTEM_VALUE_TESS_LEVEL_INNER
:
5274 return TGSI_SEMANTIC_TESSINNER
;
5276 /* Compute shader */
5277 case SYSTEM_VALUE_LOCAL_INVOCATION_ID
:
5278 return TGSI_SEMANTIC_THREAD_ID
;
5279 case SYSTEM_VALUE_WORK_GROUP_ID
:
5280 return TGSI_SEMANTIC_BLOCK_ID
;
5281 case SYSTEM_VALUE_NUM_WORK_GROUPS
:
5282 return TGSI_SEMANTIC_GRID_SIZE
;
5283 case SYSTEM_VALUE_LOCAL_GROUP_SIZE
:
5284 return TGSI_SEMANTIC_BLOCK_SIZE
;
5287 case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX
:
5288 case SYSTEM_VALUE_GLOBAL_INVOCATION_ID
:
5289 case SYSTEM_VALUE_VERTEX_CNT
:
5291 assert(!"Unexpected SYSTEM_VALUE_ enum");
5292 return TGSI_SEMANTIC_COUNT
;
5297 * Map a glsl_to_tgsi constant/immediate to a TGSI immediate.
5299 static struct ureg_src
5300 emit_immediate(struct st_translate
*t
,
5301 gl_constant_value values
[4],
5304 struct ureg_program
*ureg
= t
->ureg
;
5309 return ureg_DECL_immediate(ureg
, &values
[0].f
, size
);
5311 return ureg_DECL_immediate_f64(ureg
, (double *)&values
[0].f
, size
);
5313 return ureg_DECL_immediate_int(ureg
, &values
[0].i
, size
);
5314 case GL_UNSIGNED_INT
:
5316 return ureg_DECL_immediate_uint(ureg
, &values
[0].u
, size
);
5318 assert(!"should not get here - type must be float, int, uint, or bool");
5319 return ureg_src_undef();
5324 * Map a glsl_to_tgsi dst register to a TGSI ureg_dst register.
5326 static struct ureg_dst
5327 dst_register(struct st_translate
*t
, gl_register_file file
, unsigned index
,
5333 case PROGRAM_UNDEFINED
:
5334 return ureg_dst_undef();
5336 case PROGRAM_TEMPORARY
:
5337 /* Allocate space for temporaries on demand. */
5338 if (index
>= t
->temps_size
) {
5339 const int inc
= align(index
- t
->temps_size
+ 1, 4096);
5341 t
->temps
= (struct ureg_dst
*)
5343 (t
->temps_size
+ inc
) * sizeof(struct ureg_dst
));
5345 return ureg_dst_undef();
5347 memset(t
->temps
+ t
->temps_size
, 0, inc
* sizeof(struct ureg_dst
));
5348 t
->temps_size
+= inc
;
5351 if (ureg_dst_is_undef(t
->temps
[index
]))
5352 t
->temps
[index
] = ureg_DECL_local_temporary(t
->ureg
);
5354 return t
->temps
[index
];
5357 assert(array_id
&& array_id
<= t
->num_temp_arrays
);
5358 array
= array_id
- 1;
5360 if (ureg_dst_is_undef(t
->arrays
[array
]))
5361 t
->arrays
[array
] = ureg_DECL_array_temporary(
5362 t
->ureg
, t
->array_sizes
[array
], TRUE
);
5364 return ureg_dst_array_offset(t
->arrays
[array
], index
);
5366 case PROGRAM_OUTPUT
:
5368 if (t
->procType
== PIPE_SHADER_FRAGMENT
)
5369 assert(index
< 2 * FRAG_RESULT_MAX
);
5370 else if (t
->procType
== PIPE_SHADER_TESS_CTRL
||
5371 t
->procType
== PIPE_SHADER_TESS_EVAL
)
5372 assert(index
< VARYING_SLOT_TESS_MAX
);
5374 assert(index
< VARYING_SLOT_MAX
);
5376 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
5377 assert(t
->outputs
[t
->outputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5378 return t
->outputs
[t
->outputMapping
[index
]];
5381 struct inout_decl
*decl
= find_inout_array(t
->output_decls
, t
->num_output_decls
, array_id
);
5382 unsigned mesa_index
= decl
->mesa_index
;
5383 int slot
= t
->outputMapping
[mesa_index
];
5385 assert(slot
!= -1 && t
->outputs
[slot
].File
== TGSI_FILE_OUTPUT
);
5387 struct ureg_dst dst
= t
->outputs
[slot
];
5388 dst
.ArrayID
= array_id
;
5389 return ureg_dst_array_offset(dst
, index
- mesa_index
);
5392 case PROGRAM_ADDRESS
:
5393 return t
->address
[index
];
5396 assert(!"unknown dst register file");
5397 return ureg_dst_undef();
5402 * Map a glsl_to_tgsi src register to a TGSI ureg_src register.
5404 static struct ureg_src
5405 src_register(struct st_translate
*t
, const st_src_reg
*reg
)
5407 int index
= reg
->index
;
5408 int double_reg2
= reg
->double_reg2
? 1 : 0;
5411 case PROGRAM_UNDEFINED
:
5412 return ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5414 case PROGRAM_TEMPORARY
:
5416 return ureg_src(dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
));
5418 case PROGRAM_OUTPUT
: {
5419 struct ureg_dst dst
= dst_register(t
, reg
->file
, reg
->index
, reg
->array_id
);
5420 assert(dst
.WriteMask
!= 0);
5421 unsigned shift
= ffs(dst
.WriteMask
) - 1;
5422 return ureg_swizzle(ureg_src(dst
),
5426 MIN2(shift
+ 3, 3));
5429 case PROGRAM_UNIFORM
:
5430 assert(reg
->index
>= 0);
5431 return reg
->index
< t
->num_constants
?
5432 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5433 case PROGRAM_STATE_VAR
:
5434 case PROGRAM_CONSTANT
: /* ie, immediate */
5435 if (reg
->has_index2
)
5436 return ureg_src_register(TGSI_FILE_CONSTANT
, reg
->index
);
5438 return reg
->index
>= 0 && reg
->index
< t
->num_constants
?
5439 t
->constants
[reg
->index
] : ureg_imm4f(t
->ureg
, 0, 0, 0, 0);
5441 case PROGRAM_IMMEDIATE
:
5442 assert(reg
->index
>= 0 && reg
->index
< t
->num_immediates
);
5443 return t
->immediates
[reg
->index
];
5446 /* GLSL inputs are 64-bit containers, so we have to
5447 * map back to the original index and add the offset after
5449 index
-= double_reg2
;
5450 if (!reg
->array_id
) {
5451 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
5452 assert(t
->inputs
[t
->inputMapping
[index
]].File
!= TGSI_FILE_NULL
);
5453 return t
->inputs
[t
->inputMapping
[index
] + double_reg2
];
5456 struct inout_decl
*decl
= find_inout_array(t
->input_decls
, t
->num_input_decls
, reg
->array_id
);
5457 unsigned mesa_index
= decl
->mesa_index
;
5458 int slot
= t
->inputMapping
[mesa_index
];
5460 assert(slot
!= -1 && t
->inputs
[slot
].File
== TGSI_FILE_INPUT
);
5462 struct ureg_src src
= t
->inputs
[slot
];
5463 src
.ArrayID
= reg
->array_id
;
5464 return ureg_src_array_offset(src
, index
+ double_reg2
- mesa_index
);
5467 case PROGRAM_ADDRESS
:
5468 return ureg_src(t
->address
[reg
->index
]);
5470 case PROGRAM_SYSTEM_VALUE
:
5471 assert(reg
->index
< (int) ARRAY_SIZE(t
->systemValues
));
5472 return t
->systemValues
[reg
->index
];
5475 assert(!"unknown src register file");
5476 return ureg_src_undef();
5481 * Create a TGSI ureg_dst register from an st_dst_reg.
5483 static struct ureg_dst
5484 translate_dst(struct st_translate
*t
,
5485 const st_dst_reg
*dst_reg
,
5488 struct ureg_dst dst
= dst_register(t
, dst_reg
->file
, dst_reg
->index
,
5491 if (dst
.File
== TGSI_FILE_NULL
)
5494 dst
= ureg_writemask(dst
, dst_reg
->writemask
);
5497 dst
= ureg_saturate(dst
);
5499 if (dst_reg
->reladdr
!= NULL
) {
5500 assert(dst_reg
->file
!= PROGRAM_TEMPORARY
);
5501 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
5504 if (dst_reg
->has_index2
) {
5505 if (dst_reg
->reladdr2
)
5506 dst
= ureg_dst_dimension_indirect(dst
, ureg_src(t
->address
[1]),
5509 dst
= ureg_dst_dimension(dst
, dst_reg
->index2D
);
5516 * Create a TGSI ureg_src register from an st_src_reg.
5518 static struct ureg_src
5519 translate_src(struct st_translate
*t
, const st_src_reg
*src_reg
)
5521 struct ureg_src src
= src_register(t
, src_reg
);
5523 if (src_reg
->has_index2
) {
5524 /* 2D indexes occur with geometry shader inputs (attrib, vertex)
5525 * and UBO constant buffers (buffer, position).
5527 if (src_reg
->reladdr2
)
5528 src
= ureg_src_dimension_indirect(src
, ureg_src(t
->address
[1]),
5531 src
= ureg_src_dimension(src
, src_reg
->index2D
);
5534 src
= ureg_swizzle(src
,
5535 GET_SWZ(src_reg
->swizzle
, 0) & 0x3,
5536 GET_SWZ(src_reg
->swizzle
, 1) & 0x3,
5537 GET_SWZ(src_reg
->swizzle
, 2) & 0x3,
5538 GET_SWZ(src_reg
->swizzle
, 3) & 0x3);
5541 src
= ureg_abs(src
);
5543 if ((src_reg
->negate
& 0xf) == NEGATE_XYZW
)
5544 src
= ureg_negate(src
);
5546 if (src_reg
->reladdr
!= NULL
) {
5547 assert(src_reg
->file
!= PROGRAM_TEMPORARY
);
5548 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
5554 static struct tgsi_texture_offset
5555 translate_tex_offset(struct st_translate
*t
,
5556 const st_src_reg
*in_offset
)
5558 struct tgsi_texture_offset offset
;
5559 struct ureg_src src
= translate_src(t
, in_offset
);
5561 offset
.File
= src
.File
;
5562 offset
.Index
= src
.Index
;
5563 offset
.SwizzleX
= src
.SwizzleX
;
5564 offset
.SwizzleY
= src
.SwizzleY
;
5565 offset
.SwizzleZ
= src
.SwizzleZ
;
5568 assert(!src
.Indirect
);
5569 assert(!src
.DimIndirect
);
5570 assert(!src
.Dimension
);
5571 assert(!src
.Absolute
); /* those shouldn't be used with integers anyway */
5572 assert(!src
.Negate
);
5578 compile_tgsi_instruction(struct st_translate
*t
,
5579 const glsl_to_tgsi_instruction
*inst
)
5581 struct ureg_program
*ureg
= t
->ureg
;
5583 struct ureg_dst dst
[2];
5584 struct ureg_src src
[4];
5585 struct tgsi_texture_offset texoffsets
[MAX_GLSL_TEXTURE_OFFSET
];
5589 unsigned tex_target
= 0;
5591 num_dst
= num_inst_dst_regs(inst
);
5592 num_src
= num_inst_src_regs(inst
);
5594 for (i
= 0; i
< num_dst
; i
++)
5595 dst
[i
] = translate_dst(t
,
5599 for (i
= 0; i
< num_src
; i
++)
5600 src
[i
] = translate_src(t
, &inst
->src
[i
]);
5603 case TGSI_OPCODE_BGNLOOP
:
5604 case TGSI_OPCODE_ELSE
:
5605 case TGSI_OPCODE_ENDLOOP
:
5606 case TGSI_OPCODE_IF
:
5607 case TGSI_OPCODE_UIF
:
5608 assert(num_dst
== 0);
5609 ureg_insn(ureg
, inst
->op
, NULL
, 0, src
, num_src
);
5612 case TGSI_OPCODE_TEX
:
5613 case TGSI_OPCODE_TXB
:
5614 case TGSI_OPCODE_TXD
:
5615 case TGSI_OPCODE_TXL
:
5616 case TGSI_OPCODE_TXP
:
5617 case TGSI_OPCODE_TXQ
:
5618 case TGSI_OPCODE_TXQS
:
5619 case TGSI_OPCODE_TXF
:
5620 case TGSI_OPCODE_TEX2
:
5621 case TGSI_OPCODE_TXB2
:
5622 case TGSI_OPCODE_TXL2
:
5623 case TGSI_OPCODE_TG4
:
5624 case TGSI_OPCODE_LODQ
:
5625 src
[num_src
] = t
->samplers
[inst
->resource
.index
];
5626 assert(src
[num_src
].File
!= TGSI_FILE_NULL
);
5627 if (inst
->resource
.reladdr
)
5629 ureg_src_indirect(src
[num_src
], ureg_src(t
->address
[2]));
5631 for (i
= 0; i
< (int)inst
->tex_offset_num_offset
; i
++) {
5632 texoffsets
[i
] = translate_tex_offset(t
, &inst
->tex_offsets
[i
]);
5634 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5640 texoffsets
, inst
->tex_offset_num_offset
,
5644 case TGSI_OPCODE_RESQ
:
5645 case TGSI_OPCODE_LOAD
:
5646 case TGSI_OPCODE_ATOMUADD
:
5647 case TGSI_OPCODE_ATOMXCHG
:
5648 case TGSI_OPCODE_ATOMCAS
:
5649 case TGSI_OPCODE_ATOMAND
:
5650 case TGSI_OPCODE_ATOMOR
:
5651 case TGSI_OPCODE_ATOMXOR
:
5652 case TGSI_OPCODE_ATOMUMIN
:
5653 case TGSI_OPCODE_ATOMUMAX
:
5654 case TGSI_OPCODE_ATOMIMIN
:
5655 case TGSI_OPCODE_ATOMIMAX
:
5656 for (i
= num_src
- 1; i
>= 0; i
--)
5657 src
[i
+ 1] = src
[i
];
5659 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5660 src
[0] = t
->shared_memory
;
5661 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5662 src
[0] = t
->buffers
[inst
->resource
.index
];
5664 src
[0] = t
->images
[inst
->resource
.index
];
5665 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5667 if (inst
->resource
.reladdr
)
5668 src
[0] = ureg_src_indirect(src
[0], ureg_src(t
->address
[2]));
5669 assert(src
[0].File
!= TGSI_FILE_NULL
);
5670 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5671 inst
->buffer_access
,
5672 tex_target
, inst
->image_format
);
5675 case TGSI_OPCODE_STORE
:
5676 if (inst
->resource
.file
== PROGRAM_MEMORY
) {
5677 dst
[0] = ureg_dst(t
->shared_memory
);
5678 } else if (inst
->resource
.file
== PROGRAM_BUFFER
) {
5679 dst
[0] = ureg_dst(t
->buffers
[inst
->resource
.index
]);
5681 dst
[0] = ureg_dst(t
->images
[inst
->resource
.index
]);
5682 tex_target
= st_translate_texture_target(inst
->tex_target
, inst
->tex_shadow
);
5684 dst
[0] = ureg_writemask(dst
[0], inst
->dst
[0].writemask
);
5685 if (inst
->resource
.reladdr
)
5686 dst
[0] = ureg_dst_indirect(dst
[0], ureg_src(t
->address
[2]));
5687 assert(dst
[0].File
!= TGSI_FILE_NULL
);
5688 ureg_memory_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
,
5689 inst
->buffer_access
,
5690 tex_target
, inst
->image_format
);
5693 case TGSI_OPCODE_SCS
:
5694 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
5695 ureg_insn(ureg
, inst
->op
, dst
, num_dst
, src
, num_src
);
5708 * Emit the TGSI instructions for inverting and adjusting WPOS.
5709 * This code is unavoidable because it also depends on whether
5710 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
5713 emit_wpos_adjustment(struct gl_context
*ctx
,
5714 struct st_translate
*t
,
5715 int wpos_transform_const
,
5717 GLfloat adjX
, GLfloat adjY
[2])
5719 struct ureg_program
*ureg
= t
->ureg
;
5721 assert(wpos_transform_const
>= 0);
5723 /* Fragment program uses fragment position input.
5724 * Need to replace instances of INPUT[WPOS] with temp T
5725 * where T = INPUT[WPOS] is inverted by Y.
5727 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wpos_transform_const
);
5728 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
5729 struct ureg_src
*wpos
=
5730 ctx
->Const
.GLSLFragCoordIsSysVal
?
5731 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
5732 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
5733 struct ureg_src wpos_input
= *wpos
;
5735 /* First, apply the coordinate shift: */
5736 if (adjX
|| adjY
[0] || adjY
[1]) {
5737 if (adjY
[0] != adjY
[1]) {
5738 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
5739 * depending on whether inversion is actually going to be applied
5740 * or not, which is determined by testing against the inversion
5741 * state variable used below, which will be either +1 or -1.
5743 struct ureg_dst adj_temp
= ureg_DECL_local_temporary(ureg
);
5745 ureg_CMP(ureg
, adj_temp
,
5746 ureg_scalar(wpostrans
, invert
? 2 : 0),
5747 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
5748 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
5749 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
5751 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
5752 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
5754 wpos_input
= ureg_src(wpos_temp
);
5756 /* MOV wpos_temp, input[wpos]
5758 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
5761 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
5762 * inversion/identity, or the other way around if we're drawing to an FBO.
5765 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
5768 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5770 ureg_scalar(wpostrans
, 0),
5771 ureg_scalar(wpostrans
, 1));
5773 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
5776 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
5778 ureg_scalar(wpostrans
, 2),
5779 ureg_scalar(wpostrans
, 3));
5782 /* Use wpos_temp as position input from here on:
5784 *wpos
= ureg_src(wpos_temp
);
5789 * Emit fragment position/ooordinate code.
5792 emit_wpos(struct st_context
*st
,
5793 struct st_translate
*t
,
5794 const struct gl_program
*program
,
5795 struct ureg_program
*ureg
,
5796 int wpos_transform_const
)
5798 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
5799 GLfloat adjX
= 0.0f
;
5800 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
5801 boolean invert
= FALSE
;
5803 /* Query the pixel center conventions supported by the pipe driver and set
5804 * adjX, adjY to help out if it cannot handle the requested one internally.
5806 * The bias of the y-coordinate depends on whether y-inversion takes place
5807 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
5808 * drawing to an FBO (causes additional inversion), and whether the pipe
5809 * driver origin and the requested origin differ (the latter condition is
5810 * stored in the 'invert' variable).
5812 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
5814 * center shift only:
5819 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
5820 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
5821 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
5822 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
5824 * inversion and center shift:
5825 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
5826 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
5827 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
5828 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
5830 if (program
->OriginUpperLeft
) {
5831 /* Fragment shader wants origin in upper-left */
5832 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
5833 /* the driver supports upper-left origin */
5835 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
5836 /* the driver supports lower-left origin, need to invert Y */
5837 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5838 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5845 /* Fragment shader wants origin in lower-left */
5846 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
5847 /* the driver supports lower-left origin */
5848 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
5849 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
5850 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
5851 /* the driver supports upper-left origin, need to invert Y */
5857 if (program
->PixelCenterInteger
) {
5858 /* Fragment shader wants pixel center integer */
5859 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5860 /* the driver supports pixel center integer */
5862 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5863 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5865 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5866 /* the driver supports pixel center half integer, need to bias X,Y */
5875 /* Fragment shader wants pixel center half integer */
5876 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
5877 /* the driver supports pixel center half integer */
5879 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
5880 /* the driver supports pixel center integer, need to bias X,Y */
5881 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
5882 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
5883 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
5889 /* we invert after adjustment so that we avoid the MOV to temporary,
5890 * and reuse the adjustment ADD instead */
5891 emit_wpos_adjustment(st
->ctx
, t
, wpos_transform_const
, invert
, adjX
, adjY
);
5895 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
5896 * TGSI uses +1 for front, -1 for back.
5897 * This function converts the TGSI value to the GL value. Simply clamping/
5898 * saturating the value to [0,1] does the job.
5901 emit_face_var(struct gl_context
*ctx
, struct st_translate
*t
)
5903 struct ureg_program
*ureg
= t
->ureg
;
5904 struct ureg_dst face_temp
= ureg_DECL_temporary(ureg
);
5905 struct ureg_src face_input
= t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]];
5907 if (ctx
->Const
.NativeIntegers
) {
5908 ureg_FSGE(ureg
, face_temp
, face_input
, ureg_imm1f(ureg
, 0));
5911 /* MOV_SAT face_temp, input[face] */
5912 ureg_MOV(ureg
, ureg_saturate(face_temp
), face_input
);
5915 /* Use face_temp as face input from here on: */
5916 t
->inputs
[t
->inputMapping
[VARYING_SLOT_FACE
]] = ureg_src(face_temp
);
5920 emit_compute_block_size(const struct gl_program
*prog
,
5921 struct ureg_program
*ureg
) {
5922 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
,
5923 prog
->info
.cs
.local_size
[0]);
5924 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
,
5925 prog
->info
.cs
.local_size
[1]);
5926 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
,
5927 prog
->info
.cs
.local_size
[2]);
5930 struct sort_inout_decls
{
5931 bool operator()(const struct inout_decl
&a
, const struct inout_decl
&b
) const {
5932 return mapping
[a
.mesa_index
] < mapping
[b
.mesa_index
];
5935 const GLuint
*mapping
;
5938 /* Sort the given array of decls by the corresponding slot (TGSI file index).
5940 * This is for the benefit of older drivers which are broken when the
5941 * declarations aren't sorted in this way.
5944 sort_inout_decls_by_slot(struct inout_decl
*decls
,
5946 const GLuint mapping
[])
5948 sort_inout_decls sorter
;
5949 sorter
.mapping
= mapping
;
5950 std::sort(decls
, decls
+ count
, sorter
);
5954 st_translate_interp(enum glsl_interp_mode glsl_qual
, GLuint varying
)
5956 switch (glsl_qual
) {
5957 case INTERP_MODE_NONE
:
5958 if (varying
== VARYING_SLOT_COL0
|| varying
== VARYING_SLOT_COL1
)
5959 return TGSI_INTERPOLATE_COLOR
;
5960 return TGSI_INTERPOLATE_PERSPECTIVE
;
5961 case INTERP_MODE_SMOOTH
:
5962 return TGSI_INTERPOLATE_PERSPECTIVE
;
5963 case INTERP_MODE_FLAT
:
5964 return TGSI_INTERPOLATE_CONSTANT
;
5965 case INTERP_MODE_NOPERSPECTIVE
:
5966 return TGSI_INTERPOLATE_LINEAR
;
5968 assert(0 && "unexpected interp mode in st_translate_interp()");
5969 return TGSI_INTERPOLATE_PERSPECTIVE
;
5974 * Translate intermediate IR (glsl_to_tgsi_instruction) to TGSI format.
5975 * \param program the program to translate
5976 * \param numInputs number of input registers used
5977 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
5979 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
5980 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
5982 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
5983 * \param numOutputs number of output registers used
5984 * \param outputMapping maps Mesa fragment program outputs to TGSI
5986 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
5987 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
5990 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
5992 extern "C" enum pipe_error
5993 st_translate_program(
5994 struct gl_context
*ctx
,
5996 struct ureg_program
*ureg
,
5997 glsl_to_tgsi_visitor
*program
,
5998 const struct gl_program
*proginfo
,
6000 const GLuint inputMapping
[],
6001 const GLuint inputSlotToAttr
[],
6002 const ubyte inputSemanticName
[],
6003 const ubyte inputSemanticIndex
[],
6004 const GLuint interpMode
[],
6006 const GLuint outputMapping
[],
6007 const GLuint outputSlotToAttr
[],
6008 const ubyte outputSemanticName
[],
6009 const ubyte outputSemanticIndex
[])
6011 struct st_translate
*t
;
6013 struct gl_program_constants
*frag_const
=
6014 &ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
];
6015 enum pipe_error ret
= PIPE_OK
;
6017 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
6018 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
6020 t
= CALLOC_STRUCT(st_translate
);
6022 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6026 t
->procType
= procType
;
6027 t
->inputMapping
= inputMapping
;
6028 t
->outputMapping
= outputMapping
;
6030 t
->num_temp_arrays
= program
->next_array
;
6031 if (t
->num_temp_arrays
)
6032 t
->arrays
= (struct ureg_dst
*)
6033 calloc(t
->num_temp_arrays
, sizeof(t
->arrays
[0]));
6036 * Declare input attributes.
6039 case PIPE_SHADER_FRAGMENT
:
6040 case PIPE_SHADER_GEOMETRY
:
6041 case PIPE_SHADER_TESS_EVAL
:
6042 case PIPE_SHADER_TESS_CTRL
:
6043 sort_inout_decls_by_slot(program
->inputs
, program
->num_inputs
, inputMapping
);
6045 for (i
= 0; i
< program
->num_inputs
; ++i
) {
6046 struct inout_decl
*decl
= &program
->inputs
[i
];
6047 unsigned slot
= inputMapping
[decl
->mesa_index
];
6048 struct ureg_src src
;
6049 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6051 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6052 if (tgsi_usage_mask
== 1)
6053 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6054 else if (tgsi_usage_mask
== 2)
6055 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6057 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6060 unsigned interp_mode
= 0;
6061 unsigned interp_location
= 0;
6062 if (procType
== PIPE_SHADER_FRAGMENT
) {
6064 interp_mode
= interpMode
[slot
] != TGSI_INTERPOLATE_COUNT
?
6066 st_translate_interp(decl
->interp
, inputSlotToAttr
[slot
]);
6068 interp_location
= decl
->interp_loc
;
6071 src
= ureg_DECL_fs_input_cyl_centroid_layout(ureg
,
6072 inputSemanticName
[slot
], inputSemanticIndex
[slot
],
6073 interp_mode
, 0, interp_location
, slot
, tgsi_usage_mask
,
6074 decl
->array_id
, decl
->size
);
6076 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6077 if (t
->inputs
[slot
+ j
].File
!= TGSI_FILE_INPUT
) {
6078 /* The ArrayID is set up in dst_register */
6079 t
->inputs
[slot
+ j
] = src
;
6080 t
->inputs
[slot
+ j
].ArrayID
= 0;
6081 t
->inputs
[slot
+ j
].Index
+= j
;
6086 case PIPE_SHADER_VERTEX
:
6087 for (i
= 0; i
< numInputs
; i
++) {
6088 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
6091 case PIPE_SHADER_COMPUTE
:
6098 * Declare output attributes.
6101 case PIPE_SHADER_FRAGMENT
:
6102 case PIPE_SHADER_COMPUTE
:
6104 case PIPE_SHADER_GEOMETRY
:
6105 case PIPE_SHADER_TESS_EVAL
:
6106 case PIPE_SHADER_TESS_CTRL
:
6107 case PIPE_SHADER_VERTEX
:
6108 sort_inout_decls_by_slot(program
->outputs
, program
->num_outputs
, outputMapping
);
6110 for (i
= 0; i
< program
->num_outputs
; ++i
) {
6111 struct inout_decl
*decl
= &program
->outputs
[i
];
6112 unsigned slot
= outputMapping
[decl
->mesa_index
];
6113 struct ureg_dst dst
;
6114 ubyte tgsi_usage_mask
= decl
->usage_mask
;
6116 if (glsl_base_type_is_64bit(decl
->base_type
)) {
6117 if (tgsi_usage_mask
== 1)
6118 tgsi_usage_mask
= TGSI_WRITEMASK_XY
;
6119 else if (tgsi_usage_mask
== 2)
6120 tgsi_usage_mask
= TGSI_WRITEMASK_ZW
;
6122 tgsi_usage_mask
= TGSI_WRITEMASK_XYZW
;
6125 dst
= ureg_DECL_output_layout(ureg
,
6126 outputSemanticName
[slot
], outputSemanticIndex
[slot
],
6127 decl
->gs_out_streams
,
6128 slot
, tgsi_usage_mask
, decl
->array_id
, decl
->size
);
6130 for (unsigned j
= 0; j
< decl
->size
; ++j
) {
6131 if (t
->outputs
[slot
+ j
].File
!= TGSI_FILE_OUTPUT
) {
6132 /* The ArrayID is set up in dst_register */
6133 t
->outputs
[slot
+ j
] = dst
;
6134 t
->outputs
[slot
+ j
].ArrayID
= 0;
6135 t
->outputs
[slot
+ j
].Index
+= j
;
6144 if (procType
== PIPE_SHADER_FRAGMENT
) {
6145 if (program
->shader
->info
.EarlyFragmentTests
)
6146 ureg_property(ureg
, TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
, 1);
6148 if (proginfo
->info
.inputs_read
& VARYING_BIT_POS
) {
6149 /* Must do this after setting up t->inputs. */
6150 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6151 program
->wpos_transform_const
);
6154 if (proginfo
->info
.inputs_read
& VARYING_BIT_FACE
)
6155 emit_face_var(ctx
, t
);
6157 for (i
= 0; i
< numOutputs
; i
++) {
6158 switch (outputSemanticName
[i
]) {
6159 case TGSI_SEMANTIC_POSITION
:
6160 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6161 TGSI_SEMANTIC_POSITION
, /* Z/Depth */
6162 outputSemanticIndex
[i
]);
6163 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Z
);
6165 case TGSI_SEMANTIC_STENCIL
:
6166 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6167 TGSI_SEMANTIC_STENCIL
, /* Stencil */
6168 outputSemanticIndex
[i
]);
6169 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_Y
);
6171 case TGSI_SEMANTIC_COLOR
:
6172 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6173 TGSI_SEMANTIC_COLOR
,
6174 outputSemanticIndex
[i
]);
6176 case TGSI_SEMANTIC_SAMPLEMASK
:
6177 t
->outputs
[i
] = ureg_DECL_output(ureg
,
6178 TGSI_SEMANTIC_SAMPLEMASK
,
6179 outputSemanticIndex
[i
]);
6180 /* TODO: If we ever support more than 32 samples, this will have
6181 * to become an array.
6183 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6186 assert(!"fragment shader outputs must be POSITION/STENCIL/COLOR");
6187 ret
= PIPE_ERROR_BAD_INPUT
;
6192 else if (procType
== PIPE_SHADER_VERTEX
) {
6193 for (i
= 0; i
< numOutputs
; i
++) {
6194 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
6195 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
6197 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
6198 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
6199 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
6204 if (procType
== PIPE_SHADER_COMPUTE
) {
6205 emit_compute_block_size(proginfo
, ureg
);
6208 /* Declare address register.
6210 if (program
->num_address_regs
> 0) {
6211 assert(program
->num_address_regs
<= 3);
6212 for (int i
= 0; i
< program
->num_address_regs
; i
++)
6213 t
->address
[i
] = ureg_DECL_address(ureg
);
6216 /* Declare misc input registers
6219 GLbitfield sysInputs
= proginfo
->info
.system_values_read
;
6221 for (i
= 0; sysInputs
; i
++) {
6222 if (sysInputs
& (1 << i
)) {
6223 unsigned semName
= _mesa_sysval_to_semantic(i
);
6225 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
6227 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
6228 semName
== TGSI_SEMANTIC_VERTEXID
) {
6229 /* From Gallium perspective, these system values are always
6230 * integer, and require native integer support. However, if
6231 * native integer is supported on the vertex stage but not the
6232 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
6233 * assumes these system values are floats. To resolve the
6234 * inconsistency, we insert a U2F.
6236 struct st_context
*st
= st_context(ctx
);
6237 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
6238 assert(procType
== PIPE_SHADER_VERTEX
);
6239 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
6241 if (!ctx
->Const
.NativeIntegers
) {
6242 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
6243 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
6244 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
6248 if (procType
== PIPE_SHADER_FRAGMENT
&&
6249 semName
== TGSI_SEMANTIC_POSITION
)
6250 emit_wpos(st_context(ctx
), t
, proginfo
, ureg
,
6251 program
->wpos_transform_const
);
6253 sysInputs
&= ~(1 << i
);
6258 t
->array_sizes
= program
->array_sizes
;
6259 t
->input_decls
= program
->inputs
;
6260 t
->num_input_decls
= program
->num_inputs
;
6261 t
->output_decls
= program
->outputs
;
6262 t
->num_output_decls
= program
->num_outputs
;
6264 /* Emit constants and uniforms. TGSI uses a single index space for these,
6265 * so we put all the translated regs in t->constants.
6267 if (proginfo
->Parameters
) {
6268 t
->constants
= (struct ureg_src
*)
6269 calloc(proginfo
->Parameters
->NumParameters
, sizeof(t
->constants
[0]));
6270 if (t
->constants
== NULL
) {
6271 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6274 t
->num_constants
= proginfo
->Parameters
->NumParameters
;
6276 for (i
= 0; i
< proginfo
->Parameters
->NumParameters
; i
++) {
6277 switch (proginfo
->Parameters
->Parameters
[i
].Type
) {
6278 case PROGRAM_STATE_VAR
:
6279 case PROGRAM_UNIFORM
:
6280 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6283 /* Emit immediates for PROGRAM_CONSTANT only when there's no indirect
6284 * addressing of the const buffer.
6285 * FIXME: Be smarter and recognize param arrays:
6286 * indirect addressing is only valid within the referenced
6289 case PROGRAM_CONSTANT
:
6290 if (program
->indirect_addr_consts
)
6291 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
6293 t
->constants
[i
] = emit_immediate(t
,
6294 proginfo
->Parameters
->ParameterValues
[i
],
6295 proginfo
->Parameters
->Parameters
[i
].DataType
,
6304 for (i
= 0; i
< proginfo
->info
.num_ubos
; i
++) {
6305 unsigned size
= proginfo
->sh
.UniformBlocks
[i
]->UniformBufferSize
;
6306 unsigned num_const_vecs
= (size
+ 15) / 16;
6307 unsigned first
, last
;
6308 assert(num_const_vecs
> 0);
6310 last
= num_const_vecs
> 0 ? num_const_vecs
- 1 : 0;
6311 ureg_DECL_constant2D(t
->ureg
, first
, last
, i
+ 1);
6314 /* Emit immediate values.
6316 t
->immediates
= (struct ureg_src
*)
6317 calloc(program
->num_immediates
, sizeof(struct ureg_src
));
6318 if (t
->immediates
== NULL
) {
6319 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
6322 t
->num_immediates
= program
->num_immediates
;
6325 foreach_in_list(immediate_storage
, imm
, &program
->immediates
) {
6326 assert(i
< program
->num_immediates
);
6327 t
->immediates
[i
++] = emit_immediate(t
, imm
->values
, imm
->type
, imm
->size32
);
6329 assert(i
== program
->num_immediates
);
6331 /* texture samplers */
6332 for (i
= 0; i
< frag_const
->MaxTextureImageUnits
; i
++) {
6333 if (program
->samplers_used
& (1u << i
)) {
6336 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
6338 switch (program
->sampler_types
[i
]) {
6340 type
= TGSI_RETURN_TYPE_SINT
;
6342 case GLSL_TYPE_UINT
:
6343 type
= TGSI_RETURN_TYPE_UINT
;
6345 case GLSL_TYPE_FLOAT
:
6346 type
= TGSI_RETURN_TYPE_FLOAT
;
6349 unreachable("not reached");
6352 ureg_DECL_sampler_view( ureg
, i
, program
->sampler_targets
[i
],
6353 type
, type
, type
, type
);
6357 for (i
= 0; i
< frag_const
->MaxAtomicBuffers
; i
++) {
6358 if (program
->buffers_used
& (1 << i
)) {
6359 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, true);
6363 for (; i
< frag_const
->MaxAtomicBuffers
+ frag_const
->MaxShaderStorageBlocks
;
6365 if (program
->buffers_used
& (1 << i
)) {
6366 t
->buffers
[i
] = ureg_DECL_buffer(ureg
, i
, false);
6370 if (program
->use_shared_memory
)
6371 t
->shared_memory
= ureg_DECL_memory(ureg
, TGSI_MEMORY_TYPE_SHARED
);
6373 for (i
= 0; i
< program
->shader
->NumImages
; i
++) {
6374 if (program
->images_used
& (1 << i
)) {
6375 t
->images
[i
] = ureg_DECL_image(ureg
, i
,
6376 program
->image_targets
[i
],
6377 program
->image_formats
[i
],
6382 /* Emit each instruction in turn:
6384 foreach_in_list(glsl_to_tgsi_instruction
, inst
, &program
->instructions
)
6385 compile_tgsi_instruction(t
, inst
);
6387 /* Set the next shader stage hint for VS and TES. */
6389 case PIPE_SHADER_VERTEX
:
6390 case PIPE_SHADER_TESS_EVAL
:
6391 if (program
->shader_program
->SeparateShader
)
6394 for (i
= program
->shader
->Stage
+1; i
<= MESA_SHADER_FRAGMENT
; i
++) {
6395 if (program
->shader_program
->_LinkedShaders
[i
]) {
6399 case MESA_SHADER_TESS_CTRL
:
6400 next
= PIPE_SHADER_TESS_CTRL
;
6402 case MESA_SHADER_TESS_EVAL
:
6403 next
= PIPE_SHADER_TESS_EVAL
;
6405 case MESA_SHADER_GEOMETRY
:
6406 next
= PIPE_SHADER_GEOMETRY
;
6408 case MESA_SHADER_FRAGMENT
:
6409 next
= PIPE_SHADER_FRAGMENT
;
6416 ureg_set_next_shader_processor(ureg
, next
);
6428 t
->num_constants
= 0;
6429 free(t
->immediates
);
6430 t
->num_immediates
= 0;
6436 /* ----------------------------- End TGSI code ------------------------------ */
6440 * Convert a shader's GLSL IR into a Mesa gl_program, although without
6441 * generating Mesa IR.
6443 static struct gl_program
*
6444 get_mesa_program_tgsi(struct gl_context
*ctx
,
6445 struct gl_shader_program
*shader_program
,
6446 struct gl_linked_shader
*shader
)
6448 glsl_to_tgsi_visitor
* v
;
6449 struct gl_program
*prog
;
6450 struct gl_shader_compiler_options
*options
=
6451 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
6452 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6453 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6455 validate_ir_tree(shader
->ir
);
6457 prog
= shader
->Program
;
6459 prog
->Parameters
= _mesa_new_parameter_list();
6460 v
= new glsl_to_tgsi_visitor();
6463 v
->shader_program
= shader_program
;
6465 v
->options
= options
;
6466 v
->glsl_version
= ctx
->Const
.GLSLVersion
;
6467 v
->native_integers
= ctx
->Const
.NativeIntegers
;
6469 v
->have_sqrt
= pscreen
->get_shader_param(pscreen
, ptarget
,
6470 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
);
6471 v
->have_fma
= pscreen
->get_shader_param(pscreen
, ptarget
,
6472 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
);
6474 _mesa_generate_parameters_list_for_uniforms(shader_program
, shader
,
6477 /* Remove reads from output registers. */
6478 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_CAN_READ_OUTPUTS
))
6479 lower_output_reads(shader
->Stage
, shader
->ir
);
6481 /* Emit intermediate IR for main(). */
6482 visit_exec_list(shader
->ir
, v
);
6485 /* Print out some information (for debugging purposes) used by the
6486 * optimization passes. */
6489 int *first_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6490 int *first_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6491 int *last_writes
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6492 int *last_reads
= rzalloc_array(v
->mem_ctx
, int, v
->next_temp
);
6494 for (i
= 0; i
< v
->next_temp
; i
++) {
6495 first_writes
[i
] = -1;
6496 first_reads
[i
] = -1;
6497 last_writes
[i
] = -1;
6500 v
->get_first_temp_read(first_reads
);
6501 v
->get_last_temp_read_first_temp_write(last_reads
, first_writes
);
6502 v
->get_last_temp_write(last_writes
);
6503 for (i
= 0; i
< v
->next_temp
; i
++)
6504 printf("Temp %d: FR=%3d FW=%3d LR=%3d LW=%3d\n", i
, first_reads
[i
],
6508 ralloc_free(first_writes
);
6509 ralloc_free(first_reads
);
6510 ralloc_free(last_writes
);
6511 ralloc_free(last_reads
);
6515 /* Perform optimizations on the instructions in the glsl_to_tgsi_visitor. */
6518 if (shader
->Stage
!= MESA_SHADER_TESS_CTRL
&&
6519 shader
->Stage
!= MESA_SHADER_TESS_EVAL
)
6520 v
->copy_propagate();
6522 while (v
->eliminate_dead_code());
6524 v
->merge_two_dsts();
6525 v
->merge_registers();
6526 v
->renumber_registers();
6528 /* Write the END instruction. */
6529 v
->emit_asm(NULL
, TGSI_OPCODE_END
);
6531 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
6533 _mesa_log("GLSL IR for linked %s program %d:\n",
6534 _mesa_shader_stage_to_string(shader
->Stage
),
6535 shader_program
->Name
);
6536 _mesa_print_ir(_mesa_get_log_file(), shader
->ir
, NULL
);
6540 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
6541 _mesa_copy_linked_program_data(shader_program
, shader
);
6542 shrink_array_declarations(v
->inputs
, v
->num_inputs
,
6543 &prog
->info
.inputs_read
,
6544 prog
->info
.double_inputs_read
,
6545 &prog
->info
.patch_inputs_read
);
6546 shrink_array_declarations(v
->outputs
, v
->num_outputs
,
6547 &prog
->info
.outputs_written
, 0ULL,
6548 &prog
->info
.patch_outputs_written
);
6549 count_resources(v
, prog
);
6551 /* The GLSL IR won't be needed anymore. */
6552 ralloc_free(shader
->ir
);
6555 /* This must be done before the uniform storage is associated. */
6556 if (shader
->Stage
== MESA_SHADER_FRAGMENT
&&
6557 (prog
->info
.inputs_read
& VARYING_BIT_POS
||
6558 prog
->info
.system_values_read
& (1 << SYSTEM_VALUE_FRAG_COORD
))) {
6559 static const gl_state_index wposTransformState
[STATE_LENGTH
] = {
6560 STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
6563 v
->wpos_transform_const
= _mesa_add_state_reference(prog
->Parameters
,
6564 wposTransformState
);
6567 /* Avoid reallocation of the program parameter list, because the uniform
6568 * storage is only associated with the original parameter list.
6569 * This should be enough for Bitmap and DrawPixels constants.
6571 _mesa_reserve_parameter_storage(prog
->Parameters
, 8);
6573 /* This has to be done last. Any operation the can cause
6574 * prog->ParameterValues to get reallocated (e.g., anything that adds a
6575 * program constant) has to happen before creating this linkage.
6577 _mesa_associate_uniform_storage(ctx
, shader_program
, prog
->Parameters
);
6578 if (!shader_program
->data
->LinkStatus
) {
6579 free_glsl_to_tgsi_visitor(v
);
6580 _mesa_reference_program(ctx
, &shader
->Program
, NULL
);
6584 struct st_vertex_program
*stvp
;
6585 struct st_fragment_program
*stfp
;
6586 struct st_geometry_program
*stgp
;
6587 struct st_tessctrl_program
*sttcp
;
6588 struct st_tesseval_program
*sttep
;
6589 struct st_compute_program
*stcp
;
6591 switch (shader
->Stage
) {
6592 case MESA_SHADER_VERTEX
:
6593 stvp
= (struct st_vertex_program
*)prog
;
6594 stvp
->glsl_to_tgsi
= v
;
6596 case MESA_SHADER_FRAGMENT
:
6597 stfp
= (struct st_fragment_program
*)prog
;
6598 stfp
->glsl_to_tgsi
= v
;
6600 case MESA_SHADER_GEOMETRY
:
6601 stgp
= (struct st_geometry_program
*)prog
;
6602 stgp
->glsl_to_tgsi
= v
;
6604 case MESA_SHADER_TESS_CTRL
:
6605 sttcp
= (struct st_tessctrl_program
*)prog
;
6606 sttcp
->glsl_to_tgsi
= v
;
6608 case MESA_SHADER_TESS_EVAL
:
6609 sttep
= (struct st_tesseval_program
*)prog
;
6610 sttep
->glsl_to_tgsi
= v
;
6612 case MESA_SHADER_COMPUTE
:
6613 stcp
= (struct st_compute_program
*)prog
;
6614 stcp
->glsl_to_tgsi
= v
;
6617 assert(!"should not be reached");
6625 set_affected_state_flags(uint64_t *states
,
6626 struct gl_program
*prog
,
6627 struct gl_linked_shader
*shader
,
6628 uint64_t new_constants
,
6629 uint64_t new_sampler_views
,
6630 uint64_t new_samplers
,
6631 uint64_t new_images
,
6634 uint64_t new_atomics
)
6636 if (prog
->Parameters
->NumParameters
)
6637 *states
|= new_constants
;
6639 if (shader
->num_samplers
)
6640 *states
|= new_sampler_views
| new_samplers
;
6642 if (shader
->NumImages
)
6643 *states
|= new_images
;
6645 if (prog
->info
.num_ubos
)
6646 *states
|= new_ubos
;
6648 if (prog
->info
.num_ssbos
)
6649 *states
|= new_ssbos
;
6651 if (prog
->info
.num_abos
)
6652 *states
|= new_atomics
;
6655 static struct gl_program
*
6656 get_mesa_program(struct gl_context
*ctx
,
6657 struct gl_shader_program
*shader_program
,
6658 struct gl_linked_shader
*shader
)
6660 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6661 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(shader
->Stage
);
6662 enum pipe_shader_ir preferred_ir
= (enum pipe_shader_ir
)
6663 pscreen
->get_shader_param(pscreen
, ptarget
, PIPE_SHADER_CAP_PREFERRED_IR
);
6664 struct gl_program
*prog
= NULL
;
6666 if (preferred_ir
== PIPE_SHADER_IR_NIR
) {
6667 /* TODO only for GLSL VS/FS for now: */
6668 switch (shader
->Stage
) {
6669 case MESA_SHADER_VERTEX
:
6670 case MESA_SHADER_FRAGMENT
:
6671 prog
= st_nir_get_mesa_program(ctx
, shader_program
, shader
);
6676 prog
= get_mesa_program_tgsi(ctx
, shader_program
, shader
);
6682 /* This determines which states will be updated when the shader is
6685 switch (shader
->Stage
) {
6686 case MESA_SHADER_VERTEX
:
6687 states
= &((struct st_vertex_program
*)prog
)->affected_states
;
6689 *states
= ST_NEW_VS_STATE
|
6691 ST_NEW_VERTEX_ARRAYS
;
6693 set_affected_state_flags(states
, prog
, shader
,
6694 ST_NEW_VS_CONSTANTS
,
6695 ST_NEW_VS_SAMPLER_VIEWS
,
6696 ST_NEW_RENDER_SAMPLERS
,
6703 case MESA_SHADER_TESS_CTRL
:
6704 states
= &((struct st_tessctrl_program
*)prog
)->affected_states
;
6706 *states
= ST_NEW_TCS_STATE
;
6708 set_affected_state_flags(states
, prog
, shader
,
6709 ST_NEW_TCS_CONSTANTS
,
6710 ST_NEW_TCS_SAMPLER_VIEWS
,
6711 ST_NEW_RENDER_SAMPLERS
,
6715 ST_NEW_TCS_ATOMICS
);
6718 case MESA_SHADER_TESS_EVAL
:
6719 states
= &((struct st_tesseval_program
*)prog
)->affected_states
;
6721 *states
= ST_NEW_TES_STATE
|
6724 set_affected_state_flags(states
, prog
, shader
,
6725 ST_NEW_TES_CONSTANTS
,
6726 ST_NEW_TES_SAMPLER_VIEWS
,
6727 ST_NEW_RENDER_SAMPLERS
,
6731 ST_NEW_TES_ATOMICS
);
6734 case MESA_SHADER_GEOMETRY
:
6735 states
= &((struct st_geometry_program
*)prog
)->affected_states
;
6737 *states
= ST_NEW_GS_STATE
|
6740 set_affected_state_flags(states
, prog
, shader
,
6741 ST_NEW_GS_CONSTANTS
,
6742 ST_NEW_GS_SAMPLER_VIEWS
,
6743 ST_NEW_RENDER_SAMPLERS
,
6750 case MESA_SHADER_FRAGMENT
:
6751 states
= &((struct st_fragment_program
*)prog
)->affected_states
;
6753 /* gl_FragCoord and glDrawPixels always use constants. */
6754 *states
= ST_NEW_FS_STATE
|
6755 ST_NEW_SAMPLE_SHADING
|
6756 ST_NEW_FS_CONSTANTS
;
6758 set_affected_state_flags(states
, prog
, shader
,
6759 ST_NEW_FS_CONSTANTS
,
6760 ST_NEW_FS_SAMPLER_VIEWS
,
6761 ST_NEW_RENDER_SAMPLERS
,
6768 case MESA_SHADER_COMPUTE
:
6769 states
= &((struct st_compute_program
*)prog
)->affected_states
;
6771 *states
= ST_NEW_CS_STATE
;
6773 set_affected_state_flags(states
, prog
, shader
,
6774 ST_NEW_CS_CONSTANTS
,
6775 ST_NEW_CS_SAMPLER_VIEWS
,
6784 unreachable("unhandled shader stage");
6791 /* See if there are unsupported control flow statements. */
6792 class ir_control_flow_info_visitor
: public ir_hierarchical_visitor
{
6794 const struct gl_shader_compiler_options
*options
;
6796 ir_control_flow_info_visitor(const struct gl_shader_compiler_options
*options
)
6802 virtual ir_visitor_status
visit_enter(ir_function
*ir
)
6804 /* Other functions are skipped (same as glsl_to_tgsi). */
6805 if (strcmp(ir
->name
, "main") == 0)
6806 return visit_continue
;
6808 return visit_continue_with_parent
;
6811 virtual ir_visitor_status
visit_enter(ir_call
*ir
)
6813 if (!ir
->callee
->is_intrinsic()) {
6814 unsupported
= true; /* it's a function call */
6817 return visit_continue
;
6820 virtual ir_visitor_status
visit_enter(ir_return
*ir
)
6822 if (options
->EmitNoMainReturn
) {
6826 return visit_continue
;
6833 has_unsupported_control_flow(exec_list
*ir
,
6834 const struct gl_shader_compiler_options
*options
)
6836 ir_control_flow_info_visitor
visitor(options
);
6837 visit_list_elements(&visitor
, ir
);
6838 return visitor
.unsupported
;
6845 * Called via ctx->Driver.LinkShader()
6846 * This actually involves converting GLSL IR into an intermediate TGSI-like IR
6847 * with code lowering and other optimizations.
6850 st_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
6852 struct pipe_screen
*pscreen
= ctx
->st
->pipe
->screen
;
6853 assert(prog
->data
->LinkStatus
);
6855 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6856 if (prog
->_LinkedShaders
[i
] == NULL
)
6859 exec_list
*ir
= prog
->_LinkedShaders
[i
]->ir
;
6860 gl_shader_stage stage
= prog
->_LinkedShaders
[i
]->Stage
;
6861 const struct gl_shader_compiler_options
*options
=
6862 &ctx
->Const
.ShaderCompilerOptions
[stage
];
6863 enum pipe_shader_type ptarget
= st_shader_stage_to_ptarget(stage
);
6864 bool have_dround
= pscreen
->get_shader_param(pscreen
, ptarget
,
6865 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
);
6866 bool have_dfrexp
= pscreen
->get_shader_param(pscreen
, ptarget
,
6867 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
);
6868 unsigned if_threshold
= pscreen
->get_shader_param(pscreen
, ptarget
,
6869 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
);
6871 /* If there are forms of indirect addressing that the driver
6872 * cannot handle, perform the lowering pass.
6874 if (options
->EmitNoIndirectInput
|| options
->EmitNoIndirectOutput
||
6875 options
->EmitNoIndirectTemp
|| options
->EmitNoIndirectUniform
) {
6876 lower_variable_index_to_cond_assign(prog
->_LinkedShaders
[i
]->Stage
, ir
,
6877 options
->EmitNoIndirectInput
,
6878 options
->EmitNoIndirectOutput
,
6879 options
->EmitNoIndirectTemp
,
6880 options
->EmitNoIndirectUniform
);
6883 if (ctx
->Extensions
.ARB_shading_language_packing
) {
6884 unsigned lower_inst
= LOWER_PACK_SNORM_2x16
|
6885 LOWER_UNPACK_SNORM_2x16
|
6886 LOWER_PACK_UNORM_2x16
|
6887 LOWER_UNPACK_UNORM_2x16
|
6888 LOWER_PACK_SNORM_4x8
|
6889 LOWER_UNPACK_SNORM_4x8
|
6890 LOWER_UNPACK_UNORM_4x8
|
6891 LOWER_PACK_UNORM_4x8
;
6893 if (ctx
->Extensions
.ARB_gpu_shader5
)
6894 lower_inst
|= LOWER_PACK_USE_BFI
|
6896 if (!ctx
->st
->has_half_float_packing
)
6897 lower_inst
|= LOWER_PACK_HALF_2x16
|
6898 LOWER_UNPACK_HALF_2x16
;
6900 lower_packing_builtins(ir
, lower_inst
);
6903 if (!pscreen
->get_param(pscreen
, PIPE_CAP_TEXTURE_GATHER_OFFSETS
))
6904 lower_offset_arrays(ir
);
6905 do_mat_op_to_vec(ir
);
6906 lower_instructions(ir
,
6912 (have_dfrexp
? 0 : DFREXP_DLDEXP_TO_ARITH
) |
6915 (have_dround
? 0 : DOPS_TO_DFRAC
) |
6916 (options
->EmitNoPow
? POW_TO_EXP2
: 0) |
6917 (!ctx
->Const
.NativeIntegers
? INT_DIV_TO_MUL_RCP
: 0) |
6918 (options
->EmitNoSat
? SAT_TO_CLAMP
: 0) |
6919 /* Assume that if ARB_gpu_shader5 is not supported
6920 * then all of the extended integer functions need
6921 * lowering. It may be necessary to add some caps
6922 * for individual instructions.
6924 (!ctx
->Extensions
.ARB_gpu_shader5
6925 ? BIT_COUNT_TO_MATH
|
6929 FIND_LSB_TO_FLOAT_CAST
|
6930 FIND_MSB_TO_FLOAT_CAST
|
6934 do_vec_index_to_cond_assign(ir
);
6935 lower_vector_insert(ir
, true);
6936 lower_quadop_vector(ir
, false);
6938 if (options
->MaxIfDepth
== 0) {
6942 if (ctx
->Const
.GLSLOptimizeConservatively
) {
6943 /* Do it once and repeat only if there's unsupported control flow. */
6945 do_common_optimization(ir
, true, true, options
,
6946 ctx
->Const
.NativeIntegers
);
6947 lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6948 options
->MaxIfDepth
, if_threshold
);
6949 } while (has_unsupported_control_flow(ir
, options
));
6951 /* Repeat it until it stops making changes. */
6954 progress
= do_common_optimization(ir
, true, true, options
,
6955 ctx
->Const
.NativeIntegers
);
6956 progress
|= lower_if_to_cond_assign((gl_shader_stage
)i
, ir
,
6957 options
->MaxIfDepth
, if_threshold
);
6961 validate_ir_tree(ir
);
6964 build_program_resource_list(ctx
, prog
);
6966 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
6967 struct gl_program
*linked_prog
;
6969 if (prog
->_LinkedShaders
[i
] == NULL
)
6972 linked_prog
= get_mesa_program(ctx
, prog
, prog
->_LinkedShaders
[i
]);
6975 if (!ctx
->Driver
.ProgramStringNotify(ctx
,
6976 _mesa_shader_stage_to_program(i
),
6978 _mesa_reference_program(ctx
, &prog
->_LinkedShaders
[i
]->Program
,
6989 st_translate_stream_output_info(glsl_to_tgsi_visitor
*glsl_to_tgsi
,
6990 const GLuint outputMapping
[],
6991 struct pipe_stream_output_info
*so
)
6993 struct gl_transform_feedback_info
*info
=
6994 glsl_to_tgsi
->shader_program
->xfb_program
->sh
.LinkedTransformFeedback
;
6995 st_translate_stream_output_info2(info
, outputMapping
, so
);
6999 st_translate_stream_output_info2(struct gl_transform_feedback_info
*info
,
7000 const GLuint outputMapping
[],
7001 struct pipe_stream_output_info
*so
)
7005 for (i
= 0; i
< info
->NumOutputs
; i
++) {
7006 so
->output
[i
].register_index
=
7007 outputMapping
[info
->Outputs
[i
].OutputRegister
];
7008 so
->output
[i
].start_component
= info
->Outputs
[i
].ComponentOffset
;
7009 so
->output
[i
].num_components
= info
->Outputs
[i
].NumComponents
;
7010 so
->output
[i
].output_buffer
= info
->Outputs
[i
].OutputBuffer
;
7011 so
->output
[i
].dst_offset
= info
->Outputs
[i
].DstOffset
;
7012 so
->output
[i
].stream
= info
->Outputs
[i
].StreamId
;
7015 for (i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
7016 so
->stride
[i
] = info
->Buffers
[i
].Stride
;
7018 so
->num_outputs
= info
->NumOutputs
;