1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
51 (1 << PROGRAM_CONSTANT) | \
52 (1 << PROGRAM_UNIFORM))
55 * Intermediate state used during shader translation.
58 struct ureg_program
*ureg
;
60 struct ureg_dst temps
[MAX_PROGRAM_TEMPS
];
61 struct ureg_src
*constants
;
62 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
63 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
64 struct ureg_dst address
[1];
65 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
66 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
68 const ubyte
*inputMapping
;
69 const ubyte
*outputMapping
;
71 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
76 * Map a Mesa dst register to a TGSI ureg_dst register.
78 static struct ureg_dst
79 dst_register(struct st_translate
*t
, gl_register_file file
, GLuint index
)
82 case PROGRAM_UNDEFINED
:
83 return ureg_dst_undef();
85 case PROGRAM_TEMPORARY
:
86 if (ureg_dst_is_undef(t
->temps
[index
]))
87 t
->temps
[index
] = ureg_DECL_temporary(t
->ureg
);
89 return t
->temps
[index
];
92 if (t
->procType
== PIPE_SHADER_VERTEX
)
93 assert(index
< VARYING_SLOT_MAX
);
94 else if (t
->procType
== PIPE_SHADER_FRAGMENT
)
95 assert(index
< FRAG_RESULT_MAX
);
97 assert(index
< VARYING_SLOT_MAX
);
99 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
101 return t
->outputs
[t
->outputMapping
[index
]];
103 case PROGRAM_ADDRESS
:
104 return t
->address
[index
];
108 return ureg_dst_undef();
114 * Map a Mesa src register to a TGSI ureg_src register.
116 static struct ureg_src
117 src_register(struct st_translate
*t
,
118 gl_register_file file
,
122 case PROGRAM_UNDEFINED
:
123 return ureg_src_undef();
125 case PROGRAM_TEMPORARY
:
127 assert(index
< ARRAY_SIZE(t
->temps
));
128 if (ureg_dst_is_undef(t
->temps
[index
]))
129 t
->temps
[index
] = ureg_DECL_temporary(t
->ureg
);
130 return ureg_src(t
->temps
[index
]);
132 case PROGRAM_UNIFORM
:
134 return t
->constants
[index
];
135 case PROGRAM_STATE_VAR
:
136 case PROGRAM_CONSTANT
: /* ie, immediate */
138 return ureg_DECL_constant(t
->ureg
, 0);
140 return t
->constants
[index
];
143 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
144 return t
->inputs
[t
->inputMapping
[index
]];
147 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
148 return ureg_src(t
->outputs
[t
->outputMapping
[index
]]); /* not needed? */
150 case PROGRAM_ADDRESS
:
151 return ureg_src(t
->address
[index
]);
153 case PROGRAM_SYSTEM_VALUE
:
154 assert(index
< ARRAY_SIZE(t
->systemValues
));
155 return t
->systemValues
[index
];
159 return ureg_src_undef();
165 * Map mesa texture target to TGSI texture target.
167 enum tgsi_texture_type
168 st_translate_texture_target(gl_texture_index textarget
, GLboolean shadow
)
172 case TEXTURE_1D_INDEX
:
173 return TGSI_TEXTURE_SHADOW1D
;
174 case TEXTURE_2D_INDEX
:
175 return TGSI_TEXTURE_SHADOW2D
;
176 case TEXTURE_RECT_INDEX
:
177 return TGSI_TEXTURE_SHADOWRECT
;
178 case TEXTURE_1D_ARRAY_INDEX
:
179 return TGSI_TEXTURE_SHADOW1D_ARRAY
;
180 case TEXTURE_2D_ARRAY_INDEX
:
181 return TGSI_TEXTURE_SHADOW2D_ARRAY
;
182 case TEXTURE_CUBE_INDEX
:
183 return TGSI_TEXTURE_SHADOWCUBE
;
184 case TEXTURE_CUBE_ARRAY_INDEX
:
185 return TGSI_TEXTURE_SHADOWCUBE_ARRAY
;
192 case TEXTURE_2D_MULTISAMPLE_INDEX
:
193 return TGSI_TEXTURE_2D_MSAA
;
194 case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
:
195 return TGSI_TEXTURE_2D_ARRAY_MSAA
;
196 case TEXTURE_BUFFER_INDEX
:
197 return TGSI_TEXTURE_BUFFER
;
198 case TEXTURE_1D_INDEX
:
199 return TGSI_TEXTURE_1D
;
200 case TEXTURE_2D_INDEX
:
201 return TGSI_TEXTURE_2D
;
202 case TEXTURE_3D_INDEX
:
203 return TGSI_TEXTURE_3D
;
204 case TEXTURE_CUBE_INDEX
:
205 return TGSI_TEXTURE_CUBE
;
206 case TEXTURE_CUBE_ARRAY_INDEX
:
207 return TGSI_TEXTURE_CUBE_ARRAY
;
208 case TEXTURE_RECT_INDEX
:
209 return TGSI_TEXTURE_RECT
;
210 case TEXTURE_1D_ARRAY_INDEX
:
211 return TGSI_TEXTURE_1D_ARRAY
;
212 case TEXTURE_2D_ARRAY_INDEX
:
213 return TGSI_TEXTURE_2D_ARRAY
;
214 case TEXTURE_EXTERNAL_INDEX
:
215 return TGSI_TEXTURE_2D
;
217 debug_assert(!"unexpected texture target index");
218 return TGSI_TEXTURE_1D
;
224 * Map GLSL base type to TGSI return type.
226 enum tgsi_return_type
227 st_translate_texture_type(enum glsl_base_type type
)
231 return TGSI_RETURN_TYPE_SINT
;
233 return TGSI_RETURN_TYPE_UINT
;
234 case GLSL_TYPE_FLOAT
:
235 return TGSI_RETURN_TYPE_FLOAT
;
237 assert(!"unexpected texture type");
238 return TGSI_RETURN_TYPE_UNKNOWN
;
244 * Translate a (1 << TEXTURE_x_INDEX) bit into a TGSI_TEXTURE_x enum.
247 translate_texture_index(GLbitfield texBit
, bool shadow
)
249 int index
= ffs(texBit
);
251 assert(index
- 1 < NUM_TEXTURE_TARGETS
);
252 return st_translate_texture_target(index
- 1, shadow
);
257 * Create a TGSI ureg_dst register from a Mesa dest register.
259 static struct ureg_dst
260 translate_dst(struct st_translate
*t
,
261 const struct prog_dst_register
*DstReg
,
264 struct ureg_dst dst
= dst_register(t
, DstReg
->File
, DstReg
->Index
);
266 dst
= ureg_writemask(dst
, DstReg
->WriteMask
);
269 dst
= ureg_saturate(dst
);
272 dst
= ureg_dst_indirect(dst
, ureg_src(t
->address
[0]));
279 * Create a TGSI ureg_src register from a Mesa src register.
281 static struct ureg_src
282 translate_src(struct st_translate
*t
,
283 const struct prog_src_register
*SrcReg
)
285 struct ureg_src src
= src_register(t
, SrcReg
->File
, SrcReg
->Index
);
287 src
= ureg_swizzle(src
,
288 GET_SWZ(SrcReg
->Swizzle
, 0) & 0x3,
289 GET_SWZ(SrcReg
->Swizzle
, 1) & 0x3,
290 GET_SWZ(SrcReg
->Swizzle
, 2) & 0x3,
291 GET_SWZ(SrcReg
->Swizzle
, 3) & 0x3);
293 if (SrcReg
->Negate
== NEGATE_XYZW
)
294 src
= ureg_negate(src
);
296 if (SrcReg
->RelAddr
) {
297 src
= ureg_src_indirect(src
, ureg_src(t
->address
[0]));
298 if (SrcReg
->File
!= PROGRAM_INPUT
&&
299 SrcReg
->File
!= PROGRAM_OUTPUT
) {
300 /* If SrcReg->Index was negative, it was set to zero in
301 * src_register(). Reassign it now. But don't do this
302 * for input/output regs since they get remapped while
303 * const buffers don't.
305 src
.Index
= SrcReg
->Index
;
313 static struct ureg_src
314 swizzle_4v(struct ureg_src src
, const unsigned *swz
)
316 return ureg_swizzle(src
, swz
[0], swz
[1], swz
[2], swz
[3]);
321 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
327 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
330 emit_swz(struct st_translate
*t
,
332 const struct prog_src_register
*SrcReg
)
334 struct ureg_program
*ureg
= t
->ureg
;
335 struct ureg_src src
= src_register(t
, SrcReg
->File
, SrcReg
->Index
);
337 unsigned negate_mask
= SrcReg
->Negate
;
339 unsigned one_mask
= ((GET_SWZ(SrcReg
->Swizzle
, 0) == SWIZZLE_ONE
) << 0 |
340 (GET_SWZ(SrcReg
->Swizzle
, 1) == SWIZZLE_ONE
) << 1 |
341 (GET_SWZ(SrcReg
->Swizzle
, 2) == SWIZZLE_ONE
) << 2 |
342 (GET_SWZ(SrcReg
->Swizzle
, 3) == SWIZZLE_ONE
) << 3);
344 unsigned zero_mask
= ((GET_SWZ(SrcReg
->Swizzle
, 0) == SWIZZLE_ZERO
) << 0 |
345 (GET_SWZ(SrcReg
->Swizzle
, 1) == SWIZZLE_ZERO
) << 1 |
346 (GET_SWZ(SrcReg
->Swizzle
, 2) == SWIZZLE_ZERO
) << 2 |
347 (GET_SWZ(SrcReg
->Swizzle
, 3) == SWIZZLE_ZERO
) << 3);
349 unsigned negative_one_mask
= one_mask
& negate_mask
;
350 unsigned positive_one_mask
= one_mask
& ~negate_mask
;
354 unsigned mul_swizzle
[4] = {0,0,0,0};
355 unsigned add_swizzle
[4] = {0,0,0,0};
356 unsigned src_swizzle
[4] = {0,0,0,0};
357 boolean need_add
= FALSE
;
358 boolean need_mul
= FALSE
;
360 if (dst
.WriteMask
== 0)
363 /* Is this just a MOV?
365 if (zero_mask
== 0 &&
367 (negate_mask
== 0 || negate_mask
== TGSI_WRITEMASK_XYZW
)) {
368 ureg_MOV(ureg
, dst
, translate_src(t
, SrcReg
));
374 #define IMM_NEG_ONE 2
376 imm
= ureg_imm3f(ureg
, 0, 1, -1);
378 for (i
= 0; i
< 4; i
++) {
379 unsigned bit
= 1 << i
;
381 if (dst
.WriteMask
& bit
) {
382 if (positive_one_mask
& bit
) {
383 mul_swizzle
[i
] = IMM_ZERO
;
384 add_swizzle
[i
] = IMM_ONE
;
387 else if (negative_one_mask
& bit
) {
388 mul_swizzle
[i
] = IMM_ZERO
;
389 add_swizzle
[i
] = IMM_NEG_ONE
;
392 else if (zero_mask
& bit
) {
393 mul_swizzle
[i
] = IMM_ZERO
;
394 add_swizzle
[i
] = IMM_ZERO
;
398 add_swizzle
[i
] = IMM_ZERO
;
399 src_swizzle
[i
] = GET_SWZ(SrcReg
->Swizzle
, i
);
401 if (negate_mask
& bit
) {
402 mul_swizzle
[i
] = IMM_NEG_ONE
;
405 mul_swizzle
[i
] = IMM_ONE
;
411 if (need_mul
&& need_add
) {
414 swizzle_4v(src
, src_swizzle
),
415 swizzle_4v(imm
, mul_swizzle
),
416 swizzle_4v(imm
, add_swizzle
));
421 swizzle_4v(src
, src_swizzle
),
422 swizzle_4v(imm
, mul_swizzle
));
427 swizzle_4v(imm
, add_swizzle
));
440 translate_opcode(unsigned op
)
444 return TGSI_OPCODE_ARL
;
446 return TGSI_OPCODE_ADD
;
448 return TGSI_OPCODE_CMP
;
450 return TGSI_OPCODE_COS
;
452 return TGSI_OPCODE_DP3
;
454 return TGSI_OPCODE_DP4
;
456 return TGSI_OPCODE_DST
;
458 return TGSI_OPCODE_EX2
;
460 return TGSI_OPCODE_EXP
;
462 return TGSI_OPCODE_FLR
;
464 return TGSI_OPCODE_FRC
;
466 return TGSI_OPCODE_KILL_IF
;
468 return TGSI_OPCODE_LG2
;
470 return TGSI_OPCODE_LOG
;
472 return TGSI_OPCODE_LIT
;
474 return TGSI_OPCODE_LRP
;
476 return TGSI_OPCODE_MAD
;
478 return TGSI_OPCODE_MAX
;
480 return TGSI_OPCODE_MIN
;
482 return TGSI_OPCODE_MOV
;
484 return TGSI_OPCODE_MUL
;
486 return TGSI_OPCODE_POW
;
488 return TGSI_OPCODE_RCP
;
490 return TGSI_OPCODE_SGE
;
492 return TGSI_OPCODE_SIN
;
494 return TGSI_OPCODE_SLT
;
496 return TGSI_OPCODE_TEX
;
498 return TGSI_OPCODE_TXB
;
500 return TGSI_OPCODE_TXP
;
502 return TGSI_OPCODE_END
;
505 return TGSI_OPCODE_NOP
;
511 compile_instruction(struct gl_context
*ctx
,
512 struct st_translate
*t
,
513 const struct prog_instruction
*inst
)
515 struct ureg_program
*ureg
= t
->ureg
;
517 struct ureg_dst dst
[1] = { { 0 } };
518 struct ureg_src src
[4];
522 num_dst
= _mesa_num_inst_dst_regs(inst
->Opcode
);
523 num_src
= _mesa_num_inst_src_regs(inst
->Opcode
);
526 dst
[0] = translate_dst(t
, &inst
->DstReg
, inst
->Saturate
);
528 for (i
= 0; i
< num_src
; i
++)
529 src
[i
] = translate_src(t
, &inst
->SrcReg
[i
]);
531 switch(inst
->Opcode
) {
533 emit_swz(t
, dst
[0], &inst
->SrcReg
[0]);
539 src
[num_src
++] = t
->samplers
[inst
->TexSrcUnit
];
541 translate_opcode(inst
->Opcode
),
543 st_translate_texture_target(inst
->TexSrcTarget
,
545 TGSI_RETURN_TYPE_FLOAT
,
551 ureg_COS(ureg
, ureg_writemask(dst
[0], TGSI_WRITEMASK_X
),
552 ureg_scalar(src
[0], TGSI_SWIZZLE_X
));
553 ureg_SIN(ureg
, ureg_writemask(dst
[0], TGSI_WRITEMASK_Y
),
554 ureg_scalar(src
[0], TGSI_SWIZZLE_X
));
558 struct ureg_dst tmp
= ureg_DECL_temporary(ureg
);
560 ureg_MUL(ureg
, ureg_writemask(tmp
, TGSI_WRITEMASK_XYZ
),
561 ureg_swizzle(src
[0], TGSI_SWIZZLE_Y
, TGSI_SWIZZLE_Z
,
563 ureg_swizzle(src
[1], TGSI_SWIZZLE_Z
, TGSI_SWIZZLE_X
,
565 ureg_MAD(ureg
, ureg_writemask(dst
[0], TGSI_WRITEMASK_XYZ
),
566 ureg_swizzle(src
[0], TGSI_SWIZZLE_Z
, TGSI_SWIZZLE_X
,
568 ureg_negate(ureg_swizzle(src
[1], TGSI_SWIZZLE_Y
,
569 TGSI_SWIZZLE_Z
, TGSI_SWIZZLE_X
, 0)),
575 ureg_RSQ(ureg
, dst
[0], ureg_abs(src
[0]));
579 ureg_MOV(ureg
, dst
[0], ureg_abs(src
[0]));
583 ureg_ADD(ureg
, dst
[0], src
[0], ureg_negate(src
[1]));
587 struct ureg_dst temp
= ureg_DECL_temporary(ureg
);
589 /* DPH = DP4(src0, src1) where src0.w = 1. */
590 ureg_MOV(ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_XYZ
), src
[0]);
591 ureg_MOV(ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_W
),
592 ureg_imm1f(ureg
, 1));
593 ureg_DP4(ureg
, dst
[0], ureg_src(temp
), src
[1]);
599 translate_opcode(inst
->Opcode
),
608 * Emit the TGSI instructions for inverting and adjusting WPOS.
609 * This code is unavoidable because it also depends on whether
610 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
613 emit_wpos_adjustment(struct gl_context
*ctx
,
614 struct st_translate
*t
,
615 const struct gl_program
*program
,
617 GLfloat adjX
, GLfloat adjY
[2])
619 struct ureg_program
*ureg
= t
->ureg
;
621 /* Fragment program uses fragment position input.
622 * Need to replace instances of INPUT[WPOS] with temp T
623 * where T = INPUT[WPOS] by y is inverted.
625 static const gl_state_index16 wposTransformState
[STATE_LENGTH
]
626 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0 };
628 /* XXX: note we are modifying the incoming shader here! Need to
629 * do this before emitting the constant decls below, or this
632 unsigned wposTransConst
= _mesa_add_state_reference(program
->Parameters
,
635 struct ureg_src wpostrans
= ureg_DECL_constant(ureg
, wposTransConst
);
636 struct ureg_dst wpos_temp
= ureg_DECL_temporary(ureg
);
637 struct ureg_src
*wpos
=
638 ctx
->Const
.GLSLFragCoordIsSysVal
?
639 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
640 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
641 struct ureg_src wpos_input
= *wpos
;
643 /* First, apply the coordinate shift: */
644 if (adjX
|| adjY
[0] || adjY
[1]) {
645 if (adjY
[0] != adjY
[1]) {
646 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
647 * depending on whether inversion is actually going to be applied
648 * or not, which is determined by testing against the inversion
649 * state variable used below, which will be either +1 or -1.
651 struct ureg_dst adj_temp
= ureg_DECL_temporary(ureg
);
653 ureg_CMP(ureg
, adj_temp
,
654 ureg_scalar(wpostrans
, invert
? 2 : 0),
655 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
656 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
657 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
659 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
660 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
662 wpos_input
= ureg_src(wpos_temp
);
664 /* MOV wpos_temp, input[wpos]
666 ureg_MOV(ureg
, wpos_temp
, wpos_input
);
669 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
670 * inversion/identity, or the other way around if we're drawing to an FBO.
673 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
676 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
678 ureg_scalar(wpostrans
, 0),
679 ureg_scalar(wpostrans
, 1));
681 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
684 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
686 ureg_scalar(wpostrans
, 2),
687 ureg_scalar(wpostrans
, 3));
690 /* Use wpos_temp as position input from here on:
692 *wpos
= ureg_src(wpos_temp
);
697 * Emit fragment position/coordinate code.
700 emit_wpos(struct st_context
*st
,
701 struct st_translate
*t
,
702 const struct gl_program
*program
,
703 struct ureg_program
*ureg
)
705 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
707 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
708 boolean invert
= FALSE
;
710 /* Query the pixel center conventions supported by the pipe driver and set
711 * adjX, adjY to help out if it cannot handle the requested one internally.
713 * The bias of the y-coordinate depends on whether y-inversion takes place
714 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
715 * drawing to an FBO (causes additional inversion), and whether the pipe
716 * driver origin and the requested origin differ (the latter condition is
717 * stored in the 'invert' variable).
719 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
726 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
727 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
728 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
729 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
731 * inversion and center shift:
732 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
733 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
734 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
735 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
737 if (program
->OriginUpperLeft
) {
738 /* Fragment shader wants origin in upper-left */
739 if (pscreen
->get_param(pscreen
,
740 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
741 /* the driver supports upper-left origin */
743 else if (pscreen
->get_param(pscreen
,
744 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
745 /* the driver supports lower-left origin, need to invert Y */
746 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
747 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
754 /* Fragment shader wants origin in lower-left */
755 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
756 /* the driver supports lower-left origin */
757 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
758 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
759 else if (pscreen
->get_param(pscreen
,
760 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
761 /* the driver supports upper-left origin, need to invert Y */
767 if (program
->PixelCenterInteger
) {
768 /* Fragment shader wants pixel center integer */
769 if (pscreen
->get_param(pscreen
,
770 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
771 /* the driver supports pixel center integer */
773 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
774 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
776 else if (pscreen
->get_param(pscreen
,
777 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
778 /* the driver supports pixel center half integer, need to bias X,Y */
787 /* Fragment shader wants pixel center half integer */
788 if (pscreen
->get_param(pscreen
,
789 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
790 /* the driver supports pixel center half integer */
792 else if (pscreen
->get_param(pscreen
,
793 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
794 /* the driver supports pixel center integer, need to bias X,Y */
795 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
796 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
797 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
803 /* we invert after adjustment so that we avoid the MOV to temporary,
804 * and reuse the adjustment ADD instead */
805 emit_wpos_adjustment(st
->ctx
, t
, program
, invert
, adjX
, adjY
);
810 * Translate Mesa program to TGSI format.
811 * \param program the program to translate
812 * \param numInputs number of input registers used
813 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
815 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
816 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
818 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
819 * \param numOutputs number of output registers used
820 * \param outputMapping maps Mesa fragment program outputs to TGSI
822 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
823 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
826 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
829 st_translate_mesa_program(struct gl_context
*ctx
,
831 struct ureg_program
*ureg
,
832 const struct gl_program
*program
,
834 const ubyte inputMapping
[],
835 const ubyte inputSemanticName
[],
836 const ubyte inputSemanticIndex
[],
837 const ubyte interpMode
[],
839 const ubyte outputMapping
[],
840 const ubyte outputSemanticName
[],
841 const ubyte outputSemanticIndex
[])
843 struct st_translate translate
, *t
;
845 enum pipe_error ret
= PIPE_OK
;
847 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
848 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
851 memset(t
, 0, sizeof *t
);
853 t
->procType
= procType
;
854 t
->inputMapping
= inputMapping
;
855 t
->outputMapping
= outputMapping
;
858 /*_mesa_print_program(program);*/
861 * Declare input attributes.
863 if (procType
== PIPE_SHADER_FRAGMENT
) {
864 for (i
= 0; i
< numInputs
; i
++) {
865 t
->inputs
[i
] = ureg_DECL_fs_input(ureg
,
866 inputSemanticName
[i
],
867 inputSemanticIndex
[i
],
871 if (program
->info
.inputs_read
& VARYING_BIT_POS
) {
872 /* Must do this after setting up t->inputs, and before
873 * emitting constant references, below:
875 emit_wpos(st_context(ctx
), t
, program
, ureg
);
879 * Declare output attributes.
881 for (i
= 0; i
< numOutputs
; i
++) {
882 switch (outputSemanticName
[i
]) {
883 case TGSI_SEMANTIC_POSITION
:
884 t
->outputs
[i
] = ureg_DECL_output(ureg
,
885 TGSI_SEMANTIC_POSITION
, /* Z / Depth */
886 outputSemanticIndex
[i
]);
888 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
],
891 case TGSI_SEMANTIC_STENCIL
:
892 t
->outputs
[i
] = ureg_DECL_output(ureg
,
893 TGSI_SEMANTIC_STENCIL
, /* Stencil */
894 outputSemanticIndex
[i
]);
895 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
],
898 case TGSI_SEMANTIC_COLOR
:
899 t
->outputs
[i
] = ureg_DECL_output(ureg
,
901 outputSemanticIndex
[i
]);
909 else if (procType
== PIPE_SHADER_GEOMETRY
) {
910 for (i
= 0; i
< numInputs
; i
++) {
911 t
->inputs
[i
] = ureg_DECL_input(ureg
,
912 inputSemanticName
[i
],
913 inputSemanticIndex
[i
], 0, 1);
916 for (i
= 0; i
< numOutputs
; i
++) {
917 t
->outputs
[i
] = ureg_DECL_output(ureg
,
918 outputSemanticName
[i
],
919 outputSemanticIndex
[i
]);
923 assert(procType
== PIPE_SHADER_VERTEX
);
925 for (i
= 0; i
< numInputs
; i
++) {
926 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
929 for (i
= 0; i
< numOutputs
; i
++) {
930 t
->outputs
[i
] = ureg_DECL_output(ureg
,
931 outputSemanticName
[i
],
932 outputSemanticIndex
[i
]);
933 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
934 /* force register to contain a fog coordinate in the
938 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
939 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
940 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
945 /* Declare address register.
947 if (program
->arb
.NumAddressRegs
> 0) {
948 debug_assert(program
->arb
.NumAddressRegs
== 1);
949 t
->address
[0] = ureg_DECL_address(ureg
);
952 /* Declare misc input registers
954 GLbitfield64 sysInputs
= program
->info
.system_values_read
;
955 for (i
= 0; sysInputs
; i
++) {
956 if (sysInputs
& (1ull << i
)) {
957 unsigned semName
= _mesa_sysval_to_semantic(i
);
959 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
961 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
962 semName
== TGSI_SEMANTIC_VERTEXID
) {
963 /* From Gallium perspective, these system values are always
964 * integer, and require native integer support. However, if
965 * native integer is supported on the vertex stage but not the
966 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
967 * assumes these system values are floats. To resolve the
968 * inconsistency, we insert a U2F.
970 struct st_context
*st
= st_context(ctx
);
971 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
972 assert(procType
== PIPE_SHADER_VERTEX
);
973 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
,
974 PIPE_SHADER_CAP_INTEGERS
));
975 (void) pscreen
; /* silence non-debug build warnings */
976 if (!ctx
->Const
.NativeIntegers
) {
977 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
978 ureg_U2F(t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
),
980 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
984 if (procType
== PIPE_SHADER_FRAGMENT
&&
985 semName
== TGSI_SEMANTIC_POSITION
)
986 emit_wpos(st_context(ctx
), t
, program
, ureg
);
988 sysInputs
&= ~(1ull << i
);
992 if (program
->arb
.IndirectRegisterFiles
& (1 << PROGRAM_TEMPORARY
)) {
993 /* If temps are accessed with indirect addressing, declare temporaries
994 * in sequential order. Else, we declare them on demand elsewhere.
996 for (i
= 0; i
< program
->arb
.NumTemporaries
; i
++) {
997 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
998 t
->temps
[i
] = ureg_DECL_temporary(t
->ureg
);
1002 /* Emit constants and immediates. Mesa uses a single index space
1003 * for these, so we put all the translated regs in t->constants.
1005 if (program
->Parameters
) {
1006 t
->constants
= calloc(program
->Parameters
->NumParameters
,
1007 sizeof t
->constants
[0]);
1008 if (t
->constants
== NULL
) {
1009 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
1013 for (i
= 0; i
< program
->Parameters
->NumParameters
; i
++) {
1014 unsigned pvo
= program
->Parameters
->ParameterValueOffset
[i
];
1016 switch (program
->Parameters
->Parameters
[i
].Type
) {
1017 case PROGRAM_STATE_VAR
:
1018 case PROGRAM_UNIFORM
:
1019 t
->constants
[i
] = ureg_DECL_constant(ureg
, i
);
1022 /* Emit immediates only when there's no indirect addressing of
1024 * FIXME: Be smarter and recognize param arrays:
1025 * indirect addressing is only valid within the referenced
1028 case PROGRAM_CONSTANT
:
1029 if (program
->arb
.IndirectRegisterFiles
& PROGRAM_ANY_CONST
)
1030 t
->constants
[i
] = ureg_DECL_constant( ureg
, i
);
1033 ureg_DECL_immediate(ureg
,
1035 program
->Parameters
->ParameterValues
+ pvo
,
1044 /* texture samplers */
1046 i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
1047 if (program
->SamplersUsed
& (1u << i
)) {
1049 translate_texture_index(program
->TexturesUsed
[i
],
1050 !!(program
->ShadowSamplers
& (1 << i
)));
1051 t
->samplers
[i
] = ureg_DECL_sampler(ureg
, i
);
1052 ureg_DECL_sampler_view(ureg
, i
, target
,
1053 TGSI_RETURN_TYPE_FLOAT
,
1054 TGSI_RETURN_TYPE_FLOAT
,
1055 TGSI_RETURN_TYPE_FLOAT
,
1056 TGSI_RETURN_TYPE_FLOAT
);
1061 /* Emit each instruction in turn:
1063 for (i
= 0; i
< program
->arb
.NumInstructions
; i
++)
1064 compile_instruction(ctx
, t
, &program
->arb
.Instructions
[i
]);