src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_screen.h"
  37 #include "pipe/p_shader_tokens.h"
  38 #include "pipe/p_state.h"
  39 #include "tgsi/tgsi_ureg.h"
  40 #include "st_mesa_to_tgsi.h"
  41 #include "st_context.h"
  42 #include "program/prog_instruction.h"
  43 #include "program/prog_parameter.h"
  44 #include "util/u_debug.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
  48
  49
  50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |    \
  51                            (1 << PROGRAM_CONSTANT) |     \
  52                            (1 << PROGRAM_UNIFORM))
  53
  54 /**
  55  * Intermediate state used during shader translation.
  56  */
  57 struct st_translate {
  58    struct ureg_program *ureg;
  59
  60    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  61    struct ureg_src *constants;
  62    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  63    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  64    struct ureg_dst address[1];
  65    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  66    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  67
  68    const GLuint *inputMapping;
  69    const GLuint *outputMapping;
  70
  71    unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
  72 };
  73
  74
  75 /**
  76  * Map a Mesa dst register to a TGSI ureg_dst register.
  77  */
  78 static struct ureg_dst
  79 dst_register( struct st_translate *t,
  80               gl_register_file file,
  81               GLuint index )
  82 {
  83    switch( file ) {
  84    case PROGRAM_UNDEFINED:
  85       return ureg_dst_undef();
  86
  87    case PROGRAM_TEMPORARY:
  88       if (ureg_dst_is_undef(t->temps[index]))
  89          t->temps[index] = ureg_DECL_temporary( t->ureg );
  90
  91       return t->temps[index];
  92
  93    case PROGRAM_OUTPUT:
  94       if (t->procType == PIPE_SHADER_VERTEX)
  95          assert(index < VARYING_SLOT_MAX);
  96       else if (t->procType == PIPE_SHADER_FRAGMENT)
  97          assert(index < FRAG_RESULT_MAX);
  98       else
  99          assert(index < VARYING_SLOT_MAX);
 100
 101       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 102
 103       return t->outputs[t->outputMapping[index]];
 104
 105    case PROGRAM_ADDRESS:
 106       return t->address[index];
 107
 108    default:
 109       debug_assert( 0 );
 110       return ureg_dst_undef();
 111    }
 112 }
 113
 114
 115 /**
 116  * Map a Mesa src register to a TGSI ureg_src register.
 117  */
 118 static struct ureg_src
 119 src_register( struct st_translate *t,
 120               gl_register_file file,
 121               GLint index )
 122 {
 123    switch( file ) {
 124    case PROGRAM_UNDEFINED:
 125       return ureg_src_undef();
 126
 127    case PROGRAM_TEMPORARY:
 128       assert(index >= 0);
 129       assert(index < ARRAY_SIZE(t->temps));
 130       if (ureg_dst_is_undef(t->temps[index]))
 131          t->temps[index] = ureg_DECL_temporary( t->ureg );
 132       return ureg_src(t->temps[index]);
 133
 134    case PROGRAM_UNIFORM:
 135       assert(index >= 0);
 136       return t->constants[index];
 137    case PROGRAM_STATE_VAR:
 138    case PROGRAM_CONSTANT:       /* ie, immediate */
 139       if (index < 0)
 140          return ureg_DECL_constant( t->ureg, 0 );
 141       else
 142          return t->constants[index];
 143
 144    case PROGRAM_INPUT:
 145       assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
 146       return t->inputs[t->inputMapping[index]];
 147
 148    case PROGRAM_OUTPUT:
 149       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 150       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 151
 152    case PROGRAM_ADDRESS:
 153       return ureg_src(t->address[index]);
 154
 155    case PROGRAM_SYSTEM_VALUE:
 156       assert(index < ARRAY_SIZE(t->systemValues));
 157       return t->systemValues[index];
 158
 159    default:
 160       debug_assert( 0 );
 161       return ureg_src_undef();
 162    }
 163 }
 164
 165
 166 /**
 167  * Map mesa texture target to TGSI texture target.
 168  */
 169 unsigned
 170 st_translate_texture_target(GLuint textarget, GLboolean shadow)
 171 {
 172    if (shadow) {
 173       switch (textarget) {
 174       case TEXTURE_1D_INDEX:
 175          return TGSI_TEXTURE_SHADOW1D;
 176       case TEXTURE_2D_INDEX:
 177          return TGSI_TEXTURE_SHADOW2D;
 178       case TEXTURE_RECT_INDEX:
 179          return TGSI_TEXTURE_SHADOWRECT;
 180       case TEXTURE_1D_ARRAY_INDEX:
 181          return TGSI_TEXTURE_SHADOW1D_ARRAY;
 182       case TEXTURE_2D_ARRAY_INDEX:
 183          return TGSI_TEXTURE_SHADOW2D_ARRAY;
 184       case TEXTURE_CUBE_INDEX:
 185          return TGSI_TEXTURE_SHADOWCUBE;
 186       case TEXTURE_CUBE_ARRAY_INDEX:
 187          return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
 188       default:
 189          break;
 190       }
 191    }
 192
 193    switch (textarget) {
 194    case TEXTURE_2D_MULTISAMPLE_INDEX:
 195       return TGSI_TEXTURE_2D_MSAA;
 196    case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX:
 197       return TGSI_TEXTURE_2D_ARRAY_MSAA;
 198    case TEXTURE_BUFFER_INDEX:
 199       return TGSI_TEXTURE_BUFFER;
 200    case TEXTURE_1D_INDEX:
 201       return TGSI_TEXTURE_1D;
 202    case TEXTURE_2D_INDEX:
 203       return TGSI_TEXTURE_2D;
 204    case TEXTURE_3D_INDEX:
 205       return TGSI_TEXTURE_3D;
 206    case TEXTURE_CUBE_INDEX:
 207       return TGSI_TEXTURE_CUBE;
 208    case TEXTURE_CUBE_ARRAY_INDEX:
 209       return TGSI_TEXTURE_CUBE_ARRAY;
 210    case TEXTURE_RECT_INDEX:
 211       return TGSI_TEXTURE_RECT;
 212    case TEXTURE_1D_ARRAY_INDEX:
 213       return TGSI_TEXTURE_1D_ARRAY;
 214    case TEXTURE_2D_ARRAY_INDEX:
 215       return TGSI_TEXTURE_2D_ARRAY;
 216    case TEXTURE_EXTERNAL_INDEX:
 217       return TGSI_TEXTURE_2D;
 218    default:
 219       debug_assert(!"unexpected texture target index");
 220       return TGSI_TEXTURE_1D;
 221    }
 222 }
 223
 224
 225 /**
 226  * Translate a (1 << TEXTURE_x_INDEX) bit into a TGSI_TEXTURE_x enum.
 227  */
 228 static unsigned
 229 translate_texture_index(GLbitfield texBit, bool shadow)
 230 {
 231    int index = ffs(texBit);
 232    assert(index > 0);
 233    assert(index - 1 < NUM_TEXTURE_TARGETS);
 234    return st_translate_texture_target(index - 1, shadow);
 235 }
 236
 237
 238 /**
 239  * Create a TGSI ureg_dst register from a Mesa dest register.
 240  */
 241 static struct ureg_dst
 242 translate_dst( struct st_translate *t,
 243                const struct prog_dst_register *DstReg,
 244                boolean saturate)
 245 {
 246    struct ureg_dst dst = dst_register( t,
 247                                        DstReg->File,
 248                                        DstReg->Index );
 249
 250    dst = ureg_writemask( dst,
 251                          DstReg->WriteMask );
 252
 253    if (saturate)
 254       dst = ureg_saturate( dst );
 255
 256    if (DstReg->RelAddr)
 257       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 258
 259    return dst;
 260 }
 261
 262
 263 /**
 264  * Create a TGSI ureg_src register from a Mesa src register.
 265  */
 266 static struct ureg_src
 267 translate_src( struct st_translate *t,
 268                const struct prog_src_register *SrcReg )
 269 {
 270    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 271
 272    src = ureg_swizzle( src,
 273                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
 274                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
 275                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
 276                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 277
 278    if (SrcReg->Negate == NEGATE_XYZW)
 279       src = ureg_negate(src);
 280
 281    if (SrcReg->RelAddr) {
 282       src = ureg_src_indirect( src, ureg_src(t->address[0]));
 283       if (SrcReg->File != PROGRAM_INPUT &&
 284           SrcReg->File != PROGRAM_OUTPUT) {
 285          /* If SrcReg->Index was negative, it was set to zero in
 286           * src_register().  Reassign it now.  But don't do this
 287           * for input/output regs since they get remapped while
 288           * const buffers don't.
 289           */
 290          src.Index = SrcReg->Index;
 291       }
 292    }
 293
 294    return src;
 295 }
 296
 297
 298 static struct ureg_src swizzle_4v( struct ureg_src src,
 299                                    const unsigned *swz )
 300 {
 301    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
 302 }
 303
 304
 305 /**
 306  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 307  *
 308  *   SWZ dst, src.x-y10
 309  *
 310  * becomes:
 311  *
 312  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 313  */
 314 static void emit_swz( struct st_translate *t,
 315                       struct ureg_dst dst,
 316                       const struct prog_src_register *SrcReg )
 317 {
 318    struct ureg_program *ureg = t->ureg;
 319    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 320
 321    unsigned negate_mask =  SrcReg->Negate;
 322
 323    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 324                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 325                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 326                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 327
 328    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 329                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 330                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 331                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 332
 333    unsigned negative_one_mask = one_mask & negate_mask;
 334    unsigned positive_one_mask = one_mask & ~negate_mask;
 335
 336    struct ureg_src imm;
 337    unsigned i;
 338    unsigned mul_swizzle[4] = {0,0,0,0};
 339    unsigned add_swizzle[4] = {0,0,0,0};
 340    unsigned src_swizzle[4] = {0,0,0,0};
 341    boolean need_add = FALSE;
 342    boolean need_mul = FALSE;
 343
 344    if (dst.WriteMask == 0)
 345       return;
 346
 347    /* Is this just a MOV?
 348     */
 349    if (zero_mask == 0 &&
 350        one_mask == 0 &&
 351        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
 352    {
 353       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
 354       return;
 355    }
 356
 357 #define IMM_ZERO    0
 358 #define IMM_ONE     1
 359 #define IMM_NEG_ONE 2
 360
 361    imm = ureg_imm3f( ureg, 0, 1, -1 );
 362
 363    for (i = 0; i < 4; i++) {
 364       unsigned bit = 1 << i;
 365
 366       if (dst.WriteMask & bit) {
 367          if (positive_one_mask & bit) {
 368             mul_swizzle[i] = IMM_ZERO;
 369             add_swizzle[i] = IMM_ONE;
 370             need_add = TRUE;
 371          }
 372          else if (negative_one_mask & bit) {
 373             mul_swizzle[i] = IMM_ZERO;
 374             add_swizzle[i] = IMM_NEG_ONE;
 375             need_add = TRUE;
 376          }
 377          else if (zero_mask & bit) {
 378             mul_swizzle[i] = IMM_ZERO;
 379             add_swizzle[i] = IMM_ZERO;
 380             need_add = TRUE;
 381          }
 382          else {
 383             add_swizzle[i] = IMM_ZERO;
 384             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 385             need_mul = TRUE;
 386             if (negate_mask & bit) {
 387                mul_swizzle[i] = IMM_NEG_ONE;
 388             }
 389             else {
 390                mul_swizzle[i] = IMM_ONE;
 391             }
 392          }
 393       }
 394    }
 395
 396    if (need_mul && need_add) {
 397       ureg_MAD( ureg,
 398                 dst,
 399                 swizzle_4v( src, src_swizzle ),
 400                 swizzle_4v( imm, mul_swizzle ),
 401                 swizzle_4v( imm, add_swizzle ) );
 402    }
 403    else if (need_mul) {
 404       ureg_MUL( ureg,
 405                 dst,
 406                 swizzle_4v( src, src_swizzle ),
 407                 swizzle_4v( imm, mul_swizzle ) );
 408    }
 409    else if (need_add) {
 410       ureg_MOV( ureg,
 411                 dst,
 412                 swizzle_4v( imm, add_swizzle ) );
 413    }
 414    else {
 415       debug_assert(0);
 416    }
 417
 418 #undef IMM_ZERO
 419 #undef IMM_ONE
 420 #undef IMM_NEG_ONE
 421 }
 422
 423
 424 static unsigned
 425 translate_opcode( unsigned op )
 426 {
 427    switch( op ) {
 428    case OPCODE_ARL:
 429       return TGSI_OPCODE_ARL;
 430    case OPCODE_ADD:
 431       return TGSI_OPCODE_ADD;
 432    case OPCODE_CMP:
 433       return TGSI_OPCODE_CMP;
 434    case OPCODE_COS:
 435       return TGSI_OPCODE_COS;
 436    case OPCODE_DP3:
 437       return TGSI_OPCODE_DP3;
 438    case OPCODE_DP4:
 439       return TGSI_OPCODE_DP4;
 440    case OPCODE_DPH:
 441       return TGSI_OPCODE_DPH;
 442    case OPCODE_DST:
 443       return TGSI_OPCODE_DST;
 444    case OPCODE_EX2:
 445       return TGSI_OPCODE_EX2;
 446    case OPCODE_EXP:
 447       return TGSI_OPCODE_EXP;
 448    case OPCODE_FLR:
 449       return TGSI_OPCODE_FLR;
 450    case OPCODE_FRC:
 451       return TGSI_OPCODE_FRC;
 452    case OPCODE_KIL:
 453       return TGSI_OPCODE_KILL_IF;
 454    case OPCODE_LG2:
 455       return TGSI_OPCODE_LG2;
 456    case OPCODE_LOG:
 457       return TGSI_OPCODE_LOG;
 458    case OPCODE_LIT:
 459       return TGSI_OPCODE_LIT;
 460    case OPCODE_LRP:
 461       return TGSI_OPCODE_LRP;
 462    case OPCODE_MAD:
 463       return TGSI_OPCODE_MAD;
 464    case OPCODE_MAX:
 465       return TGSI_OPCODE_MAX;
 466    case OPCODE_MIN:
 467       return TGSI_OPCODE_MIN;
 468    case OPCODE_MOV:
 469       return TGSI_OPCODE_MOV;
 470    case OPCODE_MUL:
 471       return TGSI_OPCODE_MUL;
 472    case OPCODE_POW:
 473       return TGSI_OPCODE_POW;
 474    case OPCODE_RCP:
 475       return TGSI_OPCODE_RCP;
 476    case OPCODE_SCS:
 477       return TGSI_OPCODE_SCS;
 478    case OPCODE_SGE:
 479       return TGSI_OPCODE_SGE;
 480    case OPCODE_SIN:
 481       return TGSI_OPCODE_SIN;
 482    case OPCODE_SLT:
 483       return TGSI_OPCODE_SLT;
 484    case OPCODE_SUB:
 485       return TGSI_OPCODE_SUB;
 486    case OPCODE_TEX:
 487       return TGSI_OPCODE_TEX;
 488    case OPCODE_TXB:
 489       return TGSI_OPCODE_TXB;
 490    case OPCODE_TXP:
 491       return TGSI_OPCODE_TXP;
 492    case OPCODE_XPD:
 493       return TGSI_OPCODE_XPD;
 494    case OPCODE_END:
 495       return TGSI_OPCODE_END;
 496    default:
 497       debug_assert( 0 );
 498       return TGSI_OPCODE_NOP;
 499    }
 500 }
 501
 502
 503 static void
 504 compile_instruction(
 505    struct gl_context *ctx,
 506    struct st_translate *t,
 507    const struct prog_instruction *inst)
 508 {
 509    struct ureg_program *ureg = t->ureg;
 510    GLuint i;
 511    struct ureg_dst dst[1] = { { 0 } };
 512    struct ureg_src src[4];
 513    unsigned num_dst;
 514    unsigned num_src;
 515
 516    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
 517    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 518
 519    if (num_dst)
 520       dst[0] = translate_dst( t,
 521                               &inst->DstReg,
 522                               inst->Saturate);
 523
 524    for (i = 0; i < num_src; i++)
 525       src[i] = translate_src( t, &inst->SrcReg[i] );
 526
 527    switch( inst->Opcode ) {
 528    case OPCODE_SWZ:
 529       emit_swz( t, dst[0], &inst->SrcReg[0] );
 530       return;
 531
 532    case OPCODE_TEX:
 533    case OPCODE_TXB:
 534    case OPCODE_TXP:
 535       src[num_src++] = t->samplers[inst->TexSrcUnit];
 536       ureg_tex_insn( ureg,
 537                      translate_opcode( inst->Opcode ),
 538                      dst, num_dst,
 539                      st_translate_texture_target( inst->TexSrcTarget,
 540                                                inst->TexShadow ),
 541                      NULL, 0,
 542                      src, num_src );
 543       return;
 544
 545    case OPCODE_SCS:
 546       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
 547       ureg_insn( ureg,
 548                  translate_opcode( inst->Opcode ),
 549                  dst, num_dst,
 550                  src, num_src );
 551       break;
 552
 553    case OPCODE_XPD:
 554       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
 555       ureg_insn( ureg,
 556                  translate_opcode( inst->Opcode ),
 557                  dst, num_dst,
 558                  src, num_src );
 559       break;
 560
 561    case OPCODE_RSQ:
 562       ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
 563       break;
 564
 565    case OPCODE_ABS:
 566       ureg_MOV(ureg, dst[0], ureg_abs(src[0]));
 567       break;
 568
 569    default:
 570       ureg_insn( ureg,
 571                  translate_opcode( inst->Opcode ),
 572                  dst, num_dst,
 573                  src, num_src );
 574       break;
 575    }
 576 }
 577
 578
 579 /**
 580  * Emit the TGSI instructions for inverting and adjusting WPOS.
 581  * This code is unavoidable because it also depends on whether
 582  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
 583  */
 584 static void
 585 emit_wpos_adjustment(struct gl_context *ctx,
 586                      struct st_translate *t,
 587                      const struct gl_program *program,
 588                      boolean invert,
 589                      GLfloat adjX, GLfloat adjY[2])
 590 {
 591    struct ureg_program *ureg = t->ureg;
 592
 593    /* Fragment program uses fragment position input.
 594     * Need to replace instances of INPUT[WPOS] with temp T
 595     * where T = INPUT[WPOS] by y is inverted.
 596     */
 597    static const gl_state_index wposTransformState[STATE_LENGTH]
 598       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
 599
 600    /* XXX: note we are modifying the incoming shader here!  Need to
 601     * do this before emitting the constant decls below, or this
 602     * will be missed:
 603     */
 604    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
 605                                                        wposTransformState);
 606
 607    struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
 608    struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
 609    struct ureg_src *wpos =
 610       ctx->Const.GLSLFragCoordIsSysVal ?
 611          &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
 612          &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
 613    struct ureg_src wpos_input = *wpos;
 614
 615    /* First, apply the coordinate shift: */
 616    if (adjX || adjY[0] || adjY[1]) {
 617       if (adjY[0] != adjY[1]) {
 618          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
 619           * depending on whether inversion is actually going to be applied
 620           * or not, which is determined by testing against the inversion
 621           * state variable used below, which will be either +1 or -1.
 622           */
 623          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
 624
 625          ureg_CMP(ureg, adj_temp,
 626                   ureg_scalar(wpostrans, invert ? 2 : 0),
 627                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
 628                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
 629          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
 630       } else {
 631          ureg_ADD(ureg, wpos_temp, wpos_input,
 632                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
 633       }
 634       wpos_input = ureg_src(wpos_temp);
 635    } else {
 636       /* MOV wpos_temp, input[wpos]
 637        */
 638       ureg_MOV( ureg, wpos_temp, wpos_input );
 639    }
 640
 641    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
 642     * inversion/identity, or the other way around if we're drawing to an FBO.
 643     */
 644    if (invert) {
 645       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
 646        */
 647       ureg_MAD( ureg,
 648                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 649                 wpos_input,
 650                 ureg_scalar(wpostrans, 0),
 651                 ureg_scalar(wpostrans, 1));
 652    } else {
 653       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
 654        */
 655       ureg_MAD( ureg,
 656                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 657                 wpos_input,
 658                 ureg_scalar(wpostrans, 2),
 659                 ureg_scalar(wpostrans, 3));
 660    }
 661
 662    /* Use wpos_temp as position input from here on:
 663     */
 664    *wpos = ureg_src(wpos_temp);
 665 }
 666
 667
 668 /**
 669  * Emit fragment position/coordinate code.
 670  */
 671 static void
 672 emit_wpos(struct st_context *st,
 673           struct st_translate *t,
 674           const struct gl_program *program,
 675           struct ureg_program *ureg)
 676 {
 677    struct pipe_screen *pscreen = st->pipe->screen;
 678    GLfloat adjX = 0.0f;
 679    GLfloat adjY[2] = { 0.0f, 0.0f };
 680    boolean invert = FALSE;
 681
 682    /* Query the pixel center conventions supported by the pipe driver and set
 683     * adjX, adjY to help out if it cannot handle the requested one internally.
 684     *
 685     * The bias of the y-coordinate depends on whether y-inversion takes place
 686     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
 687     * drawing to an FBO (causes additional inversion), and whether the pipe
 688     * driver origin and the requested origin differ (the latter condition is
 689     * stored in the 'invert' variable).
 690     *
 691     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
 692     *
 693     * center shift only:
 694     * i -> h: +0.5
 695     * h -> i: -0.5
 696     *
 697     * inversion only:
 698     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
 699     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
 700     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
 701     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
 702     *
 703     * inversion and center shift:
 704     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
 705     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
 706     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
 707     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
 708     */
 709    if (program->OriginUpperLeft) {
 710       /* Fragment shader wants origin in upper-left */
 711       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 712          /* the driver supports upper-left origin */
 713       }
 714       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 715          /* the driver supports lower-left origin, need to invert Y */
 716          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 717                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 718          invert = TRUE;
 719       }
 720       else
 721          assert(0);
 722    }
 723    else {
 724       /* Fragment shader wants origin in lower-left */
 725       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 726          /* the driver supports lower-left origin */
 727          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 728                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 729       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 730          /* the driver supports upper-left origin, need to invert Y */
 731          invert = TRUE;
 732       else
 733          assert(0);
 734    }
 735
 736    if (program->PixelCenterInteger) {
 737       /* Fragment shader wants pixel center integer */
 738       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 739          /* the driver supports pixel center integer */
 740          adjY[1] = 1.0f;
 741          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 742                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 743       }
 744       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 745          /* the driver supports pixel center half integer, need to bias X,Y */
 746          adjX = -0.5f;
 747          adjY[0] = -0.5f;
 748          adjY[1] = 0.5f;
 749       }
 750       else
 751          assert(0);
 752    }
 753    else {
 754       /* Fragment shader wants pixel center half integer */
 755       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 756          /* the driver supports pixel center half integer */
 757       }
 758       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 759          /* the driver supports pixel center integer, need to bias X,Y */
 760          adjX = adjY[0] = adjY[1] = 0.5f;
 761          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 762                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 763       }
 764       else
 765          assert(0);
 766    }
 767
 768    /* we invert after adjustment so that we avoid the MOV to temporary,
 769     * and reuse the adjustment ADD instead */
 770    emit_wpos_adjustment(st->ctx, t, program, invert, adjX, adjY);
 771 }
 772
 773
 774 /**
 775  * Translate Mesa program to TGSI format.
 776  * \param program  the program to translate
 777  * \param numInputs  number of input registers used
 778  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
 779  *                      input indexes
 780  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
 781  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
 782  *                            each input
 783  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
 784  * \param numOutputs  number of output registers used
 785  * \param outputMapping  maps Mesa fragment program outputs to TGSI
 786  *                       generic outputs
 787  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
 788  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
 789  *                             each output
 790  *
 791  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
 792  */
 793 enum pipe_error
 794 st_translate_mesa_program(
 795    struct gl_context *ctx,
 796    uint procType,
 797    struct ureg_program *ureg,
 798    const struct gl_program *program,
 799    GLuint numInputs,
 800    const GLuint inputMapping[],
 801    const ubyte inputSemanticName[],
 802    const ubyte inputSemanticIndex[],
 803    const GLuint interpMode[],
 804    GLuint numOutputs,
 805    const GLuint outputMapping[],
 806    const ubyte outputSemanticName[],
 807    const ubyte outputSemanticIndex[])
 808 {
 809    struct st_translate translate, *t;
 810    unsigned i;
 811    enum pipe_error ret = PIPE_OK;
 812
 813    assert(numInputs <= ARRAY_SIZE(t->inputs));
 814    assert(numOutputs <= ARRAY_SIZE(t->outputs));
 815
 816    t = &translate;
 817    memset(t, 0, sizeof *t);
 818
 819    t->procType = procType;
 820    t->inputMapping = inputMapping;
 821    t->outputMapping = outputMapping;
 822    t->ureg = ureg;
 823
 824    /*_mesa_print_program(program);*/
 825
 826    /*
 827     * Declare input attributes.
 828     */
 829    if (procType == PIPE_SHADER_FRAGMENT) {
 830       for (i = 0; i < numInputs; i++) {
 831          t->inputs[i] = ureg_DECL_fs_input(ureg,
 832                                            inputSemanticName[i],
 833                                            inputSemanticIndex[i],
 834                                            interpMode[i]);
 835       }
 836
 837       if (program->info.inputs_read & VARYING_BIT_POS) {
 838          /* Must do this after setting up t->inputs, and before
 839           * emitting constant references, below:
 840           */
 841          emit_wpos(st_context(ctx), t, program, ureg);
 842       }
 843
 844       /*
 845        * Declare output attributes.
 846        */
 847       for (i = 0; i < numOutputs; i++) {
 848          switch (outputSemanticName[i]) {
 849          case TGSI_SEMANTIC_POSITION:
 850             t->outputs[i] = ureg_DECL_output( ureg,
 851                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
 852                                               outputSemanticIndex[i] );
 853
 854             t->outputs[i] = ureg_writemask( t->outputs[i],
 855                                             TGSI_WRITEMASK_Z );
 856             break;
 857          case TGSI_SEMANTIC_STENCIL:
 858             t->outputs[i] = ureg_DECL_output( ureg,
 859                                               TGSI_SEMANTIC_STENCIL, /* Stencil */
 860                                               outputSemanticIndex[i] );
 861             t->outputs[i] = ureg_writemask( t->outputs[i],
 862                                             TGSI_WRITEMASK_Y );
 863             break;
 864          case TGSI_SEMANTIC_COLOR:
 865             t->outputs[i] = ureg_DECL_output( ureg,
 866                                               TGSI_SEMANTIC_COLOR,
 867                                               outputSemanticIndex[i] );
 868             break;
 869          default:
 870             debug_assert(0);
 871             return 0;
 872          }
 873       }
 874    }
 875    else if (procType == PIPE_SHADER_GEOMETRY) {
 876       for (i = 0; i < numInputs; i++) {
 877          t->inputs[i] = ureg_DECL_input(ureg,
 878                                         inputSemanticName[i],
 879                                         inputSemanticIndex[i], 0, 1);
 880       }
 881
 882       for (i = 0; i < numOutputs; i++) {
 883          t->outputs[i] = ureg_DECL_output( ureg,
 884                                            outputSemanticName[i],
 885                                            outputSemanticIndex[i] );
 886       }
 887    }
 888    else {
 889       assert(procType == PIPE_SHADER_VERTEX);
 890
 891       for (i = 0; i < numInputs; i++) {
 892          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
 893       }
 894
 895       for (i = 0; i < numOutputs; i++) {
 896          t->outputs[i] = ureg_DECL_output( ureg,
 897                                            outputSemanticName[i],
 898                                            outputSemanticIndex[i] );
 899          if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
 900             /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
 901             ureg_MOV(ureg,
 902                      ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
 903                      ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
 904             t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
 905          }
 906       }
 907    }
 908
 909    /* Declare address register.
 910     */
 911    if (program->arb.NumAddressRegs > 0) {
 912       debug_assert( program->arb.NumAddressRegs == 1 );
 913       t->address[0] = ureg_DECL_address( ureg );
 914    }
 915
 916    /* Declare misc input registers
 917     */
 918    {
 919       GLbitfield sysInputs = program->info.system_values_read;
 920
 921       for (i = 0; sysInputs; i++) {
 922          if (sysInputs & (1 << i)) {
 923             unsigned semName = _mesa_sysval_to_semantic(i);
 924
 925             t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
 926
 927             if (semName == TGSI_SEMANTIC_INSTANCEID ||
 928                 semName == TGSI_SEMANTIC_VERTEXID) {
 929                /* From Gallium perspective, these system values are always
 930                 * integer, and require native integer support.  However, if
 931                 * native integer is supported on the vertex stage but not the
 932                 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
 933                 * assumes these system values are floats. To resolve the
 934                 * inconsistency, we insert a U2F.
 935                 */
 936                struct st_context *st = st_context(ctx);
 937                struct pipe_screen *pscreen = st->pipe->screen;
 938                assert(procType == PIPE_SHADER_VERTEX);
 939                assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
 940                (void) pscreen;  /* silence non-debug build warnings */
 941                if (!ctx->Const.NativeIntegers) {
 942                   struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
 943                   ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
 944                   t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
 945                }
 946             }
 947
 948             if (procType == PIPE_SHADER_FRAGMENT &&
 949                 semName == TGSI_SEMANTIC_POSITION)
 950                emit_wpos(st_context(ctx), t, program, ureg);
 951
 952             sysInputs &= ~(1 << i);
 953          }
 954       }
 955    }
 956
 957    if (program->arb.IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
 958       /* If temps are accessed with indirect addressing, declare temporaries
 959        * in sequential order.  Else, we declare them on demand elsewhere.
 960        */
 961       for (i = 0; i < program->arb.NumTemporaries; i++) {
 962          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
 963          t->temps[i] = ureg_DECL_temporary( t->ureg );
 964       }
 965    }
 966
 967    /* Emit constants and immediates.  Mesa uses a single index space
 968     * for these, so we put all the translated regs in t->constants.
 969     */
 970    if (program->Parameters) {
 971       t->constants = calloc( program->Parameters->NumParameters,
 972                              sizeof t->constants[0] );
 973       if (t->constants == NULL) {
 974          ret = PIPE_ERROR_OUT_OF_MEMORY;
 975          goto out;
 976       }
 977
 978       for (i = 0; i < program->Parameters->NumParameters; i++) {
 979          switch (program->Parameters->Parameters[i].Type) {
 980          case PROGRAM_STATE_VAR:
 981          case PROGRAM_UNIFORM:
 982             t->constants[i] = ureg_DECL_constant( ureg, i );
 983             break;
 984
 985             /* Emit immediates only when there's no indirect addressing of
 986              * the const buffer.
 987              * FIXME: Be smarter and recognize param arrays:
 988              * indirect addressing is only valid within the referenced
 989              * array.
 990              */
 991          case PROGRAM_CONSTANT:
 992             if (program->arb.IndirectRegisterFiles & PROGRAM_ANY_CONST)
 993                t->constants[i] = ureg_DECL_constant( ureg, i );
 994             else
 995                t->constants[i] =
 996                   ureg_DECL_immediate( ureg,
 997                                        (const float*) program->Parameters->ParameterValues[i],
 998                                        4 );
 999             break;
1000          default:
1001             break;
1002          }
1003       }
1004    }
1005
1006    /* texture samplers */
1007    for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
1008       if (program->SamplersUsed & (1u << i)) {
1009          unsigned target =
1010             translate_texture_index(program->TexturesUsed[i],
1011                                     !!(program->ShadowSamplers & (1 << i)));
1012          t->samplers[i] = ureg_DECL_sampler( ureg, i );
1013          ureg_DECL_sampler_view(ureg, i, target,
1014                                 TGSI_RETURN_TYPE_FLOAT,
1015                                 TGSI_RETURN_TYPE_FLOAT,
1016                                 TGSI_RETURN_TYPE_FLOAT,
1017                                 TGSI_RETURN_TYPE_FLOAT);
1018
1019       }
1020    }
1021
1022    /* Emit each instruction in turn:
1023     */
1024    for (i = 0; i < program->arb.NumInstructions; i++)
1025       compile_instruction(ctx, t, &program->arb.Instructions[i]);
1026
1027 out:
1028    free(t->constants);
1029    return ret;
1030 }