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mesa: convert _NEW_RASTERIZER_DISCARD to a driver flag
[mesa.git] / src / mesa / state_tracker / st_mesa_to_tgsi.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * \author
30 * Michal Krol,
31 * Keith Whitwell
32 */
33
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47
48
49 #define PROGRAM_ANY_CONST ((1 << PROGRAM_LOCAL_PARAM) | \
50 (1 << PROGRAM_ENV_PARAM) | \
51 (1 << PROGRAM_STATE_VAR) | \
52 (1 << PROGRAM_CONSTANT) | \
53 (1 << PROGRAM_UNIFORM))
54
55
56 struct label {
57 unsigned branch_target;
58 unsigned token;
59 };
60
61
62 /**
63 * Intermediate state used during shader translation.
64 */
65 struct st_translate {
66 struct ureg_program *ureg;
67
68 struct ureg_dst temps[MAX_PROGRAM_TEMPS];
69 struct ureg_src *constants;
70 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
71 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
72 struct ureg_dst address[1];
73 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
74 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
75
76 const GLuint *inputMapping;
77 const GLuint *outputMapping;
78
79 /* For every instruction that contains a label (eg CALL), keep
80 * details so that we can go back afterwards and emit the correct
81 * tgsi instruction number for each label.
82 */
83 struct label *labels;
84 unsigned labels_size;
85 unsigned labels_count;
86
87 /* Keep a record of the tgsi instruction number that each mesa
88 * instruction starts at, will be used to fix up labels after
89 * translation.
90 */
91 unsigned *insn;
92 unsigned insn_size;
93 unsigned insn_count;
94
95 unsigned procType; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
96
97 boolean error;
98 };
99
100
101 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
102 static unsigned mesa_sysval_to_semantic[SYSTEM_VALUE_MAX] = {
103 TGSI_SEMANTIC_FACE,
104 TGSI_SEMANTIC_VERTEXID,
105 TGSI_SEMANTIC_INSTANCEID
106 };
107
108
109 /**
110 * Make note of a branch to a label in the TGSI code.
111 * After we've emitted all instructions, we'll go over the list
112 * of labels built here and patch the TGSI code with the actual
113 * location of each label.
114 */
115 static unsigned *get_label( struct st_translate *t,
116 unsigned branch_target )
117 {
118 unsigned i;
119
120 if (t->labels_count + 1 >= t->labels_size) {
121 t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
122 t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
123 if (t->labels == NULL) {
124 static unsigned dummy;
125 t->error = TRUE;
126 return &dummy;
127 }
128 }
129
130 i = t->labels_count++;
131 t->labels[i].branch_target = branch_target;
132 return &t->labels[i].token;
133 }
134
135
136 /**
137 * Called prior to emitting the TGSI code for each Mesa instruction.
138 * Allocate additional space for instructions if needed.
139 * Update the insn[] array so the next Mesa instruction points to
140 * the next TGSI instruction.
141 */
142 static void set_insn_start( struct st_translate *t,
143 unsigned start )
144 {
145 if (t->insn_count + 1 >= t->insn_size) {
146 t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
147 t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
148 if (t->insn == NULL) {
149 t->error = TRUE;
150 return;
151 }
152 }
153
154 t->insn[t->insn_count++] = start;
155 }
156
157
158 /**
159 * Map a Mesa dst register to a TGSI ureg_dst register.
160 */
161 static struct ureg_dst
162 dst_register( struct st_translate *t,
163 gl_register_file file,
164 GLuint index )
165 {
166 switch( file ) {
167 case PROGRAM_UNDEFINED:
168 return ureg_dst_undef();
169
170 case PROGRAM_TEMPORARY:
171 if (ureg_dst_is_undef(t->temps[index]))
172 t->temps[index] = ureg_DECL_temporary( t->ureg );
173
174 return t->temps[index];
175
176 case PROGRAM_OUTPUT:
177 if (t->procType == TGSI_PROCESSOR_VERTEX)
178 assert(index < VARYING_SLOT_MAX);
179 else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
180 assert(index < FRAG_RESULT_MAX);
181 else
182 assert(index < VARYING_SLOT_MAX);
183
184 assert(t->outputMapping[index] < Elements(t->outputs));
185
186 return t->outputs[t->outputMapping[index]];
187
188 case PROGRAM_ADDRESS:
189 return t->address[index];
190
191 default:
192 debug_assert( 0 );
193 return ureg_dst_undef();
194 }
195 }
196
197
198 /**
199 * Map a Mesa src register to a TGSI ureg_src register.
200 */
201 static struct ureg_src
202 src_register( struct st_translate *t,
203 gl_register_file file,
204 GLint index )
205 {
206 switch( file ) {
207 case PROGRAM_UNDEFINED:
208 return ureg_src_undef();
209
210 case PROGRAM_TEMPORARY:
211 assert(index >= 0);
212 assert(index < Elements(t->temps));
213 if (ureg_dst_is_undef(t->temps[index]))
214 t->temps[index] = ureg_DECL_temporary( t->ureg );
215 return ureg_src(t->temps[index]);
216
217 case PROGRAM_ENV_PARAM:
218 case PROGRAM_LOCAL_PARAM:
219 case PROGRAM_UNIFORM:
220 assert(index >= 0);
221 return t->constants[index];
222 case PROGRAM_STATE_VAR:
223 case PROGRAM_CONSTANT: /* ie, immediate */
224 if (index < 0)
225 return ureg_DECL_constant( t->ureg, 0 );
226 else
227 return t->constants[index];
228
229 case PROGRAM_INPUT:
230 assert(t->inputMapping[index] < Elements(t->inputs));
231 return t->inputs[t->inputMapping[index]];
232
233 case PROGRAM_OUTPUT:
234 assert(t->outputMapping[index] < Elements(t->outputs));
235 return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
236
237 case PROGRAM_ADDRESS:
238 return ureg_src(t->address[index]);
239
240 case PROGRAM_SYSTEM_VALUE:
241 assert(index < Elements(t->systemValues));
242 return t->systemValues[index];
243
244 default:
245 debug_assert( 0 );
246 return ureg_src_undef();
247 }
248 }
249
250
251 /**
252 * Map mesa texture target to TGSI texture target.
253 */
254 unsigned
255 st_translate_texture_target( GLuint textarget,
256 GLboolean shadow )
257 {
258 if (shadow) {
259 switch( textarget ) {
260 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_SHADOW1D;
261 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_SHADOW2D;
262 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
263 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
264 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
265 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
266 case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
267 default: break;
268 }
269 }
270
271 switch( textarget ) {
272 case TEXTURE_2D_MULTISAMPLE_INDEX: return TGSI_TEXTURE_2D_MSAA;
273 case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY_MSAA;
274 case TEXTURE_BUFFER_INDEX: return TGSI_TEXTURE_BUFFER;
275 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_1D;
276 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_2D;
277 case TEXTURE_3D_INDEX: return TGSI_TEXTURE_3D;
278 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
279 case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_CUBE_ARRAY;
280 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
281 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_1D_ARRAY;
282 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY;
283 case TEXTURE_EXTERNAL_INDEX: return TGSI_TEXTURE_2D;
284 default:
285 debug_assert( 0 );
286 return TGSI_TEXTURE_1D;
287 }
288 }
289
290
291 /**
292 * Create a TGSI ureg_dst register from a Mesa dest register.
293 */
294 static struct ureg_dst
295 translate_dst( struct st_translate *t,
296 const struct prog_dst_register *DstReg,
297 boolean saturate,
298 boolean clamp_color)
299 {
300 struct ureg_dst dst = dst_register( t,
301 DstReg->File,
302 DstReg->Index );
303
304 dst = ureg_writemask( dst,
305 DstReg->WriteMask );
306
307 if (saturate)
308 dst = ureg_saturate( dst );
309 else if (clamp_color && DstReg->File == PROGRAM_OUTPUT) {
310 /* Clamp colors for ARB_color_buffer_float. */
311 switch (t->procType) {
312 case TGSI_PROCESSOR_VERTEX:
313 /* XXX if the geometry shader is present, this must be done there
314 * instead of here. */
315 if (DstReg->Index == VARYING_SLOT_COL0 ||
316 DstReg->Index == VARYING_SLOT_COL1 ||
317 DstReg->Index == VARYING_SLOT_BFC0 ||
318 DstReg->Index == VARYING_SLOT_BFC1) {
319 dst = ureg_saturate(dst);
320 }
321 break;
322
323 case TGSI_PROCESSOR_FRAGMENT:
324 if (DstReg->Index >= FRAG_RESULT_COLOR) {
325 dst = ureg_saturate(dst);
326 }
327 break;
328 }
329 }
330
331 if (DstReg->RelAddr)
332 dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
333
334 return dst;
335 }
336
337
338 /**
339 * Create a TGSI ureg_src register from a Mesa src register.
340 */
341 static struct ureg_src
342 translate_src( struct st_translate *t,
343 const struct prog_src_register *SrcReg )
344 {
345 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
346
347 if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
348 src = src_register( t, SrcReg->File, SrcReg->Index2 );
349 if (SrcReg->RelAddr2)
350 src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
351 SrcReg->Index);
352 else
353 src = ureg_src_dimension( src, SrcReg->Index);
354 }
355
356 src = ureg_swizzle( src,
357 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
358 GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
359 GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
360 GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
361
362 if (SrcReg->Negate == NEGATE_XYZW)
363 src = ureg_negate(src);
364
365 if (SrcReg->Abs)
366 src = ureg_abs(src);
367
368 if (SrcReg->RelAddr) {
369 src = ureg_src_indirect( src, ureg_src(t->address[0]));
370 if (SrcReg->File != PROGRAM_INPUT &&
371 SrcReg->File != PROGRAM_OUTPUT) {
372 /* If SrcReg->Index was negative, it was set to zero in
373 * src_register(). Reassign it now. But don't do this
374 * for input/output regs since they get remapped while
375 * const buffers don't.
376 */
377 src.Index = SrcReg->Index;
378 }
379 }
380
381 return src;
382 }
383
384
385 static struct ureg_src swizzle_4v( struct ureg_src src,
386 const unsigned *swz )
387 {
388 return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
389 }
390
391
392 /**
393 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
394 *
395 * SWZ dst, src.x-y10
396 *
397 * becomes:
398 *
399 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
400 */
401 static void emit_swz( struct st_translate *t,
402 struct ureg_dst dst,
403 const struct prog_src_register *SrcReg )
404 {
405 struct ureg_program *ureg = t->ureg;
406 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
407
408 unsigned negate_mask = SrcReg->Negate;
409
410 unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
411 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
412 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
413 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
414
415 unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
416 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
417 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
418 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
419
420 unsigned negative_one_mask = one_mask & negate_mask;
421 unsigned positive_one_mask = one_mask & ~negate_mask;
422
423 struct ureg_src imm;
424 unsigned i;
425 unsigned mul_swizzle[4] = {0,0,0,0};
426 unsigned add_swizzle[4] = {0,0,0,0};
427 unsigned src_swizzle[4] = {0,0,0,0};
428 boolean need_add = FALSE;
429 boolean need_mul = FALSE;
430
431 if (dst.WriteMask == 0)
432 return;
433
434 /* Is this just a MOV?
435 */
436 if (zero_mask == 0 &&
437 one_mask == 0 &&
438 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
439 {
440 ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
441 return;
442 }
443
444 #define IMM_ZERO 0
445 #define IMM_ONE 1
446 #define IMM_NEG_ONE 2
447
448 imm = ureg_imm3f( ureg, 0, 1, -1 );
449
450 for (i = 0; i < 4; i++) {
451 unsigned bit = 1 << i;
452
453 if (dst.WriteMask & bit) {
454 if (positive_one_mask & bit) {
455 mul_swizzle[i] = IMM_ZERO;
456 add_swizzle[i] = IMM_ONE;
457 need_add = TRUE;
458 }
459 else if (negative_one_mask & bit) {
460 mul_swizzle[i] = IMM_ZERO;
461 add_swizzle[i] = IMM_NEG_ONE;
462 need_add = TRUE;
463 }
464 else if (zero_mask & bit) {
465 mul_swizzle[i] = IMM_ZERO;
466 add_swizzle[i] = IMM_ZERO;
467 need_add = TRUE;
468 }
469 else {
470 add_swizzle[i] = IMM_ZERO;
471 src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
472 need_mul = TRUE;
473 if (negate_mask & bit) {
474 mul_swizzle[i] = IMM_NEG_ONE;
475 }
476 else {
477 mul_swizzle[i] = IMM_ONE;
478 }
479 }
480 }
481 }
482
483 if (need_mul && need_add) {
484 ureg_MAD( ureg,
485 dst,
486 swizzle_4v( src, src_swizzle ),
487 swizzle_4v( imm, mul_swizzle ),
488 swizzle_4v( imm, add_swizzle ) );
489 }
490 else if (need_mul) {
491 ureg_MUL( ureg,
492 dst,
493 swizzle_4v( src, src_swizzle ),
494 swizzle_4v( imm, mul_swizzle ) );
495 }
496 else if (need_add) {
497 ureg_MOV( ureg,
498 dst,
499 swizzle_4v( imm, add_swizzle ) );
500 }
501 else {
502 debug_assert(0);
503 }
504
505 #undef IMM_ZERO
506 #undef IMM_ONE
507 #undef IMM_NEG_ONE
508 }
509
510
511 /**
512 * Negate the value of DDY to match GL semantics where (0,0) is the
513 * lower-left corner of the window.
514 * Note that the GL_ARB_fragment_coord_conventions extension will
515 * effect this someday.
516 */
517 static void emit_ddy( struct st_translate *t,
518 struct ureg_dst dst,
519 const struct prog_src_register *SrcReg )
520 {
521 struct ureg_program *ureg = t->ureg;
522 struct ureg_src src = translate_src( t, SrcReg );
523 src = ureg_negate( src );
524 ureg_DDY( ureg, dst, src );
525 }
526
527
528
529 static unsigned
530 translate_opcode( unsigned op )
531 {
532 switch( op ) {
533 case OPCODE_ARL:
534 return TGSI_OPCODE_ARL;
535 case OPCODE_ABS:
536 return TGSI_OPCODE_ABS;
537 case OPCODE_ADD:
538 return TGSI_OPCODE_ADD;
539 case OPCODE_BGNLOOP:
540 return TGSI_OPCODE_BGNLOOP;
541 case OPCODE_BGNSUB:
542 return TGSI_OPCODE_BGNSUB;
543 case OPCODE_BRK:
544 return TGSI_OPCODE_BRK;
545 case OPCODE_CAL:
546 return TGSI_OPCODE_CAL;
547 case OPCODE_CMP:
548 return TGSI_OPCODE_CMP;
549 case OPCODE_CONT:
550 return TGSI_OPCODE_CONT;
551 case OPCODE_COS:
552 return TGSI_OPCODE_COS;
553 case OPCODE_DDX:
554 return TGSI_OPCODE_DDX;
555 case OPCODE_DDY:
556 return TGSI_OPCODE_DDY;
557 case OPCODE_DP2:
558 return TGSI_OPCODE_DP2;
559 case OPCODE_DP2A:
560 return TGSI_OPCODE_DP2A;
561 case OPCODE_DP3:
562 return TGSI_OPCODE_DP3;
563 case OPCODE_DP4:
564 return TGSI_OPCODE_DP4;
565 case OPCODE_DPH:
566 return TGSI_OPCODE_DPH;
567 case OPCODE_DST:
568 return TGSI_OPCODE_DST;
569 case OPCODE_ELSE:
570 return TGSI_OPCODE_ELSE;
571 case OPCODE_ENDIF:
572 return TGSI_OPCODE_ENDIF;
573 case OPCODE_ENDLOOP:
574 return TGSI_OPCODE_ENDLOOP;
575 case OPCODE_ENDSUB:
576 return TGSI_OPCODE_ENDSUB;
577 case OPCODE_EX2:
578 return TGSI_OPCODE_EX2;
579 case OPCODE_EXP:
580 return TGSI_OPCODE_EXP;
581 case OPCODE_FLR:
582 return TGSI_OPCODE_FLR;
583 case OPCODE_FRC:
584 return TGSI_OPCODE_FRC;
585 case OPCODE_IF:
586 return TGSI_OPCODE_IF;
587 case OPCODE_TRUNC:
588 return TGSI_OPCODE_TRUNC;
589 case OPCODE_KIL:
590 return TGSI_OPCODE_KIL;
591 case OPCODE_KIL_NV:
592 return TGSI_OPCODE_KILP;
593 case OPCODE_LG2:
594 return TGSI_OPCODE_LG2;
595 case OPCODE_LOG:
596 return TGSI_OPCODE_LOG;
597 case OPCODE_LIT:
598 return TGSI_OPCODE_LIT;
599 case OPCODE_LRP:
600 return TGSI_OPCODE_LRP;
601 case OPCODE_MAD:
602 return TGSI_OPCODE_MAD;
603 case OPCODE_MAX:
604 return TGSI_OPCODE_MAX;
605 case OPCODE_MIN:
606 return TGSI_OPCODE_MIN;
607 case OPCODE_MOV:
608 return TGSI_OPCODE_MOV;
609 case OPCODE_MUL:
610 return TGSI_OPCODE_MUL;
611 case OPCODE_NOP:
612 return TGSI_OPCODE_NOP;
613 case OPCODE_NRM3:
614 return TGSI_OPCODE_NRM;
615 case OPCODE_NRM4:
616 return TGSI_OPCODE_NRM4;
617 case OPCODE_POW:
618 return TGSI_OPCODE_POW;
619 case OPCODE_RCP:
620 return TGSI_OPCODE_RCP;
621 case OPCODE_RET:
622 return TGSI_OPCODE_RET;
623 case OPCODE_RSQ:
624 return TGSI_OPCODE_RSQ;
625 case OPCODE_SCS:
626 return TGSI_OPCODE_SCS;
627 case OPCODE_SEQ:
628 return TGSI_OPCODE_SEQ;
629 case OPCODE_SGE:
630 return TGSI_OPCODE_SGE;
631 case OPCODE_SGT:
632 return TGSI_OPCODE_SGT;
633 case OPCODE_SIN:
634 return TGSI_OPCODE_SIN;
635 case OPCODE_SLE:
636 return TGSI_OPCODE_SLE;
637 case OPCODE_SLT:
638 return TGSI_OPCODE_SLT;
639 case OPCODE_SNE:
640 return TGSI_OPCODE_SNE;
641 case OPCODE_SSG:
642 return TGSI_OPCODE_SSG;
643 case OPCODE_SUB:
644 return TGSI_OPCODE_SUB;
645 case OPCODE_TEX:
646 return TGSI_OPCODE_TEX;
647 case OPCODE_TXB:
648 return TGSI_OPCODE_TXB;
649 case OPCODE_TXD:
650 return TGSI_OPCODE_TXD;
651 case OPCODE_TXL:
652 return TGSI_OPCODE_TXL;
653 case OPCODE_TXP:
654 return TGSI_OPCODE_TXP;
655 case OPCODE_XPD:
656 return TGSI_OPCODE_XPD;
657 case OPCODE_END:
658 return TGSI_OPCODE_END;
659 default:
660 debug_assert( 0 );
661 return TGSI_OPCODE_NOP;
662 }
663 }
664
665
666 static void
667 compile_instruction(
668 struct gl_context *ctx,
669 struct st_translate *t,
670 const struct prog_instruction *inst,
671 boolean clamp_dst_color_output)
672 {
673 struct ureg_program *ureg = t->ureg;
674 GLuint i;
675 struct ureg_dst dst[1] = { { 0 } };
676 struct ureg_src src[4];
677 unsigned num_dst;
678 unsigned num_src;
679
680 num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
681 num_src = _mesa_num_inst_src_regs( inst->Opcode );
682
683 if (num_dst)
684 dst[0] = translate_dst( t,
685 &inst->DstReg,
686 inst->SaturateMode,
687 clamp_dst_color_output);
688
689 for (i = 0; i < num_src; i++)
690 src[i] = translate_src( t, &inst->SrcReg[i] );
691
692 switch( inst->Opcode ) {
693 case OPCODE_SWZ:
694 emit_swz( t, dst[0], &inst->SrcReg[0] );
695 return;
696
697 case OPCODE_BGNLOOP:
698 case OPCODE_CAL:
699 case OPCODE_ELSE:
700 case OPCODE_ENDLOOP:
701 debug_assert(num_dst == 0);
702 ureg_label_insn( ureg,
703 translate_opcode( inst->Opcode ),
704 src, num_src,
705 get_label( t, inst->BranchTarget ));
706 return;
707
708 case OPCODE_IF:
709 debug_assert(num_dst == 0);
710 ureg_label_insn( ureg,
711 ctx->Const.NativeIntegers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF,
712 src, num_src,
713 get_label( t, inst->BranchTarget ));
714 return;
715
716 case OPCODE_TEX:
717 case OPCODE_TXB:
718 case OPCODE_TXD:
719 case OPCODE_TXL:
720 case OPCODE_TXP:
721 src[num_src++] = t->samplers[inst->TexSrcUnit];
722 ureg_tex_insn( ureg,
723 translate_opcode( inst->Opcode ),
724 dst, num_dst,
725 st_translate_texture_target( inst->TexSrcTarget,
726 inst->TexShadow ),
727 NULL, 0,
728 src, num_src );
729 return;
730
731 case OPCODE_SCS:
732 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
733 ureg_insn( ureg,
734 translate_opcode( inst->Opcode ),
735 dst, num_dst,
736 src, num_src );
737 break;
738
739 case OPCODE_XPD:
740 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
741 ureg_insn( ureg,
742 translate_opcode( inst->Opcode ),
743 dst, num_dst,
744 src, num_src );
745 break;
746
747 case OPCODE_NOISE1:
748 case OPCODE_NOISE2:
749 case OPCODE_NOISE3:
750 case OPCODE_NOISE4:
751 /* At some point, a motivated person could add a better
752 * implementation of noise. Currently not even the nvidia
753 * binary drivers do anything more than this. In any case, the
754 * place to do this is in the GL state tracker, not the poor
755 * driver.
756 */
757 ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
758 break;
759
760 case OPCODE_DDY:
761 emit_ddy( t, dst[0], &inst->SrcReg[0] );
762 break;
763
764 default:
765 ureg_insn( ureg,
766 translate_opcode( inst->Opcode ),
767 dst, num_dst,
768 src, num_src );
769 break;
770 }
771 }
772
773
774 /**
775 * Emit the TGSI instructions for inverting and adjusting WPOS.
776 * This code is unavoidable because it also depends on whether
777 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
778 */
779 static void
780 emit_wpos_adjustment( struct st_translate *t,
781 const struct gl_program *program,
782 boolean invert,
783 GLfloat adjX, GLfloat adjY[2])
784 {
785 struct ureg_program *ureg = t->ureg;
786
787 /* Fragment program uses fragment position input.
788 * Need to replace instances of INPUT[WPOS] with temp T
789 * where T = INPUT[WPOS] by y is inverted.
790 */
791 static const gl_state_index wposTransformState[STATE_LENGTH]
792 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
793
794 /* XXX: note we are modifying the incoming shader here! Need to
795 * do this before emitting the constant decls below, or this
796 * will be missed:
797 */
798 unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
799 wposTransformState);
800
801 struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
802 struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
803 struct ureg_src wpos_input = t->inputs[t->inputMapping[VARYING_SLOT_POS]];
804
805 /* First, apply the coordinate shift: */
806 if (adjX || adjY[0] || adjY[1]) {
807 if (adjY[0] != adjY[1]) {
808 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
809 * depending on whether inversion is actually going to be applied
810 * or not, which is determined by testing against the inversion
811 * state variable used below, which will be either +1 or -1.
812 */
813 struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
814
815 ureg_CMP(ureg, adj_temp,
816 ureg_scalar(wpostrans, invert ? 2 : 0),
817 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
818 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
819 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
820 } else {
821 ureg_ADD(ureg, wpos_temp, wpos_input,
822 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
823 }
824 wpos_input = ureg_src(wpos_temp);
825 } else {
826 /* MOV wpos_temp, input[wpos]
827 */
828 ureg_MOV( ureg, wpos_temp, wpos_input );
829 }
830
831 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
832 * inversion/identity, or the other way around if we're drawing to an FBO.
833 */
834 if (invert) {
835 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
836 */
837 ureg_MAD( ureg,
838 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
839 wpos_input,
840 ureg_scalar(wpostrans, 0),
841 ureg_scalar(wpostrans, 1));
842 } else {
843 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
844 */
845 ureg_MAD( ureg,
846 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
847 wpos_input,
848 ureg_scalar(wpostrans, 2),
849 ureg_scalar(wpostrans, 3));
850 }
851
852 /* Use wpos_temp as position input from here on:
853 */
854 t->inputs[t->inputMapping[VARYING_SLOT_POS]] = ureg_src(wpos_temp);
855 }
856
857
858 /**
859 * Emit fragment position/ooordinate code.
860 */
861 static void
862 emit_wpos(struct st_context *st,
863 struct st_translate *t,
864 const struct gl_program *program,
865 struct ureg_program *ureg)
866 {
867 const struct gl_fragment_program *fp =
868 (const struct gl_fragment_program *) program;
869 struct pipe_screen *pscreen = st->pipe->screen;
870 GLfloat adjX = 0.0f;
871 GLfloat adjY[2] = { 0.0f, 0.0f };
872 boolean invert = FALSE;
873
874 /* Query the pixel center conventions supported by the pipe driver and set
875 * adjX, adjY to help out if it cannot handle the requested one internally.
876 *
877 * The bias of the y-coordinate depends on whether y-inversion takes place
878 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
879 * drawing to an FBO (causes additional inversion), and whether the the pipe
880 * driver origin and the requested origin differ (the latter condition is
881 * stored in the 'invert' variable).
882 *
883 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
884 *
885 * center shift only:
886 * i -> h: +0.5
887 * h -> i: -0.5
888 *
889 * inversion only:
890 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
891 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
892 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
893 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
894 *
895 * inversion and center shift:
896 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
897 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
898 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
899 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
900 */
901 if (fp->OriginUpperLeft) {
902 /* Fragment shader wants origin in upper-left */
903 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
904 /* the driver supports upper-left origin */
905 }
906 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
907 /* the driver supports lower-left origin, need to invert Y */
908 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
909 invert = TRUE;
910 }
911 else
912 assert(0);
913 }
914 else {
915 /* Fragment shader wants origin in lower-left */
916 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
917 /* the driver supports lower-left origin */
918 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
919 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
920 /* the driver supports upper-left origin, need to invert Y */
921 invert = TRUE;
922 else
923 assert(0);
924 }
925
926 if (fp->PixelCenterInteger) {
927 /* Fragment shader wants pixel center integer */
928 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
929 /* the driver supports pixel center integer */
930 adjY[1] = 1.0f;
931 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
932 }
933 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
934 /* the driver supports pixel center half integer, need to bias X,Y */
935 adjX = -0.5f;
936 adjY[0] = -0.5f;
937 adjY[1] = 0.5f;
938 }
939 else
940 assert(0);
941 }
942 else {
943 /* Fragment shader wants pixel center half integer */
944 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
945 /* the driver supports pixel center half integer */
946 }
947 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
948 /* the driver supports pixel center integer, need to bias X,Y */
949 adjX = adjY[0] = adjY[1] = 0.5f;
950 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
951 }
952 else
953 assert(0);
954 }
955
956 /* we invert after adjustment so that we avoid the MOV to temporary,
957 * and reuse the adjustment ADD instead */
958 emit_wpos_adjustment(t, program, invert, adjX, adjY);
959 }
960
961
962 /**
963 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
964 * TGSI uses +1 for front, -1 for back.
965 * This function converts the TGSI value to the GL value. Simply clamping/
966 * saturating the value to [0,1] does the job.
967 */
968 static void
969 emit_face_var( struct st_translate *t,
970 const struct gl_program *program )
971 {
972 struct ureg_program *ureg = t->ureg;
973 struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
974 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
975
976 /* MOV_SAT face_temp, input[face]
977 */
978 face_temp = ureg_saturate( face_temp );
979 ureg_MOV( ureg, face_temp, face_input );
980
981 /* Use face_temp as face input from here on:
982 */
983 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
984 }
985
986
987 static void
988 emit_edgeflags( struct st_translate *t,
989 const struct gl_program *program )
990 {
991 struct ureg_program *ureg = t->ureg;
992 struct ureg_dst edge_dst = t->outputs[t->outputMapping[VARYING_SLOT_EDGE]];
993 struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
994
995 ureg_MOV( ureg, edge_dst, edge_src );
996 }
997
998
999 /**
1000 * Translate Mesa program to TGSI format.
1001 * \param program the program to translate
1002 * \param numInputs number of input registers used
1003 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
1004 * input indexes
1005 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
1006 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
1007 * each input
1008 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
1009 * \param numOutputs number of output registers used
1010 * \param outputMapping maps Mesa fragment program outputs to TGSI
1011 * generic outputs
1012 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
1013 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
1014 * each output
1015 *
1016 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
1017 */
1018 enum pipe_error
1019 st_translate_mesa_program(
1020 struct gl_context *ctx,
1021 uint procType,
1022 struct ureg_program *ureg,
1023 const struct gl_program *program,
1024 GLuint numInputs,
1025 const GLuint inputMapping[],
1026 const ubyte inputSemanticName[],
1027 const ubyte inputSemanticIndex[],
1028 const GLuint interpMode[],
1029 GLuint numOutputs,
1030 const GLuint outputMapping[],
1031 const ubyte outputSemanticName[],
1032 const ubyte outputSemanticIndex[],
1033 boolean passthrough_edgeflags,
1034 boolean clamp_color)
1035 {
1036 struct st_translate translate, *t;
1037 unsigned i;
1038 enum pipe_error ret = PIPE_OK;
1039
1040 assert(numInputs <= Elements(t->inputs));
1041 assert(numOutputs <= Elements(t->outputs));
1042
1043 t = &translate;
1044 memset(t, 0, sizeof *t);
1045
1046 t->procType = procType;
1047 t->inputMapping = inputMapping;
1048 t->outputMapping = outputMapping;
1049 t->ureg = ureg;
1050
1051 /*_mesa_print_program(program);*/
1052
1053 /*
1054 * Declare input attributes.
1055 */
1056 if (procType == TGSI_PROCESSOR_FRAGMENT) {
1057 for (i = 0; i < numInputs; i++) {
1058 t->inputs[i] = ureg_DECL_fs_input(ureg,
1059 inputSemanticName[i],
1060 inputSemanticIndex[i],
1061 interpMode[i]);
1062 }
1063
1064 if (program->InputsRead & VARYING_BIT_POS) {
1065 /* Must do this after setting up t->inputs, and before
1066 * emitting constant references, below:
1067 */
1068 emit_wpos(st_context(ctx), t, program, ureg);
1069 }
1070
1071 if (program->InputsRead & VARYING_BIT_FACE) {
1072 emit_face_var( t, program );
1073 }
1074
1075 /*
1076 * Declare output attributes.
1077 */
1078 for (i = 0; i < numOutputs; i++) {
1079 switch (outputSemanticName[i]) {
1080 case TGSI_SEMANTIC_POSITION:
1081 t->outputs[i] = ureg_DECL_output( ureg,
1082 TGSI_SEMANTIC_POSITION, /* Z / Depth */
1083 outputSemanticIndex[i] );
1084
1085 t->outputs[i] = ureg_writemask( t->outputs[i],
1086 TGSI_WRITEMASK_Z );
1087 break;
1088 case TGSI_SEMANTIC_STENCIL:
1089 t->outputs[i] = ureg_DECL_output( ureg,
1090 TGSI_SEMANTIC_STENCIL, /* Stencil */
1091 outputSemanticIndex[i] );
1092 t->outputs[i] = ureg_writemask( t->outputs[i],
1093 TGSI_WRITEMASK_Y );
1094 break;
1095 case TGSI_SEMANTIC_COLOR:
1096 t->outputs[i] = ureg_DECL_output( ureg,
1097 TGSI_SEMANTIC_COLOR,
1098 outputSemanticIndex[i] );
1099 break;
1100 default:
1101 debug_assert(0);
1102 return 0;
1103 }
1104 }
1105 }
1106 else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1107 for (i = 0; i < numInputs; i++) {
1108 t->inputs[i] = ureg_DECL_gs_input(ureg,
1109 i,
1110 inputSemanticName[i],
1111 inputSemanticIndex[i]);
1112 }
1113
1114 for (i = 0; i < numOutputs; i++) {
1115 t->outputs[i] = ureg_DECL_output( ureg,
1116 outputSemanticName[i],
1117 outputSemanticIndex[i] );
1118 }
1119 }
1120 else {
1121 assert(procType == TGSI_PROCESSOR_VERTEX);
1122
1123 for (i = 0; i < numInputs; i++) {
1124 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1125 }
1126
1127 for (i = 0; i < numOutputs; i++) {
1128 t->outputs[i] = ureg_DECL_output( ureg,
1129 outputSemanticName[i],
1130 outputSemanticIndex[i] );
1131 }
1132 if (passthrough_edgeflags)
1133 emit_edgeflags( t, program );
1134 }
1135
1136 /* Declare address register.
1137 */
1138 if (program->NumAddressRegs > 0) {
1139 debug_assert( program->NumAddressRegs == 1 );
1140 t->address[0] = ureg_DECL_address( ureg );
1141 }
1142
1143 /* Declare misc input registers
1144 */
1145 {
1146 GLbitfield sysInputs = program->SystemValuesRead;
1147 unsigned numSys = 0;
1148 for (i = 0; sysInputs; i++) {
1149 if (sysInputs & (1 << i)) {
1150 unsigned semName = mesa_sysval_to_semantic[i];
1151 t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1152 if (semName == TGSI_SEMANTIC_INSTANCEID ||
1153 semName == TGSI_SEMANTIC_VERTEXID) {
1154 /* From Gallium perspective, these system values are always
1155 * integer, and require native integer support. However, if
1156 * native integer is supported on the vertex stage but not the
1157 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1158 * assumes these system values are floats. To resolve the
1159 * inconsistency, we insert a U2F.
1160 */
1161 struct st_context *st = st_context(ctx);
1162 struct pipe_screen *pscreen = st->pipe->screen;
1163 assert(procType == TGSI_PROCESSOR_VERTEX);
1164 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
1165 (void) pscreen; /* silence non-debug build warnings */
1166 if (!ctx->Const.NativeIntegers) {
1167 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
1168 ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
1169 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
1170 }
1171 }
1172 numSys++;
1173 sysInputs &= ~(1 << i);
1174 }
1175 }
1176 }
1177
1178 if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1179 /* If temps are accessed with indirect addressing, declare temporaries
1180 * in sequential order. Else, we declare them on demand elsewhere.
1181 */
1182 for (i = 0; i < program->NumTemporaries; i++) {
1183 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1184 t->temps[i] = ureg_DECL_temporary( t->ureg );
1185 }
1186 }
1187
1188 /* Emit constants and immediates. Mesa uses a single index space
1189 * for these, so we put all the translated regs in t->constants.
1190 */
1191 if (program->Parameters) {
1192 t->constants = calloc( program->Parameters->NumParameters,
1193 sizeof t->constants[0] );
1194 if (t->constants == NULL) {
1195 ret = PIPE_ERROR_OUT_OF_MEMORY;
1196 goto out;
1197 }
1198
1199 for (i = 0; i < program->Parameters->NumParameters; i++) {
1200 switch (program->Parameters->Parameters[i].Type) {
1201 case PROGRAM_ENV_PARAM:
1202 case PROGRAM_LOCAL_PARAM:
1203 case PROGRAM_STATE_VAR:
1204 case PROGRAM_UNIFORM:
1205 t->constants[i] = ureg_DECL_constant( ureg, i );
1206 break;
1207
1208 /* Emit immediates only when there's no indirect addressing of
1209 * the const buffer.
1210 * FIXME: Be smarter and recognize param arrays:
1211 * indirect addressing is only valid within the referenced
1212 * array.
1213 */
1214 case PROGRAM_CONSTANT:
1215 if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1216 t->constants[i] = ureg_DECL_constant( ureg, i );
1217 else
1218 t->constants[i] =
1219 ureg_DECL_immediate( ureg,
1220 (const float*) program->Parameters->ParameterValues[i],
1221 4 );
1222 break;
1223 default:
1224 break;
1225 }
1226 }
1227 }
1228
1229 /* texture samplers */
1230 for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
1231 if (program->SamplersUsed & (1 << i)) {
1232 t->samplers[i] = ureg_DECL_sampler( ureg, i );
1233 }
1234 }
1235
1236 /* Emit each instruction in turn:
1237 */
1238 for (i = 0; i < program->NumInstructions; i++) {
1239 set_insn_start( t, ureg_get_instruction_number( ureg ));
1240 compile_instruction( ctx, t, &program->Instructions[i], clamp_color );
1241 }
1242
1243 /* Fix up all emitted labels:
1244 */
1245 for (i = 0; i < t->labels_count; i++) {
1246 ureg_fixup_label( ureg,
1247 t->labels[i].token,
1248 t->insn[t->labels[i].branch_target] );
1249 }
1250
1251 out:
1252 free(t->insn);
1253 free(t->labels);
1254 free(t->constants);
1255
1256 if (t->error) {
1257 debug_printf("%s: translate error flag set\n", __FUNCTION__);
1258 }
1259
1260 return ret;
1261 }
1262
1263
1264 /**
1265 * Tokens cannot be free with free otherwise the builtin gallium
1266 * malloc debugging will get confused.
1267 */
1268 void
1269 st_free_tokens(const struct tgsi_token *tokens)
1270 {
1271 ureg_free_tokens(tokens);
1272 }