src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_screen.h"
  37 #include "pipe/p_shader_tokens.h"
  38 #include "pipe/p_state.h"
  39 #include "tgsi/tgsi_ureg.h"
  40 #include "st_mesa_to_tgsi.h"
  41 #include "st_context.h"
  42 #include "program/prog_instruction.h"
  43 #include "program/prog_parameter.h"
  44 #include "util/u_debug.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47
  48
  49 #define PROGRAM_ANY_CONST ((1 << PROGRAM_LOCAL_PARAM) |  \
  50                            (1 << PROGRAM_ENV_PARAM) |    \
  51                            (1 << PROGRAM_STATE_VAR) |    \
  52                            (1 << PROGRAM_CONSTANT) |     \
  53                            (1 << PROGRAM_UNIFORM))
  54
  55
  56 struct label {
  57    unsigned branch_target;
  58    unsigned token;
  59 };
  60
  61
  62 /**
  63  * Intermediate state used during shader translation.
  64  */
  65 struct st_translate {
  66    struct ureg_program *ureg;
  67
  68    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  69    struct ureg_src *constants;
  70    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  71    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  72    struct ureg_dst address[1];
  73    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  74    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  75
  76    const GLuint *inputMapping;
  77    const GLuint *outputMapping;
  78
  79    /* For every instruction that contains a label (eg CALL), keep
  80     * details so that we can go back afterwards and emit the correct
  81     * tgsi instruction number for each label.
  82     */
  83    struct label *labels;
  84    unsigned labels_size;
  85    unsigned labels_count;
  86
  87    /* Keep a record of the tgsi instruction number that each mesa
  88     * instruction starts at, will be used to fix up labels after
  89     * translation.
  90     */
  91    unsigned *insn;
  92    unsigned insn_size;
  93    unsigned insn_count;
  94
  95    unsigned procType;  /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
  96
  97    boolean error;
  98 };
  99
 100
 101 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
 102 static unsigned mesa_sysval_to_semantic[SYSTEM_VALUE_MAX] = {
 103    TGSI_SEMANTIC_FACE,
 104    TGSI_SEMANTIC_VERTEXID,
 105    TGSI_SEMANTIC_INSTANCEID
 106 };
 107
 108
 109 /**
 110  * Make note of a branch to a label in the TGSI code.
 111  * After we've emitted all instructions, we'll go over the list
 112  * of labels built here and patch the TGSI code with the actual
 113  * location of each label.
 114  */
 115 static unsigned *get_label( struct st_translate *t,
 116                             unsigned branch_target )
 117 {
 118    unsigned i;
 119
 120    if (t->labels_count + 1 >= t->labels_size) {
 121       t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
 122       t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
 123       if (t->labels == NULL) {
 124          static unsigned dummy;
 125          t->error = TRUE;
 126          return &dummy;
 127       }
 128    }
 129
 130    i = t->labels_count++;
 131    t->labels[i].branch_target = branch_target;
 132    return &t->labels[i].token;
 133 }
 134
 135
 136 /**
 137  * Called prior to emitting the TGSI code for each Mesa instruction.
 138  * Allocate additional space for instructions if needed.
 139  * Update the insn[] array so the next Mesa instruction points to
 140  * the next TGSI instruction.
 141  */
 142 static void set_insn_start( struct st_translate *t,
 143                             unsigned start )
 144 {
 145    if (t->insn_count + 1 >= t->insn_size) {
 146       t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
 147       t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
 148       if (t->insn == NULL) {
 149          t->error = TRUE;
 150          return;
 151       }
 152    }
 153
 154    t->insn[t->insn_count++] = start;
 155 }
 156
 157
 158 /**
 159  * Map a Mesa dst register to a TGSI ureg_dst register.
 160  */
 161 static struct ureg_dst
 162 dst_register( struct st_translate *t,
 163               gl_register_file file,
 164               GLuint index )
 165 {
 166    switch( file ) {
 167    case PROGRAM_UNDEFINED:
 168       return ureg_dst_undef();
 169
 170    case PROGRAM_TEMPORARY:
 171       if (ureg_dst_is_undef(t->temps[index]))
 172          t->temps[index] = ureg_DECL_temporary( t->ureg );
 173
 174       return t->temps[index];
 175
 176    case PROGRAM_OUTPUT:
 177       if (t->procType == TGSI_PROCESSOR_VERTEX)
 178          assert(index < VARYING_SLOT_MAX);
 179       else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
 180          assert(index < FRAG_RESULT_MAX);
 181       else
 182          assert(index < VARYING_SLOT_MAX);
 183
 184       assert(t->outputMapping[index] < Elements(t->outputs));
 185
 186       return t->outputs[t->outputMapping[index]];
 187
 188    case PROGRAM_ADDRESS:
 189       return t->address[index];
 190
 191    default:
 192       debug_assert( 0 );
 193       return ureg_dst_undef();
 194    }
 195 }
 196
 197
 198 /**
 199  * Map a Mesa src register to a TGSI ureg_src register.
 200  */
 201 static struct ureg_src
 202 src_register( struct st_translate *t,
 203               gl_register_file file,
 204               GLint index )
 205 {
 206    switch( file ) {
 207    case PROGRAM_UNDEFINED:
 208       return ureg_src_undef();
 209
 210    case PROGRAM_TEMPORARY:
 211       assert(index >= 0);
 212       assert(index < Elements(t->temps));
 213       if (ureg_dst_is_undef(t->temps[index]))
 214          t->temps[index] = ureg_DECL_temporary( t->ureg );
 215       return ureg_src(t->temps[index]);
 216
 217    case PROGRAM_ENV_PARAM:
 218    case PROGRAM_LOCAL_PARAM:
 219    case PROGRAM_UNIFORM:
 220       assert(index >= 0);
 221       return t->constants[index];
 222    case PROGRAM_STATE_VAR:
 223    case PROGRAM_CONSTANT:       /* ie, immediate */
 224       if (index < 0)
 225          return ureg_DECL_constant( t->ureg, 0 );
 226       else
 227          return t->constants[index];
 228
 229    case PROGRAM_INPUT:
 230       assert(t->inputMapping[index] < Elements(t->inputs));
 231       return t->inputs[t->inputMapping[index]];
 232
 233    case PROGRAM_OUTPUT:
 234       assert(t->outputMapping[index] < Elements(t->outputs));
 235       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 236
 237    case PROGRAM_ADDRESS:
 238       return ureg_src(t->address[index]);
 239
 240    case PROGRAM_SYSTEM_VALUE:
 241       assert(index < Elements(t->systemValues));
 242       return t->systemValues[index];
 243
 244    default:
 245       debug_assert( 0 );
 246       return ureg_src_undef();
 247    }
 248 }
 249
 250
 251 /**
 252  * Map mesa texture target to TGSI texture target.
 253  */
 254 unsigned
 255 st_translate_texture_target( GLuint textarget,
 256                           GLboolean shadow )
 257 {
 258    if (shadow) {
 259       switch( textarget ) {
 260       case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_SHADOW1D;
 261       case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_SHADOW2D;
 262       case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
 263       case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
 264       case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
 265       case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
 266       case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
 267       default: break;
 268       }
 269    }
 270
 271    switch( textarget ) {
 272    case TEXTURE_2D_MULTISAMPLE_INDEX: return TGSI_TEXTURE_2D_MSAA;
 273    case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY_MSAA;
 274    case TEXTURE_BUFFER_INDEX: return TGSI_TEXTURE_BUFFER;
 275    case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_1D;
 276    case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_2D;
 277    case TEXTURE_3D_INDEX:   return TGSI_TEXTURE_3D;
 278    case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
 279    case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_CUBE_ARRAY;
 280    case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
 281    case TEXTURE_1D_ARRAY_INDEX:   return TGSI_TEXTURE_1D_ARRAY;
 282    case TEXTURE_2D_ARRAY_INDEX:   return TGSI_TEXTURE_2D_ARRAY;
 283    case TEXTURE_EXTERNAL_INDEX:   return TGSI_TEXTURE_2D;
 284    default:
 285       debug_assert( 0 );
 286       return TGSI_TEXTURE_1D;
 287    }
 288 }
 289
 290
 291 /**
 292  * Create a TGSI ureg_dst register from a Mesa dest register.
 293  */
 294 static struct ureg_dst
 295 translate_dst( struct st_translate *t,
 296                const struct prog_dst_register *DstReg,
 297                boolean saturate,
 298                boolean clamp_color)
 299 {
 300    struct ureg_dst dst = dst_register( t,
 301                                        DstReg->File,
 302                                        DstReg->Index );
 303
 304    dst = ureg_writemask( dst,
 305                          DstReg->WriteMask );
 306
 307    if (saturate)
 308       dst = ureg_saturate( dst );
 309    else if (clamp_color && DstReg->File == PROGRAM_OUTPUT) {
 310       /* Clamp colors for ARB_color_buffer_float. */
 311       switch (t->procType) {
 312       case TGSI_PROCESSOR_VERTEX:
 313          /* XXX if the geometry shader is present, this must be done there
 314           * instead of here. */
 315          if (DstReg->Index == VARYING_SLOT_COL0 ||
 316              DstReg->Index == VARYING_SLOT_COL1 ||
 317              DstReg->Index == VARYING_SLOT_BFC0 ||
 318              DstReg->Index == VARYING_SLOT_BFC1) {
 319             dst = ureg_saturate(dst);
 320          }
 321          break;
 322
 323       case TGSI_PROCESSOR_FRAGMENT:
 324          if (DstReg->Index >= FRAG_RESULT_COLOR) {
 325             dst = ureg_saturate(dst);
 326          }
 327          break;
 328       }
 329    }
 330
 331    if (DstReg->RelAddr)
 332       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 333
 334    return dst;
 335 }
 336
 337
 338 /**
 339  * Create a TGSI ureg_src register from a Mesa src register.
 340  */
 341 static struct ureg_src
 342 translate_src( struct st_translate *t,
 343                const struct prog_src_register *SrcReg )
 344 {
 345    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 346
 347    if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
 348       src = src_register( t, SrcReg->File, SrcReg->Index2 );
 349       if (SrcReg->RelAddr2)
 350          src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
 351                                             SrcReg->Index);
 352       else
 353          src = ureg_src_dimension( src, SrcReg->Index);
 354    }
 355
 356    src = ureg_swizzle( src,
 357                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
 358                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
 359                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
 360                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 361
 362    if (SrcReg->Negate == NEGATE_XYZW)
 363       src = ureg_negate(src);
 364
 365    if (SrcReg->Abs)
 366       src = ureg_abs(src);
 367
 368    if (SrcReg->RelAddr) {
 369       src = ureg_src_indirect( src, ureg_src(t->address[0]));
 370       if (SrcReg->File != PROGRAM_INPUT &&
 371           SrcReg->File != PROGRAM_OUTPUT) {
 372          /* If SrcReg->Index was negative, it was set to zero in
 373           * src_register().  Reassign it now.  But don't do this
 374           * for input/output regs since they get remapped while
 375           * const buffers don't.
 376           */
 377          src.Index = SrcReg->Index;
 378       }
 379    }
 380
 381    return src;
 382 }
 383
 384
 385 static struct ureg_src swizzle_4v( struct ureg_src src,
 386                                    const unsigned *swz )
 387 {
 388    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
 389 }
 390
 391
 392 /**
 393  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 394  *
 395  *   SWZ dst, src.x-y10
 396  *
 397  * becomes:
 398  *
 399  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 400  */
 401 static void emit_swz( struct st_translate *t,
 402                       struct ureg_dst dst,
 403                       const struct prog_src_register *SrcReg )
 404 {
 405    struct ureg_program *ureg = t->ureg;
 406    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 407
 408    unsigned negate_mask =  SrcReg->Negate;
 409
 410    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 411                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 412                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 413                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 414
 415    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 416                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 417                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 418                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 419
 420    unsigned negative_one_mask = one_mask & negate_mask;
 421    unsigned positive_one_mask = one_mask & ~negate_mask;
 422
 423    struct ureg_src imm;
 424    unsigned i;
 425    unsigned mul_swizzle[4] = {0,0,0,0};
 426    unsigned add_swizzle[4] = {0,0,0,0};
 427    unsigned src_swizzle[4] = {0,0,0,0};
 428    boolean need_add = FALSE;
 429    boolean need_mul = FALSE;
 430
 431    if (dst.WriteMask == 0)
 432       return;
 433
 434    /* Is this just a MOV?
 435     */
 436    if (zero_mask == 0 &&
 437        one_mask == 0 &&
 438        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
 439    {
 440       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
 441       return;
 442    }
 443
 444 #define IMM_ZERO    0
 445 #define IMM_ONE     1
 446 #define IMM_NEG_ONE 2
 447
 448    imm = ureg_imm3f( ureg, 0, 1, -1 );
 449
 450    for (i = 0; i < 4; i++) {
 451       unsigned bit = 1 << i;
 452
 453       if (dst.WriteMask & bit) {
 454          if (positive_one_mask & bit) {
 455             mul_swizzle[i] = IMM_ZERO;
 456             add_swizzle[i] = IMM_ONE;
 457             need_add = TRUE;
 458          }
 459          else if (negative_one_mask & bit) {
 460             mul_swizzle[i] = IMM_ZERO;
 461             add_swizzle[i] = IMM_NEG_ONE;
 462             need_add = TRUE;
 463          }
 464          else if (zero_mask & bit) {
 465             mul_swizzle[i] = IMM_ZERO;
 466             add_swizzle[i] = IMM_ZERO;
 467             need_add = TRUE;
 468          }
 469          else {
 470             add_swizzle[i] = IMM_ZERO;
 471             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 472             need_mul = TRUE;
 473             if (negate_mask & bit) {
 474                mul_swizzle[i] = IMM_NEG_ONE;
 475             }
 476             else {
 477                mul_swizzle[i] = IMM_ONE;
 478             }
 479          }
 480       }
 481    }
 482
 483    if (need_mul && need_add) {
 484       ureg_MAD( ureg,
 485                 dst,
 486                 swizzle_4v( src, src_swizzle ),
 487                 swizzle_4v( imm, mul_swizzle ),
 488                 swizzle_4v( imm, add_swizzle ) );
 489    }
 490    else if (need_mul) {
 491       ureg_MUL( ureg,
 492                 dst,
 493                 swizzle_4v( src, src_swizzle ),
 494                 swizzle_4v( imm, mul_swizzle ) );
 495    }
 496    else if (need_add) {
 497       ureg_MOV( ureg,
 498                 dst,
 499                 swizzle_4v( imm, add_swizzle ) );
 500    }
 501    else {
 502       debug_assert(0);
 503    }
 504
 505 #undef IMM_ZERO
 506 #undef IMM_ONE
 507 #undef IMM_NEG_ONE
 508 }
 509
 510
 511 /**
 512  * Negate the value of DDY to match GL semantics where (0,0) is the
 513  * lower-left corner of the window.
 514  * Note that the GL_ARB_fragment_coord_conventions extension will
 515  * effect this someday.
 516  */
 517 static void emit_ddy( struct st_translate *t,
 518                       struct ureg_dst dst,
 519                       const struct prog_src_register *SrcReg )
 520 {
 521    struct ureg_program *ureg = t->ureg;
 522    struct ureg_src src = translate_src( t, SrcReg );
 523    src = ureg_negate( src );
 524    ureg_DDY( ureg, dst, src );
 525 }
 526
 527
 528
 529 static unsigned
 530 translate_opcode( unsigned op )
 531 {
 532    switch( op ) {
 533    case OPCODE_ARL:
 534       return TGSI_OPCODE_ARL;
 535    case OPCODE_ABS:
 536       return TGSI_OPCODE_ABS;
 537    case OPCODE_ADD:
 538       return TGSI_OPCODE_ADD;
 539    case OPCODE_BGNLOOP:
 540       return TGSI_OPCODE_BGNLOOP;
 541    case OPCODE_BGNSUB:
 542       return TGSI_OPCODE_BGNSUB;
 543    case OPCODE_BRK:
 544       return TGSI_OPCODE_BRK;
 545    case OPCODE_CAL:
 546       return TGSI_OPCODE_CAL;
 547    case OPCODE_CMP:
 548       return TGSI_OPCODE_CMP;
 549    case OPCODE_CONT:
 550       return TGSI_OPCODE_CONT;
 551    case OPCODE_COS:
 552       return TGSI_OPCODE_COS;
 553    case OPCODE_DDX:
 554       return TGSI_OPCODE_DDX;
 555    case OPCODE_DDY:
 556       return TGSI_OPCODE_DDY;
 557    case OPCODE_DP2:
 558       return TGSI_OPCODE_DP2;
 559    case OPCODE_DP3:
 560       return TGSI_OPCODE_DP3;
 561    case OPCODE_DP4:
 562       return TGSI_OPCODE_DP4;
 563    case OPCODE_DPH:
 564       return TGSI_OPCODE_DPH;
 565    case OPCODE_DST:
 566       return TGSI_OPCODE_DST;
 567    case OPCODE_ELSE:
 568       return TGSI_OPCODE_ELSE;
 569    case OPCODE_ENDIF:
 570       return TGSI_OPCODE_ENDIF;
 571    case OPCODE_ENDLOOP:
 572       return TGSI_OPCODE_ENDLOOP;
 573    case OPCODE_ENDSUB:
 574       return TGSI_OPCODE_ENDSUB;
 575    case OPCODE_EX2:
 576       return TGSI_OPCODE_EX2;
 577    case OPCODE_EXP:
 578       return TGSI_OPCODE_EXP;
 579    case OPCODE_FLR:
 580       return TGSI_OPCODE_FLR;
 581    case OPCODE_FRC:
 582       return TGSI_OPCODE_FRC;
 583    case OPCODE_IF:
 584       return TGSI_OPCODE_IF;
 585    case OPCODE_TRUNC:
 586       return TGSI_OPCODE_TRUNC;
 587    case OPCODE_KIL:
 588       return TGSI_OPCODE_KILL_IF;
 589    case OPCODE_KIL_NV:
 590       /* XXX we don't support condition codes in TGSI */
 591       return TGSI_OPCODE_KILL;
 592    case OPCODE_LG2:
 593       return TGSI_OPCODE_LG2;
 594    case OPCODE_LOG:
 595       return TGSI_OPCODE_LOG;
 596    case OPCODE_LIT:
 597       return TGSI_OPCODE_LIT;
 598    case OPCODE_LRP:
 599       return TGSI_OPCODE_LRP;
 600    case OPCODE_MAD:
 601       return TGSI_OPCODE_MAD;
 602    case OPCODE_MAX:
 603       return TGSI_OPCODE_MAX;
 604    case OPCODE_MIN:
 605       return TGSI_OPCODE_MIN;
 606    case OPCODE_MOV:
 607       return TGSI_OPCODE_MOV;
 608    case OPCODE_MUL:
 609       return TGSI_OPCODE_MUL;
 610    case OPCODE_NOP:
 611       return TGSI_OPCODE_NOP;
 612    case OPCODE_POW:
 613       return TGSI_OPCODE_POW;
 614    case OPCODE_RCP:
 615       return TGSI_OPCODE_RCP;
 616    case OPCODE_RET:
 617       return TGSI_OPCODE_RET;
 618    case OPCODE_SCS:
 619       return TGSI_OPCODE_SCS;
 620    case OPCODE_SEQ:
 621       return TGSI_OPCODE_SEQ;
 622    case OPCODE_SGE:
 623       return TGSI_OPCODE_SGE;
 624    case OPCODE_SGT:
 625       return TGSI_OPCODE_SGT;
 626    case OPCODE_SIN:
 627       return TGSI_OPCODE_SIN;
 628    case OPCODE_SLE:
 629       return TGSI_OPCODE_SLE;
 630    case OPCODE_SLT:
 631       return TGSI_OPCODE_SLT;
 632    case OPCODE_SNE:
 633       return TGSI_OPCODE_SNE;
 634    case OPCODE_SSG:
 635       return TGSI_OPCODE_SSG;
 636    case OPCODE_SUB:
 637       return TGSI_OPCODE_SUB;
 638    case OPCODE_TEX:
 639       return TGSI_OPCODE_TEX;
 640    case OPCODE_TXB:
 641       return TGSI_OPCODE_TXB;
 642    case OPCODE_TXD:
 643       return TGSI_OPCODE_TXD;
 644    case OPCODE_TXL:
 645       return TGSI_OPCODE_TXL;
 646    case OPCODE_TXP:
 647       return TGSI_OPCODE_TXP;
 648    case OPCODE_XPD:
 649       return TGSI_OPCODE_XPD;
 650    case OPCODE_END:
 651       return TGSI_OPCODE_END;
 652    default:
 653       debug_assert( 0 );
 654       return TGSI_OPCODE_NOP;
 655    }
 656 }
 657
 658
 659 static void
 660 compile_instruction(
 661    struct gl_context *ctx,
 662    struct st_translate *t,
 663    const struct prog_instruction *inst,
 664    boolean clamp_dst_color_output)
 665 {
 666    struct ureg_program *ureg = t->ureg;
 667    GLuint i;
 668    struct ureg_dst dst[1] = { { 0 } };
 669    struct ureg_src src[4];
 670    unsigned num_dst;
 671    unsigned num_src;
 672
 673    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
 674    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 675
 676    if (num_dst)
 677       dst[0] = translate_dst( t,
 678                               &inst->DstReg,
 679                               inst->SaturateMode,
 680                               clamp_dst_color_output);
 681
 682    for (i = 0; i < num_src; i++)
 683       src[i] = translate_src( t, &inst->SrcReg[i] );
 684
 685    switch( inst->Opcode ) {
 686    case OPCODE_SWZ:
 687       emit_swz( t, dst[0], &inst->SrcReg[0] );
 688       return;
 689
 690    case OPCODE_BGNLOOP:
 691    case OPCODE_CAL:
 692    case OPCODE_ELSE:
 693    case OPCODE_ENDLOOP:
 694       debug_assert(num_dst == 0);
 695       ureg_label_insn( ureg,
 696                        translate_opcode( inst->Opcode ),
 697                        src, num_src,
 698                        get_label( t, inst->BranchTarget ));
 699       return;
 700
 701    case OPCODE_IF:
 702       debug_assert(num_dst == 0);
 703       ureg_label_insn( ureg,
 704                        ctx->Const.NativeIntegers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF,
 705                        src, num_src,
 706                        get_label( t, inst->BranchTarget ));
 707       return;
 708
 709    case OPCODE_TEX:
 710    case OPCODE_TXB:
 711    case OPCODE_TXD:
 712    case OPCODE_TXL:
 713    case OPCODE_TXP:
 714       src[num_src++] = t->samplers[inst->TexSrcUnit];
 715       ureg_tex_insn( ureg,
 716                      translate_opcode( inst->Opcode ),
 717                      dst, num_dst,
 718                      st_translate_texture_target( inst->TexSrcTarget,
 719                                                inst->TexShadow ),
 720                      NULL, 0,
 721                      src, num_src );
 722       return;
 723
 724    case OPCODE_SCS:
 725       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
 726       ureg_insn( ureg,
 727                  translate_opcode( inst->Opcode ),
 728                  dst, num_dst,
 729                  src, num_src );
 730       break;
 731
 732    case OPCODE_XPD:
 733       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
 734       ureg_insn( ureg,
 735                  translate_opcode( inst->Opcode ),
 736                  dst, num_dst,
 737                  src, num_src );
 738       break;
 739
 740    case OPCODE_NOISE1:
 741    case OPCODE_NOISE2:
 742    case OPCODE_NOISE3:
 743    case OPCODE_NOISE4:
 744       /* At some point, a motivated person could add a better
 745        * implementation of noise.  Currently not even the nvidia
 746        * binary drivers do anything more than this.  In any case, the
 747        * place to do this is in the GL state tracker, not the poor
 748        * driver.
 749        */
 750       ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
 751       break;
 752
 753    case OPCODE_DDY:
 754       emit_ddy( t, dst[0], &inst->SrcReg[0] );
 755       break;
 756
 757    case OPCODE_RSQ:
 758       ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
 759       break;
 760
 761    default:
 762       ureg_insn( ureg,
 763                  translate_opcode( inst->Opcode ),
 764                  dst, num_dst,
 765                  src, num_src );
 766       break;
 767    }
 768 }
 769
 770
 771 /**
 772  * Emit the TGSI instructions for inverting and adjusting WPOS.
 773  * This code is unavoidable because it also depends on whether
 774  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
 775  */
 776 static void
 777 emit_wpos_adjustment( struct st_translate *t,
 778                       const struct gl_program *program,
 779                       boolean invert,
 780                       GLfloat adjX, GLfloat adjY[2])
 781 {
 782    struct ureg_program *ureg = t->ureg;
 783
 784    /* Fragment program uses fragment position input.
 785     * Need to replace instances of INPUT[WPOS] with temp T
 786     * where T = INPUT[WPOS] by y is inverted.
 787     */
 788    static const gl_state_index wposTransformState[STATE_LENGTH]
 789       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
 790
 791    /* XXX: note we are modifying the incoming shader here!  Need to
 792     * do this before emitting the constant decls below, or this
 793     * will be missed:
 794     */
 795    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
 796                                                        wposTransformState);
 797
 798    struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
 799    struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
 800    struct ureg_src wpos_input = t->inputs[t->inputMapping[VARYING_SLOT_POS]];
 801
 802    /* First, apply the coordinate shift: */
 803    if (adjX || adjY[0] || adjY[1]) {
 804       if (adjY[0] != adjY[1]) {
 805          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
 806           * depending on whether inversion is actually going to be applied
 807           * or not, which is determined by testing against the inversion
 808           * state variable used below, which will be either +1 or -1.
 809           */
 810          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
 811
 812          ureg_CMP(ureg, adj_temp,
 813                   ureg_scalar(wpostrans, invert ? 2 : 0),
 814                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
 815                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
 816          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
 817       } else {
 818          ureg_ADD(ureg, wpos_temp, wpos_input,
 819                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
 820       }
 821       wpos_input = ureg_src(wpos_temp);
 822    } else {
 823       /* MOV wpos_temp, input[wpos]
 824        */
 825       ureg_MOV( ureg, wpos_temp, wpos_input );
 826    }
 827
 828    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
 829     * inversion/identity, or the other way around if we're drawing to an FBO.
 830     */
 831    if (invert) {
 832       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
 833        */
 834       ureg_MAD( ureg,
 835                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 836                 wpos_input,
 837                 ureg_scalar(wpostrans, 0),
 838                 ureg_scalar(wpostrans, 1));
 839    } else {
 840       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
 841        */
 842       ureg_MAD( ureg,
 843                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 844                 wpos_input,
 845                 ureg_scalar(wpostrans, 2),
 846                 ureg_scalar(wpostrans, 3));
 847    }
 848
 849    /* Use wpos_temp as position input from here on:
 850     */
 851    t->inputs[t->inputMapping[VARYING_SLOT_POS]] = ureg_src(wpos_temp);
 852 }
 853
 854
 855 /**
 856  * Emit fragment position/ooordinate code.
 857  */
 858 static void
 859 emit_wpos(struct st_context *st,
 860           struct st_translate *t,
 861           const struct gl_program *program,
 862           struct ureg_program *ureg)
 863 {
 864    const struct gl_fragment_program *fp =
 865       (const struct gl_fragment_program *) program;
 866    struct pipe_screen *pscreen = st->pipe->screen;
 867    GLfloat adjX = 0.0f;
 868    GLfloat adjY[2] = { 0.0f, 0.0f };
 869    boolean invert = FALSE;
 870
 871    /* Query the pixel center conventions supported by the pipe driver and set
 872     * adjX, adjY to help out if it cannot handle the requested one internally.
 873     *
 874     * The bias of the y-coordinate depends on whether y-inversion takes place
 875     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
 876     * drawing to an FBO (causes additional inversion), and whether the the pipe
 877     * driver origin and the requested origin differ (the latter condition is
 878     * stored in the 'invert' variable).
 879     *
 880     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
 881     *
 882     * center shift only:
 883     * i -> h: +0.5
 884     * h -> i: -0.5
 885     *
 886     * inversion only:
 887     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
 888     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
 889     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
 890     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
 891     *
 892     * inversion and center shift:
 893     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
 894     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
 895     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
 896     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
 897     */
 898    if (fp->OriginUpperLeft) {
 899       /* Fragment shader wants origin in upper-left */
 900       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 901          /* the driver supports upper-left origin */
 902       }
 903       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 904          /* the driver supports lower-left origin, need to invert Y */
 905          ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 906          invert = TRUE;
 907       }
 908       else
 909          assert(0);
 910    }
 911    else {
 912       /* Fragment shader wants origin in lower-left */
 913       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 914          /* the driver supports lower-left origin */
 915          ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 916       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 917          /* the driver supports upper-left origin, need to invert Y */
 918          invert = TRUE;
 919       else
 920          assert(0);
 921    }
 922
 923    if (fp->PixelCenterInteger) {
 924       /* Fragment shader wants pixel center integer */
 925       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 926          /* the driver supports pixel center integer */
 927          adjY[1] = 1.0f;
 928          ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 929       }
 930       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 931          /* the driver supports pixel center half integer, need to bias X,Y */
 932          adjX = -0.5f;
 933          adjY[0] = -0.5f;
 934          adjY[1] = 0.5f;
 935       }
 936       else
 937          assert(0);
 938    }
 939    else {
 940       /* Fragment shader wants pixel center half integer */
 941       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 942          /* the driver supports pixel center half integer */
 943       }
 944       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 945          /* the driver supports pixel center integer, need to bias X,Y */
 946          adjX = adjY[0] = adjY[1] = 0.5f;
 947          ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 948       }
 949       else
 950          assert(0);
 951    }
 952
 953    /* we invert after adjustment so that we avoid the MOV to temporary,
 954     * and reuse the adjustment ADD instead */
 955    emit_wpos_adjustment(t, program, invert, adjX, adjY);
 956 }
 957
 958
 959 /**
 960  * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
 961  * TGSI uses +1 for front, -1 for back.
 962  * This function converts the TGSI value to the GL value.  Simply clamping/
 963  * saturating the value to [0,1] does the job.
 964  */
 965 static void
 966 emit_face_var( struct st_translate *t,
 967                const struct gl_program *program )
 968 {
 969    struct ureg_program *ureg = t->ureg;
 970    struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
 971    struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
 972
 973    /* MOV_SAT face_temp, input[face]
 974     */
 975    face_temp = ureg_saturate( face_temp );
 976    ureg_MOV( ureg, face_temp, face_input );
 977
 978    /* Use face_temp as face input from here on:
 979     */
 980    t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
 981 }
 982
 983
 984 static void
 985 emit_edgeflags( struct st_translate *t,
 986                  const struct gl_program *program )
 987 {
 988    struct ureg_program *ureg = t->ureg;
 989    struct ureg_dst edge_dst = t->outputs[t->outputMapping[VARYING_SLOT_EDGE]];
 990    struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
 991
 992    ureg_MOV( ureg, edge_dst, edge_src );
 993 }
 994
 995
 996 /**
 997  * Translate Mesa program to TGSI format.
 998  * \param program  the program to translate
 999  * \param numInputs  number of input registers used
1000  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
1001  *                      input indexes
1002  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
1003  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
1004  *                            each input
1005  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
1006  * \param numOutputs  number of output registers used
1007  * \param outputMapping  maps Mesa fragment program outputs to TGSI
1008  *                       generic outputs
1009  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
1010  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
1011  *                             each output
1012  *
1013  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
1014  */
1015 enum pipe_error
1016 st_translate_mesa_program(
1017    struct gl_context *ctx,
1018    uint procType,
1019    struct ureg_program *ureg,
1020    const struct gl_program *program,
1021    GLuint numInputs,
1022    const GLuint inputMapping[],
1023    const ubyte inputSemanticName[],
1024    const ubyte inputSemanticIndex[],
1025    const GLuint interpMode[],
1026    GLuint numOutputs,
1027    const GLuint outputMapping[],
1028    const ubyte outputSemanticName[],
1029    const ubyte outputSemanticIndex[],
1030    boolean passthrough_edgeflags,
1031    boolean clamp_color)
1032 {
1033    struct st_translate translate, *t;
1034    unsigned i;
1035    enum pipe_error ret = PIPE_OK;
1036
1037    assert(numInputs <= Elements(t->inputs));
1038    assert(numOutputs <= Elements(t->outputs));
1039
1040    t = &translate;
1041    memset(t, 0, sizeof *t);
1042
1043    t->procType = procType;
1044    t->inputMapping = inputMapping;
1045    t->outputMapping = outputMapping;
1046    t->ureg = ureg;
1047
1048    /*_mesa_print_program(program);*/
1049
1050    /*
1051     * Declare input attributes.
1052     */
1053    if (procType == TGSI_PROCESSOR_FRAGMENT) {
1054       for (i = 0; i < numInputs; i++) {
1055          t->inputs[i] = ureg_DECL_fs_input(ureg,
1056                                            inputSemanticName[i],
1057                                            inputSemanticIndex[i],
1058                                            interpMode[i]);
1059       }
1060
1061       if (program->InputsRead & VARYING_BIT_POS) {
1062          /* Must do this after setting up t->inputs, and before
1063           * emitting constant references, below:
1064           */
1065          emit_wpos(st_context(ctx), t, program, ureg);
1066       }
1067
1068       if (program->InputsRead & VARYING_BIT_FACE) {
1069          emit_face_var( t, program );
1070       }
1071
1072       /*
1073        * Declare output attributes.
1074        */
1075       for (i = 0; i < numOutputs; i++) {
1076          switch (outputSemanticName[i]) {
1077          case TGSI_SEMANTIC_POSITION:
1078             t->outputs[i] = ureg_DECL_output( ureg,
1079                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
1080                                               outputSemanticIndex[i] );
1081
1082             t->outputs[i] = ureg_writemask( t->outputs[i],
1083                                             TGSI_WRITEMASK_Z );
1084             break;
1085          case TGSI_SEMANTIC_STENCIL:
1086             t->outputs[i] = ureg_DECL_output( ureg,
1087                                               TGSI_SEMANTIC_STENCIL, /* Stencil */
1088                                               outputSemanticIndex[i] );
1089             t->outputs[i] = ureg_writemask( t->outputs[i],
1090                                             TGSI_WRITEMASK_Y );
1091             break;
1092          case TGSI_SEMANTIC_COLOR:
1093             t->outputs[i] = ureg_DECL_output( ureg,
1094                                               TGSI_SEMANTIC_COLOR,
1095                                               outputSemanticIndex[i] );
1096             break;
1097          default:
1098             debug_assert(0);
1099             return 0;
1100          }
1101       }
1102    }
1103    else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1104       for (i = 0; i < numInputs; i++) {
1105          t->inputs[i] = ureg_DECL_gs_input(ureg,
1106                                            i,
1107                                            inputSemanticName[i],
1108                                            inputSemanticIndex[i]);
1109       }
1110
1111       for (i = 0; i < numOutputs; i++) {
1112          t->outputs[i] = ureg_DECL_output( ureg,
1113                                            outputSemanticName[i],
1114                                            outputSemanticIndex[i] );
1115       }
1116    }
1117    else {
1118       assert(procType == TGSI_PROCESSOR_VERTEX);
1119
1120       for (i = 0; i < numInputs; i++) {
1121          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1122       }
1123
1124       for (i = 0; i < numOutputs; i++) {
1125          t->outputs[i] = ureg_DECL_output( ureg,
1126                                            outputSemanticName[i],
1127                                            outputSemanticIndex[i] );
1128       }
1129       if (passthrough_edgeflags)
1130          emit_edgeflags( t, program );
1131    }
1132
1133    /* Declare address register.
1134     */
1135    if (program->NumAddressRegs > 0) {
1136       debug_assert( program->NumAddressRegs == 1 );
1137       t->address[0] = ureg_DECL_address( ureg );
1138    }
1139
1140    /* Declare misc input registers
1141     */
1142    {
1143       GLbitfield sysInputs = program->SystemValuesRead;
1144       unsigned numSys = 0;
1145       for (i = 0; sysInputs; i++) {
1146          if (sysInputs & (1 << i)) {
1147             unsigned semName = mesa_sysval_to_semantic[i];
1148             t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1149             if (semName == TGSI_SEMANTIC_INSTANCEID ||
1150                 semName == TGSI_SEMANTIC_VERTEXID) {
1151                /* From Gallium perspective, these system values are always
1152                 * integer, and require native integer support.  However, if
1153                 * native integer is supported on the vertex stage but not the
1154                 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1155                 * assumes these system values are floats. To resolve the
1156                 * inconsistency, we insert a U2F.
1157                 */
1158                struct st_context *st = st_context(ctx);
1159                struct pipe_screen *pscreen = st->pipe->screen;
1160                assert(procType == TGSI_PROCESSOR_VERTEX);
1161                assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
1162                (void) pscreen;  /* silence non-debug build warnings */
1163                if (!ctx->Const.NativeIntegers) {
1164                   struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
1165                   ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
1166                   t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
1167                }
1168             }
1169             numSys++;
1170             sysInputs &= ~(1 << i);
1171          }
1172       }
1173    }
1174
1175    if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1176       /* If temps are accessed with indirect addressing, declare temporaries
1177        * in sequential order.  Else, we declare them on demand elsewhere.
1178        */
1179       for (i = 0; i < program->NumTemporaries; i++) {
1180          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1181          t->temps[i] = ureg_DECL_temporary( t->ureg );
1182       }
1183    }
1184
1185    /* Emit constants and immediates.  Mesa uses a single index space
1186     * for these, so we put all the translated regs in t->constants.
1187     */
1188    if (program->Parameters) {
1189       t->constants = calloc( program->Parameters->NumParameters,
1190                              sizeof t->constants[0] );
1191       if (t->constants == NULL) {
1192          ret = PIPE_ERROR_OUT_OF_MEMORY;
1193          goto out;
1194       }
1195
1196       for (i = 0; i < program->Parameters->NumParameters; i++) {
1197          switch (program->Parameters->Parameters[i].Type) {
1198          case PROGRAM_ENV_PARAM:
1199          case PROGRAM_LOCAL_PARAM:
1200          case PROGRAM_STATE_VAR:
1201          case PROGRAM_UNIFORM:
1202             t->constants[i] = ureg_DECL_constant( ureg, i );
1203             break;
1204
1205             /* Emit immediates only when there's no indirect addressing of
1206              * the const buffer.
1207              * FIXME: Be smarter and recognize param arrays:
1208              * indirect addressing is only valid within the referenced
1209              * array.
1210              */
1211          case PROGRAM_CONSTANT:
1212             if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1213                t->constants[i] = ureg_DECL_constant( ureg, i );
1214             else
1215                t->constants[i] =
1216                   ureg_DECL_immediate( ureg,
1217                                        (const float*) program->Parameters->ParameterValues[i],
1218                                        4 );
1219             break;
1220          default:
1221             break;
1222          }
1223       }
1224    }
1225
1226    /* texture samplers */
1227    for (i = 0; i < ctx->Const.FragmentProgram.MaxTextureImageUnits; i++) {
1228       if (program->SamplersUsed & (1 << i)) {
1229          t->samplers[i] = ureg_DECL_sampler( ureg, i );
1230       }
1231    }
1232
1233    /* Emit each instruction in turn:
1234     */
1235    for (i = 0; i < program->NumInstructions; i++) {
1236       set_insn_start( t, ureg_get_instruction_number( ureg ));
1237       compile_instruction( ctx, t, &program->Instructions[i], clamp_color );
1238    }
1239
1240    /* Fix up all emitted labels:
1241     */
1242    for (i = 0; i < t->labels_count; i++) {
1243       ureg_fixup_label( ureg,
1244                         t->labels[i].token,
1245                         t->insn[t->labels[i].branch_target] );
1246    }
1247
1248 out:
1249    free(t->insn);
1250    free(t->labels);
1251    free(t->constants);
1252
1253    if (t->error) {
1254       debug_printf("%s: translate error flag set\n", __FUNCTION__);
1255    }
1256
1257    return ret;
1258 }
1259
1260
1261 /**
1262  * Tokens cannot be free with free otherwise the builtin gallium
1263  * malloc debugging will get confused.
1264  */
1265 void
1266 st_free_tokens(const struct tgsi_token *tokens)
1267 {
1268    ureg_free_tokens(tokens);
1269 }