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tgsi: rename the TGSI fragment kill opcodes
[mesa.git] / src / mesa / state_tracker / st_mesa_to_tgsi.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * \author
30 * Michal Krol,
31 * Keith Whitwell
32 */
33
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47
48
49 #define PROGRAM_ANY_CONST ((1 << PROGRAM_LOCAL_PARAM) | \
50 (1 << PROGRAM_ENV_PARAM) | \
51 (1 << PROGRAM_STATE_VAR) | \
52 (1 << PROGRAM_CONSTANT) | \
53 (1 << PROGRAM_UNIFORM))
54
55
56 struct label {
57 unsigned branch_target;
58 unsigned token;
59 };
60
61
62 /**
63 * Intermediate state used during shader translation.
64 */
65 struct st_translate {
66 struct ureg_program *ureg;
67
68 struct ureg_dst temps[MAX_PROGRAM_TEMPS];
69 struct ureg_src *constants;
70 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
71 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
72 struct ureg_dst address[1];
73 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
74 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
75
76 const GLuint *inputMapping;
77 const GLuint *outputMapping;
78
79 /* For every instruction that contains a label (eg CALL), keep
80 * details so that we can go back afterwards and emit the correct
81 * tgsi instruction number for each label.
82 */
83 struct label *labels;
84 unsigned labels_size;
85 unsigned labels_count;
86
87 /* Keep a record of the tgsi instruction number that each mesa
88 * instruction starts at, will be used to fix up labels after
89 * translation.
90 */
91 unsigned *insn;
92 unsigned insn_size;
93 unsigned insn_count;
94
95 unsigned procType; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
96
97 boolean error;
98 };
99
100
101 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
102 static unsigned mesa_sysval_to_semantic[SYSTEM_VALUE_MAX] = {
103 TGSI_SEMANTIC_FACE,
104 TGSI_SEMANTIC_VERTEXID,
105 TGSI_SEMANTIC_INSTANCEID
106 };
107
108
109 /**
110 * Make note of a branch to a label in the TGSI code.
111 * After we've emitted all instructions, we'll go over the list
112 * of labels built here and patch the TGSI code with the actual
113 * location of each label.
114 */
115 static unsigned *get_label( struct st_translate *t,
116 unsigned branch_target )
117 {
118 unsigned i;
119
120 if (t->labels_count + 1 >= t->labels_size) {
121 t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
122 t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
123 if (t->labels == NULL) {
124 static unsigned dummy;
125 t->error = TRUE;
126 return &dummy;
127 }
128 }
129
130 i = t->labels_count++;
131 t->labels[i].branch_target = branch_target;
132 return &t->labels[i].token;
133 }
134
135
136 /**
137 * Called prior to emitting the TGSI code for each Mesa instruction.
138 * Allocate additional space for instructions if needed.
139 * Update the insn[] array so the next Mesa instruction points to
140 * the next TGSI instruction.
141 */
142 static void set_insn_start( struct st_translate *t,
143 unsigned start )
144 {
145 if (t->insn_count + 1 >= t->insn_size) {
146 t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
147 t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
148 if (t->insn == NULL) {
149 t->error = TRUE;
150 return;
151 }
152 }
153
154 t->insn[t->insn_count++] = start;
155 }
156
157
158 /**
159 * Map a Mesa dst register to a TGSI ureg_dst register.
160 */
161 static struct ureg_dst
162 dst_register( struct st_translate *t,
163 gl_register_file file,
164 GLuint index )
165 {
166 switch( file ) {
167 case PROGRAM_UNDEFINED:
168 return ureg_dst_undef();
169
170 case PROGRAM_TEMPORARY:
171 if (ureg_dst_is_undef(t->temps[index]))
172 t->temps[index] = ureg_DECL_temporary( t->ureg );
173
174 return t->temps[index];
175
176 case PROGRAM_OUTPUT:
177 if (t->procType == TGSI_PROCESSOR_VERTEX)
178 assert(index < VARYING_SLOT_MAX);
179 else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
180 assert(index < FRAG_RESULT_MAX);
181 else
182 assert(index < VARYING_SLOT_MAX);
183
184 assert(t->outputMapping[index] < Elements(t->outputs));
185
186 return t->outputs[t->outputMapping[index]];
187
188 case PROGRAM_ADDRESS:
189 return t->address[index];
190
191 default:
192 debug_assert( 0 );
193 return ureg_dst_undef();
194 }
195 }
196
197
198 /**
199 * Map a Mesa src register to a TGSI ureg_src register.
200 */
201 static struct ureg_src
202 src_register( struct st_translate *t,
203 gl_register_file file,
204 GLint index )
205 {
206 switch( file ) {
207 case PROGRAM_UNDEFINED:
208 return ureg_src_undef();
209
210 case PROGRAM_TEMPORARY:
211 assert(index >= 0);
212 assert(index < Elements(t->temps));
213 if (ureg_dst_is_undef(t->temps[index]))
214 t->temps[index] = ureg_DECL_temporary( t->ureg );
215 return ureg_src(t->temps[index]);
216
217 case PROGRAM_ENV_PARAM:
218 case PROGRAM_LOCAL_PARAM:
219 case PROGRAM_UNIFORM:
220 assert(index >= 0);
221 return t->constants[index];
222 case PROGRAM_STATE_VAR:
223 case PROGRAM_CONSTANT: /* ie, immediate */
224 if (index < 0)
225 return ureg_DECL_constant( t->ureg, 0 );
226 else
227 return t->constants[index];
228
229 case PROGRAM_INPUT:
230 assert(t->inputMapping[index] < Elements(t->inputs));
231 return t->inputs[t->inputMapping[index]];
232
233 case PROGRAM_OUTPUT:
234 assert(t->outputMapping[index] < Elements(t->outputs));
235 return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
236
237 case PROGRAM_ADDRESS:
238 return ureg_src(t->address[index]);
239
240 case PROGRAM_SYSTEM_VALUE:
241 assert(index < Elements(t->systemValues));
242 return t->systemValues[index];
243
244 default:
245 debug_assert( 0 );
246 return ureg_src_undef();
247 }
248 }
249
250
251 /**
252 * Map mesa texture target to TGSI texture target.
253 */
254 unsigned
255 st_translate_texture_target( GLuint textarget,
256 GLboolean shadow )
257 {
258 if (shadow) {
259 switch( textarget ) {
260 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_SHADOW1D;
261 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_SHADOW2D;
262 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
263 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
264 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
265 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
266 case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
267 default: break;
268 }
269 }
270
271 switch( textarget ) {
272 case TEXTURE_2D_MULTISAMPLE_INDEX: return TGSI_TEXTURE_2D_MSAA;
273 case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY_MSAA;
274 case TEXTURE_BUFFER_INDEX: return TGSI_TEXTURE_BUFFER;
275 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_1D;
276 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_2D;
277 case TEXTURE_3D_INDEX: return TGSI_TEXTURE_3D;
278 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
279 case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_CUBE_ARRAY;
280 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
281 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_1D_ARRAY;
282 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY;
283 case TEXTURE_EXTERNAL_INDEX: return TGSI_TEXTURE_2D;
284 default:
285 debug_assert( 0 );
286 return TGSI_TEXTURE_1D;
287 }
288 }
289
290
291 /**
292 * Create a TGSI ureg_dst register from a Mesa dest register.
293 */
294 static struct ureg_dst
295 translate_dst( struct st_translate *t,
296 const struct prog_dst_register *DstReg,
297 boolean saturate,
298 boolean clamp_color)
299 {
300 struct ureg_dst dst = dst_register( t,
301 DstReg->File,
302 DstReg->Index );
303
304 dst = ureg_writemask( dst,
305 DstReg->WriteMask );
306
307 if (saturate)
308 dst = ureg_saturate( dst );
309 else if (clamp_color && DstReg->File == PROGRAM_OUTPUT) {
310 /* Clamp colors for ARB_color_buffer_float. */
311 switch (t->procType) {
312 case TGSI_PROCESSOR_VERTEX:
313 /* XXX if the geometry shader is present, this must be done there
314 * instead of here. */
315 if (DstReg->Index == VARYING_SLOT_COL0 ||
316 DstReg->Index == VARYING_SLOT_COL1 ||
317 DstReg->Index == VARYING_SLOT_BFC0 ||
318 DstReg->Index == VARYING_SLOT_BFC1) {
319 dst = ureg_saturate(dst);
320 }
321 break;
322
323 case TGSI_PROCESSOR_FRAGMENT:
324 if (DstReg->Index >= FRAG_RESULT_COLOR) {
325 dst = ureg_saturate(dst);
326 }
327 break;
328 }
329 }
330
331 if (DstReg->RelAddr)
332 dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
333
334 return dst;
335 }
336
337
338 /**
339 * Create a TGSI ureg_src register from a Mesa src register.
340 */
341 static struct ureg_src
342 translate_src( struct st_translate *t,
343 const struct prog_src_register *SrcReg )
344 {
345 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
346
347 if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
348 src = src_register( t, SrcReg->File, SrcReg->Index2 );
349 if (SrcReg->RelAddr2)
350 src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
351 SrcReg->Index);
352 else
353 src = ureg_src_dimension( src, SrcReg->Index);
354 }
355
356 src = ureg_swizzle( src,
357 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
358 GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
359 GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
360 GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
361
362 if (SrcReg->Negate == NEGATE_XYZW)
363 src = ureg_negate(src);
364
365 if (SrcReg->Abs)
366 src = ureg_abs(src);
367
368 if (SrcReg->RelAddr) {
369 src = ureg_src_indirect( src, ureg_src(t->address[0]));
370 if (SrcReg->File != PROGRAM_INPUT &&
371 SrcReg->File != PROGRAM_OUTPUT) {
372 /* If SrcReg->Index was negative, it was set to zero in
373 * src_register(). Reassign it now. But don't do this
374 * for input/output regs since they get remapped while
375 * const buffers don't.
376 */
377 src.Index = SrcReg->Index;
378 }
379 }
380
381 return src;
382 }
383
384
385 static struct ureg_src swizzle_4v( struct ureg_src src,
386 const unsigned *swz )
387 {
388 return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
389 }
390
391
392 /**
393 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
394 *
395 * SWZ dst, src.x-y10
396 *
397 * becomes:
398 *
399 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
400 */
401 static void emit_swz( struct st_translate *t,
402 struct ureg_dst dst,
403 const struct prog_src_register *SrcReg )
404 {
405 struct ureg_program *ureg = t->ureg;
406 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
407
408 unsigned negate_mask = SrcReg->Negate;
409
410 unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
411 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
412 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
413 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
414
415 unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
416 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
417 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
418 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
419
420 unsigned negative_one_mask = one_mask & negate_mask;
421 unsigned positive_one_mask = one_mask & ~negate_mask;
422
423 struct ureg_src imm;
424 unsigned i;
425 unsigned mul_swizzle[4] = {0,0,0,0};
426 unsigned add_swizzle[4] = {0,0,0,0};
427 unsigned src_swizzle[4] = {0,0,0,0};
428 boolean need_add = FALSE;
429 boolean need_mul = FALSE;
430
431 if (dst.WriteMask == 0)
432 return;
433
434 /* Is this just a MOV?
435 */
436 if (zero_mask == 0 &&
437 one_mask == 0 &&
438 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
439 {
440 ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
441 return;
442 }
443
444 #define IMM_ZERO 0
445 #define IMM_ONE 1
446 #define IMM_NEG_ONE 2
447
448 imm = ureg_imm3f( ureg, 0, 1, -1 );
449
450 for (i = 0; i < 4; i++) {
451 unsigned bit = 1 << i;
452
453 if (dst.WriteMask & bit) {
454 if (positive_one_mask & bit) {
455 mul_swizzle[i] = IMM_ZERO;
456 add_swizzle[i] = IMM_ONE;
457 need_add = TRUE;
458 }
459 else if (negative_one_mask & bit) {
460 mul_swizzle[i] = IMM_ZERO;
461 add_swizzle[i] = IMM_NEG_ONE;
462 need_add = TRUE;
463 }
464 else if (zero_mask & bit) {
465 mul_swizzle[i] = IMM_ZERO;
466 add_swizzle[i] = IMM_ZERO;
467 need_add = TRUE;
468 }
469 else {
470 add_swizzle[i] = IMM_ZERO;
471 src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
472 need_mul = TRUE;
473 if (negate_mask & bit) {
474 mul_swizzle[i] = IMM_NEG_ONE;
475 }
476 else {
477 mul_swizzle[i] = IMM_ONE;
478 }
479 }
480 }
481 }
482
483 if (need_mul && need_add) {
484 ureg_MAD( ureg,
485 dst,
486 swizzle_4v( src, src_swizzle ),
487 swizzle_4v( imm, mul_swizzle ),
488 swizzle_4v( imm, add_swizzle ) );
489 }
490 else if (need_mul) {
491 ureg_MUL( ureg,
492 dst,
493 swizzle_4v( src, src_swizzle ),
494 swizzle_4v( imm, mul_swizzle ) );
495 }
496 else if (need_add) {
497 ureg_MOV( ureg,
498 dst,
499 swizzle_4v( imm, add_swizzle ) );
500 }
501 else {
502 debug_assert(0);
503 }
504
505 #undef IMM_ZERO
506 #undef IMM_ONE
507 #undef IMM_NEG_ONE
508 }
509
510
511 /**
512 * Negate the value of DDY to match GL semantics where (0,0) is the
513 * lower-left corner of the window.
514 * Note that the GL_ARB_fragment_coord_conventions extension will
515 * effect this someday.
516 */
517 static void emit_ddy( struct st_translate *t,
518 struct ureg_dst dst,
519 const struct prog_src_register *SrcReg )
520 {
521 struct ureg_program *ureg = t->ureg;
522 struct ureg_src src = translate_src( t, SrcReg );
523 src = ureg_negate( src );
524 ureg_DDY( ureg, dst, src );
525 }
526
527
528
529 static unsigned
530 translate_opcode( unsigned op )
531 {
532 switch( op ) {
533 case OPCODE_ARL:
534 return TGSI_OPCODE_ARL;
535 case OPCODE_ABS:
536 return TGSI_OPCODE_ABS;
537 case OPCODE_ADD:
538 return TGSI_OPCODE_ADD;
539 case OPCODE_BGNLOOP:
540 return TGSI_OPCODE_BGNLOOP;
541 case OPCODE_BGNSUB:
542 return TGSI_OPCODE_BGNSUB;
543 case OPCODE_BRK:
544 return TGSI_OPCODE_BRK;
545 case OPCODE_CAL:
546 return TGSI_OPCODE_CAL;
547 case OPCODE_CMP:
548 return TGSI_OPCODE_CMP;
549 case OPCODE_CONT:
550 return TGSI_OPCODE_CONT;
551 case OPCODE_COS:
552 return TGSI_OPCODE_COS;
553 case OPCODE_DDX:
554 return TGSI_OPCODE_DDX;
555 case OPCODE_DDY:
556 return TGSI_OPCODE_DDY;
557 case OPCODE_DP2:
558 return TGSI_OPCODE_DP2;
559 case OPCODE_DP3:
560 return TGSI_OPCODE_DP3;
561 case OPCODE_DP4:
562 return TGSI_OPCODE_DP4;
563 case OPCODE_DPH:
564 return TGSI_OPCODE_DPH;
565 case OPCODE_DST:
566 return TGSI_OPCODE_DST;
567 case OPCODE_ELSE:
568 return TGSI_OPCODE_ELSE;
569 case OPCODE_ENDIF:
570 return TGSI_OPCODE_ENDIF;
571 case OPCODE_ENDLOOP:
572 return TGSI_OPCODE_ENDLOOP;
573 case OPCODE_ENDSUB:
574 return TGSI_OPCODE_ENDSUB;
575 case OPCODE_EX2:
576 return TGSI_OPCODE_EX2;
577 case OPCODE_EXP:
578 return TGSI_OPCODE_EXP;
579 case OPCODE_FLR:
580 return TGSI_OPCODE_FLR;
581 case OPCODE_FRC:
582 return TGSI_OPCODE_FRC;
583 case OPCODE_IF:
584 return TGSI_OPCODE_IF;
585 case OPCODE_TRUNC:
586 return TGSI_OPCODE_TRUNC;
587 case OPCODE_KIL:
588 return TGSI_OPCODE_KILL_IF;
589 case OPCODE_KIL_NV:
590 /* XXX we don't support condition codes in TGSI */
591 return TGSI_OPCODE_KILL;
592 case OPCODE_LG2:
593 return TGSI_OPCODE_LG2;
594 case OPCODE_LOG:
595 return TGSI_OPCODE_LOG;
596 case OPCODE_LIT:
597 return TGSI_OPCODE_LIT;
598 case OPCODE_LRP:
599 return TGSI_OPCODE_LRP;
600 case OPCODE_MAD:
601 return TGSI_OPCODE_MAD;
602 case OPCODE_MAX:
603 return TGSI_OPCODE_MAX;
604 case OPCODE_MIN:
605 return TGSI_OPCODE_MIN;
606 case OPCODE_MOV:
607 return TGSI_OPCODE_MOV;
608 case OPCODE_MUL:
609 return TGSI_OPCODE_MUL;
610 case OPCODE_NOP:
611 return TGSI_OPCODE_NOP;
612 case OPCODE_POW:
613 return TGSI_OPCODE_POW;
614 case OPCODE_RCP:
615 return TGSI_OPCODE_RCP;
616 case OPCODE_RET:
617 return TGSI_OPCODE_RET;
618 case OPCODE_RSQ:
619 return TGSI_OPCODE_RSQ;
620 case OPCODE_SCS:
621 return TGSI_OPCODE_SCS;
622 case OPCODE_SEQ:
623 return TGSI_OPCODE_SEQ;
624 case OPCODE_SGE:
625 return TGSI_OPCODE_SGE;
626 case OPCODE_SGT:
627 return TGSI_OPCODE_SGT;
628 case OPCODE_SIN:
629 return TGSI_OPCODE_SIN;
630 case OPCODE_SLE:
631 return TGSI_OPCODE_SLE;
632 case OPCODE_SLT:
633 return TGSI_OPCODE_SLT;
634 case OPCODE_SNE:
635 return TGSI_OPCODE_SNE;
636 case OPCODE_SSG:
637 return TGSI_OPCODE_SSG;
638 case OPCODE_SUB:
639 return TGSI_OPCODE_SUB;
640 case OPCODE_TEX:
641 return TGSI_OPCODE_TEX;
642 case OPCODE_TXB:
643 return TGSI_OPCODE_TXB;
644 case OPCODE_TXD:
645 return TGSI_OPCODE_TXD;
646 case OPCODE_TXL:
647 return TGSI_OPCODE_TXL;
648 case OPCODE_TXP:
649 return TGSI_OPCODE_TXP;
650 case OPCODE_XPD:
651 return TGSI_OPCODE_XPD;
652 case OPCODE_END:
653 return TGSI_OPCODE_END;
654 default:
655 debug_assert( 0 );
656 return TGSI_OPCODE_NOP;
657 }
658 }
659
660
661 static void
662 compile_instruction(
663 struct gl_context *ctx,
664 struct st_translate *t,
665 const struct prog_instruction *inst,
666 boolean clamp_dst_color_output)
667 {
668 struct ureg_program *ureg = t->ureg;
669 GLuint i;
670 struct ureg_dst dst[1] = { { 0 } };
671 struct ureg_src src[4];
672 unsigned num_dst;
673 unsigned num_src;
674
675 num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
676 num_src = _mesa_num_inst_src_regs( inst->Opcode );
677
678 if (num_dst)
679 dst[0] = translate_dst( t,
680 &inst->DstReg,
681 inst->SaturateMode,
682 clamp_dst_color_output);
683
684 for (i = 0; i < num_src; i++)
685 src[i] = translate_src( t, &inst->SrcReg[i] );
686
687 switch( inst->Opcode ) {
688 case OPCODE_SWZ:
689 emit_swz( t, dst[0], &inst->SrcReg[0] );
690 return;
691
692 case OPCODE_BGNLOOP:
693 case OPCODE_CAL:
694 case OPCODE_ELSE:
695 case OPCODE_ENDLOOP:
696 debug_assert(num_dst == 0);
697 ureg_label_insn( ureg,
698 translate_opcode( inst->Opcode ),
699 src, num_src,
700 get_label( t, inst->BranchTarget ));
701 return;
702
703 case OPCODE_IF:
704 debug_assert(num_dst == 0);
705 ureg_label_insn( ureg,
706 ctx->Const.NativeIntegers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF,
707 src, num_src,
708 get_label( t, inst->BranchTarget ));
709 return;
710
711 case OPCODE_TEX:
712 case OPCODE_TXB:
713 case OPCODE_TXD:
714 case OPCODE_TXL:
715 case OPCODE_TXP:
716 src[num_src++] = t->samplers[inst->TexSrcUnit];
717 ureg_tex_insn( ureg,
718 translate_opcode( inst->Opcode ),
719 dst, num_dst,
720 st_translate_texture_target( inst->TexSrcTarget,
721 inst->TexShadow ),
722 NULL, 0,
723 src, num_src );
724 return;
725
726 case OPCODE_SCS:
727 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
728 ureg_insn( ureg,
729 translate_opcode( inst->Opcode ),
730 dst, num_dst,
731 src, num_src );
732 break;
733
734 case OPCODE_XPD:
735 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
736 ureg_insn( ureg,
737 translate_opcode( inst->Opcode ),
738 dst, num_dst,
739 src, num_src );
740 break;
741
742 case OPCODE_NOISE1:
743 case OPCODE_NOISE2:
744 case OPCODE_NOISE3:
745 case OPCODE_NOISE4:
746 /* At some point, a motivated person could add a better
747 * implementation of noise. Currently not even the nvidia
748 * binary drivers do anything more than this. In any case, the
749 * place to do this is in the GL state tracker, not the poor
750 * driver.
751 */
752 ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
753 break;
754
755 case OPCODE_DDY:
756 emit_ddy( t, dst[0], &inst->SrcReg[0] );
757 break;
758
759 default:
760 ureg_insn( ureg,
761 translate_opcode( inst->Opcode ),
762 dst, num_dst,
763 src, num_src );
764 break;
765 }
766 }
767
768
769 /**
770 * Emit the TGSI instructions for inverting and adjusting WPOS.
771 * This code is unavoidable because it also depends on whether
772 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
773 */
774 static void
775 emit_wpos_adjustment( struct st_translate *t,
776 const struct gl_program *program,
777 boolean invert,
778 GLfloat adjX, GLfloat adjY[2])
779 {
780 struct ureg_program *ureg = t->ureg;
781
782 /* Fragment program uses fragment position input.
783 * Need to replace instances of INPUT[WPOS] with temp T
784 * where T = INPUT[WPOS] by y is inverted.
785 */
786 static const gl_state_index wposTransformState[STATE_LENGTH]
787 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
788
789 /* XXX: note we are modifying the incoming shader here! Need to
790 * do this before emitting the constant decls below, or this
791 * will be missed:
792 */
793 unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
794 wposTransformState);
795
796 struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
797 struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
798 struct ureg_src wpos_input = t->inputs[t->inputMapping[VARYING_SLOT_POS]];
799
800 /* First, apply the coordinate shift: */
801 if (adjX || adjY[0] || adjY[1]) {
802 if (adjY[0] != adjY[1]) {
803 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
804 * depending on whether inversion is actually going to be applied
805 * or not, which is determined by testing against the inversion
806 * state variable used below, which will be either +1 or -1.
807 */
808 struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
809
810 ureg_CMP(ureg, adj_temp,
811 ureg_scalar(wpostrans, invert ? 2 : 0),
812 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
813 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
814 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
815 } else {
816 ureg_ADD(ureg, wpos_temp, wpos_input,
817 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
818 }
819 wpos_input = ureg_src(wpos_temp);
820 } else {
821 /* MOV wpos_temp, input[wpos]
822 */
823 ureg_MOV( ureg, wpos_temp, wpos_input );
824 }
825
826 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
827 * inversion/identity, or the other way around if we're drawing to an FBO.
828 */
829 if (invert) {
830 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
831 */
832 ureg_MAD( ureg,
833 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
834 wpos_input,
835 ureg_scalar(wpostrans, 0),
836 ureg_scalar(wpostrans, 1));
837 } else {
838 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
839 */
840 ureg_MAD( ureg,
841 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
842 wpos_input,
843 ureg_scalar(wpostrans, 2),
844 ureg_scalar(wpostrans, 3));
845 }
846
847 /* Use wpos_temp as position input from here on:
848 */
849 t->inputs[t->inputMapping[VARYING_SLOT_POS]] = ureg_src(wpos_temp);
850 }
851
852
853 /**
854 * Emit fragment position/ooordinate code.
855 */
856 static void
857 emit_wpos(struct st_context *st,
858 struct st_translate *t,
859 const struct gl_program *program,
860 struct ureg_program *ureg)
861 {
862 const struct gl_fragment_program *fp =
863 (const struct gl_fragment_program *) program;
864 struct pipe_screen *pscreen = st->pipe->screen;
865 GLfloat adjX = 0.0f;
866 GLfloat adjY[2] = { 0.0f, 0.0f };
867 boolean invert = FALSE;
868
869 /* Query the pixel center conventions supported by the pipe driver and set
870 * adjX, adjY to help out if it cannot handle the requested one internally.
871 *
872 * The bias of the y-coordinate depends on whether y-inversion takes place
873 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
874 * drawing to an FBO (causes additional inversion), and whether the the pipe
875 * driver origin and the requested origin differ (the latter condition is
876 * stored in the 'invert' variable).
877 *
878 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
879 *
880 * center shift only:
881 * i -> h: +0.5
882 * h -> i: -0.5
883 *
884 * inversion only:
885 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
886 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
887 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
888 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
889 *
890 * inversion and center shift:
891 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
892 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
893 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
894 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
895 */
896 if (fp->OriginUpperLeft) {
897 /* Fragment shader wants origin in upper-left */
898 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
899 /* the driver supports upper-left origin */
900 }
901 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
902 /* the driver supports lower-left origin, need to invert Y */
903 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
904 invert = TRUE;
905 }
906 else
907 assert(0);
908 }
909 else {
910 /* Fragment shader wants origin in lower-left */
911 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
912 /* the driver supports lower-left origin */
913 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
914 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
915 /* the driver supports upper-left origin, need to invert Y */
916 invert = TRUE;
917 else
918 assert(0);
919 }
920
921 if (fp->PixelCenterInteger) {
922 /* Fragment shader wants pixel center integer */
923 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
924 /* the driver supports pixel center integer */
925 adjY[1] = 1.0f;
926 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
927 }
928 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
929 /* the driver supports pixel center half integer, need to bias X,Y */
930 adjX = -0.5f;
931 adjY[0] = -0.5f;
932 adjY[1] = 0.5f;
933 }
934 else
935 assert(0);
936 }
937 else {
938 /* Fragment shader wants pixel center half integer */
939 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
940 /* the driver supports pixel center half integer */
941 }
942 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
943 /* the driver supports pixel center integer, need to bias X,Y */
944 adjX = adjY[0] = adjY[1] = 0.5f;
945 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
946 }
947 else
948 assert(0);
949 }
950
951 /* we invert after adjustment so that we avoid the MOV to temporary,
952 * and reuse the adjustment ADD instead */
953 emit_wpos_adjustment(t, program, invert, adjX, adjY);
954 }
955
956
957 /**
958 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
959 * TGSI uses +1 for front, -1 for back.
960 * This function converts the TGSI value to the GL value. Simply clamping/
961 * saturating the value to [0,1] does the job.
962 */
963 static void
964 emit_face_var( struct st_translate *t,
965 const struct gl_program *program )
966 {
967 struct ureg_program *ureg = t->ureg;
968 struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
969 struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
970
971 /* MOV_SAT face_temp, input[face]
972 */
973 face_temp = ureg_saturate( face_temp );
974 ureg_MOV( ureg, face_temp, face_input );
975
976 /* Use face_temp as face input from here on:
977 */
978 t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
979 }
980
981
982 static void
983 emit_edgeflags( struct st_translate *t,
984 const struct gl_program *program )
985 {
986 struct ureg_program *ureg = t->ureg;
987 struct ureg_dst edge_dst = t->outputs[t->outputMapping[VARYING_SLOT_EDGE]];
988 struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
989
990 ureg_MOV( ureg, edge_dst, edge_src );
991 }
992
993
994 /**
995 * Translate Mesa program to TGSI format.
996 * \param program the program to translate
997 * \param numInputs number of input registers used
998 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
999 * input indexes
1000 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
1001 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
1002 * each input
1003 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
1004 * \param numOutputs number of output registers used
1005 * \param outputMapping maps Mesa fragment program outputs to TGSI
1006 * generic outputs
1007 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
1008 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
1009 * each output
1010 *
1011 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
1012 */
1013 enum pipe_error
1014 st_translate_mesa_program(
1015 struct gl_context *ctx,
1016 uint procType,
1017 struct ureg_program *ureg,
1018 const struct gl_program *program,
1019 GLuint numInputs,
1020 const GLuint inputMapping[],
1021 const ubyte inputSemanticName[],
1022 const ubyte inputSemanticIndex[],
1023 const GLuint interpMode[],
1024 GLuint numOutputs,
1025 const GLuint outputMapping[],
1026 const ubyte outputSemanticName[],
1027 const ubyte outputSemanticIndex[],
1028 boolean passthrough_edgeflags,
1029 boolean clamp_color)
1030 {
1031 struct st_translate translate, *t;
1032 unsigned i;
1033 enum pipe_error ret = PIPE_OK;
1034
1035 assert(numInputs <= Elements(t->inputs));
1036 assert(numOutputs <= Elements(t->outputs));
1037
1038 t = &translate;
1039 memset(t, 0, sizeof *t);
1040
1041 t->procType = procType;
1042 t->inputMapping = inputMapping;
1043 t->outputMapping = outputMapping;
1044 t->ureg = ureg;
1045
1046 /*_mesa_print_program(program);*/
1047
1048 /*
1049 * Declare input attributes.
1050 */
1051 if (procType == TGSI_PROCESSOR_FRAGMENT) {
1052 for (i = 0; i < numInputs; i++) {
1053 t->inputs[i] = ureg_DECL_fs_input(ureg,
1054 inputSemanticName[i],
1055 inputSemanticIndex[i],
1056 interpMode[i]);
1057 }
1058
1059 if (program->InputsRead & VARYING_BIT_POS) {
1060 /* Must do this after setting up t->inputs, and before
1061 * emitting constant references, below:
1062 */
1063 emit_wpos(st_context(ctx), t, program, ureg);
1064 }
1065
1066 if (program->InputsRead & VARYING_BIT_FACE) {
1067 emit_face_var( t, program );
1068 }
1069
1070 /*
1071 * Declare output attributes.
1072 */
1073 for (i = 0; i < numOutputs; i++) {
1074 switch (outputSemanticName[i]) {
1075 case TGSI_SEMANTIC_POSITION:
1076 t->outputs[i] = ureg_DECL_output( ureg,
1077 TGSI_SEMANTIC_POSITION, /* Z / Depth */
1078 outputSemanticIndex[i] );
1079
1080 t->outputs[i] = ureg_writemask( t->outputs[i],
1081 TGSI_WRITEMASK_Z );
1082 break;
1083 case TGSI_SEMANTIC_STENCIL:
1084 t->outputs[i] = ureg_DECL_output( ureg,
1085 TGSI_SEMANTIC_STENCIL, /* Stencil */
1086 outputSemanticIndex[i] );
1087 t->outputs[i] = ureg_writemask( t->outputs[i],
1088 TGSI_WRITEMASK_Y );
1089 break;
1090 case TGSI_SEMANTIC_COLOR:
1091 t->outputs[i] = ureg_DECL_output( ureg,
1092 TGSI_SEMANTIC_COLOR,
1093 outputSemanticIndex[i] );
1094 break;
1095 default:
1096 debug_assert(0);
1097 return 0;
1098 }
1099 }
1100 }
1101 else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1102 for (i = 0; i < numInputs; i++) {
1103 t->inputs[i] = ureg_DECL_gs_input(ureg,
1104 i,
1105 inputSemanticName[i],
1106 inputSemanticIndex[i]);
1107 }
1108
1109 for (i = 0; i < numOutputs; i++) {
1110 t->outputs[i] = ureg_DECL_output( ureg,
1111 outputSemanticName[i],
1112 outputSemanticIndex[i] );
1113 }
1114 }
1115 else {
1116 assert(procType == TGSI_PROCESSOR_VERTEX);
1117
1118 for (i = 0; i < numInputs; i++) {
1119 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1120 }
1121
1122 for (i = 0; i < numOutputs; i++) {
1123 t->outputs[i] = ureg_DECL_output( ureg,
1124 outputSemanticName[i],
1125 outputSemanticIndex[i] );
1126 }
1127 if (passthrough_edgeflags)
1128 emit_edgeflags( t, program );
1129 }
1130
1131 /* Declare address register.
1132 */
1133 if (program->NumAddressRegs > 0) {
1134 debug_assert( program->NumAddressRegs == 1 );
1135 t->address[0] = ureg_DECL_address( ureg );
1136 }
1137
1138 /* Declare misc input registers
1139 */
1140 {
1141 GLbitfield sysInputs = program->SystemValuesRead;
1142 unsigned numSys = 0;
1143 for (i = 0; sysInputs; i++) {
1144 if (sysInputs & (1 << i)) {
1145 unsigned semName = mesa_sysval_to_semantic[i];
1146 t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1147 if (semName == TGSI_SEMANTIC_INSTANCEID ||
1148 semName == TGSI_SEMANTIC_VERTEXID) {
1149 /* From Gallium perspective, these system values are always
1150 * integer, and require native integer support. However, if
1151 * native integer is supported on the vertex stage but not the
1152 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1153 * assumes these system values are floats. To resolve the
1154 * inconsistency, we insert a U2F.
1155 */
1156 struct st_context *st = st_context(ctx);
1157 struct pipe_screen *pscreen = st->pipe->screen;
1158 assert(procType == TGSI_PROCESSOR_VERTEX);
1159 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
1160 (void) pscreen; /* silence non-debug build warnings */
1161 if (!ctx->Const.NativeIntegers) {
1162 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
1163 ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
1164 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
1165 }
1166 }
1167 numSys++;
1168 sysInputs &= ~(1 << i);
1169 }
1170 }
1171 }
1172
1173 if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1174 /* If temps are accessed with indirect addressing, declare temporaries
1175 * in sequential order. Else, we declare them on demand elsewhere.
1176 */
1177 for (i = 0; i < program->NumTemporaries; i++) {
1178 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1179 t->temps[i] = ureg_DECL_temporary( t->ureg );
1180 }
1181 }
1182
1183 /* Emit constants and immediates. Mesa uses a single index space
1184 * for these, so we put all the translated regs in t->constants.
1185 */
1186 if (program->Parameters) {
1187 t->constants = calloc( program->Parameters->NumParameters,
1188 sizeof t->constants[0] );
1189 if (t->constants == NULL) {
1190 ret = PIPE_ERROR_OUT_OF_MEMORY;
1191 goto out;
1192 }
1193
1194 for (i = 0; i < program->Parameters->NumParameters; i++) {
1195 switch (program->Parameters->Parameters[i].Type) {
1196 case PROGRAM_ENV_PARAM:
1197 case PROGRAM_LOCAL_PARAM:
1198 case PROGRAM_STATE_VAR:
1199 case PROGRAM_UNIFORM:
1200 t->constants[i] = ureg_DECL_constant( ureg, i );
1201 break;
1202
1203 /* Emit immediates only when there's no indirect addressing of
1204 * the const buffer.
1205 * FIXME: Be smarter and recognize param arrays:
1206 * indirect addressing is only valid within the referenced
1207 * array.
1208 */
1209 case PROGRAM_CONSTANT:
1210 if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1211 t->constants[i] = ureg_DECL_constant( ureg, i );
1212 else
1213 t->constants[i] =
1214 ureg_DECL_immediate( ureg,
1215 (const float*) program->Parameters->ParameterValues[i],
1216 4 );
1217 break;
1218 default:
1219 break;
1220 }
1221 }
1222 }
1223
1224 /* texture samplers */
1225 for (i = 0; i < ctx->Const.FragmentProgram.MaxTextureImageUnits; i++) {
1226 if (program->SamplersUsed & (1 << i)) {
1227 t->samplers[i] = ureg_DECL_sampler( ureg, i );
1228 }
1229 }
1230
1231 /* Emit each instruction in turn:
1232 */
1233 for (i = 0; i < program->NumInstructions; i++) {
1234 set_insn_start( t, ureg_get_instruction_number( ureg ));
1235 compile_instruction( ctx, t, &program->Instructions[i], clamp_color );
1236 }
1237
1238 /* Fix up all emitted labels:
1239 */
1240 for (i = 0; i < t->labels_count; i++) {
1241 ureg_fixup_label( ureg,
1242 t->labels[i].token,
1243 t->insn[t->labels[i].branch_target] );
1244 }
1245
1246 out:
1247 free(t->insn);
1248 free(t->labels);
1249 free(t->constants);
1250
1251 if (t->error) {
1252 debug_printf("%s: translate error flag set\n", __FUNCTION__);
1253 }
1254
1255 return ret;
1256 }
1257
1258
1259 /**
1260 * Tokens cannot be free with free otherwise the builtin gallium
1261 * malloc debugging will get confused.
1262 */
1263 void
1264 st_free_tokens(const struct tgsi_token *tokens)
1265 {
1266 ureg_free_tokens(tokens);
1267 }