src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_screen.h"
  37 #include "pipe/p_shader_tokens.h"
  38 #include "pipe/p_state.h"
  39 #include "tgsi/tgsi_ureg.h"
  40 #include "st_mesa_to_tgsi.h"
  41 #include "st_context.h"
  42 #include "program/prog_instruction.h"
  43 #include "program/prog_parameter.h"
  44 #include "util/u_debug.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47
  48
  49 #define PROGRAM_ANY_CONST ((1 << PROGRAM_LOCAL_PARAM) |  \
  50                            (1 << PROGRAM_ENV_PARAM) |    \
  51                            (1 << PROGRAM_STATE_VAR) |    \
  52                            (1 << PROGRAM_CONSTANT) |     \
  53                            (1 << PROGRAM_UNIFORM))
  54
  55
  56 struct label {
  57    unsigned branch_target;
  58    unsigned token;
  59 };
  60
  61
  62 /**
  63  * Intermediate state used during shader translation.
  64  */
  65 struct st_translate {
  66    struct ureg_program *ureg;
  67
  68    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  69    struct ureg_src *constants;
  70    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  71    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  72    struct ureg_dst address[1];
  73    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  74    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  75
  76    const GLuint *inputMapping;
  77    const GLuint *outputMapping;
  78
  79    /* For every instruction that contains a label (eg CALL), keep
  80     * details so that we can go back afterwards and emit the correct
  81     * tgsi instruction number for each label.
  82     */
  83    struct label *labels;
  84    unsigned labels_size;
  85    unsigned labels_count;
  86
  87    /* Keep a record of the tgsi instruction number that each mesa
  88     * instruction starts at, will be used to fix up labels after
  89     * translation.
  90     */
  91    unsigned *insn;
  92    unsigned insn_size;
  93    unsigned insn_count;
  94
  95    unsigned procType;  /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
  96
  97    boolean error;
  98 };
  99
 100
 101 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
 102 static unsigned mesa_sysval_to_semantic[SYSTEM_VALUE_MAX] = {
 103    TGSI_SEMANTIC_FACE,
 104    TGSI_SEMANTIC_VERTEXID,
 105    TGSI_SEMANTIC_INSTANCEID
 106 };
 107
 108
 109 /**
 110  * Make note of a branch to a label in the TGSI code.
 111  * After we've emitted all instructions, we'll go over the list
 112  * of labels built here and patch the TGSI code with the actual
 113  * location of each label.
 114  */
 115 static unsigned *get_label( struct st_translate *t,
 116                             unsigned branch_target )
 117 {
 118    unsigned i;
 119
 120    if (t->labels_count + 1 >= t->labels_size) {
 121       t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
 122       t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
 123       if (t->labels == NULL) {
 124          static unsigned dummy;
 125          t->error = TRUE;
 126          return &dummy;
 127       }
 128    }
 129
 130    i = t->labels_count++;
 131    t->labels[i].branch_target = branch_target;
 132    return &t->labels[i].token;
 133 }
 134
 135
 136 /**
 137  * Called prior to emitting the TGSI code for each Mesa instruction.
 138  * Allocate additional space for instructions if needed.
 139  * Update the insn[] array so the next Mesa instruction points to
 140  * the next TGSI instruction.
 141  */
 142 static void set_insn_start( struct st_translate *t,
 143                             unsigned start )
 144 {
 145    if (t->insn_count + 1 >= t->insn_size) {
 146       t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
 147       t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
 148       if (t->insn == NULL) {
 149          t->error = TRUE;
 150          return;
 151       }
 152    }
 153
 154    t->insn[t->insn_count++] = start;
 155 }
 156
 157
 158 /**
 159  * Map a Mesa dst register to a TGSI ureg_dst register.
 160  */
 161 static struct ureg_dst
 162 dst_register( struct st_translate *t,
 163               gl_register_file file,
 164               GLuint index )
 165 {
 166    switch( file ) {
 167    case PROGRAM_UNDEFINED:
 168       return ureg_dst_undef();
 169
 170    case PROGRAM_TEMPORARY:
 171       if (ureg_dst_is_undef(t->temps[index]))
 172          t->temps[index] = ureg_DECL_temporary( t->ureg );
 173
 174       return t->temps[index];
 175
 176    case PROGRAM_OUTPUT:
 177       if (t->procType == TGSI_PROCESSOR_VERTEX)
 178          assert(index < VERT_RESULT_MAX);
 179       else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
 180          assert(index < FRAG_RESULT_MAX);
 181       else
 182          assert(index < GEOM_RESULT_MAX);
 183
 184       assert(t->outputMapping[index] < Elements(t->outputs));
 185
 186       return t->outputs[t->outputMapping[index]];
 187
 188    case PROGRAM_ADDRESS:
 189       return t->address[index];
 190
 191    default:
 192       debug_assert( 0 );
 193       return ureg_dst_undef();
 194    }
 195 }
 196
 197
 198 /**
 199  * Map a Mesa src register to a TGSI ureg_src register.
 200  */
 201 static struct ureg_src
 202 src_register( struct st_translate *t,
 203               gl_register_file file,
 204               GLint index )
 205 {
 206    switch( file ) {
 207    case PROGRAM_UNDEFINED:
 208       return ureg_src_undef();
 209
 210    case PROGRAM_TEMPORARY:
 211       assert(index >= 0);
 212       assert(index < Elements(t->temps));
 213       if (ureg_dst_is_undef(t->temps[index]))
 214          t->temps[index] = ureg_DECL_temporary( t->ureg );
 215       return ureg_src(t->temps[index]);
 216
 217    case PROGRAM_ENV_PARAM:
 218    case PROGRAM_LOCAL_PARAM:
 219    case PROGRAM_UNIFORM:
 220       assert(index >= 0);
 221       return t->constants[index];
 222    case PROGRAM_STATE_VAR:
 223    case PROGRAM_CONSTANT:       /* ie, immediate */
 224       if (index < 0)
 225          return ureg_DECL_constant( t->ureg, 0 );
 226       else
 227          return t->constants[index];
 228
 229    case PROGRAM_INPUT:
 230       assert(t->inputMapping[index] < Elements(t->inputs));
 231       return t->inputs[t->inputMapping[index]];
 232
 233    case PROGRAM_OUTPUT:
 234       assert(t->outputMapping[index] < Elements(t->outputs));
 235       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 236
 237    case PROGRAM_ADDRESS:
 238       return ureg_src(t->address[index]);
 239
 240    case PROGRAM_SYSTEM_VALUE:
 241       assert(index < Elements(t->systemValues));
 242       return t->systemValues[index];
 243
 244    default:
 245       debug_assert( 0 );
 246       return ureg_src_undef();
 247    }
 248 }
 249
 250
 251 /**
 252  * Map mesa texture target to TGSI texture target.
 253  */
 254 unsigned
 255 st_translate_texture_target( GLuint textarget,
 256                           GLboolean shadow )
 257 {
 258    if (shadow) {
 259       switch( textarget ) {
 260       case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_SHADOW1D;
 261       case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_SHADOW2D;
 262       case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
 263       case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
 264       case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
 265       case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
 266       case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
 267       default: break;
 268       }
 269    }
 270
 271    switch( textarget ) {
 272    case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_1D;
 273    case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_2D;
 274    case TEXTURE_3D_INDEX:   return TGSI_TEXTURE_3D;
 275    case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
 276    case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_CUBE_ARRAY;
 277    case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
 278    case TEXTURE_1D_ARRAY_INDEX:   return TGSI_TEXTURE_1D_ARRAY;
 279    case TEXTURE_2D_ARRAY_INDEX:   return TGSI_TEXTURE_2D_ARRAY;
 280    case TEXTURE_EXTERNAL_INDEX:   return TGSI_TEXTURE_2D;
 281    default:
 282       debug_assert( 0 );
 283       return TGSI_TEXTURE_1D;
 284    }
 285 }
 286
 287
 288 /**
 289  * Create a TGSI ureg_dst register from a Mesa dest register.
 290  */
 291 static struct ureg_dst
 292 translate_dst( struct st_translate *t,
 293                const struct prog_dst_register *DstReg,
 294                boolean saturate,
 295                boolean clamp_color)
 296 {
 297    struct ureg_dst dst = dst_register( t,
 298                                        DstReg->File,
 299                                        DstReg->Index );
 300
 301    dst = ureg_writemask( dst,
 302                          DstReg->WriteMask );
 303
 304    if (saturate)
 305       dst = ureg_saturate( dst );
 306    else if (clamp_color && DstReg->File == PROGRAM_OUTPUT) {
 307       /* Clamp colors for ARB_color_buffer_float. */
 308       switch (t->procType) {
 309       case TGSI_PROCESSOR_VERTEX:
 310          /* XXX if the geometry shader is present, this must be done there
 311           * instead of here. */
 312          if (DstReg->Index == VERT_RESULT_COL0 ||
 313              DstReg->Index == VERT_RESULT_COL1 ||
 314              DstReg->Index == VERT_RESULT_BFC0 ||
 315              DstReg->Index == VERT_RESULT_BFC1) {
 316             dst = ureg_saturate(dst);
 317          }
 318          break;
 319
 320       case TGSI_PROCESSOR_FRAGMENT:
 321          if (DstReg->Index >= FRAG_RESULT_COLOR) {
 322             dst = ureg_saturate(dst);
 323          }
 324          break;
 325       }
 326    }
 327
 328    if (DstReg->RelAddr)
 329       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 330
 331    return dst;
 332 }
 333
 334
 335 /**
 336  * Create a TGSI ureg_src register from a Mesa src register.
 337  */
 338 static struct ureg_src
 339 translate_src( struct st_translate *t,
 340                const struct prog_src_register *SrcReg )
 341 {
 342    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 343
 344    if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
 345       src = src_register( t, SrcReg->File, SrcReg->Index2 );
 346       if (SrcReg->RelAddr2)
 347          src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
 348                                             SrcReg->Index);
 349       else
 350          src = ureg_src_dimension( src, SrcReg->Index);
 351    }
 352
 353    src = ureg_swizzle( src,
 354                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
 355                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
 356                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
 357                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 358
 359    if (SrcReg->Negate == NEGATE_XYZW)
 360       src = ureg_negate(src);
 361
 362    if (SrcReg->Abs)
 363       src = ureg_abs(src);
 364
 365    if (SrcReg->RelAddr) {
 366       src = ureg_src_indirect( src, ureg_src(t->address[0]));
 367       if (SrcReg->File != PROGRAM_INPUT &&
 368           SrcReg->File != PROGRAM_OUTPUT) {
 369          /* If SrcReg->Index was negative, it was set to zero in
 370           * src_register().  Reassign it now.  But don't do this
 371           * for input/output regs since they get remapped while
 372           * const buffers don't.
 373           */
 374          src.Index = SrcReg->Index;
 375       }
 376    }
 377
 378    return src;
 379 }
 380
 381
 382 static struct ureg_src swizzle_4v( struct ureg_src src,
 383                                    const unsigned *swz )
 384 {
 385    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
 386 }
 387
 388
 389 /**
 390  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 391  *
 392  *   SWZ dst, src.x-y10
 393  *
 394  * becomes:
 395  *
 396  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 397  */
 398 static void emit_swz( struct st_translate *t,
 399                       struct ureg_dst dst,
 400                       const struct prog_src_register *SrcReg )
 401 {
 402    struct ureg_program *ureg = t->ureg;
 403    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 404
 405    unsigned negate_mask =  SrcReg->Negate;
 406
 407    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 408                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 409                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 410                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 411
 412    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 413                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 414                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 415                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 416
 417    unsigned negative_one_mask = one_mask & negate_mask;
 418    unsigned positive_one_mask = one_mask & ~negate_mask;
 419
 420    struct ureg_src imm;
 421    unsigned i;
 422    unsigned mul_swizzle[4] = {0,0,0,0};
 423    unsigned add_swizzle[4] = {0,0,0,0};
 424    unsigned src_swizzle[4] = {0,0,0,0};
 425    boolean need_add = FALSE;
 426    boolean need_mul = FALSE;
 427
 428    if (dst.WriteMask == 0)
 429       return;
 430
 431    /* Is this just a MOV?
 432     */
 433    if (zero_mask == 0 &&
 434        one_mask == 0 &&
 435        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
 436    {
 437       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
 438       return;
 439    }
 440
 441 #define IMM_ZERO    0
 442 #define IMM_ONE     1
 443 #define IMM_NEG_ONE 2
 444
 445    imm = ureg_imm3f( ureg, 0, 1, -1 );
 446
 447    for (i = 0; i < 4; i++) {
 448       unsigned bit = 1 << i;
 449
 450       if (dst.WriteMask & bit) {
 451          if (positive_one_mask & bit) {
 452             mul_swizzle[i] = IMM_ZERO;
 453             add_swizzle[i] = IMM_ONE;
 454             need_add = TRUE;
 455          }
 456          else if (negative_one_mask & bit) {
 457             mul_swizzle[i] = IMM_ZERO;
 458             add_swizzle[i] = IMM_NEG_ONE;
 459             need_add = TRUE;
 460          }
 461          else if (zero_mask & bit) {
 462             mul_swizzle[i] = IMM_ZERO;
 463             add_swizzle[i] = IMM_ZERO;
 464             need_add = TRUE;
 465          }
 466          else {
 467             add_swizzle[i] = IMM_ZERO;
 468             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 469             need_mul = TRUE;
 470             if (negate_mask & bit) {
 471                mul_swizzle[i] = IMM_NEG_ONE;
 472             }
 473             else {
 474                mul_swizzle[i] = IMM_ONE;
 475             }
 476          }
 477       }
 478    }
 479
 480    if (need_mul && need_add) {
 481       ureg_MAD( ureg,
 482                 dst,
 483                 swizzle_4v( src, src_swizzle ),
 484                 swizzle_4v( imm, mul_swizzle ),
 485                 swizzle_4v( imm, add_swizzle ) );
 486    }
 487    else if (need_mul) {
 488       ureg_MUL( ureg,
 489                 dst,
 490                 swizzle_4v( src, src_swizzle ),
 491                 swizzle_4v( imm, mul_swizzle ) );
 492    }
 493    else if (need_add) {
 494       ureg_MOV( ureg,
 495                 dst,
 496                 swizzle_4v( imm, add_swizzle ) );
 497    }
 498    else {
 499       debug_assert(0);
 500    }
 501
 502 #undef IMM_ZERO
 503 #undef IMM_ONE
 504 #undef IMM_NEG_ONE
 505 }
 506
 507
 508 /**
 509  * Negate the value of DDY to match GL semantics where (0,0) is the
 510  * lower-left corner of the window.
 511  * Note that the GL_ARB_fragment_coord_conventions extension will
 512  * effect this someday.
 513  */
 514 static void emit_ddy( struct st_translate *t,
 515                       struct ureg_dst dst,
 516                       const struct prog_src_register *SrcReg )
 517 {
 518    struct ureg_program *ureg = t->ureg;
 519    struct ureg_src src = translate_src( t, SrcReg );
 520    src = ureg_negate( src );
 521    ureg_DDY( ureg, dst, src );
 522 }
 523
 524
 525
 526 static unsigned
 527 translate_opcode( unsigned op )
 528 {
 529    switch( op ) {
 530    case OPCODE_ARL:
 531       return TGSI_OPCODE_ARL;
 532    case OPCODE_ABS:
 533       return TGSI_OPCODE_ABS;
 534    case OPCODE_ADD:
 535       return TGSI_OPCODE_ADD;
 536    case OPCODE_BGNLOOP:
 537       return TGSI_OPCODE_BGNLOOP;
 538    case OPCODE_BGNSUB:
 539       return TGSI_OPCODE_BGNSUB;
 540    case OPCODE_BRK:
 541       return TGSI_OPCODE_BRK;
 542    case OPCODE_CAL:
 543       return TGSI_OPCODE_CAL;
 544    case OPCODE_CMP:
 545       return TGSI_OPCODE_CMP;
 546    case OPCODE_CONT:
 547       return TGSI_OPCODE_CONT;
 548    case OPCODE_COS:
 549       return TGSI_OPCODE_COS;
 550    case OPCODE_DDX:
 551       return TGSI_OPCODE_DDX;
 552    case OPCODE_DDY:
 553       return TGSI_OPCODE_DDY;
 554    case OPCODE_DP2:
 555       return TGSI_OPCODE_DP2;
 556    case OPCODE_DP2A:
 557       return TGSI_OPCODE_DP2A;
 558    case OPCODE_DP3:
 559       return TGSI_OPCODE_DP3;
 560    case OPCODE_DP4:
 561       return TGSI_OPCODE_DP4;
 562    case OPCODE_DPH:
 563       return TGSI_OPCODE_DPH;
 564    case OPCODE_DST:
 565       return TGSI_OPCODE_DST;
 566    case OPCODE_ELSE:
 567       return TGSI_OPCODE_ELSE;
 568    case OPCODE_ENDIF:
 569       return TGSI_OPCODE_ENDIF;
 570    case OPCODE_ENDLOOP:
 571       return TGSI_OPCODE_ENDLOOP;
 572    case OPCODE_ENDSUB:
 573       return TGSI_OPCODE_ENDSUB;
 574    case OPCODE_EX2:
 575       return TGSI_OPCODE_EX2;
 576    case OPCODE_EXP:
 577       return TGSI_OPCODE_EXP;
 578    case OPCODE_FLR:
 579       return TGSI_OPCODE_FLR;
 580    case OPCODE_FRC:
 581       return TGSI_OPCODE_FRC;
 582    case OPCODE_IF:
 583       return TGSI_OPCODE_IF;
 584    case OPCODE_TRUNC:
 585       return TGSI_OPCODE_TRUNC;
 586    case OPCODE_KIL:
 587       return TGSI_OPCODE_KIL;
 588    case OPCODE_KIL_NV:
 589       return TGSI_OPCODE_KILP;
 590    case OPCODE_LG2:
 591       return TGSI_OPCODE_LG2;
 592    case OPCODE_LOG:
 593       return TGSI_OPCODE_LOG;
 594    case OPCODE_LIT:
 595       return TGSI_OPCODE_LIT;
 596    case OPCODE_LRP:
 597       return TGSI_OPCODE_LRP;
 598    case OPCODE_MAD:
 599       return TGSI_OPCODE_MAD;
 600    case OPCODE_MAX:
 601       return TGSI_OPCODE_MAX;
 602    case OPCODE_MIN:
 603       return TGSI_OPCODE_MIN;
 604    case OPCODE_MOV:
 605       return TGSI_OPCODE_MOV;
 606    case OPCODE_MUL:
 607       return TGSI_OPCODE_MUL;
 608    case OPCODE_NOP:
 609       return TGSI_OPCODE_NOP;
 610    case OPCODE_NRM3:
 611       return TGSI_OPCODE_NRM;
 612    case OPCODE_NRM4:
 613       return TGSI_OPCODE_NRM4;
 614    case OPCODE_POW:
 615       return TGSI_OPCODE_POW;
 616    case OPCODE_RCP:
 617       return TGSI_OPCODE_RCP;
 618    case OPCODE_RET:
 619       return TGSI_OPCODE_RET;
 620    case OPCODE_RSQ:
 621       return TGSI_OPCODE_RSQ;
 622    case OPCODE_SCS:
 623       return TGSI_OPCODE_SCS;
 624    case OPCODE_SEQ:
 625       return TGSI_OPCODE_SEQ;
 626    case OPCODE_SGE:
 627       return TGSI_OPCODE_SGE;
 628    case OPCODE_SGT:
 629       return TGSI_OPCODE_SGT;
 630    case OPCODE_SIN:
 631       return TGSI_OPCODE_SIN;
 632    case OPCODE_SLE:
 633       return TGSI_OPCODE_SLE;
 634    case OPCODE_SLT:
 635       return TGSI_OPCODE_SLT;
 636    case OPCODE_SNE:
 637       return TGSI_OPCODE_SNE;
 638    case OPCODE_SSG:
 639       return TGSI_OPCODE_SSG;
 640    case OPCODE_SUB:
 641       return TGSI_OPCODE_SUB;
 642    case OPCODE_TEX:
 643       return TGSI_OPCODE_TEX;
 644    case OPCODE_TXB:
 645       return TGSI_OPCODE_TXB;
 646    case OPCODE_TXD:
 647       return TGSI_OPCODE_TXD;
 648    case OPCODE_TXL:
 649       return TGSI_OPCODE_TXL;
 650    case OPCODE_TXP:
 651       return TGSI_OPCODE_TXP;
 652    case OPCODE_XPD:
 653       return TGSI_OPCODE_XPD;
 654    case OPCODE_END:
 655       return TGSI_OPCODE_END;
 656    default:
 657       debug_assert( 0 );
 658       return TGSI_OPCODE_NOP;
 659    }
 660 }
 661
 662
 663 static void
 664 compile_instruction(
 665    struct st_translate *t,
 666    const struct prog_instruction *inst,
 667    boolean clamp_dst_color_output)
 668 {
 669    struct ureg_program *ureg = t->ureg;
 670    GLuint i;
 671    struct ureg_dst dst[1] = { { 0 } };
 672    struct ureg_src src[4];
 673    unsigned num_dst;
 674    unsigned num_src;
 675
 676    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
 677    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 678
 679    if (num_dst)
 680       dst[0] = translate_dst( t,
 681                               &inst->DstReg,
 682                               inst->SaturateMode,
 683                               clamp_dst_color_output);
 684
 685    for (i = 0; i < num_src; i++)
 686       src[i] = translate_src( t, &inst->SrcReg[i] );
 687
 688    switch( inst->Opcode ) {
 689    case OPCODE_SWZ:
 690       emit_swz( t, dst[0], &inst->SrcReg[0] );
 691       return;
 692
 693    case OPCODE_BGNLOOP:
 694    case OPCODE_CAL:
 695    case OPCODE_ELSE:
 696    case OPCODE_ENDLOOP:
 697    case OPCODE_IF:
 698       debug_assert(num_dst == 0);
 699       ureg_label_insn( ureg,
 700                        translate_opcode( inst->Opcode ),
 701                        src, num_src,
 702                        get_label( t, inst->BranchTarget ));
 703       return;
 704
 705    case OPCODE_TEX:
 706    case OPCODE_TXB:
 707    case OPCODE_TXD:
 708    case OPCODE_TXL:
 709    case OPCODE_TXP:
 710       src[num_src++] = t->samplers[inst->TexSrcUnit];
 711       ureg_tex_insn( ureg,
 712                      translate_opcode( inst->Opcode ),
 713                      dst, num_dst,
 714                      st_translate_texture_target( inst->TexSrcTarget,
 715                                                inst->TexShadow ),
 716                      NULL, 0,
 717                      src, num_src );
 718       return;
 719
 720    case OPCODE_SCS:
 721       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
 722       ureg_insn( ureg,
 723                  translate_opcode( inst->Opcode ),
 724                  dst, num_dst,
 725                  src, num_src );
 726       break;
 727
 728    case OPCODE_XPD:
 729       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
 730       ureg_insn( ureg,
 731                  translate_opcode( inst->Opcode ),
 732                  dst, num_dst,
 733                  src, num_src );
 734       break;
 735
 736    case OPCODE_NOISE1:
 737    case OPCODE_NOISE2:
 738    case OPCODE_NOISE3:
 739    case OPCODE_NOISE4:
 740       /* At some point, a motivated person could add a better
 741        * implementation of noise.  Currently not even the nvidia
 742        * binary drivers do anything more than this.  In any case, the
 743        * place to do this is in the GL state tracker, not the poor
 744        * driver.
 745        */
 746       ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
 747       break;
 748
 749    case OPCODE_DDY:
 750       emit_ddy( t, dst[0], &inst->SrcReg[0] );
 751       break;
 752
 753    default:
 754       ureg_insn( ureg,
 755                  translate_opcode( inst->Opcode ),
 756                  dst, num_dst,
 757                  src, num_src );
 758       break;
 759    }
 760 }
 761
 762
 763 /**
 764  * Emit the TGSI instructions for inverting and adjusting WPOS.
 765  * This code is unavoidable because it also depends on whether
 766  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
 767  */
 768 static void
 769 emit_wpos_adjustment( struct st_translate *t,
 770                       const struct gl_program *program,
 771                       boolean invert,
 772                       GLfloat adjX, GLfloat adjY[2])
 773 {
 774    struct ureg_program *ureg = t->ureg;
 775
 776    /* Fragment program uses fragment position input.
 777     * Need to replace instances of INPUT[WPOS] with temp T
 778     * where T = INPUT[WPOS] by y is inverted.
 779     */
 780    static const gl_state_index wposTransformState[STATE_LENGTH]
 781       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
 782
 783    /* XXX: note we are modifying the incoming shader here!  Need to
 784     * do this before emitting the constant decls below, or this
 785     * will be missed:
 786     */
 787    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
 788                                                        wposTransformState);
 789
 790    struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
 791    struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
 792    struct ureg_src wpos_input = t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]];
 793
 794    /* First, apply the coordinate shift: */
 795    if (adjX || adjY[0] || adjY[1]) {
 796       if (adjY[0] != adjY[1]) {
 797          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
 798           * depending on whether inversion is actually going to be applied
 799           * or not, which is determined by testing against the inversion
 800           * state variable used below, which will be either +1 or -1.
 801           */
 802          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
 803
 804          ureg_CMP(ureg, adj_temp,
 805                   ureg_scalar(wpostrans, invert ? 2 : 0),
 806                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
 807                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
 808          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
 809       } else {
 810          ureg_ADD(ureg, wpos_temp, wpos_input,
 811                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
 812       }
 813       wpos_input = ureg_src(wpos_temp);
 814    } else {
 815       /* MOV wpos_temp, input[wpos]
 816        */
 817       ureg_MOV( ureg, wpos_temp, wpos_input );
 818    }
 819
 820    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
 821     * inversion/identity, or the other way around if we're drawing to an FBO.
 822     */
 823    if (invert) {
 824       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
 825        */
 826       ureg_MAD( ureg,
 827                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 828                 wpos_input,
 829                 ureg_scalar(wpostrans, 0),
 830                 ureg_scalar(wpostrans, 1));
 831    } else {
 832       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
 833        */
 834       ureg_MAD( ureg,
 835                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 836                 wpos_input,
 837                 ureg_scalar(wpostrans, 2),
 838                 ureg_scalar(wpostrans, 3));
 839    }
 840
 841    /* Use wpos_temp as position input from here on:
 842     */
 843    t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]] = ureg_src(wpos_temp);
 844 }
 845
 846
 847 /**
 848  * Emit fragment position/ooordinate code.
 849  */
 850 static void
 851 emit_wpos(struct st_context *st,
 852           struct st_translate *t,
 853           const struct gl_program *program,
 854           struct ureg_program *ureg)
 855 {
 856    const struct gl_fragment_program *fp =
 857       (const struct gl_fragment_program *) program;
 858    struct pipe_screen *pscreen = st->pipe->screen;
 859    GLfloat adjX = 0.0f;
 860    GLfloat adjY[2] = { 0.0f, 0.0f };
 861    boolean invert = FALSE;
 862
 863    /* Query the pixel center conventions supported by the pipe driver and set
 864     * adjX, adjY to help out if it cannot handle the requested one internally.
 865     *
 866     * The bias of the y-coordinate depends on whether y-inversion takes place
 867     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
 868     * drawing to an FBO (causes additional inversion), and whether the the pipe
 869     * driver origin and the requested origin differ (the latter condition is
 870     * stored in the 'invert' variable).
 871     *
 872     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
 873     *
 874     * center shift only:
 875     * i -> h: +0.5
 876     * h -> i: -0.5
 877     *
 878     * inversion only:
 879     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
 880     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
 881     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
 882     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
 883     *
 884     * inversion and center shift:
 885     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
 886     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
 887     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
 888     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
 889     */
 890    if (fp->OriginUpperLeft) {
 891       /* Fragment shader wants origin in upper-left */
 892       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 893          /* the driver supports upper-left origin */
 894       }
 895       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 896          /* the driver supports lower-left origin, need to invert Y */
 897          ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 898          invert = TRUE;
 899       }
 900       else
 901          assert(0);
 902    }
 903    else {
 904       /* Fragment shader wants origin in lower-left */
 905       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 906          /* the driver supports lower-left origin */
 907          ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 908       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 909          /* the driver supports upper-left origin, need to invert Y */
 910          invert = TRUE;
 911       else
 912          assert(0);
 913    }
 914
 915    if (fp->PixelCenterInteger) {
 916       /* Fragment shader wants pixel center integer */
 917       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 918          /* the driver supports pixel center integer */
 919          adjY[1] = 1.0f;
 920          ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 921       }
 922       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 923          /* the driver supports pixel center half integer, need to bias X,Y */
 924          adjX = -0.5f;
 925          adjY[0] = -0.5f;
 926          adjY[1] = 0.5f;
 927       }
 928       else
 929          assert(0);
 930    }
 931    else {
 932       /* Fragment shader wants pixel center half integer */
 933       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 934          /* the driver supports pixel center half integer */
 935       }
 936       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 937          /* the driver supports pixel center integer, need to bias X,Y */
 938          adjX = adjY[0] = adjY[1] = 0.5f;
 939          ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 940       }
 941       else
 942          assert(0);
 943    }
 944
 945    /* we invert after adjustment so that we avoid the MOV to temporary,
 946     * and reuse the adjustment ADD instead */
 947    emit_wpos_adjustment(t, program, invert, adjX, adjY);
 948 }
 949
 950
 951 /**
 952  * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
 953  * TGSI uses +1 for front, -1 for back.
 954  * This function converts the TGSI value to the GL value.  Simply clamping/
 955  * saturating the value to [0,1] does the job.
 956  */
 957 static void
 958 emit_face_var( struct st_translate *t,
 959                const struct gl_program *program )
 960 {
 961    struct ureg_program *ureg = t->ureg;
 962    struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
 963    struct ureg_src face_input = t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]];
 964
 965    /* MOV_SAT face_temp, input[face]
 966     */
 967    face_temp = ureg_saturate( face_temp );
 968    ureg_MOV( ureg, face_temp, face_input );
 969
 970    /* Use face_temp as face input from here on:
 971     */
 972    t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]] = ureg_src(face_temp);
 973 }
 974
 975
 976 static void
 977 emit_edgeflags( struct st_translate *t,
 978                  const struct gl_program *program )
 979 {
 980    struct ureg_program *ureg = t->ureg;
 981    struct ureg_dst edge_dst = t->outputs[t->outputMapping[VERT_RESULT_EDGE]];
 982    struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
 983
 984    ureg_MOV( ureg, edge_dst, edge_src );
 985 }
 986
 987
 988 /**
 989  * Translate Mesa program to TGSI format.
 990  * \param program  the program to translate
 991  * \param numInputs  number of input registers used
 992  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
 993  *                      input indexes
 994  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
 995  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
 996  *                            each input
 997  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
 998  * \param numOutputs  number of output registers used
 999  * \param outputMapping  maps Mesa fragment program outputs to TGSI
1000  *                       generic outputs
1001  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
1002  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
1003  *                             each output
1004  *
1005  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
1006  */
1007 enum pipe_error
1008 st_translate_mesa_program(
1009    struct gl_context *ctx,
1010    uint procType,
1011    struct ureg_program *ureg,
1012    const struct gl_program *program,
1013    GLuint numInputs,
1014    const GLuint inputMapping[],
1015    const ubyte inputSemanticName[],
1016    const ubyte inputSemanticIndex[],
1017    const GLuint interpMode[],
1018    GLuint numOutputs,
1019    const GLuint outputMapping[],
1020    const ubyte outputSemanticName[],
1021    const ubyte outputSemanticIndex[],
1022    boolean passthrough_edgeflags,
1023    boolean clamp_color)
1024 {
1025    struct st_translate translate, *t;
1026    unsigned i;
1027    enum pipe_error ret = PIPE_OK;
1028
1029    assert(numInputs <= Elements(t->inputs));
1030    assert(numOutputs <= Elements(t->outputs));
1031
1032    t = &translate;
1033    memset(t, 0, sizeof *t);
1034
1035    t->procType = procType;
1036    t->inputMapping = inputMapping;
1037    t->outputMapping = outputMapping;
1038    t->ureg = ureg;
1039
1040    /*_mesa_print_program(program);*/
1041
1042    /*
1043     * Declare input attributes.
1044     */
1045    if (procType == TGSI_PROCESSOR_FRAGMENT) {
1046       for (i = 0; i < numInputs; i++) {
1047          t->inputs[i] = ureg_DECL_fs_input(ureg,
1048                                            inputSemanticName[i],
1049                                            inputSemanticIndex[i],
1050                                            interpMode[i]);
1051       }
1052
1053       if (program->InputsRead & FRAG_BIT_WPOS) {
1054          /* Must do this after setting up t->inputs, and before
1055           * emitting constant references, below:
1056           */
1057          emit_wpos(st_context(ctx), t, program, ureg);
1058       }
1059
1060       if (program->InputsRead & FRAG_BIT_FACE) {
1061          emit_face_var( t, program );
1062       }
1063
1064       /*
1065        * Declare output attributes.
1066        */
1067       for (i = 0; i < numOutputs; i++) {
1068          switch (outputSemanticName[i]) {
1069          case TGSI_SEMANTIC_POSITION:
1070             t->outputs[i] = ureg_DECL_output( ureg,
1071                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
1072                                               outputSemanticIndex[i] );
1073
1074             t->outputs[i] = ureg_writemask( t->outputs[i],
1075                                             TGSI_WRITEMASK_Z );
1076             break;
1077          case TGSI_SEMANTIC_STENCIL:
1078             t->outputs[i] = ureg_DECL_output( ureg,
1079                                               TGSI_SEMANTIC_STENCIL, /* Stencil */
1080                                               outputSemanticIndex[i] );
1081             t->outputs[i] = ureg_writemask( t->outputs[i],
1082                                             TGSI_WRITEMASK_Y );
1083             break;
1084          case TGSI_SEMANTIC_COLOR:
1085             t->outputs[i] = ureg_DECL_output( ureg,
1086                                               TGSI_SEMANTIC_COLOR,
1087                                               outputSemanticIndex[i] );
1088             break;
1089          default:
1090             debug_assert(0);
1091             return 0;
1092          }
1093       }
1094    }
1095    else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1096       for (i = 0; i < numInputs; i++) {
1097          t->inputs[i] = ureg_DECL_gs_input(ureg,
1098                                            i,
1099                                            inputSemanticName[i],
1100                                            inputSemanticIndex[i]);
1101       }
1102
1103       for (i = 0; i < numOutputs; i++) {
1104          t->outputs[i] = ureg_DECL_output( ureg,
1105                                            outputSemanticName[i],
1106                                            outputSemanticIndex[i] );
1107       }
1108    }
1109    else {
1110       assert(procType == TGSI_PROCESSOR_VERTEX);
1111
1112       for (i = 0; i < numInputs; i++) {
1113          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1114       }
1115
1116       for (i = 0; i < numOutputs; i++) {
1117          t->outputs[i] = ureg_DECL_output( ureg,
1118                                            outputSemanticName[i],
1119                                            outputSemanticIndex[i] );
1120       }
1121       if (passthrough_edgeflags)
1122          emit_edgeflags( t, program );
1123    }
1124
1125    /* Declare address register.
1126     */
1127    if (program->NumAddressRegs > 0) {
1128       debug_assert( program->NumAddressRegs == 1 );
1129       t->address[0] = ureg_DECL_address( ureg );
1130    }
1131
1132    /* Declare misc input registers
1133     */
1134    {
1135       GLbitfield sysInputs = program->SystemValuesRead;
1136       unsigned numSys = 0;
1137       for (i = 0; sysInputs; i++) {
1138          if (sysInputs & (1 << i)) {
1139             unsigned semName = mesa_sysval_to_semantic[i];
1140             t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1141             if (semName == TGSI_SEMANTIC_INSTANCEID ||
1142                 semName == TGSI_SEMANTIC_VERTEXID) {
1143                /* From Gallium perspective, these system values are always
1144                 * integer, and require native integer support.  However, if
1145                 * native integer is supported on the vertex stage but not the
1146                 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1147                 * assumes these system values are floats. To resolve the
1148                 * inconsistency, we insert a U2F.
1149                 */
1150                struct st_context *st = st_context(ctx);
1151                struct pipe_screen *pscreen = st->pipe->screen;
1152                assert(procType == TGSI_PROCESSOR_VERTEX);
1153                assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
1154                (void) pscreen;  /* silence non-debug build warnings */
1155                if (!ctx->Const.NativeIntegers) {
1156                   struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
1157                   ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
1158                   t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
1159                }
1160             }
1161             numSys++;
1162             sysInputs &= ~(1 << i);
1163          }
1164       }
1165    }
1166
1167    if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1168       /* If temps are accessed with indirect addressing, declare temporaries
1169        * in sequential order.  Else, we declare them on demand elsewhere.
1170        */
1171       for (i = 0; i < program->NumTemporaries; i++) {
1172          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1173          t->temps[i] = ureg_DECL_temporary( t->ureg );
1174       }
1175    }
1176
1177    /* Emit constants and immediates.  Mesa uses a single index space
1178     * for these, so we put all the translated regs in t->constants.
1179     */
1180    if (program->Parameters) {
1181       t->constants = calloc( program->Parameters->NumParameters,
1182                              sizeof t->constants[0] );
1183       if (t->constants == NULL) {
1184          ret = PIPE_ERROR_OUT_OF_MEMORY;
1185          goto out;
1186       }
1187
1188       for (i = 0; i < program->Parameters->NumParameters; i++) {
1189          switch (program->Parameters->Parameters[i].Type) {
1190          case PROGRAM_ENV_PARAM:
1191          case PROGRAM_LOCAL_PARAM:
1192          case PROGRAM_STATE_VAR:
1193          case PROGRAM_UNIFORM:
1194             t->constants[i] = ureg_DECL_constant( ureg, i );
1195             break;
1196
1197             /* Emit immediates only when there's no indirect addressing of
1198              * the const buffer.
1199              * FIXME: Be smarter and recognize param arrays:
1200              * indirect addressing is only valid within the referenced
1201              * array.
1202              */
1203          case PROGRAM_CONSTANT:
1204             if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1205                t->constants[i] = ureg_DECL_constant( ureg, i );
1206             else
1207                t->constants[i] =
1208                   ureg_DECL_immediate( ureg,
1209                                        (const float*) program->Parameters->ParameterValues[i],
1210                                        4 );
1211             break;
1212          default:
1213             break;
1214          }
1215       }
1216    }
1217
1218    /* texture samplers */
1219    for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
1220       if (program->SamplersUsed & (1 << i)) {
1221          t->samplers[i] = ureg_DECL_sampler( ureg, i );
1222       }
1223    }
1224
1225    /* Emit each instruction in turn:
1226     */
1227    for (i = 0; i < program->NumInstructions; i++) {
1228       set_insn_start( t, ureg_get_instruction_number( ureg ));
1229       compile_instruction( t, &program->Instructions[i], clamp_color );
1230    }
1231
1232    /* Fix up all emitted labels:
1233     */
1234    for (i = 0; i < t->labels_count; i++) {
1235       ureg_fixup_label( ureg,
1236                         t->labels[i].token,
1237                         t->insn[t->labels[i].branch_target] );
1238    }
1239
1240 out:
1241    free(t->insn);
1242    free(t->labels);
1243    free(t->constants);
1244
1245    if (t->error) {
1246       debug_printf("%s: translate error flag set\n", __FUNCTION__);
1247    }
1248
1249    return ret;
1250 }
1251
1252
1253 /**
1254  * Tokens cannot be free with free otherwise the builtin gallium
1255  * malloc debugging will get confused.
1256  */
1257 void
1258 st_free_tokens(const struct tgsi_token *tokens)
1259 {
1260    ureg_free_tokens(tokens);
1261 }