1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
51 (1 << PROGRAM_CONSTANT) | \
52 (1 << PROGRAM_UNIFORM))
56 unsigned branch_target
;
62 * Intermediate state used during shader translation.
65 struct ureg_program
*ureg
;
67 struct ureg_dst temps
[MAX_PROGRAM_TEMPS
];
68 struct ureg_src
*constants
;
69 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
70 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
71 struct ureg_dst address
[1];
72 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
73 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
75 const GLuint
*inputMapping
;
76 const GLuint
*outputMapping
;
78 /* For every instruction that contains a label (eg CALL), keep
79 * details so that we can go back afterwards and emit the correct
80 * tgsi instruction number for each label.
84 unsigned labels_count
;
86 /* Keep a record of the tgsi instruction number that each mesa
87 * instruction starts at, will be used to fix up labels after
94 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
101 * Make note of a branch to a label in the TGSI code.
102 * After we've emitted all instructions, we'll go over the list
103 * of labels built here and patch the TGSI code with the actual
104 * location of each label.
106 static unsigned *get_label( struct st_translate
*t
,
107 unsigned branch_target
)
111 if (t
->labels_count
+ 1 >= t
->labels_size
) {
112 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
113 t
->labels
= realloc(t
->labels
, t
->labels_size
* sizeof t
->labels
[0]);
114 if (t
->labels
== NULL
) {
115 static unsigned dummy
;
121 i
= t
->labels_count
++;
122 t
->labels
[i
].branch_target
= branch_target
;
123 return &t
->labels
[i
].token
;
128 * Called prior to emitting the TGSI code for each Mesa instruction.
129 * Allocate additional space for instructions if needed.
130 * Update the insn[] array so the next Mesa instruction points to
131 * the next TGSI instruction.
133 static void set_insn_start( struct st_translate
*t
,
136 if (t
->insn_count
+ 1 >= t
->insn_size
) {
137 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
138 t
->insn
= realloc(t
->insn
, t
->insn_size
* sizeof t
->insn
[0]);
139 if (t
->insn
== NULL
) {
145 t
->insn
[t
->insn_count
++] = start
;
150 * Map a Mesa dst register to a TGSI ureg_dst register.
152 static struct ureg_dst
153 dst_register( struct st_translate
*t
,
154 gl_register_file file
,
158 case PROGRAM_UNDEFINED
:
159 return ureg_dst_undef();
161 case PROGRAM_TEMPORARY
:
162 if (ureg_dst_is_undef(t
->temps
[index
]))
163 t
->temps
[index
] = ureg_DECL_temporary( t
->ureg
);
165 return t
->temps
[index
];
168 if (t
->procType
== TGSI_PROCESSOR_VERTEX
)
169 assert(index
< VARYING_SLOT_MAX
);
170 else if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
171 assert(index
< FRAG_RESULT_MAX
);
173 assert(index
< VARYING_SLOT_MAX
);
175 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
177 return t
->outputs
[t
->outputMapping
[index
]];
179 case PROGRAM_ADDRESS
:
180 return t
->address
[index
];
184 return ureg_dst_undef();
190 * Map a Mesa src register to a TGSI ureg_src register.
192 static struct ureg_src
193 src_register( struct st_translate
*t
,
194 gl_register_file file
,
198 case PROGRAM_UNDEFINED
:
199 return ureg_src_undef();
201 case PROGRAM_TEMPORARY
:
203 assert(index
< ARRAY_SIZE(t
->temps
));
204 if (ureg_dst_is_undef(t
->temps
[index
]))
205 t
->temps
[index
] = ureg_DECL_temporary( t
->ureg
);
206 return ureg_src(t
->temps
[index
]);
208 case PROGRAM_UNIFORM
:
210 return t
->constants
[index
];
211 case PROGRAM_STATE_VAR
:
212 case PROGRAM_CONSTANT
: /* ie, immediate */
214 return ureg_DECL_constant( t
->ureg
, 0 );
216 return t
->constants
[index
];
219 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
220 return t
->inputs
[t
->inputMapping
[index
]];
223 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
224 return ureg_src(t
->outputs
[t
->outputMapping
[index
]]); /* not needed? */
226 case PROGRAM_ADDRESS
:
227 return ureg_src(t
->address
[index
]);
229 case PROGRAM_SYSTEM_VALUE
:
230 assert(index
< ARRAY_SIZE(t
->systemValues
));
231 return t
->systemValues
[index
];
235 return ureg_src_undef();
241 * Map mesa texture target to TGSI texture target.
244 st_translate_texture_target( GLuint textarget
,
248 switch( textarget
) {
249 case TEXTURE_1D_INDEX
: return TGSI_TEXTURE_SHADOW1D
;
250 case TEXTURE_2D_INDEX
: return TGSI_TEXTURE_SHADOW2D
;
251 case TEXTURE_RECT_INDEX
: return TGSI_TEXTURE_SHADOWRECT
;
252 case TEXTURE_1D_ARRAY_INDEX
: return TGSI_TEXTURE_SHADOW1D_ARRAY
;
253 case TEXTURE_2D_ARRAY_INDEX
: return TGSI_TEXTURE_SHADOW2D_ARRAY
;
254 case TEXTURE_CUBE_INDEX
: return TGSI_TEXTURE_SHADOWCUBE
;
255 case TEXTURE_CUBE_ARRAY_INDEX
: return TGSI_TEXTURE_SHADOWCUBE_ARRAY
;
260 switch( textarget
) {
261 case TEXTURE_2D_MULTISAMPLE_INDEX
: return TGSI_TEXTURE_2D_MSAA
;
262 case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: return TGSI_TEXTURE_2D_ARRAY_MSAA
;
263 case TEXTURE_BUFFER_INDEX
: return TGSI_TEXTURE_BUFFER
;
264 case TEXTURE_1D_INDEX
: return TGSI_TEXTURE_1D
;
265 case TEXTURE_2D_INDEX
: return TGSI_TEXTURE_2D
;
266 case TEXTURE_3D_INDEX
: return TGSI_TEXTURE_3D
;
267 case TEXTURE_CUBE_INDEX
: return TGSI_TEXTURE_CUBE
;
268 case TEXTURE_CUBE_ARRAY_INDEX
: return TGSI_TEXTURE_CUBE_ARRAY
;
269 case TEXTURE_RECT_INDEX
: return TGSI_TEXTURE_RECT
;
270 case TEXTURE_1D_ARRAY_INDEX
: return TGSI_TEXTURE_1D_ARRAY
;
271 case TEXTURE_2D_ARRAY_INDEX
: return TGSI_TEXTURE_2D_ARRAY
;
272 case TEXTURE_EXTERNAL_INDEX
: return TGSI_TEXTURE_2D
;
275 return TGSI_TEXTURE_1D
;
281 * Create a TGSI ureg_dst register from a Mesa dest register.
283 static struct ureg_dst
284 translate_dst( struct st_translate
*t
,
285 const struct prog_dst_register
*DstReg
,
288 struct ureg_dst dst
= dst_register( t
,
292 dst
= ureg_writemask( dst
,
296 dst
= ureg_saturate( dst
);
299 dst
= ureg_dst_indirect( dst
, ureg_src(t
->address
[0]) );
306 * Create a TGSI ureg_src register from a Mesa src register.
308 static struct ureg_src
309 translate_src( struct st_translate
*t
,
310 const struct prog_src_register
*SrcReg
)
312 struct ureg_src src
= src_register( t
, SrcReg
->File
, SrcReg
->Index
);
314 src
= ureg_swizzle( src
,
315 GET_SWZ( SrcReg
->Swizzle
, 0 ) & 0x3,
316 GET_SWZ( SrcReg
->Swizzle
, 1 ) & 0x3,
317 GET_SWZ( SrcReg
->Swizzle
, 2 ) & 0x3,
318 GET_SWZ( SrcReg
->Swizzle
, 3 ) & 0x3);
320 if (SrcReg
->Negate
== NEGATE_XYZW
)
321 src
= ureg_negate(src
);
323 if (SrcReg
->RelAddr
) {
324 src
= ureg_src_indirect( src
, ureg_src(t
->address
[0]));
325 if (SrcReg
->File
!= PROGRAM_INPUT
&&
326 SrcReg
->File
!= PROGRAM_OUTPUT
) {
327 /* If SrcReg->Index was negative, it was set to zero in
328 * src_register(). Reassign it now. But don't do this
329 * for input/output regs since they get remapped while
330 * const buffers don't.
332 src
.Index
= SrcReg
->Index
;
340 static struct ureg_src
swizzle_4v( struct ureg_src src
,
341 const unsigned *swz
)
343 return ureg_swizzle( src
, swz
[0], swz
[1], swz
[2], swz
[3] );
348 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
354 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
356 static void emit_swz( struct st_translate
*t
,
358 const struct prog_src_register
*SrcReg
)
360 struct ureg_program
*ureg
= t
->ureg
;
361 struct ureg_src src
= src_register( t
, SrcReg
->File
, SrcReg
->Index
);
363 unsigned negate_mask
= SrcReg
->Negate
;
365 unsigned one_mask
= ((GET_SWZ(SrcReg
->Swizzle
, 0) == SWIZZLE_ONE
) << 0 |
366 (GET_SWZ(SrcReg
->Swizzle
, 1) == SWIZZLE_ONE
) << 1 |
367 (GET_SWZ(SrcReg
->Swizzle
, 2) == SWIZZLE_ONE
) << 2 |
368 (GET_SWZ(SrcReg
->Swizzle
, 3) == SWIZZLE_ONE
) << 3);
370 unsigned zero_mask
= ((GET_SWZ(SrcReg
->Swizzle
, 0) == SWIZZLE_ZERO
) << 0 |
371 (GET_SWZ(SrcReg
->Swizzle
, 1) == SWIZZLE_ZERO
) << 1 |
372 (GET_SWZ(SrcReg
->Swizzle
, 2) == SWIZZLE_ZERO
) << 2 |
373 (GET_SWZ(SrcReg
->Swizzle
, 3) == SWIZZLE_ZERO
) << 3);
375 unsigned negative_one_mask
= one_mask
& negate_mask
;
376 unsigned positive_one_mask
= one_mask
& ~negate_mask
;
380 unsigned mul_swizzle
[4] = {0,0,0,0};
381 unsigned add_swizzle
[4] = {0,0,0,0};
382 unsigned src_swizzle
[4] = {0,0,0,0};
383 boolean need_add
= FALSE
;
384 boolean need_mul
= FALSE
;
386 if (dst
.WriteMask
== 0)
389 /* Is this just a MOV?
391 if (zero_mask
== 0 &&
393 (negate_mask
== 0 || negate_mask
== TGSI_WRITEMASK_XYZW
))
395 ureg_MOV( ureg
, dst
, translate_src( t
, SrcReg
));
401 #define IMM_NEG_ONE 2
403 imm
= ureg_imm3f( ureg
, 0, 1, -1 );
405 for (i
= 0; i
< 4; i
++) {
406 unsigned bit
= 1 << i
;
408 if (dst
.WriteMask
& bit
) {
409 if (positive_one_mask
& bit
) {
410 mul_swizzle
[i
] = IMM_ZERO
;
411 add_swizzle
[i
] = IMM_ONE
;
414 else if (negative_one_mask
& bit
) {
415 mul_swizzle
[i
] = IMM_ZERO
;
416 add_swizzle
[i
] = IMM_NEG_ONE
;
419 else if (zero_mask
& bit
) {
420 mul_swizzle
[i
] = IMM_ZERO
;
421 add_swizzle
[i
] = IMM_ZERO
;
425 add_swizzle
[i
] = IMM_ZERO
;
426 src_swizzle
[i
] = GET_SWZ(SrcReg
->Swizzle
, i
);
428 if (negate_mask
& bit
) {
429 mul_swizzle
[i
] = IMM_NEG_ONE
;
432 mul_swizzle
[i
] = IMM_ONE
;
438 if (need_mul
&& need_add
) {
441 swizzle_4v( src
, src_swizzle
),
442 swizzle_4v( imm
, mul_swizzle
),
443 swizzle_4v( imm
, add_swizzle
) );
448 swizzle_4v( src
, src_swizzle
),
449 swizzle_4v( imm
, mul_swizzle
) );
454 swizzle_4v( imm
, add_swizzle
) );
467 translate_opcode( unsigned op
)
471 return TGSI_OPCODE_ARL
;
473 return TGSI_OPCODE_ABS
;
475 return TGSI_OPCODE_ADD
;
477 return TGSI_OPCODE_BGNLOOP
;
479 return TGSI_OPCODE_BGNSUB
;
481 return TGSI_OPCODE_BRK
;
483 return TGSI_OPCODE_CAL
;
485 return TGSI_OPCODE_CMP
;
487 return TGSI_OPCODE_CONT
;
489 return TGSI_OPCODE_COS
;
491 return TGSI_OPCODE_DDX
;
493 return TGSI_OPCODE_DDY
;
495 return TGSI_OPCODE_DP2
;
497 return TGSI_OPCODE_DP3
;
499 return TGSI_OPCODE_DP4
;
501 return TGSI_OPCODE_DPH
;
503 return TGSI_OPCODE_DST
;
505 return TGSI_OPCODE_ELSE
;
507 return TGSI_OPCODE_ENDIF
;
509 return TGSI_OPCODE_ENDLOOP
;
511 return TGSI_OPCODE_ENDSUB
;
513 return TGSI_OPCODE_EX2
;
515 return TGSI_OPCODE_EXP
;
517 return TGSI_OPCODE_FLR
;
519 return TGSI_OPCODE_FRC
;
521 return TGSI_OPCODE_IF
;
523 return TGSI_OPCODE_TRUNC
;
525 return TGSI_OPCODE_KILL_IF
;
527 return TGSI_OPCODE_LG2
;
529 return TGSI_OPCODE_LOG
;
531 return TGSI_OPCODE_LIT
;
533 return TGSI_OPCODE_LRP
;
535 return TGSI_OPCODE_MAD
;
537 return TGSI_OPCODE_MAX
;
539 return TGSI_OPCODE_MIN
;
541 return TGSI_OPCODE_MOV
;
543 return TGSI_OPCODE_MUL
;
545 return TGSI_OPCODE_NOP
;
547 return TGSI_OPCODE_POW
;
549 return TGSI_OPCODE_RCP
;
551 return TGSI_OPCODE_RET
;
553 return TGSI_OPCODE_SCS
;
555 return TGSI_OPCODE_SEQ
;
557 return TGSI_OPCODE_SGE
;
559 return TGSI_OPCODE_SGT
;
561 return TGSI_OPCODE_SIN
;
563 return TGSI_OPCODE_SLE
;
565 return TGSI_OPCODE_SLT
;
567 return TGSI_OPCODE_SNE
;
569 return TGSI_OPCODE_SSG
;
571 return TGSI_OPCODE_SUB
;
573 return TGSI_OPCODE_TEX
;
575 return TGSI_OPCODE_TXB
;
577 return TGSI_OPCODE_TXD
;
579 return TGSI_OPCODE_TXL
;
581 return TGSI_OPCODE_TXP
;
583 return TGSI_OPCODE_XPD
;
585 return TGSI_OPCODE_END
;
588 return TGSI_OPCODE_NOP
;
595 struct gl_context
*ctx
,
596 struct st_translate
*t
,
597 const struct prog_instruction
*inst
)
599 struct ureg_program
*ureg
= t
->ureg
;
601 struct ureg_dst dst
[1] = { { 0 } };
602 struct ureg_src src
[4];
606 num_dst
= _mesa_num_inst_dst_regs( inst
->Opcode
);
607 num_src
= _mesa_num_inst_src_regs( inst
->Opcode
);
610 dst
[0] = translate_dst( t
,
614 for (i
= 0; i
< num_src
; i
++)
615 src
[i
] = translate_src( t
, &inst
->SrcReg
[i
] );
617 switch( inst
->Opcode
) {
619 emit_swz( t
, dst
[0], &inst
->SrcReg
[0] );
626 debug_assert(num_dst
== 0);
627 ureg_label_insn( ureg
,
628 translate_opcode( inst
->Opcode
),
630 get_label( t
, inst
->BranchTarget
));
634 debug_assert(num_dst
== 0);
635 ureg_label_insn( ureg
,
636 ctx
->Const
.NativeIntegers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
,
638 get_label( t
, inst
->BranchTarget
));
646 src
[num_src
++] = t
->samplers
[inst
->TexSrcUnit
];
648 translate_opcode( inst
->Opcode
),
650 st_translate_texture_target( inst
->TexSrcTarget
,
657 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
659 translate_opcode( inst
->Opcode
),
665 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XYZ
);
667 translate_opcode( inst
->Opcode
),
676 /* At some point, a motivated person could add a better
677 * implementation of noise. Currently not even the nvidia
678 * binary drivers do anything more than this. In any case, the
679 * place to do this is in the GL state tracker, not the poor
682 ureg_MOV( ureg
, dst
[0], ureg_imm1f(ureg
, 0.5) );
686 ureg_RSQ( ureg
, dst
[0], ureg_abs(src
[0]) );
691 translate_opcode( inst
->Opcode
),
700 * Emit the TGSI instructions for inverting and adjusting WPOS.
701 * This code is unavoidable because it also depends on whether
702 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
705 emit_wpos_adjustment(struct gl_context
*ctx
,
706 struct st_translate
*t
,
707 const struct gl_program
*program
,
709 GLfloat adjX
, GLfloat adjY
[2])
711 struct ureg_program
*ureg
= t
->ureg
;
713 /* Fragment program uses fragment position input.
714 * Need to replace instances of INPUT[WPOS] with temp T
715 * where T = INPUT[WPOS] by y is inverted.
717 static const gl_state_index wposTransformState
[STATE_LENGTH
]
718 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0 };
720 /* XXX: note we are modifying the incoming shader here! Need to
721 * do this before emitting the constant decls below, or this
724 unsigned wposTransConst
= _mesa_add_state_reference(program
->Parameters
,
727 struct ureg_src wpostrans
= ureg_DECL_constant( ureg
, wposTransConst
);
728 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
729 struct ureg_src
*wpos
=
730 ctx
->Const
.GLSLFragCoordIsSysVal
?
731 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
732 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
733 struct ureg_src wpos_input
= *wpos
;
735 /* First, apply the coordinate shift: */
736 if (adjX
|| adjY
[0] || adjY
[1]) {
737 if (adjY
[0] != adjY
[1]) {
738 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
739 * depending on whether inversion is actually going to be applied
740 * or not, which is determined by testing against the inversion
741 * state variable used below, which will be either +1 or -1.
743 struct ureg_dst adj_temp
= ureg_DECL_temporary(ureg
);
745 ureg_CMP(ureg
, adj_temp
,
746 ureg_scalar(wpostrans
, invert
? 2 : 0),
747 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
748 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
749 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
751 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
752 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
754 wpos_input
= ureg_src(wpos_temp
);
756 /* MOV wpos_temp, input[wpos]
758 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
761 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
762 * inversion/identity, or the other way around if we're drawing to an FBO.
765 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
768 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
770 ureg_scalar(wpostrans
, 0),
771 ureg_scalar(wpostrans
, 1));
773 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
776 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
778 ureg_scalar(wpostrans
, 2),
779 ureg_scalar(wpostrans
, 3));
782 /* Use wpos_temp as position input from here on:
784 *wpos
= ureg_src(wpos_temp
);
789 * Emit fragment position/coordinate code.
792 emit_wpos(struct st_context
*st
,
793 struct st_translate
*t
,
794 const struct gl_program
*program
,
795 struct ureg_program
*ureg
)
797 const struct gl_fragment_program
*fp
=
798 (const struct gl_fragment_program
*) program
;
799 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
801 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
802 boolean invert
= FALSE
;
804 /* Query the pixel center conventions supported by the pipe driver and set
805 * adjX, adjY to help out if it cannot handle the requested one internally.
807 * The bias of the y-coordinate depends on whether y-inversion takes place
808 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
809 * drawing to an FBO (causes additional inversion), and whether the the pipe
810 * driver origin and the requested origin differ (the latter condition is
811 * stored in the 'invert' variable).
813 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
820 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
821 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
822 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
823 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
825 * inversion and center shift:
826 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
827 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
828 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
829 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
831 if (fp
->OriginUpperLeft
) {
832 /* Fragment shader wants origin in upper-left */
833 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
834 /* the driver supports upper-left origin */
836 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
837 /* the driver supports lower-left origin, need to invert Y */
838 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
839 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
846 /* Fragment shader wants origin in lower-left */
847 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
848 /* the driver supports lower-left origin */
849 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
850 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
851 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
852 /* the driver supports upper-left origin, need to invert Y */
858 if (fp
->PixelCenterInteger
) {
859 /* Fragment shader wants pixel center integer */
860 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
861 /* the driver supports pixel center integer */
863 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
864 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
866 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
867 /* the driver supports pixel center half integer, need to bias X,Y */
876 /* Fragment shader wants pixel center half integer */
877 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
878 /* the driver supports pixel center half integer */
880 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
881 /* the driver supports pixel center integer, need to bias X,Y */
882 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
883 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
884 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
890 /* we invert after adjustment so that we avoid the MOV to temporary,
891 * and reuse the adjustment ADD instead */
892 emit_wpos_adjustment(st
->ctx
, t
, program
, invert
, adjX
, adjY
);
897 * Translate Mesa program to TGSI format.
898 * \param program the program to translate
899 * \param numInputs number of input registers used
900 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
902 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
903 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
905 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
906 * \param numOutputs number of output registers used
907 * \param outputMapping maps Mesa fragment program outputs to TGSI
909 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
910 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
913 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
916 st_translate_mesa_program(
917 struct gl_context
*ctx
,
919 struct ureg_program
*ureg
,
920 const struct gl_program
*program
,
922 const GLuint inputMapping
[],
923 const ubyte inputSemanticName
[],
924 const ubyte inputSemanticIndex
[],
925 const GLuint interpMode
[],
927 const GLuint outputMapping
[],
928 const ubyte outputSemanticName
[],
929 const ubyte outputSemanticIndex
[])
931 struct st_translate translate
, *t
;
933 enum pipe_error ret
= PIPE_OK
;
935 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
936 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
939 memset(t
, 0, sizeof *t
);
941 t
->procType
= procType
;
942 t
->inputMapping
= inputMapping
;
943 t
->outputMapping
= outputMapping
;
946 /*_mesa_print_program(program);*/
949 * Declare input attributes.
951 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
952 for (i
= 0; i
< numInputs
; i
++) {
953 t
->inputs
[i
] = ureg_DECL_fs_input(ureg
,
954 inputSemanticName
[i
],
955 inputSemanticIndex
[i
],
959 if (program
->InputsRead
& VARYING_BIT_POS
) {
960 /* Must do this after setting up t->inputs, and before
961 * emitting constant references, below:
963 emit_wpos(st_context(ctx
), t
, program
, ureg
);
967 * Declare output attributes.
969 for (i
= 0; i
< numOutputs
; i
++) {
970 switch (outputSemanticName
[i
]) {
971 case TGSI_SEMANTIC_POSITION
:
972 t
->outputs
[i
] = ureg_DECL_output( ureg
,
973 TGSI_SEMANTIC_POSITION
, /* Z / Depth */
974 outputSemanticIndex
[i
] );
976 t
->outputs
[i
] = ureg_writemask( t
->outputs
[i
],
979 case TGSI_SEMANTIC_STENCIL
:
980 t
->outputs
[i
] = ureg_DECL_output( ureg
,
981 TGSI_SEMANTIC_STENCIL
, /* Stencil */
982 outputSemanticIndex
[i
] );
983 t
->outputs
[i
] = ureg_writemask( t
->outputs
[i
],
986 case TGSI_SEMANTIC_COLOR
:
987 t
->outputs
[i
] = ureg_DECL_output( ureg
,
989 outputSemanticIndex
[i
] );
997 else if (procType
== TGSI_PROCESSOR_GEOMETRY
) {
998 for (i
= 0; i
< numInputs
; i
++) {
999 t
->inputs
[i
] = ureg_DECL_input(ureg
,
1000 inputSemanticName
[i
],
1001 inputSemanticIndex
[i
], 0, 1);
1004 for (i
= 0; i
< numOutputs
; i
++) {
1005 t
->outputs
[i
] = ureg_DECL_output( ureg
,
1006 outputSemanticName
[i
],
1007 outputSemanticIndex
[i
] );
1011 assert(procType
== TGSI_PROCESSOR_VERTEX
);
1013 for (i
= 0; i
< numInputs
; i
++) {
1014 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
1017 for (i
= 0; i
< numOutputs
; i
++) {
1018 t
->outputs
[i
] = ureg_DECL_output( ureg
,
1019 outputSemanticName
[i
],
1020 outputSemanticIndex
[i
] );
1021 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
1022 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
1024 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
1025 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
1026 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
1031 /* Declare address register.
1033 if (program
->NumAddressRegs
> 0) {
1034 debug_assert( program
->NumAddressRegs
== 1 );
1035 t
->address
[0] = ureg_DECL_address( ureg
);
1038 /* Declare misc input registers
1041 GLbitfield sysInputs
= program
->SystemValuesRead
;
1043 for (i
= 0; sysInputs
; i
++) {
1044 if (sysInputs
& (1 << i
)) {
1045 unsigned semName
= _mesa_sysval_to_semantic
[i
];
1047 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
1049 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
1050 semName
== TGSI_SEMANTIC_VERTEXID
) {
1051 /* From Gallium perspective, these system values are always
1052 * integer, and require native integer support. However, if
1053 * native integer is supported on the vertex stage but not the
1054 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1055 * assumes these system values are floats. To resolve the
1056 * inconsistency, we insert a U2F.
1058 struct st_context
*st
= st_context(ctx
);
1059 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
1060 assert(procType
== TGSI_PROCESSOR_VERTEX
);
1061 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
1062 (void) pscreen
; /* silence non-debug build warnings */
1063 if (!ctx
->Const
.NativeIntegers
) {
1064 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
1065 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
1066 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
1070 if (procType
== TGSI_PROCESSOR_FRAGMENT
&&
1071 semName
== TGSI_SEMANTIC_POSITION
)
1072 emit_wpos(st_context(ctx
), t
, program
, ureg
);
1074 sysInputs
&= ~(1 << i
);
1079 if (program
->IndirectRegisterFiles
& (1 << PROGRAM_TEMPORARY
)) {
1080 /* If temps are accessed with indirect addressing, declare temporaries
1081 * in sequential order. Else, we declare them on demand elsewhere.
1083 for (i
= 0; i
< program
->NumTemporaries
; i
++) {
1084 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1085 t
->temps
[i
] = ureg_DECL_temporary( t
->ureg
);
1089 /* Emit constants and immediates. Mesa uses a single index space
1090 * for these, so we put all the translated regs in t->constants.
1092 if (program
->Parameters
) {
1093 t
->constants
= calloc( program
->Parameters
->NumParameters
,
1094 sizeof t
->constants
[0] );
1095 if (t
->constants
== NULL
) {
1096 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
1100 for (i
= 0; i
< program
->Parameters
->NumParameters
; i
++) {
1101 switch (program
->Parameters
->Parameters
[i
].Type
) {
1102 case PROGRAM_STATE_VAR
:
1103 case PROGRAM_UNIFORM
:
1104 t
->constants
[i
] = ureg_DECL_constant( ureg
, i
);
1107 /* Emit immediates only when there's no indirect addressing of
1109 * FIXME: Be smarter and recognize param arrays:
1110 * indirect addressing is only valid within the referenced
1113 case PROGRAM_CONSTANT
:
1114 if (program
->IndirectRegisterFiles
& PROGRAM_ANY_CONST
)
1115 t
->constants
[i
] = ureg_DECL_constant( ureg
, i
);
1118 ureg_DECL_immediate( ureg
,
1119 (const float*) program
->Parameters
->ParameterValues
[i
],
1128 /* texture samplers */
1129 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
1130 if (program
->SamplersUsed
& (1 << i
)) {
1131 t
->samplers
[i
] = ureg_DECL_sampler( ureg
, i
);
1135 /* Emit each instruction in turn:
1137 for (i
= 0; i
< program
->NumInstructions
; i
++) {
1138 set_insn_start( t
, ureg_get_instruction_number( ureg
));
1139 compile_instruction(ctx
, t
, &program
->Instructions
[i
]);
1142 /* Fix up all emitted labels:
1144 for (i
= 0; i
< t
->labels_count
; i
++) {
1145 ureg_fixup_label( ureg
,
1147 t
->insn
[t
->labels
[i
].branch_target
] );
1156 debug_printf("%s: translate error flag set\n", __func__
);