src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_screen.h"
  37 #include "pipe/p_shader_tokens.h"
  38 #include "pipe/p_state.h"
  39 #include "tgsi/tgsi_ureg.h"
  40 #include "st_mesa_to_tgsi.h"
  41 #include "st_context.h"
  42 #include "program/prog_instruction.h"
  43 #include "program/prog_parameter.h"
  44 #include "util/u_debug.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
  48
  49
  50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |    \
  51                            (1 << PROGRAM_CONSTANT) |     \
  52                            (1 << PROGRAM_UNIFORM))
  53
  54 /**
  55  * Intermediate state used during shader translation.
  56  */
  57 struct st_translate {
  58    struct ureg_program *ureg;
  59
  60    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  61    struct ureg_src *constants;
  62    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  63    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  64    struct ureg_dst address[1];
  65    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  66    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  67
  68    const ubyte *inputMapping;
  69    const ubyte *outputMapping;
  70
  71    unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
  72 };
  73
  74
  75 /**
  76  * Map a Mesa dst register to a TGSI ureg_dst register.
  77  */
  78 static struct ureg_dst
  79 dst_register( struct st_translate *t,
  80               gl_register_file file,
  81               GLuint index )
  82 {
  83    switch( file ) {
  84    case PROGRAM_UNDEFINED:
  85       return ureg_dst_undef();
  86
  87    case PROGRAM_TEMPORARY:
  88       if (ureg_dst_is_undef(t->temps[index]))
  89          t->temps[index] = ureg_DECL_temporary( t->ureg );
  90
  91       return t->temps[index];
  92
  93    case PROGRAM_OUTPUT:
  94       if (t->procType == PIPE_SHADER_VERTEX)
  95          assert(index < VARYING_SLOT_MAX);
  96       else if (t->procType == PIPE_SHADER_FRAGMENT)
  97          assert(index < FRAG_RESULT_MAX);
  98       else
  99          assert(index < VARYING_SLOT_MAX);
 100
 101       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 102
 103       return t->outputs[t->outputMapping[index]];
 104
 105    case PROGRAM_ADDRESS:
 106       return t->address[index];
 107
 108    default:
 109       debug_assert( 0 );
 110       return ureg_dst_undef();
 111    }
 112 }
 113
 114
 115 /**
 116  * Map a Mesa src register to a TGSI ureg_src register.
 117  */
 118 static struct ureg_src
 119 src_register( struct st_translate *t,
 120               gl_register_file file,
 121               GLint index )
 122 {
 123    switch( file ) {
 124    case PROGRAM_UNDEFINED:
 125       return ureg_src_undef();
 126
 127    case PROGRAM_TEMPORARY:
 128       assert(index >= 0);
 129       assert(index < ARRAY_SIZE(t->temps));
 130       if (ureg_dst_is_undef(t->temps[index]))
 131          t->temps[index] = ureg_DECL_temporary( t->ureg );
 132       return ureg_src(t->temps[index]);
 133
 134    case PROGRAM_UNIFORM:
 135       assert(index >= 0);
 136       return t->constants[index];
 137    case PROGRAM_STATE_VAR:
 138    case PROGRAM_CONSTANT:       /* ie, immediate */
 139       if (index < 0)
 140          return ureg_DECL_constant( t->ureg, 0 );
 141       else
 142          return t->constants[index];
 143
 144    case PROGRAM_INPUT:
 145       assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
 146       return t->inputs[t->inputMapping[index]];
 147
 148    case PROGRAM_OUTPUT:
 149       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 150       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 151
 152    case PROGRAM_ADDRESS:
 153       return ureg_src(t->address[index]);
 154
 155    case PROGRAM_SYSTEM_VALUE:
 156       assert(index < ARRAY_SIZE(t->systemValues));
 157       return t->systemValues[index];
 158
 159    default:
 160       debug_assert( 0 );
 161       return ureg_src_undef();
 162    }
 163 }
 164
 165
 166 /**
 167  * Map mesa texture target to TGSI texture target.
 168  */
 169 unsigned
 170 st_translate_texture_target(GLuint textarget, GLboolean shadow)
 171 {
 172    if (shadow) {
 173       switch (textarget) {
 174       case TEXTURE_1D_INDEX:
 175          return TGSI_TEXTURE_SHADOW1D;
 176       case TEXTURE_2D_INDEX:
 177          return TGSI_TEXTURE_SHADOW2D;
 178       case TEXTURE_RECT_INDEX:
 179          return TGSI_TEXTURE_SHADOWRECT;
 180       case TEXTURE_1D_ARRAY_INDEX:
 181          return TGSI_TEXTURE_SHADOW1D_ARRAY;
 182       case TEXTURE_2D_ARRAY_INDEX:
 183          return TGSI_TEXTURE_SHADOW2D_ARRAY;
 184       case TEXTURE_CUBE_INDEX:
 185          return TGSI_TEXTURE_SHADOWCUBE;
 186       case TEXTURE_CUBE_ARRAY_INDEX:
 187          return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
 188       default:
 189          break;
 190       }
 191    }
 192
 193    switch (textarget) {
 194    case TEXTURE_2D_MULTISAMPLE_INDEX:
 195       return TGSI_TEXTURE_2D_MSAA;
 196    case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX:
 197       return TGSI_TEXTURE_2D_ARRAY_MSAA;
 198    case TEXTURE_BUFFER_INDEX:
 199       return TGSI_TEXTURE_BUFFER;
 200    case TEXTURE_1D_INDEX:
 201       return TGSI_TEXTURE_1D;
 202    case TEXTURE_2D_INDEX:
 203       return TGSI_TEXTURE_2D;
 204    case TEXTURE_3D_INDEX:
 205       return TGSI_TEXTURE_3D;
 206    case TEXTURE_CUBE_INDEX:
 207       return TGSI_TEXTURE_CUBE;
 208    case TEXTURE_CUBE_ARRAY_INDEX:
 209       return TGSI_TEXTURE_CUBE_ARRAY;
 210    case TEXTURE_RECT_INDEX:
 211       return TGSI_TEXTURE_RECT;
 212    case TEXTURE_1D_ARRAY_INDEX:
 213       return TGSI_TEXTURE_1D_ARRAY;
 214    case TEXTURE_2D_ARRAY_INDEX:
 215       return TGSI_TEXTURE_2D_ARRAY;
 216    case TEXTURE_EXTERNAL_INDEX:
 217       return TGSI_TEXTURE_2D;
 218    default:
 219       debug_assert(!"unexpected texture target index");
 220       return TGSI_TEXTURE_1D;
 221    }
 222 }
 223
 224
 225 /**
 226  * Map GLSL base type to TGSI return type.
 227  */
 228 unsigned
 229 st_translate_texture_type(enum glsl_base_type type)
 230 {
 231         switch (type) {
 232         case GLSL_TYPE_INT:
 233                 return TGSI_RETURN_TYPE_SINT;
 234         case GLSL_TYPE_UINT:
 235                 return TGSI_RETURN_TYPE_UINT;
 236         case GLSL_TYPE_FLOAT:
 237                 return TGSI_RETURN_TYPE_FLOAT;
 238         default:
 239                 assert(!"unexpected texture type");
 240                 return TGSI_RETURN_TYPE_UNKNOWN;
 241         }
 242 }
 243
 244
 245 /**
 246  * Translate a (1 << TEXTURE_x_INDEX) bit into a TGSI_TEXTURE_x enum.
 247  */
 248 static unsigned
 249 translate_texture_index(GLbitfield texBit, bool shadow)
 250 {
 251    int index = ffs(texBit);
 252    assert(index > 0);
 253    assert(index - 1 < NUM_TEXTURE_TARGETS);
 254    return st_translate_texture_target(index - 1, shadow);
 255 }
 256
 257
 258 /**
 259  * Create a TGSI ureg_dst register from a Mesa dest register.
 260  */
 261 static struct ureg_dst
 262 translate_dst( struct st_translate *t,
 263                const struct prog_dst_register *DstReg,
 264                boolean saturate)
 265 {
 266    struct ureg_dst dst = dst_register( t,
 267                                        DstReg->File,
 268                                        DstReg->Index );
 269
 270    dst = ureg_writemask( dst,
 271                          DstReg->WriteMask );
 272
 273    if (saturate)
 274       dst = ureg_saturate( dst );
 275
 276    if (DstReg->RelAddr)
 277       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 278
 279    return dst;
 280 }
 281
 282
 283 /**
 284  * Create a TGSI ureg_src register from a Mesa src register.
 285  */
 286 static struct ureg_src
 287 translate_src( struct st_translate *t,
 288                const struct prog_src_register *SrcReg )
 289 {
 290    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 291
 292    src = ureg_swizzle( src,
 293                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
 294                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
 295                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
 296                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 297
 298    if (SrcReg->Negate == NEGATE_XYZW)
 299       src = ureg_negate(src);
 300
 301    if (SrcReg->RelAddr) {
 302       src = ureg_src_indirect( src, ureg_src(t->address[0]));
 303       if (SrcReg->File != PROGRAM_INPUT &&
 304           SrcReg->File != PROGRAM_OUTPUT) {
 305          /* If SrcReg->Index was negative, it was set to zero in
 306           * src_register().  Reassign it now.  But don't do this
 307           * for input/output regs since they get remapped while
 308           * const buffers don't.
 309           */
 310          src.Index = SrcReg->Index;
 311       }
 312    }
 313
 314    return src;
 315 }
 316
 317
 318 static struct ureg_src swizzle_4v( struct ureg_src src,
 319                                    const unsigned *swz )
 320 {
 321    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
 322 }
 323
 324
 325 /**
 326  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 327  *
 328  *   SWZ dst, src.x-y10
 329  *
 330  * becomes:
 331  *
 332  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 333  */
 334 static void emit_swz( struct st_translate *t,
 335                       struct ureg_dst dst,
 336                       const struct prog_src_register *SrcReg )
 337 {
 338    struct ureg_program *ureg = t->ureg;
 339    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 340
 341    unsigned negate_mask =  SrcReg->Negate;
 342
 343    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 344                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 345                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 346                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 347
 348    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 349                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 350                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 351                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 352
 353    unsigned negative_one_mask = one_mask & negate_mask;
 354    unsigned positive_one_mask = one_mask & ~negate_mask;
 355
 356    struct ureg_src imm;
 357    unsigned i;
 358    unsigned mul_swizzle[4] = {0,0,0,0};
 359    unsigned add_swizzle[4] = {0,0,0,0};
 360    unsigned src_swizzle[4] = {0,0,0,0};
 361    boolean need_add = FALSE;
 362    boolean need_mul = FALSE;
 363
 364    if (dst.WriteMask == 0)
 365       return;
 366
 367    /* Is this just a MOV?
 368     */
 369    if (zero_mask == 0 &&
 370        one_mask == 0 &&
 371        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
 372    {
 373       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
 374       return;
 375    }
 376
 377 #define IMM_ZERO    0
 378 #define IMM_ONE     1
 379 #define IMM_NEG_ONE 2
 380
 381    imm = ureg_imm3f( ureg, 0, 1, -1 );
 382
 383    for (i = 0; i < 4; i++) {
 384       unsigned bit = 1 << i;
 385
 386       if (dst.WriteMask & bit) {
 387          if (positive_one_mask & bit) {
 388             mul_swizzle[i] = IMM_ZERO;
 389             add_swizzle[i] = IMM_ONE;
 390             need_add = TRUE;
 391          }
 392          else if (negative_one_mask & bit) {
 393             mul_swizzle[i] = IMM_ZERO;
 394             add_swizzle[i] = IMM_NEG_ONE;
 395             need_add = TRUE;
 396          }
 397          else if (zero_mask & bit) {
 398             mul_swizzle[i] = IMM_ZERO;
 399             add_swizzle[i] = IMM_ZERO;
 400             need_add = TRUE;
 401          }
 402          else {
 403             add_swizzle[i] = IMM_ZERO;
 404             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 405             need_mul = TRUE;
 406             if (negate_mask & bit) {
 407                mul_swizzle[i] = IMM_NEG_ONE;
 408             }
 409             else {
 410                mul_swizzle[i] = IMM_ONE;
 411             }
 412          }
 413       }
 414    }
 415
 416    if (need_mul && need_add) {
 417       ureg_MAD( ureg,
 418                 dst,
 419                 swizzle_4v( src, src_swizzle ),
 420                 swizzle_4v( imm, mul_swizzle ),
 421                 swizzle_4v( imm, add_swizzle ) );
 422    }
 423    else if (need_mul) {
 424       ureg_MUL( ureg,
 425                 dst,
 426                 swizzle_4v( src, src_swizzle ),
 427                 swizzle_4v( imm, mul_swizzle ) );
 428    }
 429    else if (need_add) {
 430       ureg_MOV( ureg,
 431                 dst,
 432                 swizzle_4v( imm, add_swizzle ) );
 433    }
 434    else {
 435       debug_assert(0);
 436    }
 437
 438 #undef IMM_ZERO
 439 #undef IMM_ONE
 440 #undef IMM_NEG_ONE
 441 }
 442
 443
 444 static unsigned
 445 translate_opcode( unsigned op )
 446 {
 447    switch( op ) {
 448    case OPCODE_ARL:
 449       return TGSI_OPCODE_ARL;
 450    case OPCODE_ADD:
 451       return TGSI_OPCODE_ADD;
 452    case OPCODE_CMP:
 453       return TGSI_OPCODE_CMP;
 454    case OPCODE_COS:
 455       return TGSI_OPCODE_COS;
 456    case OPCODE_DP3:
 457       return TGSI_OPCODE_DP3;
 458    case OPCODE_DP4:
 459       return TGSI_OPCODE_DP4;
 460    case OPCODE_DPH:
 461       return TGSI_OPCODE_DPH;
 462    case OPCODE_DST:
 463       return TGSI_OPCODE_DST;
 464    case OPCODE_EX2:
 465       return TGSI_OPCODE_EX2;
 466    case OPCODE_EXP:
 467       return TGSI_OPCODE_EXP;
 468    case OPCODE_FLR:
 469       return TGSI_OPCODE_FLR;
 470    case OPCODE_FRC:
 471       return TGSI_OPCODE_FRC;
 472    case OPCODE_KIL:
 473       return TGSI_OPCODE_KILL_IF;
 474    case OPCODE_LG2:
 475       return TGSI_OPCODE_LG2;
 476    case OPCODE_LOG:
 477       return TGSI_OPCODE_LOG;
 478    case OPCODE_LIT:
 479       return TGSI_OPCODE_LIT;
 480    case OPCODE_LRP:
 481       return TGSI_OPCODE_LRP;
 482    case OPCODE_MAD:
 483       return TGSI_OPCODE_MAD;
 484    case OPCODE_MAX:
 485       return TGSI_OPCODE_MAX;
 486    case OPCODE_MIN:
 487       return TGSI_OPCODE_MIN;
 488    case OPCODE_MOV:
 489       return TGSI_OPCODE_MOV;
 490    case OPCODE_MUL:
 491       return TGSI_OPCODE_MUL;
 492    case OPCODE_POW:
 493       return TGSI_OPCODE_POW;
 494    case OPCODE_RCP:
 495       return TGSI_OPCODE_RCP;
 496    case OPCODE_SCS:
 497       return TGSI_OPCODE_SCS;
 498    case OPCODE_SGE:
 499       return TGSI_OPCODE_SGE;
 500    case OPCODE_SIN:
 501       return TGSI_OPCODE_SIN;
 502    case OPCODE_SLT:
 503       return TGSI_OPCODE_SLT;
 504    case OPCODE_TEX:
 505       return TGSI_OPCODE_TEX;
 506    case OPCODE_TXB:
 507       return TGSI_OPCODE_TXB;
 508    case OPCODE_TXP:
 509       return TGSI_OPCODE_TXP;
 510    case OPCODE_XPD:
 511       return TGSI_OPCODE_XPD;
 512    case OPCODE_END:
 513       return TGSI_OPCODE_END;
 514    default:
 515       debug_assert( 0 );
 516       return TGSI_OPCODE_NOP;
 517    }
 518 }
 519
 520
 521 static void
 522 compile_instruction(
 523    struct gl_context *ctx,
 524    struct st_translate *t,
 525    const struct prog_instruction *inst)
 526 {
 527    struct ureg_program *ureg = t->ureg;
 528    GLuint i;
 529    struct ureg_dst dst[1] = { { 0 } };
 530    struct ureg_src src[4];
 531    unsigned num_dst;
 532    unsigned num_src;
 533
 534    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
 535    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 536
 537    if (num_dst)
 538       dst[0] = translate_dst( t,
 539                               &inst->DstReg,
 540                               inst->Saturate);
 541
 542    for (i = 0; i < num_src; i++)
 543       src[i] = translate_src( t, &inst->SrcReg[i] );
 544
 545    switch( inst->Opcode ) {
 546    case OPCODE_SWZ:
 547       emit_swz( t, dst[0], &inst->SrcReg[0] );
 548       return;
 549
 550    case OPCODE_TEX:
 551    case OPCODE_TXB:
 552    case OPCODE_TXP:
 553       src[num_src++] = t->samplers[inst->TexSrcUnit];
 554       ureg_tex_insn( ureg,
 555                      translate_opcode( inst->Opcode ),
 556                      dst, num_dst,
 557                      st_translate_texture_target( inst->TexSrcTarget,
 558                                                inst->TexShadow ),
 559                      TGSI_RETURN_TYPE_FLOAT,
 560                      NULL, 0,
 561                      src, num_src );
 562       return;
 563
 564    case OPCODE_SCS:
 565       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
 566       ureg_insn( ureg,
 567                  translate_opcode( inst->Opcode ),
 568                  dst, num_dst,
 569                  src, num_src );
 570       break;
 571
 572    case OPCODE_XPD:
 573       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
 574       ureg_insn( ureg,
 575                  translate_opcode( inst->Opcode ),
 576                  dst, num_dst,
 577                  src, num_src );
 578       break;
 579
 580    case OPCODE_RSQ:
 581       ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
 582       break;
 583
 584    case OPCODE_ABS:
 585       ureg_MOV(ureg, dst[0], ureg_abs(src[0]));
 586       break;
 587
 588    case OPCODE_SUB:
 589       ureg_ADD(ureg, dst[0], src[0], ureg_negate(src[1]));
 590       break;
 591
 592    default:
 593       ureg_insn( ureg,
 594                  translate_opcode( inst->Opcode ),
 595                  dst, num_dst,
 596                  src, num_src );
 597       break;
 598    }
 599 }
 600
 601
 602 /**
 603  * Emit the TGSI instructions for inverting and adjusting WPOS.
 604  * This code is unavoidable because it also depends on whether
 605  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
 606  */
 607 static void
 608 emit_wpos_adjustment(struct gl_context *ctx,
 609                      struct st_translate *t,
 610                      const struct gl_program *program,
 611                      boolean invert,
 612                      GLfloat adjX, GLfloat adjY[2])
 613 {
 614    struct ureg_program *ureg = t->ureg;
 615
 616    /* Fragment program uses fragment position input.
 617     * Need to replace instances of INPUT[WPOS] with temp T
 618     * where T = INPUT[WPOS] by y is inverted.
 619     */
 620    static const gl_state_index wposTransformState[STATE_LENGTH]
 621       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
 622
 623    /* XXX: note we are modifying the incoming shader here!  Need to
 624     * do this before emitting the constant decls below, or this
 625     * will be missed:
 626     */
 627    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
 628                                                        wposTransformState);
 629
 630    struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
 631    struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
 632    struct ureg_src *wpos =
 633       ctx->Const.GLSLFragCoordIsSysVal ?
 634          &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
 635          &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
 636    struct ureg_src wpos_input = *wpos;
 637
 638    /* First, apply the coordinate shift: */
 639    if (adjX || adjY[0] || adjY[1]) {
 640       if (adjY[0] != adjY[1]) {
 641          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
 642           * depending on whether inversion is actually going to be applied
 643           * or not, which is determined by testing against the inversion
 644           * state variable used below, which will be either +1 or -1.
 645           */
 646          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
 647
 648          ureg_CMP(ureg, adj_temp,
 649                   ureg_scalar(wpostrans, invert ? 2 : 0),
 650                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
 651                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
 652          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
 653       } else {
 654          ureg_ADD(ureg, wpos_temp, wpos_input,
 655                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
 656       }
 657       wpos_input = ureg_src(wpos_temp);
 658    } else {
 659       /* MOV wpos_temp, input[wpos]
 660        */
 661       ureg_MOV( ureg, wpos_temp, wpos_input );
 662    }
 663
 664    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
 665     * inversion/identity, or the other way around if we're drawing to an FBO.
 666     */
 667    if (invert) {
 668       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
 669        */
 670       ureg_MAD( ureg,
 671                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 672                 wpos_input,
 673                 ureg_scalar(wpostrans, 0),
 674                 ureg_scalar(wpostrans, 1));
 675    } else {
 676       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
 677        */
 678       ureg_MAD( ureg,
 679                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 680                 wpos_input,
 681                 ureg_scalar(wpostrans, 2),
 682                 ureg_scalar(wpostrans, 3));
 683    }
 684
 685    /* Use wpos_temp as position input from here on:
 686     */
 687    *wpos = ureg_src(wpos_temp);
 688 }
 689
 690
 691 /**
 692  * Emit fragment position/coordinate code.
 693  */
 694 static void
 695 emit_wpos(struct st_context *st,
 696           struct st_translate *t,
 697           const struct gl_program *program,
 698           struct ureg_program *ureg)
 699 {
 700    struct pipe_screen *pscreen = st->pipe->screen;
 701    GLfloat adjX = 0.0f;
 702    GLfloat adjY[2] = { 0.0f, 0.0f };
 703    boolean invert = FALSE;
 704
 705    /* Query the pixel center conventions supported by the pipe driver and set
 706     * adjX, adjY to help out if it cannot handle the requested one internally.
 707     *
 708     * The bias of the y-coordinate depends on whether y-inversion takes place
 709     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
 710     * drawing to an FBO (causes additional inversion), and whether the pipe
 711     * driver origin and the requested origin differ (the latter condition is
 712     * stored in the 'invert' variable).
 713     *
 714     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
 715     *
 716     * center shift only:
 717     * i -> h: +0.5
 718     * h -> i: -0.5
 719     *
 720     * inversion only:
 721     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
 722     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
 723     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
 724     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
 725     *
 726     * inversion and center shift:
 727     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
 728     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
 729     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
 730     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
 731     */
 732    if (program->OriginUpperLeft) {
 733       /* Fragment shader wants origin in upper-left */
 734       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 735          /* the driver supports upper-left origin */
 736       }
 737       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 738          /* the driver supports lower-left origin, need to invert Y */
 739          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 740                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 741          invert = TRUE;
 742       }
 743       else
 744          assert(0);
 745    }
 746    else {
 747       /* Fragment shader wants origin in lower-left */
 748       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 749          /* the driver supports lower-left origin */
 750          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 751                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 752       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 753          /* the driver supports upper-left origin, need to invert Y */
 754          invert = TRUE;
 755       else
 756          assert(0);
 757    }
 758
 759    if (program->PixelCenterInteger) {
 760       /* Fragment shader wants pixel center integer */
 761       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 762          /* the driver supports pixel center integer */
 763          adjY[1] = 1.0f;
 764          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 765                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 766       }
 767       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 768          /* the driver supports pixel center half integer, need to bias X,Y */
 769          adjX = -0.5f;
 770          adjY[0] = -0.5f;
 771          adjY[1] = 0.5f;
 772       }
 773       else
 774          assert(0);
 775    }
 776    else {
 777       /* Fragment shader wants pixel center half integer */
 778       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 779          /* the driver supports pixel center half integer */
 780       }
 781       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 782          /* the driver supports pixel center integer, need to bias X,Y */
 783          adjX = adjY[0] = adjY[1] = 0.5f;
 784          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 785                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 786       }
 787       else
 788          assert(0);
 789    }
 790
 791    /* we invert after adjustment so that we avoid the MOV to temporary,
 792     * and reuse the adjustment ADD instead */
 793    emit_wpos_adjustment(st->ctx, t, program, invert, adjX, adjY);
 794 }
 795
 796
 797 /**
 798  * Translate Mesa program to TGSI format.
 799  * \param program  the program to translate
 800  * \param numInputs  number of input registers used
 801  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
 802  *                      input indexes
 803  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
 804  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
 805  *                            each input
 806  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
 807  * \param numOutputs  number of output registers used
 808  * \param outputMapping  maps Mesa fragment program outputs to TGSI
 809  *                       generic outputs
 810  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
 811  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
 812  *                             each output
 813  *
 814  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
 815  */
 816 enum pipe_error
 817 st_translate_mesa_program(
 818    struct gl_context *ctx,
 819    uint procType,
 820    struct ureg_program *ureg,
 821    const struct gl_program *program,
 822    GLuint numInputs,
 823    const ubyte inputMapping[],
 824    const ubyte inputSemanticName[],
 825    const ubyte inputSemanticIndex[],
 826    const ubyte interpMode[],
 827    GLuint numOutputs,
 828    const ubyte outputMapping[],
 829    const ubyte outputSemanticName[],
 830    const ubyte outputSemanticIndex[])
 831 {
 832    struct st_translate translate, *t;
 833    unsigned i;
 834    enum pipe_error ret = PIPE_OK;
 835
 836    assert(numInputs <= ARRAY_SIZE(t->inputs));
 837    assert(numOutputs <= ARRAY_SIZE(t->outputs));
 838
 839    t = &translate;
 840    memset(t, 0, sizeof *t);
 841
 842    t->procType = procType;
 843    t->inputMapping = inputMapping;
 844    t->outputMapping = outputMapping;
 845    t->ureg = ureg;
 846
 847    /*_mesa_print_program(program);*/
 848
 849    /*
 850     * Declare input attributes.
 851     */
 852    if (procType == PIPE_SHADER_FRAGMENT) {
 853       for (i = 0; i < numInputs; i++) {
 854          t->inputs[i] = ureg_DECL_fs_input(ureg,
 855                                            inputSemanticName[i],
 856                                            inputSemanticIndex[i],
 857                                            interpMode[i]);
 858       }
 859
 860       if (program->info.inputs_read & VARYING_BIT_POS) {
 861          /* Must do this after setting up t->inputs, and before
 862           * emitting constant references, below:
 863           */
 864          emit_wpos(st_context(ctx), t, program, ureg);
 865       }
 866
 867       /*
 868        * Declare output attributes.
 869        */
 870       for (i = 0; i < numOutputs; i++) {
 871          switch (outputSemanticName[i]) {
 872          case TGSI_SEMANTIC_POSITION:
 873             t->outputs[i] = ureg_DECL_output( ureg,
 874                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
 875                                               outputSemanticIndex[i] );
 876
 877             t->outputs[i] = ureg_writemask( t->outputs[i],
 878                                             TGSI_WRITEMASK_Z );
 879             break;
 880          case TGSI_SEMANTIC_STENCIL:
 881             t->outputs[i] = ureg_DECL_output( ureg,
 882                                               TGSI_SEMANTIC_STENCIL, /* Stencil */
 883                                               outputSemanticIndex[i] );
 884             t->outputs[i] = ureg_writemask( t->outputs[i],
 885                                             TGSI_WRITEMASK_Y );
 886             break;
 887          case TGSI_SEMANTIC_COLOR:
 888             t->outputs[i] = ureg_DECL_output( ureg,
 889                                               TGSI_SEMANTIC_COLOR,
 890                                               outputSemanticIndex[i] );
 891             break;
 892          default:
 893             debug_assert(0);
 894             return 0;
 895          }
 896       }
 897    }
 898    else if (procType == PIPE_SHADER_GEOMETRY) {
 899       for (i = 0; i < numInputs; i++) {
 900          t->inputs[i] = ureg_DECL_input(ureg,
 901                                         inputSemanticName[i],
 902                                         inputSemanticIndex[i], 0, 1);
 903       }
 904
 905       for (i = 0; i < numOutputs; i++) {
 906          t->outputs[i] = ureg_DECL_output( ureg,
 907                                            outputSemanticName[i],
 908                                            outputSemanticIndex[i] );
 909       }
 910    }
 911    else {
 912       assert(procType == PIPE_SHADER_VERTEX);
 913
 914       for (i = 0; i < numInputs; i++) {
 915          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
 916       }
 917
 918       for (i = 0; i < numOutputs; i++) {
 919          t->outputs[i] = ureg_DECL_output( ureg,
 920                                            outputSemanticName[i],
 921                                            outputSemanticIndex[i] );
 922          if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
 923             /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
 924             ureg_MOV(ureg,
 925                      ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
 926                      ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
 927             t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
 928          }
 929       }
 930    }
 931
 932    /* Declare address register.
 933     */
 934    if (program->arb.NumAddressRegs > 0) {
 935       debug_assert( program->arb.NumAddressRegs == 1 );
 936       t->address[0] = ureg_DECL_address( ureg );
 937    }
 938
 939    /* Declare misc input registers
 940     */
 941    GLbitfield sysInputs = program->info.system_values_read;
 942    for (i = 0; sysInputs; i++) {
 943       if (sysInputs & (1 << i)) {
 944          unsigned semName = _mesa_sysval_to_semantic(i);
 945
 946          t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
 947
 948          if (semName == TGSI_SEMANTIC_INSTANCEID ||
 949              semName == TGSI_SEMANTIC_VERTEXID) {
 950             /* From Gallium perspective, these system values are always
 951              * integer, and require native integer support.  However, if
 952              * native integer is supported on the vertex stage but not the
 953              * pixel stage (e.g, i915g + draw), Mesa will generate IR that
 954              * assumes these system values are floats. To resolve the
 955              * inconsistency, we insert a U2F.
 956              */
 957             struct st_context *st = st_context(ctx);
 958             struct pipe_screen *pscreen = st->pipe->screen;
 959             assert(procType == PIPE_SHADER_VERTEX);
 960             assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
 961                    PIPE_SHADER_CAP_INTEGERS));
 962             (void) pscreen;  /* silence non-debug build warnings */
 963             if (!ctx->Const.NativeIntegers) {
 964                struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
 965                ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
 966                         t->systemValues[i]);
 967                t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
 968             }
 969          }
 970
 971          if (procType == PIPE_SHADER_FRAGMENT &&
 972              semName == TGSI_SEMANTIC_POSITION)
 973             emit_wpos(st_context(ctx), t, program, ureg);
 974
 975           sysInputs &= ~(1 << i);
 976       }
 977    }
 978
 979    if (program->arb.IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
 980       /* If temps are accessed with indirect addressing, declare temporaries
 981        * in sequential order.  Else, we declare them on demand elsewhere.
 982        */
 983       for (i = 0; i < program->arb.NumTemporaries; i++) {
 984          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
 985          t->temps[i] = ureg_DECL_temporary( t->ureg );
 986       }
 987    }
 988
 989    /* Emit constants and immediates.  Mesa uses a single index space
 990     * for these, so we put all the translated regs in t->constants.
 991     */
 992    if (program->Parameters) {
 993       t->constants = calloc( program->Parameters->NumParameters,
 994                              sizeof t->constants[0] );
 995       if (t->constants == NULL) {
 996          ret = PIPE_ERROR_OUT_OF_MEMORY;
 997          goto out;
 998       }
 999
1000       for (i = 0; i < program->Parameters->NumParameters; i++) {
1001          switch (program->Parameters->Parameters[i].Type) {
1002          case PROGRAM_STATE_VAR:
1003          case PROGRAM_UNIFORM:
1004             t->constants[i] = ureg_DECL_constant( ureg, i );
1005             break;
1006
1007             /* Emit immediates only when there's no indirect addressing of
1008              * the const buffer.
1009              * FIXME: Be smarter and recognize param arrays:
1010              * indirect addressing is only valid within the referenced
1011              * array.
1012              */
1013          case PROGRAM_CONSTANT:
1014             if (program->arb.IndirectRegisterFiles & PROGRAM_ANY_CONST)
1015                t->constants[i] = ureg_DECL_constant( ureg, i );
1016             else
1017                t->constants[i] =
1018                   ureg_DECL_immediate( ureg,
1019                                        (const float*) program->Parameters->ParameterValues[i],
1020                                        4 );
1021             break;
1022          default:
1023             break;
1024          }
1025       }
1026    }
1027
1028    /* texture samplers */
1029    for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
1030       if (program->SamplersUsed & (1u << i)) {
1031          unsigned target =
1032             translate_texture_index(program->TexturesUsed[i],
1033                                     !!(program->ShadowSamplers & (1 << i)));
1034          t->samplers[i] = ureg_DECL_sampler( ureg, i );
1035          ureg_DECL_sampler_view(ureg, i, target,
1036                                 TGSI_RETURN_TYPE_FLOAT,
1037                                 TGSI_RETURN_TYPE_FLOAT,
1038                                 TGSI_RETURN_TYPE_FLOAT,
1039                                 TGSI_RETURN_TYPE_FLOAT);
1040
1041       }
1042    }
1043
1044    /* Emit each instruction in turn:
1045     */
1046    for (i = 0; i < program->arb.NumInstructions; i++)
1047       compile_instruction(ctx, t, &program->arb.Instructions[i]);
1048
1049 out:
1050    free(t->constants);
1051    return ret;
1052 }