1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
51 (1 << PROGRAM_CONSTANT) | \
52 (1 << PROGRAM_UNIFORM))
56 unsigned branch_target
;
62 * Intermediate state used during shader translation.
65 struct ureg_program
*ureg
;
67 struct ureg_dst temps
[MAX_PROGRAM_TEMPS
];
68 struct ureg_src
*constants
;
69 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
70 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
71 struct ureg_dst address
[1];
72 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
73 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
75 const GLuint
*inputMapping
;
76 const GLuint
*outputMapping
;
78 /* For every instruction that contains a label (eg CALL), keep
79 * details so that we can go back afterwards and emit the correct
80 * tgsi instruction number for each label.
84 unsigned labels_count
;
86 /* Keep a record of the tgsi instruction number that each mesa
87 * instruction starts at, will be used to fix up labels after
94 unsigned procType
; /**< PIPE_SHADER_VERTEX/FRAGMENT */
101 * Make note of a branch to a label in the TGSI code.
102 * After we've emitted all instructions, we'll go over the list
103 * of labels built here and patch the TGSI code with the actual
104 * location of each label.
106 static unsigned *get_label( struct st_translate
*t
,
107 unsigned branch_target
)
111 if (t
->labels_count
+ 1 >= t
->labels_size
) {
112 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
113 t
->labels
= realloc(t
->labels
, t
->labels_size
* sizeof t
->labels
[0]);
114 if (t
->labels
== NULL
) {
115 static unsigned dummy
;
121 i
= t
->labels_count
++;
122 t
->labels
[i
].branch_target
= branch_target
;
123 return &t
->labels
[i
].token
;
128 * Called prior to emitting the TGSI code for each Mesa instruction.
129 * Allocate additional space for instructions if needed.
130 * Update the insn[] array so the next Mesa instruction points to
131 * the next TGSI instruction.
133 static void set_insn_start( struct st_translate
*t
,
136 if (t
->insn_count
+ 1 >= t
->insn_size
) {
137 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
138 t
->insn
= realloc(t
->insn
, t
->insn_size
* sizeof t
->insn
[0]);
139 if (t
->insn
== NULL
) {
145 t
->insn
[t
->insn_count
++] = start
;
150 * Map a Mesa dst register to a TGSI ureg_dst register.
152 static struct ureg_dst
153 dst_register( struct st_translate
*t
,
154 gl_register_file file
,
158 case PROGRAM_UNDEFINED
:
159 return ureg_dst_undef();
161 case PROGRAM_TEMPORARY
:
162 if (ureg_dst_is_undef(t
->temps
[index
]))
163 t
->temps
[index
] = ureg_DECL_temporary( t
->ureg
);
165 return t
->temps
[index
];
168 if (t
->procType
== PIPE_SHADER_VERTEX
)
169 assert(index
< VARYING_SLOT_MAX
);
170 else if (t
->procType
== PIPE_SHADER_FRAGMENT
)
171 assert(index
< FRAG_RESULT_MAX
);
173 assert(index
< VARYING_SLOT_MAX
);
175 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
177 return t
->outputs
[t
->outputMapping
[index
]];
179 case PROGRAM_ADDRESS
:
180 return t
->address
[index
];
184 return ureg_dst_undef();
190 * Map a Mesa src register to a TGSI ureg_src register.
192 static struct ureg_src
193 src_register( struct st_translate
*t
,
194 gl_register_file file
,
198 case PROGRAM_UNDEFINED
:
199 return ureg_src_undef();
201 case PROGRAM_TEMPORARY
:
203 assert(index
< ARRAY_SIZE(t
->temps
));
204 if (ureg_dst_is_undef(t
->temps
[index
]))
205 t
->temps
[index
] = ureg_DECL_temporary( t
->ureg
);
206 return ureg_src(t
->temps
[index
]);
208 case PROGRAM_UNIFORM
:
210 return t
->constants
[index
];
211 case PROGRAM_STATE_VAR
:
212 case PROGRAM_CONSTANT
: /* ie, immediate */
214 return ureg_DECL_constant( t
->ureg
, 0 );
216 return t
->constants
[index
];
219 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
220 return t
->inputs
[t
->inputMapping
[index
]];
223 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
224 return ureg_src(t
->outputs
[t
->outputMapping
[index
]]); /* not needed? */
226 case PROGRAM_ADDRESS
:
227 return ureg_src(t
->address
[index
]);
229 case PROGRAM_SYSTEM_VALUE
:
230 assert(index
< ARRAY_SIZE(t
->systemValues
));
231 return t
->systemValues
[index
];
235 return ureg_src_undef();
241 * Map mesa texture target to TGSI texture target.
244 st_translate_texture_target(GLuint textarget
, GLboolean shadow
)
248 case TEXTURE_1D_INDEX
:
249 return TGSI_TEXTURE_SHADOW1D
;
250 case TEXTURE_2D_INDEX
:
251 return TGSI_TEXTURE_SHADOW2D
;
252 case TEXTURE_RECT_INDEX
:
253 return TGSI_TEXTURE_SHADOWRECT
;
254 case TEXTURE_1D_ARRAY_INDEX
:
255 return TGSI_TEXTURE_SHADOW1D_ARRAY
;
256 case TEXTURE_2D_ARRAY_INDEX
:
257 return TGSI_TEXTURE_SHADOW2D_ARRAY
;
258 case TEXTURE_CUBE_INDEX
:
259 return TGSI_TEXTURE_SHADOWCUBE
;
260 case TEXTURE_CUBE_ARRAY_INDEX
:
261 return TGSI_TEXTURE_SHADOWCUBE_ARRAY
;
268 case TEXTURE_2D_MULTISAMPLE_INDEX
:
269 return TGSI_TEXTURE_2D_MSAA
;
270 case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
:
271 return TGSI_TEXTURE_2D_ARRAY_MSAA
;
272 case TEXTURE_BUFFER_INDEX
:
273 return TGSI_TEXTURE_BUFFER
;
274 case TEXTURE_1D_INDEX
:
275 return TGSI_TEXTURE_1D
;
276 case TEXTURE_2D_INDEX
:
277 return TGSI_TEXTURE_2D
;
278 case TEXTURE_3D_INDEX
:
279 return TGSI_TEXTURE_3D
;
280 case TEXTURE_CUBE_INDEX
:
281 return TGSI_TEXTURE_CUBE
;
282 case TEXTURE_CUBE_ARRAY_INDEX
:
283 return TGSI_TEXTURE_CUBE_ARRAY
;
284 case TEXTURE_RECT_INDEX
:
285 return TGSI_TEXTURE_RECT
;
286 case TEXTURE_1D_ARRAY_INDEX
:
287 return TGSI_TEXTURE_1D_ARRAY
;
288 case TEXTURE_2D_ARRAY_INDEX
:
289 return TGSI_TEXTURE_2D_ARRAY
;
290 case TEXTURE_EXTERNAL_INDEX
:
291 return TGSI_TEXTURE_2D
;
293 debug_assert(!"unexpected texture target index");
294 return TGSI_TEXTURE_1D
;
300 * Translate a (1 << TEXTURE_x_INDEX) bit into a TGSI_TEXTURE_x enum.
303 translate_texture_index(GLbitfield texBit
, bool shadow
)
305 int index
= ffs(texBit
);
307 assert(index
- 1 < NUM_TEXTURE_TARGETS
);
308 return st_translate_texture_target(index
- 1, shadow
);
313 * Create a TGSI ureg_dst register from a Mesa dest register.
315 static struct ureg_dst
316 translate_dst( struct st_translate
*t
,
317 const struct prog_dst_register
*DstReg
,
320 struct ureg_dst dst
= dst_register( t
,
324 dst
= ureg_writemask( dst
,
328 dst
= ureg_saturate( dst
);
331 dst
= ureg_dst_indirect( dst
, ureg_src(t
->address
[0]) );
338 * Create a TGSI ureg_src register from a Mesa src register.
340 static struct ureg_src
341 translate_src( struct st_translate
*t
,
342 const struct prog_src_register
*SrcReg
)
344 struct ureg_src src
= src_register( t
, SrcReg
->File
, SrcReg
->Index
);
346 src
= ureg_swizzle( src
,
347 GET_SWZ( SrcReg
->Swizzle
, 0 ) & 0x3,
348 GET_SWZ( SrcReg
->Swizzle
, 1 ) & 0x3,
349 GET_SWZ( SrcReg
->Swizzle
, 2 ) & 0x3,
350 GET_SWZ( SrcReg
->Swizzle
, 3 ) & 0x3);
352 if (SrcReg
->Negate
== NEGATE_XYZW
)
353 src
= ureg_negate(src
);
355 if (SrcReg
->RelAddr
) {
356 src
= ureg_src_indirect( src
, ureg_src(t
->address
[0]));
357 if (SrcReg
->File
!= PROGRAM_INPUT
&&
358 SrcReg
->File
!= PROGRAM_OUTPUT
) {
359 /* If SrcReg->Index was negative, it was set to zero in
360 * src_register(). Reassign it now. But don't do this
361 * for input/output regs since they get remapped while
362 * const buffers don't.
364 src
.Index
= SrcReg
->Index
;
372 static struct ureg_src
swizzle_4v( struct ureg_src src
,
373 const unsigned *swz
)
375 return ureg_swizzle( src
, swz
[0], swz
[1], swz
[2], swz
[3] );
380 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
386 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
388 static void emit_swz( struct st_translate
*t
,
390 const struct prog_src_register
*SrcReg
)
392 struct ureg_program
*ureg
= t
->ureg
;
393 struct ureg_src src
= src_register( t
, SrcReg
->File
, SrcReg
->Index
);
395 unsigned negate_mask
= SrcReg
->Negate
;
397 unsigned one_mask
= ((GET_SWZ(SrcReg
->Swizzle
, 0) == SWIZZLE_ONE
) << 0 |
398 (GET_SWZ(SrcReg
->Swizzle
, 1) == SWIZZLE_ONE
) << 1 |
399 (GET_SWZ(SrcReg
->Swizzle
, 2) == SWIZZLE_ONE
) << 2 |
400 (GET_SWZ(SrcReg
->Swizzle
, 3) == SWIZZLE_ONE
) << 3);
402 unsigned zero_mask
= ((GET_SWZ(SrcReg
->Swizzle
, 0) == SWIZZLE_ZERO
) << 0 |
403 (GET_SWZ(SrcReg
->Swizzle
, 1) == SWIZZLE_ZERO
) << 1 |
404 (GET_SWZ(SrcReg
->Swizzle
, 2) == SWIZZLE_ZERO
) << 2 |
405 (GET_SWZ(SrcReg
->Swizzle
, 3) == SWIZZLE_ZERO
) << 3);
407 unsigned negative_one_mask
= one_mask
& negate_mask
;
408 unsigned positive_one_mask
= one_mask
& ~negate_mask
;
412 unsigned mul_swizzle
[4] = {0,0,0,0};
413 unsigned add_swizzle
[4] = {0,0,0,0};
414 unsigned src_swizzle
[4] = {0,0,0,0};
415 boolean need_add
= FALSE
;
416 boolean need_mul
= FALSE
;
418 if (dst
.WriteMask
== 0)
421 /* Is this just a MOV?
423 if (zero_mask
== 0 &&
425 (negate_mask
== 0 || negate_mask
== TGSI_WRITEMASK_XYZW
))
427 ureg_MOV( ureg
, dst
, translate_src( t
, SrcReg
));
433 #define IMM_NEG_ONE 2
435 imm
= ureg_imm3f( ureg
, 0, 1, -1 );
437 for (i
= 0; i
< 4; i
++) {
438 unsigned bit
= 1 << i
;
440 if (dst
.WriteMask
& bit
) {
441 if (positive_one_mask
& bit
) {
442 mul_swizzle
[i
] = IMM_ZERO
;
443 add_swizzle
[i
] = IMM_ONE
;
446 else if (negative_one_mask
& bit
) {
447 mul_swizzle
[i
] = IMM_ZERO
;
448 add_swizzle
[i
] = IMM_NEG_ONE
;
451 else if (zero_mask
& bit
) {
452 mul_swizzle
[i
] = IMM_ZERO
;
453 add_swizzle
[i
] = IMM_ZERO
;
457 add_swizzle
[i
] = IMM_ZERO
;
458 src_swizzle
[i
] = GET_SWZ(SrcReg
->Swizzle
, i
);
460 if (negate_mask
& bit
) {
461 mul_swizzle
[i
] = IMM_NEG_ONE
;
464 mul_swizzle
[i
] = IMM_ONE
;
470 if (need_mul
&& need_add
) {
473 swizzle_4v( src
, src_swizzle
),
474 swizzle_4v( imm
, mul_swizzle
),
475 swizzle_4v( imm
, add_swizzle
) );
480 swizzle_4v( src
, src_swizzle
),
481 swizzle_4v( imm
, mul_swizzle
) );
486 swizzle_4v( imm
, add_swizzle
) );
499 translate_opcode( unsigned op
)
503 return TGSI_OPCODE_ARL
;
505 return TGSI_OPCODE_ABS
;
507 return TGSI_OPCODE_ADD
;
509 return TGSI_OPCODE_BGNLOOP
;
511 return TGSI_OPCODE_BGNSUB
;
513 return TGSI_OPCODE_BRK
;
515 return TGSI_OPCODE_CAL
;
517 return TGSI_OPCODE_CMP
;
519 return TGSI_OPCODE_CONT
;
521 return TGSI_OPCODE_COS
;
523 return TGSI_OPCODE_DDX
;
525 return TGSI_OPCODE_DDY
;
527 return TGSI_OPCODE_DP2
;
529 return TGSI_OPCODE_DP3
;
531 return TGSI_OPCODE_DP4
;
533 return TGSI_OPCODE_DPH
;
535 return TGSI_OPCODE_DST
;
537 return TGSI_OPCODE_ELSE
;
539 return TGSI_OPCODE_ENDIF
;
541 return TGSI_OPCODE_ENDLOOP
;
543 return TGSI_OPCODE_ENDSUB
;
545 return TGSI_OPCODE_EX2
;
547 return TGSI_OPCODE_EXP
;
549 return TGSI_OPCODE_FLR
;
551 return TGSI_OPCODE_FRC
;
553 return TGSI_OPCODE_IF
;
555 return TGSI_OPCODE_TRUNC
;
557 return TGSI_OPCODE_KILL_IF
;
559 return TGSI_OPCODE_LG2
;
561 return TGSI_OPCODE_LOG
;
563 return TGSI_OPCODE_LIT
;
565 return TGSI_OPCODE_LRP
;
567 return TGSI_OPCODE_MAD
;
569 return TGSI_OPCODE_MAX
;
571 return TGSI_OPCODE_MIN
;
573 return TGSI_OPCODE_MOV
;
575 return TGSI_OPCODE_MUL
;
577 return TGSI_OPCODE_NOP
;
579 return TGSI_OPCODE_POW
;
581 return TGSI_OPCODE_RCP
;
583 return TGSI_OPCODE_RET
;
585 return TGSI_OPCODE_SCS
;
587 return TGSI_OPCODE_SGE
;
589 return TGSI_OPCODE_SIN
;
591 return TGSI_OPCODE_SLT
;
593 return TGSI_OPCODE_SSG
;
595 return TGSI_OPCODE_SUB
;
597 return TGSI_OPCODE_TEX
;
599 return TGSI_OPCODE_TXB
;
601 return TGSI_OPCODE_TXD
;
603 return TGSI_OPCODE_TXL
;
605 return TGSI_OPCODE_TXP
;
607 return TGSI_OPCODE_XPD
;
609 return TGSI_OPCODE_END
;
612 return TGSI_OPCODE_NOP
;
619 struct gl_context
*ctx
,
620 struct st_translate
*t
,
621 const struct prog_instruction
*inst
)
623 struct ureg_program
*ureg
= t
->ureg
;
625 struct ureg_dst dst
[1] = { { 0 } };
626 struct ureg_src src
[4];
630 num_dst
= _mesa_num_inst_dst_regs( inst
->Opcode
);
631 num_src
= _mesa_num_inst_src_regs( inst
->Opcode
);
634 dst
[0] = translate_dst( t
,
638 for (i
= 0; i
< num_src
; i
++)
639 src
[i
] = translate_src( t
, &inst
->SrcReg
[i
] );
641 switch( inst
->Opcode
) {
643 emit_swz( t
, dst
[0], &inst
->SrcReg
[0] );
650 debug_assert(num_dst
== 0);
651 ureg_label_insn( ureg
,
652 translate_opcode( inst
->Opcode
),
654 get_label( t
, inst
->BranchTarget
));
658 debug_assert(num_dst
== 0);
659 ureg_label_insn( ureg
,
660 ctx
->Const
.NativeIntegers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
,
662 get_label( t
, inst
->BranchTarget
));
670 src
[num_src
++] = t
->samplers
[inst
->TexSrcUnit
];
672 translate_opcode( inst
->Opcode
),
674 st_translate_texture_target( inst
->TexSrcTarget
,
681 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
683 translate_opcode( inst
->Opcode
),
689 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XYZ
);
691 translate_opcode( inst
->Opcode
),
700 /* At some point, a motivated person could add a better
701 * implementation of noise. Currently not even the nvidia
702 * binary drivers do anything more than this. In any case, the
703 * place to do this is in the GL state tracker, not the poor
706 ureg_MOV( ureg
, dst
[0], ureg_imm1f(ureg
, 0.5) );
710 ureg_RSQ( ureg
, dst
[0], ureg_abs(src
[0]) );
715 translate_opcode( inst
->Opcode
),
724 * Emit the TGSI instructions for inverting and adjusting WPOS.
725 * This code is unavoidable because it also depends on whether
726 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
729 emit_wpos_adjustment(struct gl_context
*ctx
,
730 struct st_translate
*t
,
731 const struct gl_program
*program
,
733 GLfloat adjX
, GLfloat adjY
[2])
735 struct ureg_program
*ureg
= t
->ureg
;
737 /* Fragment program uses fragment position input.
738 * Need to replace instances of INPUT[WPOS] with temp T
739 * where T = INPUT[WPOS] by y is inverted.
741 static const gl_state_index wposTransformState
[STATE_LENGTH
]
742 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0 };
744 /* XXX: note we are modifying the incoming shader here! Need to
745 * do this before emitting the constant decls below, or this
748 unsigned wposTransConst
= _mesa_add_state_reference(program
->Parameters
,
751 struct ureg_src wpostrans
= ureg_DECL_constant( ureg
, wposTransConst
);
752 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
753 struct ureg_src
*wpos
=
754 ctx
->Const
.GLSLFragCoordIsSysVal
?
755 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
756 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
757 struct ureg_src wpos_input
= *wpos
;
759 /* First, apply the coordinate shift: */
760 if (adjX
|| adjY
[0] || adjY
[1]) {
761 if (adjY
[0] != adjY
[1]) {
762 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
763 * depending on whether inversion is actually going to be applied
764 * or not, which is determined by testing against the inversion
765 * state variable used below, which will be either +1 or -1.
767 struct ureg_dst adj_temp
= ureg_DECL_temporary(ureg
);
769 ureg_CMP(ureg
, adj_temp
,
770 ureg_scalar(wpostrans
, invert
? 2 : 0),
771 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
772 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
773 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
775 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
776 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
778 wpos_input
= ureg_src(wpos_temp
);
780 /* MOV wpos_temp, input[wpos]
782 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
785 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
786 * inversion/identity, or the other way around if we're drawing to an FBO.
789 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
792 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
794 ureg_scalar(wpostrans
, 0),
795 ureg_scalar(wpostrans
, 1));
797 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
800 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
802 ureg_scalar(wpostrans
, 2),
803 ureg_scalar(wpostrans
, 3));
806 /* Use wpos_temp as position input from here on:
808 *wpos
= ureg_src(wpos_temp
);
813 * Emit fragment position/coordinate code.
816 emit_wpos(struct st_context
*st
,
817 struct st_translate
*t
,
818 const struct gl_program
*program
,
819 struct ureg_program
*ureg
)
821 const struct gl_fragment_program
*fp
=
822 (const struct gl_fragment_program
*) program
;
823 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
825 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
826 boolean invert
= FALSE
;
828 /* Query the pixel center conventions supported by the pipe driver and set
829 * adjX, adjY to help out if it cannot handle the requested one internally.
831 * The bias of the y-coordinate depends on whether y-inversion takes place
832 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
833 * drawing to an FBO (causes additional inversion), and whether the pipe
834 * driver origin and the requested origin differ (the latter condition is
835 * stored in the 'invert' variable).
837 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
844 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
845 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
846 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
847 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
849 * inversion and center shift:
850 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
851 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
852 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
853 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
855 if (fp
->OriginUpperLeft
) {
856 /* Fragment shader wants origin in upper-left */
857 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
858 /* the driver supports upper-left origin */
860 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
861 /* the driver supports lower-left origin, need to invert Y */
862 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
863 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
870 /* Fragment shader wants origin in lower-left */
871 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
872 /* the driver supports lower-left origin */
873 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
874 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
875 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
876 /* the driver supports upper-left origin, need to invert Y */
882 if (fp
->PixelCenterInteger
) {
883 /* Fragment shader wants pixel center integer */
884 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
885 /* the driver supports pixel center integer */
887 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
888 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
890 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
891 /* the driver supports pixel center half integer, need to bias X,Y */
900 /* Fragment shader wants pixel center half integer */
901 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
902 /* the driver supports pixel center half integer */
904 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
905 /* the driver supports pixel center integer, need to bias X,Y */
906 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
907 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
908 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
914 /* we invert after adjustment so that we avoid the MOV to temporary,
915 * and reuse the adjustment ADD instead */
916 emit_wpos_adjustment(st
->ctx
, t
, program
, invert
, adjX
, adjY
);
921 * Translate Mesa program to TGSI format.
922 * \param program the program to translate
923 * \param numInputs number of input registers used
924 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
926 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
927 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
929 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
930 * \param numOutputs number of output registers used
931 * \param outputMapping maps Mesa fragment program outputs to TGSI
933 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
934 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
937 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
940 st_translate_mesa_program(
941 struct gl_context
*ctx
,
943 struct ureg_program
*ureg
,
944 const struct gl_program
*program
,
946 const GLuint inputMapping
[],
947 const ubyte inputSemanticName
[],
948 const ubyte inputSemanticIndex
[],
949 const GLuint interpMode
[],
951 const GLuint outputMapping
[],
952 const ubyte outputSemanticName
[],
953 const ubyte outputSemanticIndex
[])
955 struct st_translate translate
, *t
;
957 enum pipe_error ret
= PIPE_OK
;
959 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
960 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
963 memset(t
, 0, sizeof *t
);
965 t
->procType
= procType
;
966 t
->inputMapping
= inputMapping
;
967 t
->outputMapping
= outputMapping
;
970 /*_mesa_print_program(program);*/
973 * Declare input attributes.
975 if (procType
== PIPE_SHADER_FRAGMENT
) {
976 for (i
= 0; i
< numInputs
; i
++) {
977 t
->inputs
[i
] = ureg_DECL_fs_input(ureg
,
978 inputSemanticName
[i
],
979 inputSemanticIndex
[i
],
983 if (program
->InputsRead
& VARYING_BIT_POS
) {
984 /* Must do this after setting up t->inputs, and before
985 * emitting constant references, below:
987 emit_wpos(st_context(ctx
), t
, program
, ureg
);
991 * Declare output attributes.
993 for (i
= 0; i
< numOutputs
; i
++) {
994 switch (outputSemanticName
[i
]) {
995 case TGSI_SEMANTIC_POSITION
:
996 t
->outputs
[i
] = ureg_DECL_output( ureg
,
997 TGSI_SEMANTIC_POSITION
, /* Z / Depth */
998 outputSemanticIndex
[i
] );
1000 t
->outputs
[i
] = ureg_writemask( t
->outputs
[i
],
1003 case TGSI_SEMANTIC_STENCIL
:
1004 t
->outputs
[i
] = ureg_DECL_output( ureg
,
1005 TGSI_SEMANTIC_STENCIL
, /* Stencil */
1006 outputSemanticIndex
[i
] );
1007 t
->outputs
[i
] = ureg_writemask( t
->outputs
[i
],
1010 case TGSI_SEMANTIC_COLOR
:
1011 t
->outputs
[i
] = ureg_DECL_output( ureg
,
1012 TGSI_SEMANTIC_COLOR
,
1013 outputSemanticIndex
[i
] );
1021 else if (procType
== PIPE_SHADER_GEOMETRY
) {
1022 for (i
= 0; i
< numInputs
; i
++) {
1023 t
->inputs
[i
] = ureg_DECL_input(ureg
,
1024 inputSemanticName
[i
],
1025 inputSemanticIndex
[i
], 0, 1);
1028 for (i
= 0; i
< numOutputs
; i
++) {
1029 t
->outputs
[i
] = ureg_DECL_output( ureg
,
1030 outputSemanticName
[i
],
1031 outputSemanticIndex
[i
] );
1035 assert(procType
== PIPE_SHADER_VERTEX
);
1037 for (i
= 0; i
< numInputs
; i
++) {
1038 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
1041 for (i
= 0; i
< numOutputs
; i
++) {
1042 t
->outputs
[i
] = ureg_DECL_output( ureg
,
1043 outputSemanticName
[i
],
1044 outputSemanticIndex
[i
] );
1045 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
1046 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
1048 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
1049 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
1050 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
1055 /* Declare address register.
1057 if (program
->NumAddressRegs
> 0) {
1058 debug_assert( program
->NumAddressRegs
== 1 );
1059 t
->address
[0] = ureg_DECL_address( ureg
);
1062 /* Declare misc input registers
1065 GLbitfield sysInputs
= program
->SystemValuesRead
;
1067 for (i
= 0; sysInputs
; i
++) {
1068 if (sysInputs
& (1 << i
)) {
1069 unsigned semName
= _mesa_sysval_to_semantic(i
);
1071 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
1073 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
1074 semName
== TGSI_SEMANTIC_VERTEXID
) {
1075 /* From Gallium perspective, these system values are always
1076 * integer, and require native integer support. However, if
1077 * native integer is supported on the vertex stage but not the
1078 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1079 * assumes these system values are floats. To resolve the
1080 * inconsistency, we insert a U2F.
1082 struct st_context
*st
= st_context(ctx
);
1083 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
1084 assert(procType
== PIPE_SHADER_VERTEX
);
1085 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
1086 (void) pscreen
; /* silence non-debug build warnings */
1087 if (!ctx
->Const
.NativeIntegers
) {
1088 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
1089 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
1090 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
1094 if (procType
== PIPE_SHADER_FRAGMENT
&&
1095 semName
== TGSI_SEMANTIC_POSITION
)
1096 emit_wpos(st_context(ctx
), t
, program
, ureg
);
1098 sysInputs
&= ~(1 << i
);
1103 if (program
->IndirectRegisterFiles
& (1 << PROGRAM_TEMPORARY
)) {
1104 /* If temps are accessed with indirect addressing, declare temporaries
1105 * in sequential order. Else, we declare them on demand elsewhere.
1107 for (i
= 0; i
< program
->NumTemporaries
; i
++) {
1108 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1109 t
->temps
[i
] = ureg_DECL_temporary( t
->ureg
);
1113 /* Emit constants and immediates. Mesa uses a single index space
1114 * for these, so we put all the translated regs in t->constants.
1116 if (program
->Parameters
) {
1117 t
->constants
= calloc( program
->Parameters
->NumParameters
,
1118 sizeof t
->constants
[0] );
1119 if (t
->constants
== NULL
) {
1120 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
1124 for (i
= 0; i
< program
->Parameters
->NumParameters
; i
++) {
1125 switch (program
->Parameters
->Parameters
[i
].Type
) {
1126 case PROGRAM_STATE_VAR
:
1127 case PROGRAM_UNIFORM
:
1128 t
->constants
[i
] = ureg_DECL_constant( ureg
, i
);
1131 /* Emit immediates only when there's no indirect addressing of
1133 * FIXME: Be smarter and recognize param arrays:
1134 * indirect addressing is only valid within the referenced
1137 case PROGRAM_CONSTANT
:
1138 if (program
->IndirectRegisterFiles
& PROGRAM_ANY_CONST
)
1139 t
->constants
[i
] = ureg_DECL_constant( ureg
, i
);
1142 ureg_DECL_immediate( ureg
,
1143 (const float*) program
->Parameters
->ParameterValues
[i
],
1152 /* texture samplers */
1153 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
1154 if (program
->SamplersUsed
& (1u << i
)) {
1156 translate_texture_index(program
->TexturesUsed
[i
],
1157 !!(program
->ShadowSamplers
& (1 << i
)));
1158 t
->samplers
[i
] = ureg_DECL_sampler( ureg
, i
);
1159 ureg_DECL_sampler_view(ureg
, i
, target
,
1160 TGSI_RETURN_TYPE_FLOAT
,
1161 TGSI_RETURN_TYPE_FLOAT
,
1162 TGSI_RETURN_TYPE_FLOAT
,
1163 TGSI_RETURN_TYPE_FLOAT
);
1168 /* Emit each instruction in turn:
1170 for (i
= 0; i
< program
->NumInstructions
; i
++) {
1171 set_insn_start( t
, ureg_get_instruction_number( ureg
));
1172 compile_instruction(ctx
, t
, &program
->Instructions
[i
]);
1175 /* Fix up all emitted labels:
1177 for (i
= 0; i
< t
->labels_count
; i
++) {
1178 ureg_fixup_label( ureg
,
1180 t
->insn
[t
->labels
[i
].branch_target
] );
1189 debug_printf("%s: translate error flag set\n", __func__
);