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Replace gl_vert_result enum with gl_varying_slot.
[mesa.git] / src / mesa / state_tracker / st_mesa_to_tgsi.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * \author
30 * Michal Krol,
31 * Keith Whitwell
32 */
33
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47
48
49 #define PROGRAM_ANY_CONST ((1 << PROGRAM_LOCAL_PARAM) | \
50 (1 << PROGRAM_ENV_PARAM) | \
51 (1 << PROGRAM_STATE_VAR) | \
52 (1 << PROGRAM_CONSTANT) | \
53 (1 << PROGRAM_UNIFORM))
54
55
56 struct label {
57 unsigned branch_target;
58 unsigned token;
59 };
60
61
62 /**
63 * Intermediate state used during shader translation.
64 */
65 struct st_translate {
66 struct ureg_program *ureg;
67
68 struct ureg_dst temps[MAX_PROGRAM_TEMPS];
69 struct ureg_src *constants;
70 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
71 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
72 struct ureg_dst address[1];
73 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
74 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
75
76 const GLuint *inputMapping;
77 const GLuint *outputMapping;
78
79 /* For every instruction that contains a label (eg CALL), keep
80 * details so that we can go back afterwards and emit the correct
81 * tgsi instruction number for each label.
82 */
83 struct label *labels;
84 unsigned labels_size;
85 unsigned labels_count;
86
87 /* Keep a record of the tgsi instruction number that each mesa
88 * instruction starts at, will be used to fix up labels after
89 * translation.
90 */
91 unsigned *insn;
92 unsigned insn_size;
93 unsigned insn_count;
94
95 unsigned procType; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
96
97 boolean error;
98 };
99
100
101 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
102 static unsigned mesa_sysval_to_semantic[SYSTEM_VALUE_MAX] = {
103 TGSI_SEMANTIC_FACE,
104 TGSI_SEMANTIC_VERTEXID,
105 TGSI_SEMANTIC_INSTANCEID
106 };
107
108
109 /**
110 * Make note of a branch to a label in the TGSI code.
111 * After we've emitted all instructions, we'll go over the list
112 * of labels built here and patch the TGSI code with the actual
113 * location of each label.
114 */
115 static unsigned *get_label( struct st_translate *t,
116 unsigned branch_target )
117 {
118 unsigned i;
119
120 if (t->labels_count + 1 >= t->labels_size) {
121 t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
122 t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
123 if (t->labels == NULL) {
124 static unsigned dummy;
125 t->error = TRUE;
126 return &dummy;
127 }
128 }
129
130 i = t->labels_count++;
131 t->labels[i].branch_target = branch_target;
132 return &t->labels[i].token;
133 }
134
135
136 /**
137 * Called prior to emitting the TGSI code for each Mesa instruction.
138 * Allocate additional space for instructions if needed.
139 * Update the insn[] array so the next Mesa instruction points to
140 * the next TGSI instruction.
141 */
142 static void set_insn_start( struct st_translate *t,
143 unsigned start )
144 {
145 if (t->insn_count + 1 >= t->insn_size) {
146 t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
147 t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
148 if (t->insn == NULL) {
149 t->error = TRUE;
150 return;
151 }
152 }
153
154 t->insn[t->insn_count++] = start;
155 }
156
157
158 /**
159 * Map a Mesa dst register to a TGSI ureg_dst register.
160 */
161 static struct ureg_dst
162 dst_register( struct st_translate *t,
163 gl_register_file file,
164 GLuint index )
165 {
166 switch( file ) {
167 case PROGRAM_UNDEFINED:
168 return ureg_dst_undef();
169
170 case PROGRAM_TEMPORARY:
171 if (ureg_dst_is_undef(t->temps[index]))
172 t->temps[index] = ureg_DECL_temporary( t->ureg );
173
174 return t->temps[index];
175
176 case PROGRAM_OUTPUT:
177 if (t->procType == TGSI_PROCESSOR_VERTEX)
178 assert(index < VARYING_SLOT_MAX);
179 else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
180 assert(index < FRAG_RESULT_MAX);
181 else
182 assert(index < GEOM_RESULT_MAX);
183
184 assert(t->outputMapping[index] < Elements(t->outputs));
185
186 return t->outputs[t->outputMapping[index]];
187
188 case PROGRAM_ADDRESS:
189 return t->address[index];
190
191 default:
192 debug_assert( 0 );
193 return ureg_dst_undef();
194 }
195 }
196
197
198 /**
199 * Map a Mesa src register to a TGSI ureg_src register.
200 */
201 static struct ureg_src
202 src_register( struct st_translate *t,
203 gl_register_file file,
204 GLint index )
205 {
206 switch( file ) {
207 case PROGRAM_UNDEFINED:
208 return ureg_src_undef();
209
210 case PROGRAM_TEMPORARY:
211 assert(index >= 0);
212 assert(index < Elements(t->temps));
213 if (ureg_dst_is_undef(t->temps[index]))
214 t->temps[index] = ureg_DECL_temporary( t->ureg );
215 return ureg_src(t->temps[index]);
216
217 case PROGRAM_ENV_PARAM:
218 case PROGRAM_LOCAL_PARAM:
219 case PROGRAM_UNIFORM:
220 assert(index >= 0);
221 return t->constants[index];
222 case PROGRAM_STATE_VAR:
223 case PROGRAM_CONSTANT: /* ie, immediate */
224 if (index < 0)
225 return ureg_DECL_constant( t->ureg, 0 );
226 else
227 return t->constants[index];
228
229 case PROGRAM_INPUT:
230 assert(t->inputMapping[index] < Elements(t->inputs));
231 return t->inputs[t->inputMapping[index]];
232
233 case PROGRAM_OUTPUT:
234 assert(t->outputMapping[index] < Elements(t->outputs));
235 return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
236
237 case PROGRAM_ADDRESS:
238 return ureg_src(t->address[index]);
239
240 case PROGRAM_SYSTEM_VALUE:
241 assert(index < Elements(t->systemValues));
242 return t->systemValues[index];
243
244 default:
245 debug_assert( 0 );
246 return ureg_src_undef();
247 }
248 }
249
250
251 /**
252 * Map mesa texture target to TGSI texture target.
253 */
254 unsigned
255 st_translate_texture_target( GLuint textarget,
256 GLboolean shadow )
257 {
258 if (shadow) {
259 switch( textarget ) {
260 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_SHADOW1D;
261 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_SHADOW2D;
262 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
263 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
264 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
265 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
266 case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
267 default: break;
268 }
269 }
270
271 switch( textarget ) {
272 case TEXTURE_BUFFER_INDEX: return TGSI_TEXTURE_BUFFER;
273 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_1D;
274 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_2D;
275 case TEXTURE_3D_INDEX: return TGSI_TEXTURE_3D;
276 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
277 case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_CUBE_ARRAY;
278 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
279 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_1D_ARRAY;
280 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY;
281 case TEXTURE_EXTERNAL_INDEX: return TGSI_TEXTURE_2D;
282 default:
283 debug_assert( 0 );
284 return TGSI_TEXTURE_1D;
285 }
286 }
287
288
289 /**
290 * Create a TGSI ureg_dst register from a Mesa dest register.
291 */
292 static struct ureg_dst
293 translate_dst( struct st_translate *t,
294 const struct prog_dst_register *DstReg,
295 boolean saturate,
296 boolean clamp_color)
297 {
298 struct ureg_dst dst = dst_register( t,
299 DstReg->File,
300 DstReg->Index );
301
302 dst = ureg_writemask( dst,
303 DstReg->WriteMask );
304
305 if (saturate)
306 dst = ureg_saturate( dst );
307 else if (clamp_color && DstReg->File == PROGRAM_OUTPUT) {
308 /* Clamp colors for ARB_color_buffer_float. */
309 switch (t->procType) {
310 case TGSI_PROCESSOR_VERTEX:
311 /* XXX if the geometry shader is present, this must be done there
312 * instead of here. */
313 if (DstReg->Index == VARYING_SLOT_COL0 ||
314 DstReg->Index == VARYING_SLOT_COL1 ||
315 DstReg->Index == VARYING_SLOT_BFC0 ||
316 DstReg->Index == VARYING_SLOT_BFC1) {
317 dst = ureg_saturate(dst);
318 }
319 break;
320
321 case TGSI_PROCESSOR_FRAGMENT:
322 if (DstReg->Index >= FRAG_RESULT_COLOR) {
323 dst = ureg_saturate(dst);
324 }
325 break;
326 }
327 }
328
329 if (DstReg->RelAddr)
330 dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
331
332 return dst;
333 }
334
335
336 /**
337 * Create a TGSI ureg_src register from a Mesa src register.
338 */
339 static struct ureg_src
340 translate_src( struct st_translate *t,
341 const struct prog_src_register *SrcReg )
342 {
343 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
344
345 if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
346 src = src_register( t, SrcReg->File, SrcReg->Index2 );
347 if (SrcReg->RelAddr2)
348 src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
349 SrcReg->Index);
350 else
351 src = ureg_src_dimension( src, SrcReg->Index);
352 }
353
354 src = ureg_swizzle( src,
355 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
356 GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
357 GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
358 GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
359
360 if (SrcReg->Negate == NEGATE_XYZW)
361 src = ureg_negate(src);
362
363 if (SrcReg->Abs)
364 src = ureg_abs(src);
365
366 if (SrcReg->RelAddr) {
367 src = ureg_src_indirect( src, ureg_src(t->address[0]));
368 if (SrcReg->File != PROGRAM_INPUT &&
369 SrcReg->File != PROGRAM_OUTPUT) {
370 /* If SrcReg->Index was negative, it was set to zero in
371 * src_register(). Reassign it now. But don't do this
372 * for input/output regs since they get remapped while
373 * const buffers don't.
374 */
375 src.Index = SrcReg->Index;
376 }
377 }
378
379 return src;
380 }
381
382
383 static struct ureg_src swizzle_4v( struct ureg_src src,
384 const unsigned *swz )
385 {
386 return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
387 }
388
389
390 /**
391 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
392 *
393 * SWZ dst, src.x-y10
394 *
395 * becomes:
396 *
397 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
398 */
399 static void emit_swz( struct st_translate *t,
400 struct ureg_dst dst,
401 const struct prog_src_register *SrcReg )
402 {
403 struct ureg_program *ureg = t->ureg;
404 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
405
406 unsigned negate_mask = SrcReg->Negate;
407
408 unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
409 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
410 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
411 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
412
413 unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
414 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
415 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
416 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
417
418 unsigned negative_one_mask = one_mask & negate_mask;
419 unsigned positive_one_mask = one_mask & ~negate_mask;
420
421 struct ureg_src imm;
422 unsigned i;
423 unsigned mul_swizzle[4] = {0,0,0,0};
424 unsigned add_swizzle[4] = {0,0,0,0};
425 unsigned src_swizzle[4] = {0,0,0,0};
426 boolean need_add = FALSE;
427 boolean need_mul = FALSE;
428
429 if (dst.WriteMask == 0)
430 return;
431
432 /* Is this just a MOV?
433 */
434 if (zero_mask == 0 &&
435 one_mask == 0 &&
436 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
437 {
438 ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
439 return;
440 }
441
442 #define IMM_ZERO 0
443 #define IMM_ONE 1
444 #define IMM_NEG_ONE 2
445
446 imm = ureg_imm3f( ureg, 0, 1, -1 );
447
448 for (i = 0; i < 4; i++) {
449 unsigned bit = 1 << i;
450
451 if (dst.WriteMask & bit) {
452 if (positive_one_mask & bit) {
453 mul_swizzle[i] = IMM_ZERO;
454 add_swizzle[i] = IMM_ONE;
455 need_add = TRUE;
456 }
457 else if (negative_one_mask & bit) {
458 mul_swizzle[i] = IMM_ZERO;
459 add_swizzle[i] = IMM_NEG_ONE;
460 need_add = TRUE;
461 }
462 else if (zero_mask & bit) {
463 mul_swizzle[i] = IMM_ZERO;
464 add_swizzle[i] = IMM_ZERO;
465 need_add = TRUE;
466 }
467 else {
468 add_swizzle[i] = IMM_ZERO;
469 src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
470 need_mul = TRUE;
471 if (negate_mask & bit) {
472 mul_swizzle[i] = IMM_NEG_ONE;
473 }
474 else {
475 mul_swizzle[i] = IMM_ONE;
476 }
477 }
478 }
479 }
480
481 if (need_mul && need_add) {
482 ureg_MAD( ureg,
483 dst,
484 swizzle_4v( src, src_swizzle ),
485 swizzle_4v( imm, mul_swizzle ),
486 swizzle_4v( imm, add_swizzle ) );
487 }
488 else if (need_mul) {
489 ureg_MUL( ureg,
490 dst,
491 swizzle_4v( src, src_swizzle ),
492 swizzle_4v( imm, mul_swizzle ) );
493 }
494 else if (need_add) {
495 ureg_MOV( ureg,
496 dst,
497 swizzle_4v( imm, add_swizzle ) );
498 }
499 else {
500 debug_assert(0);
501 }
502
503 #undef IMM_ZERO
504 #undef IMM_ONE
505 #undef IMM_NEG_ONE
506 }
507
508
509 /**
510 * Negate the value of DDY to match GL semantics where (0,0) is the
511 * lower-left corner of the window.
512 * Note that the GL_ARB_fragment_coord_conventions extension will
513 * effect this someday.
514 */
515 static void emit_ddy( struct st_translate *t,
516 struct ureg_dst dst,
517 const struct prog_src_register *SrcReg )
518 {
519 struct ureg_program *ureg = t->ureg;
520 struct ureg_src src = translate_src( t, SrcReg );
521 src = ureg_negate( src );
522 ureg_DDY( ureg, dst, src );
523 }
524
525
526
527 static unsigned
528 translate_opcode( unsigned op )
529 {
530 switch( op ) {
531 case OPCODE_ARL:
532 return TGSI_OPCODE_ARL;
533 case OPCODE_ABS:
534 return TGSI_OPCODE_ABS;
535 case OPCODE_ADD:
536 return TGSI_OPCODE_ADD;
537 case OPCODE_BGNLOOP:
538 return TGSI_OPCODE_BGNLOOP;
539 case OPCODE_BGNSUB:
540 return TGSI_OPCODE_BGNSUB;
541 case OPCODE_BRK:
542 return TGSI_OPCODE_BRK;
543 case OPCODE_CAL:
544 return TGSI_OPCODE_CAL;
545 case OPCODE_CMP:
546 return TGSI_OPCODE_CMP;
547 case OPCODE_CONT:
548 return TGSI_OPCODE_CONT;
549 case OPCODE_COS:
550 return TGSI_OPCODE_COS;
551 case OPCODE_DDX:
552 return TGSI_OPCODE_DDX;
553 case OPCODE_DDY:
554 return TGSI_OPCODE_DDY;
555 case OPCODE_DP2:
556 return TGSI_OPCODE_DP2;
557 case OPCODE_DP2A:
558 return TGSI_OPCODE_DP2A;
559 case OPCODE_DP3:
560 return TGSI_OPCODE_DP3;
561 case OPCODE_DP4:
562 return TGSI_OPCODE_DP4;
563 case OPCODE_DPH:
564 return TGSI_OPCODE_DPH;
565 case OPCODE_DST:
566 return TGSI_OPCODE_DST;
567 case OPCODE_ELSE:
568 return TGSI_OPCODE_ELSE;
569 case OPCODE_ENDIF:
570 return TGSI_OPCODE_ENDIF;
571 case OPCODE_ENDLOOP:
572 return TGSI_OPCODE_ENDLOOP;
573 case OPCODE_ENDSUB:
574 return TGSI_OPCODE_ENDSUB;
575 case OPCODE_EX2:
576 return TGSI_OPCODE_EX2;
577 case OPCODE_EXP:
578 return TGSI_OPCODE_EXP;
579 case OPCODE_FLR:
580 return TGSI_OPCODE_FLR;
581 case OPCODE_FRC:
582 return TGSI_OPCODE_FRC;
583 case OPCODE_IF:
584 return TGSI_OPCODE_IF;
585 case OPCODE_TRUNC:
586 return TGSI_OPCODE_TRUNC;
587 case OPCODE_KIL:
588 return TGSI_OPCODE_KIL;
589 case OPCODE_KIL_NV:
590 return TGSI_OPCODE_KILP;
591 case OPCODE_LG2:
592 return TGSI_OPCODE_LG2;
593 case OPCODE_LOG:
594 return TGSI_OPCODE_LOG;
595 case OPCODE_LIT:
596 return TGSI_OPCODE_LIT;
597 case OPCODE_LRP:
598 return TGSI_OPCODE_LRP;
599 case OPCODE_MAD:
600 return TGSI_OPCODE_MAD;
601 case OPCODE_MAX:
602 return TGSI_OPCODE_MAX;
603 case OPCODE_MIN:
604 return TGSI_OPCODE_MIN;
605 case OPCODE_MOV:
606 return TGSI_OPCODE_MOV;
607 case OPCODE_MUL:
608 return TGSI_OPCODE_MUL;
609 case OPCODE_NOP:
610 return TGSI_OPCODE_NOP;
611 case OPCODE_NRM3:
612 return TGSI_OPCODE_NRM;
613 case OPCODE_NRM4:
614 return TGSI_OPCODE_NRM4;
615 case OPCODE_POW:
616 return TGSI_OPCODE_POW;
617 case OPCODE_RCP:
618 return TGSI_OPCODE_RCP;
619 case OPCODE_RET:
620 return TGSI_OPCODE_RET;
621 case OPCODE_RSQ:
622 return TGSI_OPCODE_RSQ;
623 case OPCODE_SCS:
624 return TGSI_OPCODE_SCS;
625 case OPCODE_SEQ:
626 return TGSI_OPCODE_SEQ;
627 case OPCODE_SGE:
628 return TGSI_OPCODE_SGE;
629 case OPCODE_SGT:
630 return TGSI_OPCODE_SGT;
631 case OPCODE_SIN:
632 return TGSI_OPCODE_SIN;
633 case OPCODE_SLE:
634 return TGSI_OPCODE_SLE;
635 case OPCODE_SLT:
636 return TGSI_OPCODE_SLT;
637 case OPCODE_SNE:
638 return TGSI_OPCODE_SNE;
639 case OPCODE_SSG:
640 return TGSI_OPCODE_SSG;
641 case OPCODE_SUB:
642 return TGSI_OPCODE_SUB;
643 case OPCODE_TEX:
644 return TGSI_OPCODE_TEX;
645 case OPCODE_TXB:
646 return TGSI_OPCODE_TXB;
647 case OPCODE_TXD:
648 return TGSI_OPCODE_TXD;
649 case OPCODE_TXL:
650 return TGSI_OPCODE_TXL;
651 case OPCODE_TXP:
652 return TGSI_OPCODE_TXP;
653 case OPCODE_XPD:
654 return TGSI_OPCODE_XPD;
655 case OPCODE_END:
656 return TGSI_OPCODE_END;
657 default:
658 debug_assert( 0 );
659 return TGSI_OPCODE_NOP;
660 }
661 }
662
663
664 static void
665 compile_instruction(
666 struct st_translate *t,
667 const struct prog_instruction *inst,
668 boolean clamp_dst_color_output)
669 {
670 struct ureg_program *ureg = t->ureg;
671 GLuint i;
672 struct ureg_dst dst[1] = { { 0 } };
673 struct ureg_src src[4];
674 unsigned num_dst;
675 unsigned num_src;
676
677 num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
678 num_src = _mesa_num_inst_src_regs( inst->Opcode );
679
680 if (num_dst)
681 dst[0] = translate_dst( t,
682 &inst->DstReg,
683 inst->SaturateMode,
684 clamp_dst_color_output);
685
686 for (i = 0; i < num_src; i++)
687 src[i] = translate_src( t, &inst->SrcReg[i] );
688
689 switch( inst->Opcode ) {
690 case OPCODE_SWZ:
691 emit_swz( t, dst[0], &inst->SrcReg[0] );
692 return;
693
694 case OPCODE_BGNLOOP:
695 case OPCODE_CAL:
696 case OPCODE_ELSE:
697 case OPCODE_ENDLOOP:
698 case OPCODE_IF:
699 debug_assert(num_dst == 0);
700 ureg_label_insn( ureg,
701 translate_opcode( inst->Opcode ),
702 src, num_src,
703 get_label( t, inst->BranchTarget ));
704 return;
705
706 case OPCODE_TEX:
707 case OPCODE_TXB:
708 case OPCODE_TXD:
709 case OPCODE_TXL:
710 case OPCODE_TXP:
711 src[num_src++] = t->samplers[inst->TexSrcUnit];
712 ureg_tex_insn( ureg,
713 translate_opcode( inst->Opcode ),
714 dst, num_dst,
715 st_translate_texture_target( inst->TexSrcTarget,
716 inst->TexShadow ),
717 NULL, 0,
718 src, num_src );
719 return;
720
721 case OPCODE_SCS:
722 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
723 ureg_insn( ureg,
724 translate_opcode( inst->Opcode ),
725 dst, num_dst,
726 src, num_src );
727 break;
728
729 case OPCODE_XPD:
730 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
731 ureg_insn( ureg,
732 translate_opcode( inst->Opcode ),
733 dst, num_dst,
734 src, num_src );
735 break;
736
737 case OPCODE_NOISE1:
738 case OPCODE_NOISE2:
739 case OPCODE_NOISE3:
740 case OPCODE_NOISE4:
741 /* At some point, a motivated person could add a better
742 * implementation of noise. Currently not even the nvidia
743 * binary drivers do anything more than this. In any case, the
744 * place to do this is in the GL state tracker, not the poor
745 * driver.
746 */
747 ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
748 break;
749
750 case OPCODE_DDY:
751 emit_ddy( t, dst[0], &inst->SrcReg[0] );
752 break;
753
754 default:
755 ureg_insn( ureg,
756 translate_opcode( inst->Opcode ),
757 dst, num_dst,
758 src, num_src );
759 break;
760 }
761 }
762
763
764 /**
765 * Emit the TGSI instructions for inverting and adjusting WPOS.
766 * This code is unavoidable because it also depends on whether
767 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
768 */
769 static void
770 emit_wpos_adjustment( struct st_translate *t,
771 const struct gl_program *program,
772 boolean invert,
773 GLfloat adjX, GLfloat adjY[2])
774 {
775 struct ureg_program *ureg = t->ureg;
776
777 /* Fragment program uses fragment position input.
778 * Need to replace instances of INPUT[WPOS] with temp T
779 * where T = INPUT[WPOS] by y is inverted.
780 */
781 static const gl_state_index wposTransformState[STATE_LENGTH]
782 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
783
784 /* XXX: note we are modifying the incoming shader here! Need to
785 * do this before emitting the constant decls below, or this
786 * will be missed:
787 */
788 unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
789 wposTransformState);
790
791 struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
792 struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
793 struct ureg_src wpos_input = t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]];
794
795 /* First, apply the coordinate shift: */
796 if (adjX || adjY[0] || adjY[1]) {
797 if (adjY[0] != adjY[1]) {
798 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
799 * depending on whether inversion is actually going to be applied
800 * or not, which is determined by testing against the inversion
801 * state variable used below, which will be either +1 or -1.
802 */
803 struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
804
805 ureg_CMP(ureg, adj_temp,
806 ureg_scalar(wpostrans, invert ? 2 : 0),
807 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
808 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
809 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
810 } else {
811 ureg_ADD(ureg, wpos_temp, wpos_input,
812 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
813 }
814 wpos_input = ureg_src(wpos_temp);
815 } else {
816 /* MOV wpos_temp, input[wpos]
817 */
818 ureg_MOV( ureg, wpos_temp, wpos_input );
819 }
820
821 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
822 * inversion/identity, or the other way around if we're drawing to an FBO.
823 */
824 if (invert) {
825 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
826 */
827 ureg_MAD( ureg,
828 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
829 wpos_input,
830 ureg_scalar(wpostrans, 0),
831 ureg_scalar(wpostrans, 1));
832 } else {
833 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
834 */
835 ureg_MAD( ureg,
836 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
837 wpos_input,
838 ureg_scalar(wpostrans, 2),
839 ureg_scalar(wpostrans, 3));
840 }
841
842 /* Use wpos_temp as position input from here on:
843 */
844 t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]] = ureg_src(wpos_temp);
845 }
846
847
848 /**
849 * Emit fragment position/ooordinate code.
850 */
851 static void
852 emit_wpos(struct st_context *st,
853 struct st_translate *t,
854 const struct gl_program *program,
855 struct ureg_program *ureg)
856 {
857 const struct gl_fragment_program *fp =
858 (const struct gl_fragment_program *) program;
859 struct pipe_screen *pscreen = st->pipe->screen;
860 GLfloat adjX = 0.0f;
861 GLfloat adjY[2] = { 0.0f, 0.0f };
862 boolean invert = FALSE;
863
864 /* Query the pixel center conventions supported by the pipe driver and set
865 * adjX, adjY to help out if it cannot handle the requested one internally.
866 *
867 * The bias of the y-coordinate depends on whether y-inversion takes place
868 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
869 * drawing to an FBO (causes additional inversion), and whether the the pipe
870 * driver origin and the requested origin differ (the latter condition is
871 * stored in the 'invert' variable).
872 *
873 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
874 *
875 * center shift only:
876 * i -> h: +0.5
877 * h -> i: -0.5
878 *
879 * inversion only:
880 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
881 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
882 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
883 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
884 *
885 * inversion and center shift:
886 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
887 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
888 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
889 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
890 */
891 if (fp->OriginUpperLeft) {
892 /* Fragment shader wants origin in upper-left */
893 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
894 /* the driver supports upper-left origin */
895 }
896 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
897 /* the driver supports lower-left origin, need to invert Y */
898 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
899 invert = TRUE;
900 }
901 else
902 assert(0);
903 }
904 else {
905 /* Fragment shader wants origin in lower-left */
906 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
907 /* the driver supports lower-left origin */
908 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
909 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
910 /* the driver supports upper-left origin, need to invert Y */
911 invert = TRUE;
912 else
913 assert(0);
914 }
915
916 if (fp->PixelCenterInteger) {
917 /* Fragment shader wants pixel center integer */
918 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
919 /* the driver supports pixel center integer */
920 adjY[1] = 1.0f;
921 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
922 }
923 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
924 /* the driver supports pixel center half integer, need to bias X,Y */
925 adjX = -0.5f;
926 adjY[0] = -0.5f;
927 adjY[1] = 0.5f;
928 }
929 else
930 assert(0);
931 }
932 else {
933 /* Fragment shader wants pixel center half integer */
934 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
935 /* the driver supports pixel center half integer */
936 }
937 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
938 /* the driver supports pixel center integer, need to bias X,Y */
939 adjX = adjY[0] = adjY[1] = 0.5f;
940 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
941 }
942 else
943 assert(0);
944 }
945
946 /* we invert after adjustment so that we avoid the MOV to temporary,
947 * and reuse the adjustment ADD instead */
948 emit_wpos_adjustment(t, program, invert, adjX, adjY);
949 }
950
951
952 /**
953 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
954 * TGSI uses +1 for front, -1 for back.
955 * This function converts the TGSI value to the GL value. Simply clamping/
956 * saturating the value to [0,1] does the job.
957 */
958 static void
959 emit_face_var( struct st_translate *t,
960 const struct gl_program *program )
961 {
962 struct ureg_program *ureg = t->ureg;
963 struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
964 struct ureg_src face_input = t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]];
965
966 /* MOV_SAT face_temp, input[face]
967 */
968 face_temp = ureg_saturate( face_temp );
969 ureg_MOV( ureg, face_temp, face_input );
970
971 /* Use face_temp as face input from here on:
972 */
973 t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]] = ureg_src(face_temp);
974 }
975
976
977 static void
978 emit_edgeflags( struct st_translate *t,
979 const struct gl_program *program )
980 {
981 struct ureg_program *ureg = t->ureg;
982 struct ureg_dst edge_dst = t->outputs[t->outputMapping[VARYING_SLOT_EDGE]];
983 struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
984
985 ureg_MOV( ureg, edge_dst, edge_src );
986 }
987
988
989 /**
990 * Translate Mesa program to TGSI format.
991 * \param program the program to translate
992 * \param numInputs number of input registers used
993 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
994 * input indexes
995 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
996 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
997 * each input
998 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
999 * \param numOutputs number of output registers used
1000 * \param outputMapping maps Mesa fragment program outputs to TGSI
1001 * generic outputs
1002 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
1003 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
1004 * each output
1005 *
1006 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
1007 */
1008 enum pipe_error
1009 st_translate_mesa_program(
1010 struct gl_context *ctx,
1011 uint procType,
1012 struct ureg_program *ureg,
1013 const struct gl_program *program,
1014 GLuint numInputs,
1015 const GLuint inputMapping[],
1016 const ubyte inputSemanticName[],
1017 const ubyte inputSemanticIndex[],
1018 const GLuint interpMode[],
1019 GLuint numOutputs,
1020 const GLuint outputMapping[],
1021 const ubyte outputSemanticName[],
1022 const ubyte outputSemanticIndex[],
1023 boolean passthrough_edgeflags,
1024 boolean clamp_color)
1025 {
1026 struct st_translate translate, *t;
1027 unsigned i;
1028 enum pipe_error ret = PIPE_OK;
1029
1030 assert(numInputs <= Elements(t->inputs));
1031 assert(numOutputs <= Elements(t->outputs));
1032
1033 t = &translate;
1034 memset(t, 0, sizeof *t);
1035
1036 t->procType = procType;
1037 t->inputMapping = inputMapping;
1038 t->outputMapping = outputMapping;
1039 t->ureg = ureg;
1040
1041 /*_mesa_print_program(program);*/
1042
1043 /*
1044 * Declare input attributes.
1045 */
1046 if (procType == TGSI_PROCESSOR_FRAGMENT) {
1047 for (i = 0; i < numInputs; i++) {
1048 t->inputs[i] = ureg_DECL_fs_input(ureg,
1049 inputSemanticName[i],
1050 inputSemanticIndex[i],
1051 interpMode[i]);
1052 }
1053
1054 if (program->InputsRead & FRAG_BIT_WPOS) {
1055 /* Must do this after setting up t->inputs, and before
1056 * emitting constant references, below:
1057 */
1058 emit_wpos(st_context(ctx), t, program, ureg);
1059 }
1060
1061 if (program->InputsRead & FRAG_BIT_FACE) {
1062 emit_face_var( t, program );
1063 }
1064
1065 /*
1066 * Declare output attributes.
1067 */
1068 for (i = 0; i < numOutputs; i++) {
1069 switch (outputSemanticName[i]) {
1070 case TGSI_SEMANTIC_POSITION:
1071 t->outputs[i] = ureg_DECL_output( ureg,
1072 TGSI_SEMANTIC_POSITION, /* Z / Depth */
1073 outputSemanticIndex[i] );
1074
1075 t->outputs[i] = ureg_writemask( t->outputs[i],
1076 TGSI_WRITEMASK_Z );
1077 break;
1078 case TGSI_SEMANTIC_STENCIL:
1079 t->outputs[i] = ureg_DECL_output( ureg,
1080 TGSI_SEMANTIC_STENCIL, /* Stencil */
1081 outputSemanticIndex[i] );
1082 t->outputs[i] = ureg_writemask( t->outputs[i],
1083 TGSI_WRITEMASK_Y );
1084 break;
1085 case TGSI_SEMANTIC_COLOR:
1086 t->outputs[i] = ureg_DECL_output( ureg,
1087 TGSI_SEMANTIC_COLOR,
1088 outputSemanticIndex[i] );
1089 break;
1090 default:
1091 debug_assert(0);
1092 return 0;
1093 }
1094 }
1095 }
1096 else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1097 for (i = 0; i < numInputs; i++) {
1098 t->inputs[i] = ureg_DECL_gs_input(ureg,
1099 i,
1100 inputSemanticName[i],
1101 inputSemanticIndex[i]);
1102 }
1103
1104 for (i = 0; i < numOutputs; i++) {
1105 t->outputs[i] = ureg_DECL_output( ureg,
1106 outputSemanticName[i],
1107 outputSemanticIndex[i] );
1108 }
1109 }
1110 else {
1111 assert(procType == TGSI_PROCESSOR_VERTEX);
1112
1113 for (i = 0; i < numInputs; i++) {
1114 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1115 }
1116
1117 for (i = 0; i < numOutputs; i++) {
1118 t->outputs[i] = ureg_DECL_output( ureg,
1119 outputSemanticName[i],
1120 outputSemanticIndex[i] );
1121 }
1122 if (passthrough_edgeflags)
1123 emit_edgeflags( t, program );
1124 }
1125
1126 /* Declare address register.
1127 */
1128 if (program->NumAddressRegs > 0) {
1129 debug_assert( program->NumAddressRegs == 1 );
1130 t->address[0] = ureg_DECL_address( ureg );
1131 }
1132
1133 /* Declare misc input registers
1134 */
1135 {
1136 GLbitfield sysInputs = program->SystemValuesRead;
1137 unsigned numSys = 0;
1138 for (i = 0; sysInputs; i++) {
1139 if (sysInputs & (1 << i)) {
1140 unsigned semName = mesa_sysval_to_semantic[i];
1141 t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1142 if (semName == TGSI_SEMANTIC_INSTANCEID ||
1143 semName == TGSI_SEMANTIC_VERTEXID) {
1144 /* From Gallium perspective, these system values are always
1145 * integer, and require native integer support. However, if
1146 * native integer is supported on the vertex stage but not the
1147 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1148 * assumes these system values are floats. To resolve the
1149 * inconsistency, we insert a U2F.
1150 */
1151 struct st_context *st = st_context(ctx);
1152 struct pipe_screen *pscreen = st->pipe->screen;
1153 assert(procType == TGSI_PROCESSOR_VERTEX);
1154 assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
1155 (void) pscreen; /* silence non-debug build warnings */
1156 if (!ctx->Const.NativeIntegers) {
1157 struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
1158 ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
1159 t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
1160 }
1161 }
1162 numSys++;
1163 sysInputs &= ~(1 << i);
1164 }
1165 }
1166 }
1167
1168 if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1169 /* If temps are accessed with indirect addressing, declare temporaries
1170 * in sequential order. Else, we declare them on demand elsewhere.
1171 */
1172 for (i = 0; i < program->NumTemporaries; i++) {
1173 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1174 t->temps[i] = ureg_DECL_temporary( t->ureg );
1175 }
1176 }
1177
1178 /* Emit constants and immediates. Mesa uses a single index space
1179 * for these, so we put all the translated regs in t->constants.
1180 */
1181 if (program->Parameters) {
1182 t->constants = calloc( program->Parameters->NumParameters,
1183 sizeof t->constants[0] );
1184 if (t->constants == NULL) {
1185 ret = PIPE_ERROR_OUT_OF_MEMORY;
1186 goto out;
1187 }
1188
1189 for (i = 0; i < program->Parameters->NumParameters; i++) {
1190 switch (program->Parameters->Parameters[i].Type) {
1191 case PROGRAM_ENV_PARAM:
1192 case PROGRAM_LOCAL_PARAM:
1193 case PROGRAM_STATE_VAR:
1194 case PROGRAM_UNIFORM:
1195 t->constants[i] = ureg_DECL_constant( ureg, i );
1196 break;
1197
1198 /* Emit immediates only when there's no indirect addressing of
1199 * the const buffer.
1200 * FIXME: Be smarter and recognize param arrays:
1201 * indirect addressing is only valid within the referenced
1202 * array.
1203 */
1204 case PROGRAM_CONSTANT:
1205 if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1206 t->constants[i] = ureg_DECL_constant( ureg, i );
1207 else
1208 t->constants[i] =
1209 ureg_DECL_immediate( ureg,
1210 (const float*) program->Parameters->ParameterValues[i],
1211 4 );
1212 break;
1213 default:
1214 break;
1215 }
1216 }
1217 }
1218
1219 /* texture samplers */
1220 for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
1221 if (program->SamplersUsed & (1 << i)) {
1222 t->samplers[i] = ureg_DECL_sampler( ureg, i );
1223 }
1224 }
1225
1226 /* Emit each instruction in turn:
1227 */
1228 for (i = 0; i < program->NumInstructions; i++) {
1229 set_insn_start( t, ureg_get_instruction_number( ureg ));
1230 compile_instruction( t, &program->Instructions[i], clamp_color );
1231 }
1232
1233 /* Fix up all emitted labels:
1234 */
1235 for (i = 0; i < t->labels_count; i++) {
1236 ureg_fixup_label( ureg,
1237 t->labels[i].token,
1238 t->insn[t->labels[i].branch_target] );
1239 }
1240
1241 out:
1242 free(t->insn);
1243 free(t->labels);
1244 free(t->constants);
1245
1246 if (t->error) {
1247 debug_printf("%s: translate error flag set\n", __FUNCTION__);
1248 }
1249
1250 return ret;
1251 }
1252
1253
1254 /**
1255 * Tokens cannot be free with free otherwise the builtin gallium
1256 * malloc debugging will get confused.
1257 */
1258 void
1259 st_free_tokens(const struct tgsi_token *tokens)
1260 {
1261 ureg_free_tokens(tokens);
1262 }