src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_screen.h"
  37 #include "pipe/p_shader_tokens.h"
  38 #include "pipe/p_state.h"
  39 #include "tgsi/tgsi_ureg.h"
  40 #include "st_mesa_to_tgsi.h"
  41 #include "st_context.h"
  42 #include "program/prog_instruction.h"
  43 #include "program/prog_parameter.h"
  44 #include "util/u_debug.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
  48
  49
  50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |    \
  51                            (1 << PROGRAM_CONSTANT) |     \
  52                            (1 << PROGRAM_UNIFORM))
  53
  54 /**
  55  * Intermediate state used during shader translation.
  56  */
  57 struct st_translate {
  58    struct ureg_program *ureg;
  59
  60    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  61    struct ureg_src *constants;
  62    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  63    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  64    struct ureg_dst address[1];
  65    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  66    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  67
  68    const ubyte *inputMapping;
  69    const ubyte *outputMapping;
  70
  71    unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
  72 };
  73
  74
  75 /**
  76  * Map a Mesa dst register to a TGSI ureg_dst register.
  77  */
  78 static struct ureg_dst
  79 dst_register( struct st_translate *t,
  80               gl_register_file file,
  81               GLuint index )
  82 {
  83    switch( file ) {
  84    case PROGRAM_UNDEFINED:
  85       return ureg_dst_undef();
  86
  87    case PROGRAM_TEMPORARY:
  88       if (ureg_dst_is_undef(t->temps[index]))
  89          t->temps[index] = ureg_DECL_temporary( t->ureg );
  90
  91       return t->temps[index];
  92
  93    case PROGRAM_OUTPUT:
  94       if (t->procType == PIPE_SHADER_VERTEX)
  95          assert(index < VARYING_SLOT_MAX);
  96       else if (t->procType == PIPE_SHADER_FRAGMENT)
  97          assert(index < FRAG_RESULT_MAX);
  98       else
  99          assert(index < VARYING_SLOT_MAX);
 100
 101       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 102
 103       return t->outputs[t->outputMapping[index]];
 104
 105    case PROGRAM_ADDRESS:
 106       return t->address[index];
 107
 108    default:
 109       debug_assert( 0 );
 110       return ureg_dst_undef();
 111    }
 112 }
 113
 114
 115 /**
 116  * Map a Mesa src register to a TGSI ureg_src register.
 117  */
 118 static struct ureg_src
 119 src_register( struct st_translate *t,
 120               gl_register_file file,
 121               GLint index )
 122 {
 123    switch( file ) {
 124    case PROGRAM_UNDEFINED:
 125       return ureg_src_undef();
 126
 127    case PROGRAM_TEMPORARY:
 128       assert(index >= 0);
 129       assert(index < ARRAY_SIZE(t->temps));
 130       if (ureg_dst_is_undef(t->temps[index]))
 131          t->temps[index] = ureg_DECL_temporary( t->ureg );
 132       return ureg_src(t->temps[index]);
 133
 134    case PROGRAM_UNIFORM:
 135       assert(index >= 0);
 136       return t->constants[index];
 137    case PROGRAM_STATE_VAR:
 138    case PROGRAM_CONSTANT:       /* ie, immediate */
 139       if (index < 0)
 140          return ureg_DECL_constant( t->ureg, 0 );
 141       else
 142          return t->constants[index];
 143
 144    case PROGRAM_INPUT:
 145       assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
 146       return t->inputs[t->inputMapping[index]];
 147
 148    case PROGRAM_OUTPUT:
 149       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 150       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 151
 152    case PROGRAM_ADDRESS:
 153       return ureg_src(t->address[index]);
 154
 155    case PROGRAM_SYSTEM_VALUE:
 156       assert(index < ARRAY_SIZE(t->systemValues));
 157       return t->systemValues[index];
 158
 159    default:
 160       debug_assert( 0 );
 161       return ureg_src_undef();
 162    }
 163 }
 164
 165
 166 /**
 167  * Map mesa texture target to TGSI texture target.
 168  */
 169 unsigned
 170 st_translate_texture_target(GLuint textarget, GLboolean shadow)
 171 {
 172    if (shadow) {
 173       switch (textarget) {
 174       case TEXTURE_1D_INDEX:
 175          return TGSI_TEXTURE_SHADOW1D;
 176       case TEXTURE_2D_INDEX:
 177          return TGSI_TEXTURE_SHADOW2D;
 178       case TEXTURE_RECT_INDEX:
 179          return TGSI_TEXTURE_SHADOWRECT;
 180       case TEXTURE_1D_ARRAY_INDEX:
 181          return TGSI_TEXTURE_SHADOW1D_ARRAY;
 182       case TEXTURE_2D_ARRAY_INDEX:
 183          return TGSI_TEXTURE_SHADOW2D_ARRAY;
 184       case TEXTURE_CUBE_INDEX:
 185          return TGSI_TEXTURE_SHADOWCUBE;
 186       case TEXTURE_CUBE_ARRAY_INDEX:
 187          return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
 188       default:
 189          break;
 190       }
 191    }
 192
 193    switch (textarget) {
 194    case TEXTURE_2D_MULTISAMPLE_INDEX:
 195       return TGSI_TEXTURE_2D_MSAA;
 196    case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX:
 197       return TGSI_TEXTURE_2D_ARRAY_MSAA;
 198    case TEXTURE_BUFFER_INDEX:
 199       return TGSI_TEXTURE_BUFFER;
 200    case TEXTURE_1D_INDEX:
 201       return TGSI_TEXTURE_1D;
 202    case TEXTURE_2D_INDEX:
 203       return TGSI_TEXTURE_2D;
 204    case TEXTURE_3D_INDEX:
 205       return TGSI_TEXTURE_3D;
 206    case TEXTURE_CUBE_INDEX:
 207       return TGSI_TEXTURE_CUBE;
 208    case TEXTURE_CUBE_ARRAY_INDEX:
 209       return TGSI_TEXTURE_CUBE_ARRAY;
 210    case TEXTURE_RECT_INDEX:
 211       return TGSI_TEXTURE_RECT;
 212    case TEXTURE_1D_ARRAY_INDEX:
 213       return TGSI_TEXTURE_1D_ARRAY;
 214    case TEXTURE_2D_ARRAY_INDEX:
 215       return TGSI_TEXTURE_2D_ARRAY;
 216    case TEXTURE_EXTERNAL_INDEX:
 217       return TGSI_TEXTURE_2D;
 218    default:
 219       debug_assert(!"unexpected texture target index");
 220       return TGSI_TEXTURE_1D;
 221    }
 222 }
 223
 224
 225 /**
 226  * Map GLSL base type to TGSI return type.
 227  */
 228 unsigned
 229 st_translate_texture_type(enum glsl_base_type type)
 230 {
 231         switch (type) {
 232         case GLSL_TYPE_INT:
 233                 return TGSI_RETURN_TYPE_SINT;
 234         case GLSL_TYPE_UINT:
 235                 return TGSI_RETURN_TYPE_UINT;
 236         case GLSL_TYPE_FLOAT:
 237                 return TGSI_RETURN_TYPE_FLOAT;
 238         default:
 239                 assert(!"unexpected texture type");
 240                 return TGSI_RETURN_TYPE_UNKNOWN;
 241         }
 242 }
 243
 244
 245 /**
 246  * Translate a (1 << TEXTURE_x_INDEX) bit into a TGSI_TEXTURE_x enum.
 247  */
 248 static unsigned
 249 translate_texture_index(GLbitfield texBit, bool shadow)
 250 {
 251    int index = ffs(texBit);
 252    assert(index > 0);
 253    assert(index - 1 < NUM_TEXTURE_TARGETS);
 254    return st_translate_texture_target(index - 1, shadow);
 255 }
 256
 257
 258 /**
 259  * Create a TGSI ureg_dst register from a Mesa dest register.
 260  */
 261 static struct ureg_dst
 262 translate_dst( struct st_translate *t,
 263                const struct prog_dst_register *DstReg,
 264                boolean saturate)
 265 {
 266    struct ureg_dst dst = dst_register( t,
 267                                        DstReg->File,
 268                                        DstReg->Index );
 269
 270    dst = ureg_writemask( dst,
 271                          DstReg->WriteMask );
 272
 273    if (saturate)
 274       dst = ureg_saturate( dst );
 275
 276    if (DstReg->RelAddr)
 277       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 278
 279    return dst;
 280 }
 281
 282
 283 /**
 284  * Create a TGSI ureg_src register from a Mesa src register.
 285  */
 286 static struct ureg_src
 287 translate_src( struct st_translate *t,
 288                const struct prog_src_register *SrcReg )
 289 {
 290    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 291
 292    src = ureg_swizzle( src,
 293                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
 294                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
 295                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
 296                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 297
 298    if (SrcReg->Negate == NEGATE_XYZW)
 299       src = ureg_negate(src);
 300
 301    if (SrcReg->RelAddr) {
 302       src = ureg_src_indirect( src, ureg_src(t->address[0]));
 303       if (SrcReg->File != PROGRAM_INPUT &&
 304           SrcReg->File != PROGRAM_OUTPUT) {
 305          /* If SrcReg->Index was negative, it was set to zero in
 306           * src_register().  Reassign it now.  But don't do this
 307           * for input/output regs since they get remapped while
 308           * const buffers don't.
 309           */
 310          src.Index = SrcReg->Index;
 311       }
 312    }
 313
 314    return src;
 315 }
 316
 317
 318 static struct ureg_src swizzle_4v( struct ureg_src src,
 319                                    const unsigned *swz )
 320 {
 321    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
 322 }
 323
 324
 325 /**
 326  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 327  *
 328  *   SWZ dst, src.x-y10
 329  *
 330  * becomes:
 331  *
 332  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 333  */
 334 static void emit_swz( struct st_translate *t,
 335                       struct ureg_dst dst,
 336                       const struct prog_src_register *SrcReg )
 337 {
 338    struct ureg_program *ureg = t->ureg;
 339    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 340
 341    unsigned negate_mask =  SrcReg->Negate;
 342
 343    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 344                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 345                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 346                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 347
 348    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 349                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 350                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 351                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 352
 353    unsigned negative_one_mask = one_mask & negate_mask;
 354    unsigned positive_one_mask = one_mask & ~negate_mask;
 355
 356    struct ureg_src imm;
 357    unsigned i;
 358    unsigned mul_swizzle[4] = {0,0,0,0};
 359    unsigned add_swizzle[4] = {0,0,0,0};
 360    unsigned src_swizzle[4] = {0,0,0,0};
 361    boolean need_add = FALSE;
 362    boolean need_mul = FALSE;
 363
 364    if (dst.WriteMask == 0)
 365       return;
 366
 367    /* Is this just a MOV?
 368     */
 369    if (zero_mask == 0 &&
 370        one_mask == 0 &&
 371        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
 372    {
 373       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
 374       return;
 375    }
 376
 377 #define IMM_ZERO    0
 378 #define IMM_ONE     1
 379 #define IMM_NEG_ONE 2
 380
 381    imm = ureg_imm3f( ureg, 0, 1, -1 );
 382
 383    for (i = 0; i < 4; i++) {
 384       unsigned bit = 1 << i;
 385
 386       if (dst.WriteMask & bit) {
 387          if (positive_one_mask & bit) {
 388             mul_swizzle[i] = IMM_ZERO;
 389             add_swizzle[i] = IMM_ONE;
 390             need_add = TRUE;
 391          }
 392          else if (negative_one_mask & bit) {
 393             mul_swizzle[i] = IMM_ZERO;
 394             add_swizzle[i] = IMM_NEG_ONE;
 395             need_add = TRUE;
 396          }
 397          else if (zero_mask & bit) {
 398             mul_swizzle[i] = IMM_ZERO;
 399             add_swizzle[i] = IMM_ZERO;
 400             need_add = TRUE;
 401          }
 402          else {
 403             add_swizzle[i] = IMM_ZERO;
 404             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 405             need_mul = TRUE;
 406             if (negate_mask & bit) {
 407                mul_swizzle[i] = IMM_NEG_ONE;
 408             }
 409             else {
 410                mul_swizzle[i] = IMM_ONE;
 411             }
 412          }
 413       }
 414    }
 415
 416    if (need_mul && need_add) {
 417       ureg_MAD( ureg,
 418                 dst,
 419                 swizzle_4v( src, src_swizzle ),
 420                 swizzle_4v( imm, mul_swizzle ),
 421                 swizzle_4v( imm, add_swizzle ) );
 422    }
 423    else if (need_mul) {
 424       ureg_MUL( ureg,
 425                 dst,
 426                 swizzle_4v( src, src_swizzle ),
 427                 swizzle_4v( imm, mul_swizzle ) );
 428    }
 429    else if (need_add) {
 430       ureg_MOV( ureg,
 431                 dst,
 432                 swizzle_4v( imm, add_swizzle ) );
 433    }
 434    else {
 435       debug_assert(0);
 436    }
 437
 438 #undef IMM_ZERO
 439 #undef IMM_ONE
 440 #undef IMM_NEG_ONE
 441 }
 442
 443
 444 static unsigned
 445 translate_opcode( unsigned op )
 446 {
 447    switch( op ) {
 448    case OPCODE_ARL:
 449       return TGSI_OPCODE_ARL;
 450    case OPCODE_ADD:
 451       return TGSI_OPCODE_ADD;
 452    case OPCODE_CMP:
 453       return TGSI_OPCODE_CMP;
 454    case OPCODE_COS:
 455       return TGSI_OPCODE_COS;
 456    case OPCODE_DP3:
 457       return TGSI_OPCODE_DP3;
 458    case OPCODE_DP4:
 459       return TGSI_OPCODE_DP4;
 460    case OPCODE_DST:
 461       return TGSI_OPCODE_DST;
 462    case OPCODE_EX2:
 463       return TGSI_OPCODE_EX2;
 464    case OPCODE_EXP:
 465       return TGSI_OPCODE_EXP;
 466    case OPCODE_FLR:
 467       return TGSI_OPCODE_FLR;
 468    case OPCODE_FRC:
 469       return TGSI_OPCODE_FRC;
 470    case OPCODE_KIL:
 471       return TGSI_OPCODE_KILL_IF;
 472    case OPCODE_LG2:
 473       return TGSI_OPCODE_LG2;
 474    case OPCODE_LOG:
 475       return TGSI_OPCODE_LOG;
 476    case OPCODE_LIT:
 477       return TGSI_OPCODE_LIT;
 478    case OPCODE_LRP:
 479       return TGSI_OPCODE_LRP;
 480    case OPCODE_MAD:
 481       return TGSI_OPCODE_MAD;
 482    case OPCODE_MAX:
 483       return TGSI_OPCODE_MAX;
 484    case OPCODE_MIN:
 485       return TGSI_OPCODE_MIN;
 486    case OPCODE_MOV:
 487       return TGSI_OPCODE_MOV;
 488    case OPCODE_MUL:
 489       return TGSI_OPCODE_MUL;
 490    case OPCODE_POW:
 491       return TGSI_OPCODE_POW;
 492    case OPCODE_RCP:
 493       return TGSI_OPCODE_RCP;
 494    case OPCODE_SGE:
 495       return TGSI_OPCODE_SGE;
 496    case OPCODE_SIN:
 497       return TGSI_OPCODE_SIN;
 498    case OPCODE_SLT:
 499       return TGSI_OPCODE_SLT;
 500    case OPCODE_TEX:
 501       return TGSI_OPCODE_TEX;
 502    case OPCODE_TXB:
 503       return TGSI_OPCODE_TXB;
 504    case OPCODE_TXP:
 505       return TGSI_OPCODE_TXP;
 506    case OPCODE_END:
 507       return TGSI_OPCODE_END;
 508    default:
 509       debug_assert( 0 );
 510       return TGSI_OPCODE_NOP;
 511    }
 512 }
 513
 514
 515 static void
 516 compile_instruction(
 517    struct gl_context *ctx,
 518    struct st_translate *t,
 519    const struct prog_instruction *inst)
 520 {
 521    struct ureg_program *ureg = t->ureg;
 522    GLuint i;
 523    struct ureg_dst dst[1] = { { 0 } };
 524    struct ureg_src src[4];
 525    unsigned num_dst;
 526    unsigned num_src;
 527
 528    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
 529    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 530
 531    if (num_dst)
 532       dst[0] = translate_dst( t,
 533                               &inst->DstReg,
 534                               inst->Saturate);
 535
 536    for (i = 0; i < num_src; i++)
 537       src[i] = translate_src( t, &inst->SrcReg[i] );
 538
 539    switch( inst->Opcode ) {
 540    case OPCODE_SWZ:
 541       emit_swz( t, dst[0], &inst->SrcReg[0] );
 542       return;
 543
 544    case OPCODE_TEX:
 545    case OPCODE_TXB:
 546    case OPCODE_TXP:
 547       src[num_src++] = t->samplers[inst->TexSrcUnit];
 548       ureg_tex_insn( ureg,
 549                      translate_opcode( inst->Opcode ),
 550                      dst, num_dst,
 551                      st_translate_texture_target( inst->TexSrcTarget,
 552                                                inst->TexShadow ),
 553                      TGSI_RETURN_TYPE_FLOAT,
 554                      NULL, 0,
 555                      src, num_src );
 556       return;
 557
 558    case OPCODE_SCS:
 559       ureg_COS(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_X),
 560                ureg_scalar(src[0], TGSI_SWIZZLE_X));
 561       ureg_SIN(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_Y),
 562                ureg_scalar(src[0], TGSI_SWIZZLE_X));
 563       break;
 564
 565    case OPCODE_XPD: {
 566       struct ureg_dst tmp = ureg_DECL_temporary(ureg);
 567
 568       ureg_MUL(ureg, ureg_writemask(tmp, TGSI_WRITEMASK_XYZ),
 569                ureg_swizzle(src[0], TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Z,
 570                             TGSI_SWIZZLE_X, 0),
 571                ureg_swizzle(src[1], TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X,
 572                             TGSI_SWIZZLE_Y, 0));
 573       ureg_MAD(ureg, ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ),
 574                ureg_swizzle(src[0], TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X,
 575                             TGSI_SWIZZLE_Y, 0),
 576                ureg_negate(ureg_swizzle(src[1], TGSI_SWIZZLE_Y,
 577                                         TGSI_SWIZZLE_Z, TGSI_SWIZZLE_X, 0)),
 578                ureg_src(tmp));
 579       break;
 580    }
 581
 582    case OPCODE_RSQ:
 583       ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
 584       break;
 585
 586    case OPCODE_ABS:
 587       ureg_MOV(ureg, dst[0], ureg_abs(src[0]));
 588       break;
 589
 590    case OPCODE_SUB:
 591       ureg_ADD(ureg, dst[0], src[0], ureg_negate(src[1]));
 592       break;
 593
 594    case OPCODE_DPH: {
 595       struct ureg_dst temp = ureg_DECL_temporary(ureg);
 596
 597       /* DPH = DP4(src0, src1) where src0.w = 1. */
 598       ureg_MOV(ureg, ureg_writemask(temp, TGSI_WRITEMASK_XYZ), src[0]);
 599       ureg_MOV(ureg, ureg_writemask(temp, TGSI_WRITEMASK_W),
 600                ureg_imm1f(ureg, 1));
 601       ureg_DP4(ureg, dst[0], ureg_src(temp), src[1]);
 602       break;
 603    }
 604
 605    default:
 606       ureg_insn( ureg,
 607                  translate_opcode( inst->Opcode ),
 608                  dst, num_dst,
 609                  src, num_src, 0);
 610       break;
 611    }
 612 }
 613
 614
 615 /**
 616  * Emit the TGSI instructions for inverting and adjusting WPOS.
 617  * This code is unavoidable because it also depends on whether
 618  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
 619  */
 620 static void
 621 emit_wpos_adjustment(struct gl_context *ctx,
 622                      struct st_translate *t,
 623                      const struct gl_program *program,
 624                      boolean invert,
 625                      GLfloat adjX, GLfloat adjY[2])
 626 {
 627    struct ureg_program *ureg = t->ureg;
 628
 629    /* Fragment program uses fragment position input.
 630     * Need to replace instances of INPUT[WPOS] with temp T
 631     * where T = INPUT[WPOS] by y is inverted.
 632     */
 633    static const gl_state_index wposTransformState[STATE_LENGTH]
 634       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
 635
 636    /* XXX: note we are modifying the incoming shader here!  Need to
 637     * do this before emitting the constant decls below, or this
 638     * will be missed:
 639     */
 640    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
 641                                                        wposTransformState);
 642
 643    struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
 644    struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
 645    struct ureg_src *wpos =
 646       ctx->Const.GLSLFragCoordIsSysVal ?
 647          &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
 648          &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
 649    struct ureg_src wpos_input = *wpos;
 650
 651    /* First, apply the coordinate shift: */
 652    if (adjX || adjY[0] || adjY[1]) {
 653       if (adjY[0] != adjY[1]) {
 654          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
 655           * depending on whether inversion is actually going to be applied
 656           * or not, which is determined by testing against the inversion
 657           * state variable used below, which will be either +1 or -1.
 658           */
 659          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
 660
 661          ureg_CMP(ureg, adj_temp,
 662                   ureg_scalar(wpostrans, invert ? 2 : 0),
 663                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
 664                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
 665          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
 666       } else {
 667          ureg_ADD(ureg, wpos_temp, wpos_input,
 668                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
 669       }
 670       wpos_input = ureg_src(wpos_temp);
 671    } else {
 672       /* MOV wpos_temp, input[wpos]
 673        */
 674       ureg_MOV( ureg, wpos_temp, wpos_input );
 675    }
 676
 677    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
 678     * inversion/identity, or the other way around if we're drawing to an FBO.
 679     */
 680    if (invert) {
 681       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
 682        */
 683       ureg_MAD( ureg,
 684                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 685                 wpos_input,
 686                 ureg_scalar(wpostrans, 0),
 687                 ureg_scalar(wpostrans, 1));
 688    } else {
 689       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
 690        */
 691       ureg_MAD( ureg,
 692                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 693                 wpos_input,
 694                 ureg_scalar(wpostrans, 2),
 695                 ureg_scalar(wpostrans, 3));
 696    }
 697
 698    /* Use wpos_temp as position input from here on:
 699     */
 700    *wpos = ureg_src(wpos_temp);
 701 }
 702
 703
 704 /**
 705  * Emit fragment position/coordinate code.
 706  */
 707 static void
 708 emit_wpos(struct st_context *st,
 709           struct st_translate *t,
 710           const struct gl_program *program,
 711           struct ureg_program *ureg)
 712 {
 713    struct pipe_screen *pscreen = st->pipe->screen;
 714    GLfloat adjX = 0.0f;
 715    GLfloat adjY[2] = { 0.0f, 0.0f };
 716    boolean invert = FALSE;
 717
 718    /* Query the pixel center conventions supported by the pipe driver and set
 719     * adjX, adjY to help out if it cannot handle the requested one internally.
 720     *
 721     * The bias of the y-coordinate depends on whether y-inversion takes place
 722     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
 723     * drawing to an FBO (causes additional inversion), and whether the pipe
 724     * driver origin and the requested origin differ (the latter condition is
 725     * stored in the 'invert' variable).
 726     *
 727     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
 728     *
 729     * center shift only:
 730     * i -> h: +0.5
 731     * h -> i: -0.5
 732     *
 733     * inversion only:
 734     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
 735     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
 736     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
 737     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
 738     *
 739     * inversion and center shift:
 740     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
 741     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
 742     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
 743     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
 744     */
 745    if (program->OriginUpperLeft) {
 746       /* Fragment shader wants origin in upper-left */
 747       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 748          /* the driver supports upper-left origin */
 749       }
 750       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 751          /* the driver supports lower-left origin, need to invert Y */
 752          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 753                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 754          invert = TRUE;
 755       }
 756       else
 757          assert(0);
 758    }
 759    else {
 760       /* Fragment shader wants origin in lower-left */
 761       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 762          /* the driver supports lower-left origin */
 763          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 764                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 765       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 766          /* the driver supports upper-left origin, need to invert Y */
 767          invert = TRUE;
 768       else
 769          assert(0);
 770    }
 771
 772    if (program->PixelCenterInteger) {
 773       /* Fragment shader wants pixel center integer */
 774       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 775          /* the driver supports pixel center integer */
 776          adjY[1] = 1.0f;
 777          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 778                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 779       }
 780       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 781          /* the driver supports pixel center half integer, need to bias X,Y */
 782          adjX = -0.5f;
 783          adjY[0] = -0.5f;
 784          adjY[1] = 0.5f;
 785       }
 786       else
 787          assert(0);
 788    }
 789    else {
 790       /* Fragment shader wants pixel center half integer */
 791       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 792          /* the driver supports pixel center half integer */
 793       }
 794       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 795          /* the driver supports pixel center integer, need to bias X,Y */
 796          adjX = adjY[0] = adjY[1] = 0.5f;
 797          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 798                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 799       }
 800       else
 801          assert(0);
 802    }
 803
 804    /* we invert after adjustment so that we avoid the MOV to temporary,
 805     * and reuse the adjustment ADD instead */
 806    emit_wpos_adjustment(st->ctx, t, program, invert, adjX, adjY);
 807 }
 808
 809
 810 /**
 811  * Translate Mesa program to TGSI format.
 812  * \param program  the program to translate
 813  * \param numInputs  number of input registers used
 814  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
 815  *                      input indexes
 816  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
 817  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
 818  *                            each input
 819  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
 820  * \param numOutputs  number of output registers used
 821  * \param outputMapping  maps Mesa fragment program outputs to TGSI
 822  *                       generic outputs
 823  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
 824  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
 825  *                             each output
 826  *
 827  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
 828  */
 829 enum pipe_error
 830 st_translate_mesa_program(
 831    struct gl_context *ctx,
 832    uint procType,
 833    struct ureg_program *ureg,
 834    const struct gl_program *program,
 835    GLuint numInputs,
 836    const ubyte inputMapping[],
 837    const ubyte inputSemanticName[],
 838    const ubyte inputSemanticIndex[],
 839    const ubyte interpMode[],
 840    GLuint numOutputs,
 841    const ubyte outputMapping[],
 842    const ubyte outputSemanticName[],
 843    const ubyte outputSemanticIndex[])
 844 {
 845    struct st_translate translate, *t;
 846    unsigned i;
 847    enum pipe_error ret = PIPE_OK;
 848
 849    assert(numInputs <= ARRAY_SIZE(t->inputs));
 850    assert(numOutputs <= ARRAY_SIZE(t->outputs));
 851
 852    t = &translate;
 853    memset(t, 0, sizeof *t);
 854
 855    t->procType = procType;
 856    t->inputMapping = inputMapping;
 857    t->outputMapping = outputMapping;
 858    t->ureg = ureg;
 859
 860    /*_mesa_print_program(program);*/
 861
 862    /*
 863     * Declare input attributes.
 864     */
 865    if (procType == PIPE_SHADER_FRAGMENT) {
 866       for (i = 0; i < numInputs; i++) {
 867          t->inputs[i] = ureg_DECL_fs_input(ureg,
 868                                            inputSemanticName[i],
 869                                            inputSemanticIndex[i],
 870                                            interpMode[i]);
 871       }
 872
 873       if (program->info.inputs_read & VARYING_BIT_POS) {
 874          /* Must do this after setting up t->inputs, and before
 875           * emitting constant references, below:
 876           */
 877          emit_wpos(st_context(ctx), t, program, ureg);
 878       }
 879
 880       /*
 881        * Declare output attributes.
 882        */
 883       for (i = 0; i < numOutputs; i++) {
 884          switch (outputSemanticName[i]) {
 885          case TGSI_SEMANTIC_POSITION:
 886             t->outputs[i] = ureg_DECL_output( ureg,
 887                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
 888                                               outputSemanticIndex[i] );
 889
 890             t->outputs[i] = ureg_writemask( t->outputs[i],
 891                                             TGSI_WRITEMASK_Z );
 892             break;
 893          case TGSI_SEMANTIC_STENCIL:
 894             t->outputs[i] = ureg_DECL_output( ureg,
 895                                               TGSI_SEMANTIC_STENCIL, /* Stencil */
 896                                               outputSemanticIndex[i] );
 897             t->outputs[i] = ureg_writemask( t->outputs[i],
 898                                             TGSI_WRITEMASK_Y );
 899             break;
 900          case TGSI_SEMANTIC_COLOR:
 901             t->outputs[i] = ureg_DECL_output( ureg,
 902                                               TGSI_SEMANTIC_COLOR,
 903                                               outputSemanticIndex[i] );
 904             break;
 905          default:
 906             debug_assert(0);
 907             return 0;
 908          }
 909       }
 910    }
 911    else if (procType == PIPE_SHADER_GEOMETRY) {
 912       for (i = 0; i < numInputs; i++) {
 913          t->inputs[i] = ureg_DECL_input(ureg,
 914                                         inputSemanticName[i],
 915                                         inputSemanticIndex[i], 0, 1);
 916       }
 917
 918       for (i = 0; i < numOutputs; i++) {
 919          t->outputs[i] = ureg_DECL_output( ureg,
 920                                            outputSemanticName[i],
 921                                            outputSemanticIndex[i] );
 922       }
 923    }
 924    else {
 925       assert(procType == PIPE_SHADER_VERTEX);
 926
 927       for (i = 0; i < numInputs; i++) {
 928          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
 929       }
 930
 931       for (i = 0; i < numOutputs; i++) {
 932          t->outputs[i] = ureg_DECL_output( ureg,
 933                                            outputSemanticName[i],
 934                                            outputSemanticIndex[i] );
 935          if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
 936             /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
 937             ureg_MOV(ureg,
 938                      ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
 939                      ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
 940             t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
 941          }
 942       }
 943    }
 944
 945    /* Declare address register.
 946     */
 947    if (program->arb.NumAddressRegs > 0) {
 948       debug_assert( program->arb.NumAddressRegs == 1 );
 949       t->address[0] = ureg_DECL_address( ureg );
 950    }
 951
 952    /* Declare misc input registers
 953     */
 954    GLbitfield sysInputs = program->info.system_values_read;
 955    for (i = 0; sysInputs; i++) {
 956       if (sysInputs & (1 << i)) {
 957          unsigned semName = _mesa_sysval_to_semantic(i);
 958
 959          t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
 960
 961          if (semName == TGSI_SEMANTIC_INSTANCEID ||
 962              semName == TGSI_SEMANTIC_VERTEXID) {
 963             /* From Gallium perspective, these system values are always
 964              * integer, and require native integer support.  However, if
 965              * native integer is supported on the vertex stage but not the
 966              * pixel stage (e.g, i915g + draw), Mesa will generate IR that
 967              * assumes these system values are floats. To resolve the
 968              * inconsistency, we insert a U2F.
 969              */
 970             struct st_context *st = st_context(ctx);
 971             struct pipe_screen *pscreen = st->pipe->screen;
 972             assert(procType == PIPE_SHADER_VERTEX);
 973             assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
 974                    PIPE_SHADER_CAP_INTEGERS));
 975             (void) pscreen;  /* silence non-debug build warnings */
 976             if (!ctx->Const.NativeIntegers) {
 977                struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
 978                ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
 979                         t->systemValues[i]);
 980                t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
 981             }
 982          }
 983
 984          if (procType == PIPE_SHADER_FRAGMENT &&
 985              semName == TGSI_SEMANTIC_POSITION)
 986             emit_wpos(st_context(ctx), t, program, ureg);
 987
 988           sysInputs &= ~(1 << i);
 989       }
 990    }
 991
 992    if (program->arb.IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
 993       /* If temps are accessed with indirect addressing, declare temporaries
 994        * in sequential order.  Else, we declare them on demand elsewhere.
 995        */
 996       for (i = 0; i < program->arb.NumTemporaries; i++) {
 997          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
 998          t->temps[i] = ureg_DECL_temporary( t->ureg );
 999       }
1000    }
1001
1002    /* Emit constants and immediates.  Mesa uses a single index space
1003     * for these, so we put all the translated regs in t->constants.
1004     */
1005    if (program->Parameters) {
1006       t->constants = calloc( program->Parameters->NumParameters,
1007                              sizeof t->constants[0] );
1008       if (t->constants == NULL) {
1009          ret = PIPE_ERROR_OUT_OF_MEMORY;
1010          goto out;
1011       }
1012
1013       for (i = 0; i < program->Parameters->NumParameters; i++) {
1014          switch (program->Parameters->Parameters[i].Type) {
1015          case PROGRAM_STATE_VAR:
1016          case PROGRAM_UNIFORM:
1017             t->constants[i] = ureg_DECL_constant( ureg, i );
1018             break;
1019
1020             /* Emit immediates only when there's no indirect addressing of
1021              * the const buffer.
1022              * FIXME: Be smarter and recognize param arrays:
1023              * indirect addressing is only valid within the referenced
1024              * array.
1025              */
1026          case PROGRAM_CONSTANT:
1027             if (program->arb.IndirectRegisterFiles & PROGRAM_ANY_CONST)
1028                t->constants[i] = ureg_DECL_constant( ureg, i );
1029             else
1030                t->constants[i] =
1031                   ureg_DECL_immediate( ureg,
1032                                        (const float*) program->Parameters->ParameterValues[i],
1033                                        4 );
1034             break;
1035          default:
1036             break;
1037          }
1038       }
1039    }
1040
1041    /* texture samplers */
1042    for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
1043       if (program->SamplersUsed & (1u << i)) {
1044          unsigned target =
1045             translate_texture_index(program->TexturesUsed[i],
1046                                     !!(program->ShadowSamplers & (1 << i)));
1047          t->samplers[i] = ureg_DECL_sampler( ureg, i );
1048          ureg_DECL_sampler_view(ureg, i, target,
1049                                 TGSI_RETURN_TYPE_FLOAT,
1050                                 TGSI_RETURN_TYPE_FLOAT,
1051                                 TGSI_RETURN_TYPE_FLOAT,
1052                                 TGSI_RETURN_TYPE_FLOAT);
1053
1054       }
1055    }
1056
1057    /* Emit each instruction in turn:
1058     */
1059    for (i = 0; i < program->arb.NumInstructions; i++)
1060       compile_instruction(ctx, t, &program->arb.Instructions[i]);
1061
1062 out:
1063    free(t->constants);
1064    return ret;
1065 }