src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_screen.h"
  37 #include "pipe/p_shader_tokens.h"
  38 #include "pipe/p_state.h"
  39 #include "tgsi/tgsi_ureg.h"
  40 #include "st_mesa_to_tgsi.h"
  41 #include "st_context.h"
  42 #include "program/prog_instruction.h"
  43 #include "program/prog_parameter.h"
  44 #include "util/u_debug.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
  48
  49
  50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |    \
  51                            (1 << PROGRAM_CONSTANT) |     \
  52                            (1 << PROGRAM_UNIFORM))
  53
  54 /**
  55  * Intermediate state used during shader translation.
  56  */
  57 struct st_translate {
  58    struct ureg_program *ureg;
  59
  60    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  61    struct ureg_src *constants;
  62    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  63    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  64    struct ureg_dst address[1];
  65    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  66    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  67
  68    const ubyte *inputMapping;
  69    const ubyte *outputMapping;
  70
  71    unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
  72 };
  73
  74
  75 /**
  76  * Map a Mesa dst register to a TGSI ureg_dst register.
  77  */
  78 static struct ureg_dst
  79 dst_register( struct st_translate *t,
  80               gl_register_file file,
  81               GLuint index )
  82 {
  83    switch( file ) {
  84    case PROGRAM_UNDEFINED:
  85       return ureg_dst_undef();
  86
  87    case PROGRAM_TEMPORARY:
  88       if (ureg_dst_is_undef(t->temps[index]))
  89          t->temps[index] = ureg_DECL_temporary( t->ureg );
  90
  91       return t->temps[index];
  92
  93    case PROGRAM_OUTPUT:
  94       if (t->procType == PIPE_SHADER_VERTEX)
  95          assert(index < VARYING_SLOT_MAX);
  96       else if (t->procType == PIPE_SHADER_FRAGMENT)
  97          assert(index < FRAG_RESULT_MAX);
  98       else
  99          assert(index < VARYING_SLOT_MAX);
 100
 101       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 102
 103       return t->outputs[t->outputMapping[index]];
 104
 105    case PROGRAM_ADDRESS:
 106       return t->address[index];
 107
 108    default:
 109       debug_assert( 0 );
 110       return ureg_dst_undef();
 111    }
 112 }
 113
 114
 115 /**
 116  * Map a Mesa src register to a TGSI ureg_src register.
 117  */
 118 static struct ureg_src
 119 src_register( struct st_translate *t,
 120               gl_register_file file,
 121               GLint index )
 122 {
 123    switch( file ) {
 124    case PROGRAM_UNDEFINED:
 125       return ureg_src_undef();
 126
 127    case PROGRAM_TEMPORARY:
 128       assert(index >= 0);
 129       assert(index < ARRAY_SIZE(t->temps));
 130       if (ureg_dst_is_undef(t->temps[index]))
 131          t->temps[index] = ureg_DECL_temporary( t->ureg );
 132       return ureg_src(t->temps[index]);
 133
 134    case PROGRAM_UNIFORM:
 135       assert(index >= 0);
 136       return t->constants[index];
 137    case PROGRAM_STATE_VAR:
 138    case PROGRAM_CONSTANT:       /* ie, immediate */
 139       if (index < 0)
 140          return ureg_DECL_constant( t->ureg, 0 );
 141       else
 142          return t->constants[index];
 143
 144    case PROGRAM_INPUT:
 145       assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
 146       return t->inputs[t->inputMapping[index]];
 147
 148    case PROGRAM_OUTPUT:
 149       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 150       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 151
 152    case PROGRAM_ADDRESS:
 153       return ureg_src(t->address[index]);
 154
 155    case PROGRAM_SYSTEM_VALUE:
 156       assert(index < ARRAY_SIZE(t->systemValues));
 157       return t->systemValues[index];
 158
 159    default:
 160       debug_assert( 0 );
 161       return ureg_src_undef();
 162    }
 163 }
 164
 165
 166 /**
 167  * Map mesa texture target to TGSI texture target.
 168  */
 169 unsigned
 170 st_translate_texture_target(GLuint textarget, GLboolean shadow)
 171 {
 172    if (shadow) {
 173       switch (textarget) {
 174       case TEXTURE_1D_INDEX:
 175          return TGSI_TEXTURE_SHADOW1D;
 176       case TEXTURE_2D_INDEX:
 177          return TGSI_TEXTURE_SHADOW2D;
 178       case TEXTURE_RECT_INDEX:
 179          return TGSI_TEXTURE_SHADOWRECT;
 180       case TEXTURE_1D_ARRAY_INDEX:
 181          return TGSI_TEXTURE_SHADOW1D_ARRAY;
 182       case TEXTURE_2D_ARRAY_INDEX:
 183          return TGSI_TEXTURE_SHADOW2D_ARRAY;
 184       case TEXTURE_CUBE_INDEX:
 185          return TGSI_TEXTURE_SHADOWCUBE;
 186       case TEXTURE_CUBE_ARRAY_INDEX:
 187          return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
 188       default:
 189          break;
 190       }
 191    }
 192
 193    switch (textarget) {
 194    case TEXTURE_2D_MULTISAMPLE_INDEX:
 195       return TGSI_TEXTURE_2D_MSAA;
 196    case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX:
 197       return TGSI_TEXTURE_2D_ARRAY_MSAA;
 198    case TEXTURE_BUFFER_INDEX:
 199       return TGSI_TEXTURE_BUFFER;
 200    case TEXTURE_1D_INDEX:
 201       return TGSI_TEXTURE_1D;
 202    case TEXTURE_2D_INDEX:
 203       return TGSI_TEXTURE_2D;
 204    case TEXTURE_3D_INDEX:
 205       return TGSI_TEXTURE_3D;
 206    case TEXTURE_CUBE_INDEX:
 207       return TGSI_TEXTURE_CUBE;
 208    case TEXTURE_CUBE_ARRAY_INDEX:
 209       return TGSI_TEXTURE_CUBE_ARRAY;
 210    case TEXTURE_RECT_INDEX:
 211       return TGSI_TEXTURE_RECT;
 212    case TEXTURE_1D_ARRAY_INDEX:
 213       return TGSI_TEXTURE_1D_ARRAY;
 214    case TEXTURE_2D_ARRAY_INDEX:
 215       return TGSI_TEXTURE_2D_ARRAY;
 216    case TEXTURE_EXTERNAL_INDEX:
 217       return TGSI_TEXTURE_2D;
 218    default:
 219       debug_assert(!"unexpected texture target index");
 220       return TGSI_TEXTURE_1D;
 221    }
 222 }
 223
 224
 225 /**
 226  * Map GLSL base type to TGSI return type.
 227  */
 228 unsigned
 229 st_translate_texture_type(enum glsl_base_type type)
 230 {
 231         switch (type) {
 232         case GLSL_TYPE_INT:
 233                 return TGSI_RETURN_TYPE_SINT;
 234         case GLSL_TYPE_UINT:
 235                 return TGSI_RETURN_TYPE_UINT;
 236         case GLSL_TYPE_FLOAT:
 237                 return TGSI_RETURN_TYPE_FLOAT;
 238         default:
 239                 assert(!"unexpected texture type");
 240                 return TGSI_RETURN_TYPE_UNKNOWN;
 241         }
 242 }
 243
 244
 245 /**
 246  * Translate a (1 << TEXTURE_x_INDEX) bit into a TGSI_TEXTURE_x enum.
 247  */
 248 static unsigned
 249 translate_texture_index(GLbitfield texBit, bool shadow)
 250 {
 251    int index = ffs(texBit);
 252    assert(index > 0);
 253    assert(index - 1 < NUM_TEXTURE_TARGETS);
 254    return st_translate_texture_target(index - 1, shadow);
 255 }
 256
 257
 258 /**
 259  * Create a TGSI ureg_dst register from a Mesa dest register.
 260  */
 261 static struct ureg_dst
 262 translate_dst( struct st_translate *t,
 263                const struct prog_dst_register *DstReg,
 264                boolean saturate)
 265 {
 266    struct ureg_dst dst = dst_register( t,
 267                                        DstReg->File,
 268                                        DstReg->Index );
 269
 270    dst = ureg_writemask( dst,
 271                          DstReg->WriteMask );
 272
 273    if (saturate)
 274       dst = ureg_saturate( dst );
 275
 276    if (DstReg->RelAddr)
 277       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 278
 279    return dst;
 280 }
 281
 282
 283 /**
 284  * Create a TGSI ureg_src register from a Mesa src register.
 285  */
 286 static struct ureg_src
 287 translate_src( struct st_translate *t,
 288                const struct prog_src_register *SrcReg )
 289 {
 290    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 291
 292    src = ureg_swizzle( src,
 293                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
 294                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
 295                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
 296                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 297
 298    if (SrcReg->Negate == NEGATE_XYZW)
 299       src = ureg_negate(src);
 300
 301    if (SrcReg->RelAddr) {
 302       src = ureg_src_indirect( src, ureg_src(t->address[0]));
 303       if (SrcReg->File != PROGRAM_INPUT &&
 304           SrcReg->File != PROGRAM_OUTPUT) {
 305          /* If SrcReg->Index was negative, it was set to zero in
 306           * src_register().  Reassign it now.  But don't do this
 307           * for input/output regs since they get remapped while
 308           * const buffers don't.
 309           */
 310          src.Index = SrcReg->Index;
 311       }
 312    }
 313
 314    return src;
 315 }
 316
 317
 318 static struct ureg_src swizzle_4v( struct ureg_src src,
 319                                    const unsigned *swz )
 320 {
 321    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
 322 }
 323
 324
 325 /**
 326  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 327  *
 328  *   SWZ dst, src.x-y10
 329  *
 330  * becomes:
 331  *
 332  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 333  */
 334 static void emit_swz( struct st_translate *t,
 335                       struct ureg_dst dst,
 336                       const struct prog_src_register *SrcReg )
 337 {
 338    struct ureg_program *ureg = t->ureg;
 339    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 340
 341    unsigned negate_mask =  SrcReg->Negate;
 342
 343    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 344                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 345                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 346                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 347
 348    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 349                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 350                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 351                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 352
 353    unsigned negative_one_mask = one_mask & negate_mask;
 354    unsigned positive_one_mask = one_mask & ~negate_mask;
 355
 356    struct ureg_src imm;
 357    unsigned i;
 358    unsigned mul_swizzle[4] = {0,0,0,0};
 359    unsigned add_swizzle[4] = {0,0,0,0};
 360    unsigned src_swizzle[4] = {0,0,0,0};
 361    boolean need_add = FALSE;
 362    boolean need_mul = FALSE;
 363
 364    if (dst.WriteMask == 0)
 365       return;
 366
 367    /* Is this just a MOV?
 368     */
 369    if (zero_mask == 0 &&
 370        one_mask == 0 &&
 371        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
 372    {
 373       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
 374       return;
 375    }
 376
 377 #define IMM_ZERO    0
 378 #define IMM_ONE     1
 379 #define IMM_NEG_ONE 2
 380
 381    imm = ureg_imm3f( ureg, 0, 1, -1 );
 382
 383    for (i = 0; i < 4; i++) {
 384       unsigned bit = 1 << i;
 385
 386       if (dst.WriteMask & bit) {
 387          if (positive_one_mask & bit) {
 388             mul_swizzle[i] = IMM_ZERO;
 389             add_swizzle[i] = IMM_ONE;
 390             need_add = TRUE;
 391          }
 392          else if (negative_one_mask & bit) {
 393             mul_swizzle[i] = IMM_ZERO;
 394             add_swizzle[i] = IMM_NEG_ONE;
 395             need_add = TRUE;
 396          }
 397          else if (zero_mask & bit) {
 398             mul_swizzle[i] = IMM_ZERO;
 399             add_swizzle[i] = IMM_ZERO;
 400             need_add = TRUE;
 401          }
 402          else {
 403             add_swizzle[i] = IMM_ZERO;
 404             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 405             need_mul = TRUE;
 406             if (negate_mask & bit) {
 407                mul_swizzle[i] = IMM_NEG_ONE;
 408             }
 409             else {
 410                mul_swizzle[i] = IMM_ONE;
 411             }
 412          }
 413       }
 414    }
 415
 416    if (need_mul && need_add) {
 417       ureg_MAD( ureg,
 418                 dst,
 419                 swizzle_4v( src, src_swizzle ),
 420                 swizzle_4v( imm, mul_swizzle ),
 421                 swizzle_4v( imm, add_swizzle ) );
 422    }
 423    else if (need_mul) {
 424       ureg_MUL( ureg,
 425                 dst,
 426                 swizzle_4v( src, src_swizzle ),
 427                 swizzle_4v( imm, mul_swizzle ) );
 428    }
 429    else if (need_add) {
 430       ureg_MOV( ureg,
 431                 dst,
 432                 swizzle_4v( imm, add_swizzle ) );
 433    }
 434    else {
 435       debug_assert(0);
 436    }
 437
 438 #undef IMM_ZERO
 439 #undef IMM_ONE
 440 #undef IMM_NEG_ONE
 441 }
 442
 443
 444 static unsigned
 445 translate_opcode( unsigned op )
 446 {
 447    switch( op ) {
 448    case OPCODE_ARL:
 449       return TGSI_OPCODE_ARL;
 450    case OPCODE_ADD:
 451       return TGSI_OPCODE_ADD;
 452    case OPCODE_CMP:
 453       return TGSI_OPCODE_CMP;
 454    case OPCODE_COS:
 455       return TGSI_OPCODE_COS;
 456    case OPCODE_DP3:
 457       return TGSI_OPCODE_DP3;
 458    case OPCODE_DP4:
 459       return TGSI_OPCODE_DP4;
 460    case OPCODE_DST:
 461       return TGSI_OPCODE_DST;
 462    case OPCODE_EX2:
 463       return TGSI_OPCODE_EX2;
 464    case OPCODE_EXP:
 465       return TGSI_OPCODE_EXP;
 466    case OPCODE_FLR:
 467       return TGSI_OPCODE_FLR;
 468    case OPCODE_FRC:
 469       return TGSI_OPCODE_FRC;
 470    case OPCODE_KIL:
 471       return TGSI_OPCODE_KILL_IF;
 472    case OPCODE_LG2:
 473       return TGSI_OPCODE_LG2;
 474    case OPCODE_LOG:
 475       return TGSI_OPCODE_LOG;
 476    case OPCODE_LIT:
 477       return TGSI_OPCODE_LIT;
 478    case OPCODE_LRP:
 479       return TGSI_OPCODE_LRP;
 480    case OPCODE_MAD:
 481       return TGSI_OPCODE_MAD;
 482    case OPCODE_MAX:
 483       return TGSI_OPCODE_MAX;
 484    case OPCODE_MIN:
 485       return TGSI_OPCODE_MIN;
 486    case OPCODE_MOV:
 487       return TGSI_OPCODE_MOV;
 488    case OPCODE_MUL:
 489       return TGSI_OPCODE_MUL;
 490    case OPCODE_POW:
 491       return TGSI_OPCODE_POW;
 492    case OPCODE_RCP:
 493       return TGSI_OPCODE_RCP;
 494    case OPCODE_SCS:
 495       return TGSI_OPCODE_SCS;
 496    case OPCODE_SGE:
 497       return TGSI_OPCODE_SGE;
 498    case OPCODE_SIN:
 499       return TGSI_OPCODE_SIN;
 500    case OPCODE_SLT:
 501       return TGSI_OPCODE_SLT;
 502    case OPCODE_TEX:
 503       return TGSI_OPCODE_TEX;
 504    case OPCODE_TXB:
 505       return TGSI_OPCODE_TXB;
 506    case OPCODE_TXP:
 507       return TGSI_OPCODE_TXP;
 508    case OPCODE_XPD:
 509       return TGSI_OPCODE_XPD;
 510    case OPCODE_END:
 511       return TGSI_OPCODE_END;
 512    default:
 513       debug_assert( 0 );
 514       return TGSI_OPCODE_NOP;
 515    }
 516 }
 517
 518
 519 static void
 520 compile_instruction(
 521    struct gl_context *ctx,
 522    struct st_translate *t,
 523    const struct prog_instruction *inst)
 524 {
 525    struct ureg_program *ureg = t->ureg;
 526    GLuint i;
 527    struct ureg_dst dst[1] = { { 0 } };
 528    struct ureg_src src[4];
 529    unsigned num_dst;
 530    unsigned num_src;
 531
 532    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
 533    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 534
 535    if (num_dst)
 536       dst[0] = translate_dst( t,
 537                               &inst->DstReg,
 538                               inst->Saturate);
 539
 540    for (i = 0; i < num_src; i++)
 541       src[i] = translate_src( t, &inst->SrcReg[i] );
 542
 543    switch( inst->Opcode ) {
 544    case OPCODE_SWZ:
 545       emit_swz( t, dst[0], &inst->SrcReg[0] );
 546       return;
 547
 548    case OPCODE_TEX:
 549    case OPCODE_TXB:
 550    case OPCODE_TXP:
 551       src[num_src++] = t->samplers[inst->TexSrcUnit];
 552       ureg_tex_insn( ureg,
 553                      translate_opcode( inst->Opcode ),
 554                      dst, num_dst,
 555                      st_translate_texture_target( inst->TexSrcTarget,
 556                                                inst->TexShadow ),
 557                      TGSI_RETURN_TYPE_FLOAT,
 558                      NULL, 0,
 559                      src, num_src );
 560       return;
 561
 562    case OPCODE_SCS:
 563       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
 564       ureg_insn( ureg,
 565                  translate_opcode( inst->Opcode ),
 566                  dst, num_dst,
 567                  src, num_src, 0 );
 568       break;
 569
 570    case OPCODE_XPD:
 571       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
 572       ureg_insn( ureg,
 573                  translate_opcode( inst->Opcode ),
 574                  dst, num_dst,
 575                  src, num_src, 0 );
 576       break;
 577
 578    case OPCODE_RSQ:
 579       ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
 580       break;
 581
 582    case OPCODE_ABS:
 583       ureg_MOV(ureg, dst[0], ureg_abs(src[0]));
 584       break;
 585
 586    case OPCODE_SUB:
 587       ureg_ADD(ureg, dst[0], src[0], ureg_negate(src[1]));
 588       break;
 589
 590    case OPCODE_DPH: {
 591       struct ureg_dst temp = ureg_DECL_temporary(ureg);
 592
 593       /* DPH = DP4(src0, src1) where src0.w = 1. */
 594       ureg_MOV(ureg, ureg_writemask(temp, TGSI_WRITEMASK_XYZ), src[0]);
 595       ureg_MOV(ureg, ureg_writemask(temp, TGSI_WRITEMASK_W),
 596                ureg_imm1f(ureg, 1));
 597       ureg_DP4(ureg, dst[0], ureg_src(temp), src[1]);
 598       break;
 599    }
 600
 601    default:
 602       ureg_insn( ureg,
 603                  translate_opcode( inst->Opcode ),
 604                  dst, num_dst,
 605                  src, num_src, 0);
 606       break;
 607    }
 608 }
 609
 610
 611 /**
 612  * Emit the TGSI instructions for inverting and adjusting WPOS.
 613  * This code is unavoidable because it also depends on whether
 614  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
 615  */
 616 static void
 617 emit_wpos_adjustment(struct gl_context *ctx,
 618                      struct st_translate *t,
 619                      const struct gl_program *program,
 620                      boolean invert,
 621                      GLfloat adjX, GLfloat adjY[2])
 622 {
 623    struct ureg_program *ureg = t->ureg;
 624
 625    /* Fragment program uses fragment position input.
 626     * Need to replace instances of INPUT[WPOS] with temp T
 627     * where T = INPUT[WPOS] by y is inverted.
 628     */
 629    static const gl_state_index wposTransformState[STATE_LENGTH]
 630       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
 631
 632    /* XXX: note we are modifying the incoming shader here!  Need to
 633     * do this before emitting the constant decls below, or this
 634     * will be missed:
 635     */
 636    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
 637                                                        wposTransformState);
 638
 639    struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
 640    struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
 641    struct ureg_src *wpos =
 642       ctx->Const.GLSLFragCoordIsSysVal ?
 643          &t->systemValues[SYSTEM_VALUE_FRAG_COORD] :
 644          &t->inputs[t->inputMapping[VARYING_SLOT_POS]];
 645    struct ureg_src wpos_input = *wpos;
 646
 647    /* First, apply the coordinate shift: */
 648    if (adjX || adjY[0] || adjY[1]) {
 649       if (adjY[0] != adjY[1]) {
 650          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
 651           * depending on whether inversion is actually going to be applied
 652           * or not, which is determined by testing against the inversion
 653           * state variable used below, which will be either +1 or -1.
 654           */
 655          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
 656
 657          ureg_CMP(ureg, adj_temp,
 658                   ureg_scalar(wpostrans, invert ? 2 : 0),
 659                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
 660                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
 661          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
 662       } else {
 663          ureg_ADD(ureg, wpos_temp, wpos_input,
 664                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
 665       }
 666       wpos_input = ureg_src(wpos_temp);
 667    } else {
 668       /* MOV wpos_temp, input[wpos]
 669        */
 670       ureg_MOV( ureg, wpos_temp, wpos_input );
 671    }
 672
 673    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
 674     * inversion/identity, or the other way around if we're drawing to an FBO.
 675     */
 676    if (invert) {
 677       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
 678        */
 679       ureg_MAD( ureg,
 680                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 681                 wpos_input,
 682                 ureg_scalar(wpostrans, 0),
 683                 ureg_scalar(wpostrans, 1));
 684    } else {
 685       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
 686        */
 687       ureg_MAD( ureg,
 688                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 689                 wpos_input,
 690                 ureg_scalar(wpostrans, 2),
 691                 ureg_scalar(wpostrans, 3));
 692    }
 693
 694    /* Use wpos_temp as position input from here on:
 695     */
 696    *wpos = ureg_src(wpos_temp);
 697 }
 698
 699
 700 /**
 701  * Emit fragment position/coordinate code.
 702  */
 703 static void
 704 emit_wpos(struct st_context *st,
 705           struct st_translate *t,
 706           const struct gl_program *program,
 707           struct ureg_program *ureg)
 708 {
 709    struct pipe_screen *pscreen = st->pipe->screen;
 710    GLfloat adjX = 0.0f;
 711    GLfloat adjY[2] = { 0.0f, 0.0f };
 712    boolean invert = FALSE;
 713
 714    /* Query the pixel center conventions supported by the pipe driver and set
 715     * adjX, adjY to help out if it cannot handle the requested one internally.
 716     *
 717     * The bias of the y-coordinate depends on whether y-inversion takes place
 718     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
 719     * drawing to an FBO (causes additional inversion), and whether the pipe
 720     * driver origin and the requested origin differ (the latter condition is
 721     * stored in the 'invert' variable).
 722     *
 723     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
 724     *
 725     * center shift only:
 726     * i -> h: +0.5
 727     * h -> i: -0.5
 728     *
 729     * inversion only:
 730     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
 731     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
 732     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
 733     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
 734     *
 735     * inversion and center shift:
 736     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
 737     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
 738     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
 739     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
 740     */
 741    if (program->OriginUpperLeft) {
 742       /* Fragment shader wants origin in upper-left */
 743       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 744          /* the driver supports upper-left origin */
 745       }
 746       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 747          /* the driver supports lower-left origin, need to invert Y */
 748          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 749                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 750          invert = TRUE;
 751       }
 752       else
 753          assert(0);
 754    }
 755    else {
 756       /* Fragment shader wants origin in lower-left */
 757       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 758          /* the driver supports lower-left origin */
 759          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 760                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 761       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 762          /* the driver supports upper-left origin, need to invert Y */
 763          invert = TRUE;
 764       else
 765          assert(0);
 766    }
 767
 768    if (program->PixelCenterInteger) {
 769       /* Fragment shader wants pixel center integer */
 770       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 771          /* the driver supports pixel center integer */
 772          adjY[1] = 1.0f;
 773          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 774                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 775       }
 776       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 777          /* the driver supports pixel center half integer, need to bias X,Y */
 778          adjX = -0.5f;
 779          adjY[0] = -0.5f;
 780          adjY[1] = 0.5f;
 781       }
 782       else
 783          assert(0);
 784    }
 785    else {
 786       /* Fragment shader wants pixel center half integer */
 787       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 788          /* the driver supports pixel center half integer */
 789       }
 790       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 791          /* the driver supports pixel center integer, need to bias X,Y */
 792          adjX = adjY[0] = adjY[1] = 0.5f;
 793          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 794                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 795       }
 796       else
 797          assert(0);
 798    }
 799
 800    /* we invert after adjustment so that we avoid the MOV to temporary,
 801     * and reuse the adjustment ADD instead */
 802    emit_wpos_adjustment(st->ctx, t, program, invert, adjX, adjY);
 803 }
 804
 805
 806 /**
 807  * Translate Mesa program to TGSI format.
 808  * \param program  the program to translate
 809  * \param numInputs  number of input registers used
 810  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
 811  *                      input indexes
 812  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
 813  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
 814  *                            each input
 815  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
 816  * \param numOutputs  number of output registers used
 817  * \param outputMapping  maps Mesa fragment program outputs to TGSI
 818  *                       generic outputs
 819  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
 820  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
 821  *                             each output
 822  *
 823  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
 824  */
 825 enum pipe_error
 826 st_translate_mesa_program(
 827    struct gl_context *ctx,
 828    uint procType,
 829    struct ureg_program *ureg,
 830    const struct gl_program *program,
 831    GLuint numInputs,
 832    const ubyte inputMapping[],
 833    const ubyte inputSemanticName[],
 834    const ubyte inputSemanticIndex[],
 835    const ubyte interpMode[],
 836    GLuint numOutputs,
 837    const ubyte outputMapping[],
 838    const ubyte outputSemanticName[],
 839    const ubyte outputSemanticIndex[])
 840 {
 841    struct st_translate translate, *t;
 842    unsigned i;
 843    enum pipe_error ret = PIPE_OK;
 844
 845    assert(numInputs <= ARRAY_SIZE(t->inputs));
 846    assert(numOutputs <= ARRAY_SIZE(t->outputs));
 847
 848    t = &translate;
 849    memset(t, 0, sizeof *t);
 850
 851    t->procType = procType;
 852    t->inputMapping = inputMapping;
 853    t->outputMapping = outputMapping;
 854    t->ureg = ureg;
 855
 856    /*_mesa_print_program(program);*/
 857
 858    /*
 859     * Declare input attributes.
 860     */
 861    if (procType == PIPE_SHADER_FRAGMENT) {
 862       for (i = 0; i < numInputs; i++) {
 863          t->inputs[i] = ureg_DECL_fs_input(ureg,
 864                                            inputSemanticName[i],
 865                                            inputSemanticIndex[i],
 866                                            interpMode[i]);
 867       }
 868
 869       if (program->info.inputs_read & VARYING_BIT_POS) {
 870          /* Must do this after setting up t->inputs, and before
 871           * emitting constant references, below:
 872           */
 873          emit_wpos(st_context(ctx), t, program, ureg);
 874       }
 875
 876       /*
 877        * Declare output attributes.
 878        */
 879       for (i = 0; i < numOutputs; i++) {
 880          switch (outputSemanticName[i]) {
 881          case TGSI_SEMANTIC_POSITION:
 882             t->outputs[i] = ureg_DECL_output( ureg,
 883                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
 884                                               outputSemanticIndex[i] );
 885
 886             t->outputs[i] = ureg_writemask( t->outputs[i],
 887                                             TGSI_WRITEMASK_Z );
 888             break;
 889          case TGSI_SEMANTIC_STENCIL:
 890             t->outputs[i] = ureg_DECL_output( ureg,
 891                                               TGSI_SEMANTIC_STENCIL, /* Stencil */
 892                                               outputSemanticIndex[i] );
 893             t->outputs[i] = ureg_writemask( t->outputs[i],
 894                                             TGSI_WRITEMASK_Y );
 895             break;
 896          case TGSI_SEMANTIC_COLOR:
 897             t->outputs[i] = ureg_DECL_output( ureg,
 898                                               TGSI_SEMANTIC_COLOR,
 899                                               outputSemanticIndex[i] );
 900             break;
 901          default:
 902             debug_assert(0);
 903             return 0;
 904          }
 905       }
 906    }
 907    else if (procType == PIPE_SHADER_GEOMETRY) {
 908       for (i = 0; i < numInputs; i++) {
 909          t->inputs[i] = ureg_DECL_input(ureg,
 910                                         inputSemanticName[i],
 911                                         inputSemanticIndex[i], 0, 1);
 912       }
 913
 914       for (i = 0; i < numOutputs; i++) {
 915          t->outputs[i] = ureg_DECL_output( ureg,
 916                                            outputSemanticName[i],
 917                                            outputSemanticIndex[i] );
 918       }
 919    }
 920    else {
 921       assert(procType == PIPE_SHADER_VERTEX);
 922
 923       for (i = 0; i < numInputs; i++) {
 924          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
 925       }
 926
 927       for (i = 0; i < numOutputs; i++) {
 928          t->outputs[i] = ureg_DECL_output( ureg,
 929                                            outputSemanticName[i],
 930                                            outputSemanticIndex[i] );
 931          if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
 932             /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
 933             ureg_MOV(ureg,
 934                      ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
 935                      ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
 936             t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
 937          }
 938       }
 939    }
 940
 941    /* Declare address register.
 942     */
 943    if (program->arb.NumAddressRegs > 0) {
 944       debug_assert( program->arb.NumAddressRegs == 1 );
 945       t->address[0] = ureg_DECL_address( ureg );
 946    }
 947
 948    /* Declare misc input registers
 949     */
 950    GLbitfield sysInputs = program->info.system_values_read;
 951    for (i = 0; sysInputs; i++) {
 952       if (sysInputs & (1 << i)) {
 953          unsigned semName = _mesa_sysval_to_semantic(i);
 954
 955          t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
 956
 957          if (semName == TGSI_SEMANTIC_INSTANCEID ||
 958              semName == TGSI_SEMANTIC_VERTEXID) {
 959             /* From Gallium perspective, these system values are always
 960              * integer, and require native integer support.  However, if
 961              * native integer is supported on the vertex stage but not the
 962              * pixel stage (e.g, i915g + draw), Mesa will generate IR that
 963              * assumes these system values are floats. To resolve the
 964              * inconsistency, we insert a U2F.
 965              */
 966             struct st_context *st = st_context(ctx);
 967             struct pipe_screen *pscreen = st->pipe->screen;
 968             assert(procType == PIPE_SHADER_VERTEX);
 969             assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
 970                    PIPE_SHADER_CAP_INTEGERS));
 971             (void) pscreen;  /* silence non-debug build warnings */
 972             if (!ctx->Const.NativeIntegers) {
 973                struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
 974                ureg_U2F(t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X),
 975                         t->systemValues[i]);
 976                t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
 977             }
 978          }
 979
 980          if (procType == PIPE_SHADER_FRAGMENT &&
 981              semName == TGSI_SEMANTIC_POSITION)
 982             emit_wpos(st_context(ctx), t, program, ureg);
 983
 984           sysInputs &= ~(1 << i);
 985       }
 986    }
 987
 988    if (program->arb.IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
 989       /* If temps are accessed with indirect addressing, declare temporaries
 990        * in sequential order.  Else, we declare them on demand elsewhere.
 991        */
 992       for (i = 0; i < program->arb.NumTemporaries; i++) {
 993          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
 994          t->temps[i] = ureg_DECL_temporary( t->ureg );
 995       }
 996    }
 997
 998    /* Emit constants and immediates.  Mesa uses a single index space
 999     * for these, so we put all the translated regs in t->constants.
1000     */
1001    if (program->Parameters) {
1002       t->constants = calloc( program->Parameters->NumParameters,
1003                              sizeof t->constants[0] );
1004       if (t->constants == NULL) {
1005          ret = PIPE_ERROR_OUT_OF_MEMORY;
1006          goto out;
1007       }
1008
1009       for (i = 0; i < program->Parameters->NumParameters; i++) {
1010          switch (program->Parameters->Parameters[i].Type) {
1011          case PROGRAM_STATE_VAR:
1012          case PROGRAM_UNIFORM:
1013             t->constants[i] = ureg_DECL_constant( ureg, i );
1014             break;
1015
1016             /* Emit immediates only when there's no indirect addressing of
1017              * the const buffer.
1018              * FIXME: Be smarter and recognize param arrays:
1019              * indirect addressing is only valid within the referenced
1020              * array.
1021              */
1022          case PROGRAM_CONSTANT:
1023             if (program->arb.IndirectRegisterFiles & PROGRAM_ANY_CONST)
1024                t->constants[i] = ureg_DECL_constant( ureg, i );
1025             else
1026                t->constants[i] =
1027                   ureg_DECL_immediate( ureg,
1028                                        (const float*) program->Parameters->ParameterValues[i],
1029                                        4 );
1030             break;
1031          default:
1032             break;
1033          }
1034       }
1035    }
1036
1037    /* texture samplers */
1038    for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
1039       if (program->SamplersUsed & (1u << i)) {
1040          unsigned target =
1041             translate_texture_index(program->TexturesUsed[i],
1042                                     !!(program->ShadowSamplers & (1 << i)));
1043          t->samplers[i] = ureg_DECL_sampler( ureg, i );
1044          ureg_DECL_sampler_view(ureg, i, target,
1045                                 TGSI_RETURN_TYPE_FLOAT,
1046                                 TGSI_RETURN_TYPE_FLOAT,
1047                                 TGSI_RETURN_TYPE_FLOAT,
1048                                 TGSI_RETURN_TYPE_FLOAT);
1049
1050       }
1051    }
1052
1053    /* Emit each instruction in turn:
1054     */
1055    for (i = 0; i < program->arb.NumInstructions; i++)
1056       compile_instruction(ctx, t, &program->arb.Instructions[i]);
1057
1058 out:
1059    free(t->constants);
1060    return ret;
1061 }