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st/mesa: rename translate_texture_target, and make translate_opcode static.
[mesa.git] / src / mesa / state_tracker / st_mesa_to_tgsi.c
1 /**************************************************************************
2 *
3 * Copyright 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * \author
30 * Michal Krol,
31 * Keith Whitwell
32 */
33
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47
48
49 #define PROGRAM_ANY_CONST ((1 << PROGRAM_LOCAL_PARAM) | \
50 (1 << PROGRAM_ENV_PARAM) | \
51 (1 << PROGRAM_STATE_VAR) | \
52 (1 << PROGRAM_NAMED_PARAM) | \
53 (1 << PROGRAM_CONSTANT) | \
54 (1 << PROGRAM_UNIFORM))
55
56
57 struct label {
58 unsigned branch_target;
59 unsigned token;
60 };
61
62
63 /**
64 * Intermediate state used during shader translation.
65 */
66 struct st_translate {
67 struct ureg_program *ureg;
68
69 struct ureg_dst temps[MAX_PROGRAM_TEMPS];
70 struct ureg_src *constants;
71 struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
72 struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
73 struct ureg_dst address[1];
74 struct ureg_src samplers[PIPE_MAX_SAMPLERS];
75 struct ureg_src systemValues[SYSTEM_VALUE_MAX];
76
77 /* Extra info for handling point size clamping in vertex shader */
78 struct ureg_dst pointSizeResult; /**< Actual point size output register */
79 struct ureg_src pointSizeConst; /**< Point size range constant register */
80 GLint pointSizeOutIndex; /**< Temp point size output register */
81 GLboolean prevInstWrotePointSize;
82
83 const GLuint *inputMapping;
84 const GLuint *outputMapping;
85
86 /* For every instruction that contains a label (eg CALL), keep
87 * details so that we can go back afterwards and emit the correct
88 * tgsi instruction number for each label.
89 */
90 struct label *labels;
91 unsigned labels_size;
92 unsigned labels_count;
93
94 /* Keep a record of the tgsi instruction number that each mesa
95 * instruction starts at, will be used to fix up labels after
96 * translation.
97 */
98 unsigned *insn;
99 unsigned insn_size;
100 unsigned insn_count;
101
102 unsigned procType; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
103
104 boolean error;
105 };
106
107
108 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
109 static unsigned mesa_sysval_to_semantic[SYSTEM_VALUE_MAX] = {
110 TGSI_SEMANTIC_FACE,
111 TGSI_SEMANTIC_VERTEXID,
112 TGSI_SEMANTIC_INSTANCEID
113 };
114
115
116 /**
117 * Make note of a branch to a label in the TGSI code.
118 * After we've emitted all instructions, we'll go over the list
119 * of labels built here and patch the TGSI code with the actual
120 * location of each label.
121 */
122 static unsigned *get_label( struct st_translate *t,
123 unsigned branch_target )
124 {
125 unsigned i;
126
127 if (t->labels_count + 1 >= t->labels_size) {
128 unsigned old_size = t->labels_size;
129 t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
130 t->labels = REALLOC( t->labels,
131 old_size * sizeof t->labels[0],
132 t->labels_size * sizeof t->labels[0] );
133 if (t->labels == NULL) {
134 static unsigned dummy;
135 t->error = TRUE;
136 return &dummy;
137 }
138 }
139
140 i = t->labels_count++;
141 t->labels[i].branch_target = branch_target;
142 return &t->labels[i].token;
143 }
144
145
146 /**
147 * Called prior to emitting the TGSI code for each Mesa instruction.
148 * Allocate additional space for instructions if needed.
149 * Update the insn[] array so the next Mesa instruction points to
150 * the next TGSI instruction.
151 */
152 static void set_insn_start( struct st_translate *t,
153 unsigned start )
154 {
155 if (t->insn_count + 1 >= t->insn_size) {
156 unsigned old_size = t->insn_size;
157 t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
158 t->insn = REALLOC( t->insn,
159 old_size * sizeof t->insn[0],
160 t->insn_size * sizeof t->insn[0] );
161 if (t->insn == NULL) {
162 t->error = TRUE;
163 return;
164 }
165 }
166
167 t->insn[t->insn_count++] = start;
168 }
169
170
171 /**
172 * Map a Mesa dst register to a TGSI ureg_dst register.
173 */
174 static struct ureg_dst
175 dst_register( struct st_translate *t,
176 gl_register_file file,
177 GLuint index )
178 {
179 switch( file ) {
180 case PROGRAM_UNDEFINED:
181 return ureg_dst_undef();
182
183 case PROGRAM_TEMPORARY:
184 if (ureg_dst_is_undef(t->temps[index]))
185 t->temps[index] = ureg_DECL_temporary( t->ureg );
186
187 return t->temps[index];
188
189 case PROGRAM_OUTPUT:
190 if (t->procType == TGSI_PROCESSOR_VERTEX && index == VERT_RESULT_PSIZ)
191 t->prevInstWrotePointSize = GL_TRUE;
192
193 if (t->procType == TGSI_PROCESSOR_VERTEX)
194 assert(index < VERT_RESULT_MAX);
195 else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
196 assert(index < FRAG_RESULT_MAX);
197 else
198 assert(index < GEOM_RESULT_MAX);
199
200 assert(t->outputMapping[index] < Elements(t->outputs));
201
202 return t->outputs[t->outputMapping[index]];
203
204 case PROGRAM_ADDRESS:
205 return t->address[index];
206
207 default:
208 debug_assert( 0 );
209 return ureg_dst_undef();
210 }
211 }
212
213
214 /**
215 * Map a Mesa src register to a TGSI ureg_src register.
216 */
217 static struct ureg_src
218 src_register( struct st_translate *t,
219 gl_register_file file,
220 GLint index )
221 {
222 switch( file ) {
223 case PROGRAM_UNDEFINED:
224 return ureg_src_undef();
225
226 case PROGRAM_TEMPORARY:
227 assert(index >= 0);
228 assert(index < Elements(t->temps));
229 if (ureg_dst_is_undef(t->temps[index]))
230 t->temps[index] = ureg_DECL_temporary( t->ureg );
231 return ureg_src(t->temps[index]);
232
233 case PROGRAM_NAMED_PARAM:
234 case PROGRAM_ENV_PARAM:
235 case PROGRAM_LOCAL_PARAM:
236 case PROGRAM_UNIFORM:
237 assert(index >= 0);
238 return t->constants[index];
239 case PROGRAM_STATE_VAR:
240 case PROGRAM_CONSTANT: /* ie, immediate */
241 if (index < 0)
242 return ureg_DECL_constant( t->ureg, 0 );
243 else
244 return t->constants[index];
245
246 case PROGRAM_INPUT:
247 assert(t->inputMapping[index] < Elements(t->inputs));
248 return t->inputs[t->inputMapping[index]];
249
250 case PROGRAM_OUTPUT:
251 assert(t->outputMapping[index] < Elements(t->outputs));
252 return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
253
254 case PROGRAM_ADDRESS:
255 return ureg_src(t->address[index]);
256
257 case PROGRAM_SYSTEM_VALUE:
258 assert(index < Elements(t->systemValues));
259 return t->systemValues[index];
260
261 default:
262 debug_assert( 0 );
263 return ureg_src_undef();
264 }
265 }
266
267
268 /**
269 * Map mesa texture target to TGSI texture target.
270 */
271 unsigned
272 st_translate_texture_target( GLuint textarget,
273 GLboolean shadow )
274 {
275 if (shadow) {
276 switch( textarget ) {
277 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_SHADOW1D;
278 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_SHADOW2D;
279 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
280 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
281 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
282 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
283 default: break;
284 }
285 }
286
287 switch( textarget ) {
288 case TEXTURE_1D_INDEX: return TGSI_TEXTURE_1D;
289 case TEXTURE_2D_INDEX: return TGSI_TEXTURE_2D;
290 case TEXTURE_3D_INDEX: return TGSI_TEXTURE_3D;
291 case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
292 case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
293 case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_1D_ARRAY;
294 case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY;
295 case TEXTURE_EXTERNAL_INDEX: return TGSI_TEXTURE_2D;
296 default:
297 debug_assert( 0 );
298 return TGSI_TEXTURE_1D;
299 }
300 }
301
302
303 /**
304 * Create a TGSI ureg_dst register from a Mesa dest register.
305 */
306 static struct ureg_dst
307 translate_dst( struct st_translate *t,
308 const struct prog_dst_register *DstReg,
309 boolean saturate )
310 {
311 struct ureg_dst dst = dst_register( t,
312 DstReg->File,
313 DstReg->Index );
314
315 dst = ureg_writemask( dst,
316 DstReg->WriteMask );
317
318 if (saturate)
319 dst = ureg_saturate( dst );
320
321 if (DstReg->RelAddr)
322 dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
323
324 return dst;
325 }
326
327
328 /**
329 * Create a TGSI ureg_src register from a Mesa src register.
330 */
331 static struct ureg_src
332 translate_src( struct st_translate *t,
333 const struct prog_src_register *SrcReg )
334 {
335 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
336
337 if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
338 src = src_register( t, SrcReg->File, SrcReg->Index2 );
339 if (SrcReg->RelAddr2)
340 src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
341 SrcReg->Index);
342 else
343 src = ureg_src_dimension( src, SrcReg->Index);
344 }
345
346 src = ureg_swizzle( src,
347 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
348 GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
349 GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
350 GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
351
352 if (SrcReg->Negate == NEGATE_XYZW)
353 src = ureg_negate(src);
354
355 if (SrcReg->Abs)
356 src = ureg_abs(src);
357
358 if (SrcReg->RelAddr) {
359 src = ureg_src_indirect( src, ureg_src(t->address[0]));
360 if (SrcReg->File != PROGRAM_INPUT &&
361 SrcReg->File != PROGRAM_OUTPUT) {
362 /* If SrcReg->Index was negative, it was set to zero in
363 * src_register(). Reassign it now. But don't do this
364 * for input/output regs since they get remapped while
365 * const buffers don't.
366 */
367 src.Index = SrcReg->Index;
368 }
369 }
370
371 return src;
372 }
373
374
375 static struct ureg_src swizzle_4v( struct ureg_src src,
376 const unsigned *swz )
377 {
378 return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
379 }
380
381
382 /**
383 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
384 *
385 * SWZ dst, src.x-y10
386 *
387 * becomes:
388 *
389 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
390 */
391 static void emit_swz( struct st_translate *t,
392 struct ureg_dst dst,
393 const struct prog_src_register *SrcReg )
394 {
395 struct ureg_program *ureg = t->ureg;
396 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
397
398 unsigned negate_mask = SrcReg->Negate;
399
400 unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
401 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
402 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
403 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
404
405 unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
406 (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
407 (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
408 (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
409
410 unsigned negative_one_mask = one_mask & negate_mask;
411 unsigned positive_one_mask = one_mask & ~negate_mask;
412
413 struct ureg_src imm;
414 unsigned i;
415 unsigned mul_swizzle[4] = {0,0,0,0};
416 unsigned add_swizzle[4] = {0,0,0,0};
417 unsigned src_swizzle[4] = {0,0,0,0};
418 boolean need_add = FALSE;
419 boolean need_mul = FALSE;
420
421 if (dst.WriteMask == 0)
422 return;
423
424 /* Is this just a MOV?
425 */
426 if (zero_mask == 0 &&
427 one_mask == 0 &&
428 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
429 {
430 ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
431 return;
432 }
433
434 #define IMM_ZERO 0
435 #define IMM_ONE 1
436 #define IMM_NEG_ONE 2
437
438 imm = ureg_imm3f( ureg, 0, 1, -1 );
439
440 for (i = 0; i < 4; i++) {
441 unsigned bit = 1 << i;
442
443 if (dst.WriteMask & bit) {
444 if (positive_one_mask & bit) {
445 mul_swizzle[i] = IMM_ZERO;
446 add_swizzle[i] = IMM_ONE;
447 need_add = TRUE;
448 }
449 else if (negative_one_mask & bit) {
450 mul_swizzle[i] = IMM_ZERO;
451 add_swizzle[i] = IMM_NEG_ONE;
452 need_add = TRUE;
453 }
454 else if (zero_mask & bit) {
455 mul_swizzle[i] = IMM_ZERO;
456 add_swizzle[i] = IMM_ZERO;
457 need_add = TRUE;
458 }
459 else {
460 add_swizzle[i] = IMM_ZERO;
461 src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
462 need_mul = TRUE;
463 if (negate_mask & bit) {
464 mul_swizzle[i] = IMM_NEG_ONE;
465 }
466 else {
467 mul_swizzle[i] = IMM_ONE;
468 }
469 }
470 }
471 }
472
473 if (need_mul && need_add) {
474 ureg_MAD( ureg,
475 dst,
476 swizzle_4v( src, src_swizzle ),
477 swizzle_4v( imm, mul_swizzle ),
478 swizzle_4v( imm, add_swizzle ) );
479 }
480 else if (need_mul) {
481 ureg_MUL( ureg,
482 dst,
483 swizzle_4v( src, src_swizzle ),
484 swizzle_4v( imm, mul_swizzle ) );
485 }
486 else if (need_add) {
487 ureg_MOV( ureg,
488 dst,
489 swizzle_4v( imm, add_swizzle ) );
490 }
491 else {
492 debug_assert(0);
493 }
494
495 #undef IMM_ZERO
496 #undef IMM_ONE
497 #undef IMM_NEG_ONE
498 }
499
500
501 /**
502 * Negate the value of DDY to match GL semantics where (0,0) is the
503 * lower-left corner of the window.
504 * Note that the GL_ARB_fragment_coord_conventions extension will
505 * effect this someday.
506 */
507 static void emit_ddy( struct st_translate *t,
508 struct ureg_dst dst,
509 const struct prog_src_register *SrcReg )
510 {
511 struct ureg_program *ureg = t->ureg;
512 struct ureg_src src = translate_src( t, SrcReg );
513 src = ureg_negate( src );
514 ureg_DDY( ureg, dst, src );
515 }
516
517
518
519 static unsigned
520 translate_opcode( unsigned op )
521 {
522 switch( op ) {
523 case OPCODE_ARL:
524 return TGSI_OPCODE_ARL;
525 case OPCODE_ABS:
526 return TGSI_OPCODE_ABS;
527 case OPCODE_ADD:
528 return TGSI_OPCODE_ADD;
529 case OPCODE_BGNLOOP:
530 return TGSI_OPCODE_BGNLOOP;
531 case OPCODE_BGNSUB:
532 return TGSI_OPCODE_BGNSUB;
533 case OPCODE_BRA:
534 return TGSI_OPCODE_BRA;
535 case OPCODE_BRK:
536 return TGSI_OPCODE_BRK;
537 case OPCODE_CAL:
538 return TGSI_OPCODE_CAL;
539 case OPCODE_CMP:
540 return TGSI_OPCODE_CMP;
541 case OPCODE_CONT:
542 return TGSI_OPCODE_CONT;
543 case OPCODE_COS:
544 return TGSI_OPCODE_COS;
545 case OPCODE_DDX:
546 return TGSI_OPCODE_DDX;
547 case OPCODE_DDY:
548 return TGSI_OPCODE_DDY;
549 case OPCODE_DP2:
550 return TGSI_OPCODE_DP2;
551 case OPCODE_DP2A:
552 return TGSI_OPCODE_DP2A;
553 case OPCODE_DP3:
554 return TGSI_OPCODE_DP3;
555 case OPCODE_DP4:
556 return TGSI_OPCODE_DP4;
557 case OPCODE_DPH:
558 return TGSI_OPCODE_DPH;
559 case OPCODE_DST:
560 return TGSI_OPCODE_DST;
561 case OPCODE_ELSE:
562 return TGSI_OPCODE_ELSE;
563 case OPCODE_EMIT_VERTEX:
564 return TGSI_OPCODE_EMIT;
565 case OPCODE_END_PRIMITIVE:
566 return TGSI_OPCODE_ENDPRIM;
567 case OPCODE_ENDIF:
568 return TGSI_OPCODE_ENDIF;
569 case OPCODE_ENDLOOP:
570 return TGSI_OPCODE_ENDLOOP;
571 case OPCODE_ENDSUB:
572 return TGSI_OPCODE_ENDSUB;
573 case OPCODE_EX2:
574 return TGSI_OPCODE_EX2;
575 case OPCODE_EXP:
576 return TGSI_OPCODE_EXP;
577 case OPCODE_FLR:
578 return TGSI_OPCODE_FLR;
579 case OPCODE_FRC:
580 return TGSI_OPCODE_FRC;
581 case OPCODE_IF:
582 return TGSI_OPCODE_IF;
583 case OPCODE_TRUNC:
584 return TGSI_OPCODE_TRUNC;
585 case OPCODE_KIL:
586 return TGSI_OPCODE_KIL;
587 case OPCODE_KIL_NV:
588 return TGSI_OPCODE_KILP;
589 case OPCODE_LG2:
590 return TGSI_OPCODE_LG2;
591 case OPCODE_LOG:
592 return TGSI_OPCODE_LOG;
593 case OPCODE_LIT:
594 return TGSI_OPCODE_LIT;
595 case OPCODE_LRP:
596 return TGSI_OPCODE_LRP;
597 case OPCODE_MAD:
598 return TGSI_OPCODE_MAD;
599 case OPCODE_MAX:
600 return TGSI_OPCODE_MAX;
601 case OPCODE_MIN:
602 return TGSI_OPCODE_MIN;
603 case OPCODE_MOV:
604 return TGSI_OPCODE_MOV;
605 case OPCODE_MUL:
606 return TGSI_OPCODE_MUL;
607 case OPCODE_NOP:
608 return TGSI_OPCODE_NOP;
609 case OPCODE_NRM3:
610 return TGSI_OPCODE_NRM;
611 case OPCODE_NRM4:
612 return TGSI_OPCODE_NRM4;
613 case OPCODE_POW:
614 return TGSI_OPCODE_POW;
615 case OPCODE_RCP:
616 return TGSI_OPCODE_RCP;
617 case OPCODE_RET:
618 return TGSI_OPCODE_RET;
619 case OPCODE_RSQ:
620 return TGSI_OPCODE_RSQ;
621 case OPCODE_SCS:
622 return TGSI_OPCODE_SCS;
623 case OPCODE_SEQ:
624 return TGSI_OPCODE_SEQ;
625 case OPCODE_SGE:
626 return TGSI_OPCODE_SGE;
627 case OPCODE_SGT:
628 return TGSI_OPCODE_SGT;
629 case OPCODE_SIN:
630 return TGSI_OPCODE_SIN;
631 case OPCODE_SLE:
632 return TGSI_OPCODE_SLE;
633 case OPCODE_SLT:
634 return TGSI_OPCODE_SLT;
635 case OPCODE_SNE:
636 return TGSI_OPCODE_SNE;
637 case OPCODE_SSG:
638 return TGSI_OPCODE_SSG;
639 case OPCODE_SUB:
640 return TGSI_OPCODE_SUB;
641 case OPCODE_TEX:
642 return TGSI_OPCODE_TEX;
643 case OPCODE_TXB:
644 return TGSI_OPCODE_TXB;
645 case OPCODE_TXD:
646 return TGSI_OPCODE_TXD;
647 case OPCODE_TXL:
648 return TGSI_OPCODE_TXL;
649 case OPCODE_TXP:
650 return TGSI_OPCODE_TXP;
651 case OPCODE_XPD:
652 return TGSI_OPCODE_XPD;
653 case OPCODE_END:
654 return TGSI_OPCODE_END;
655 default:
656 debug_assert( 0 );
657 return TGSI_OPCODE_NOP;
658 }
659 }
660
661
662 static void
663 compile_instruction(
664 struct st_translate *t,
665 const struct prog_instruction *inst )
666 {
667 struct ureg_program *ureg = t->ureg;
668 GLuint i;
669 struct ureg_dst dst[1];
670 struct ureg_src src[4];
671 unsigned num_dst;
672 unsigned num_src;
673
674 num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
675 num_src = _mesa_num_inst_src_regs( inst->Opcode );
676
677 if (num_dst)
678 dst[0] = translate_dst( t,
679 &inst->DstReg,
680 inst->SaturateMode );
681
682 for (i = 0; i < num_src; i++)
683 src[i] = translate_src( t, &inst->SrcReg[i] );
684
685 switch( inst->Opcode ) {
686 case OPCODE_SWZ:
687 emit_swz( t, dst[0], &inst->SrcReg[0] );
688 return;
689
690 case OPCODE_BGNLOOP:
691 case OPCODE_CAL:
692 case OPCODE_ELSE:
693 case OPCODE_ENDLOOP:
694 case OPCODE_IF:
695 debug_assert(num_dst == 0);
696 ureg_label_insn( ureg,
697 translate_opcode( inst->Opcode ),
698 src, num_src,
699 get_label( t, inst->BranchTarget ));
700 return;
701
702 case OPCODE_TEX:
703 case OPCODE_TXB:
704 case OPCODE_TXD:
705 case OPCODE_TXL:
706 case OPCODE_TXP:
707 src[num_src++] = t->samplers[inst->TexSrcUnit];
708 ureg_tex_insn( ureg,
709 translate_opcode( inst->Opcode ),
710 dst, num_dst,
711 st_translate_texture_target( inst->TexSrcTarget,
712 inst->TexShadow ),
713 NULL, 0,
714 src, num_src );
715 return;
716
717 case OPCODE_SCS:
718 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
719 ureg_insn( ureg,
720 translate_opcode( inst->Opcode ),
721 dst, num_dst,
722 src, num_src );
723 break;
724
725 case OPCODE_XPD:
726 dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
727 ureg_insn( ureg,
728 translate_opcode( inst->Opcode ),
729 dst, num_dst,
730 src, num_src );
731 break;
732
733 case OPCODE_NOISE1:
734 case OPCODE_NOISE2:
735 case OPCODE_NOISE3:
736 case OPCODE_NOISE4:
737 /* At some point, a motivated person could add a better
738 * implementation of noise. Currently not even the nvidia
739 * binary drivers do anything more than this. In any case, the
740 * place to do this is in the GL state tracker, not the poor
741 * driver.
742 */
743 ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
744 break;
745
746 case OPCODE_DDY:
747 emit_ddy( t, dst[0], &inst->SrcReg[0] );
748 break;
749
750 default:
751 ureg_insn( ureg,
752 translate_opcode( inst->Opcode ),
753 dst, num_dst,
754 src, num_src );
755 break;
756 }
757 }
758
759
760 /**
761 * Emit the TGSI instructions for inverting and adjusting WPOS.
762 * This code is unavoidable because it also depends on whether
763 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
764 */
765 static void
766 emit_wpos_adjustment( struct st_translate *t,
767 const struct gl_program *program,
768 boolean invert,
769 GLfloat adjX, GLfloat adjY[2])
770 {
771 struct ureg_program *ureg = t->ureg;
772
773 /* Fragment program uses fragment position input.
774 * Need to replace instances of INPUT[WPOS] with temp T
775 * where T = INPUT[WPOS] by y is inverted.
776 */
777 static const gl_state_index wposTransformState[STATE_LENGTH]
778 = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
779
780 /* XXX: note we are modifying the incoming shader here! Need to
781 * do this before emitting the constant decls below, or this
782 * will be missed:
783 */
784 unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
785 wposTransformState);
786
787 struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
788 struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
789 struct ureg_src wpos_input = t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]];
790
791 /* First, apply the coordinate shift: */
792 if (adjX || adjY[0] || adjY[1]) {
793 if (adjY[0] != adjY[1]) {
794 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
795 * depending on whether inversion is actually going to be applied
796 * or not, which is determined by testing against the inversion
797 * state variable used below, which will be either +1 or -1.
798 */
799 struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
800
801 ureg_CMP(ureg, adj_temp,
802 ureg_scalar(wpostrans, invert ? 2 : 0),
803 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
804 ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
805 ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
806 } else {
807 ureg_ADD(ureg, wpos_temp, wpos_input,
808 ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
809 }
810 wpos_input = ureg_src(wpos_temp);
811 } else {
812 /* MOV wpos_temp, input[wpos]
813 */
814 ureg_MOV( ureg, wpos_temp, wpos_input );
815 }
816
817 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
818 * inversion/identity, or the other way around if we're drawing to an FBO.
819 */
820 if (invert) {
821 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
822 */
823 ureg_MAD( ureg,
824 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
825 wpos_input,
826 ureg_scalar(wpostrans, 0),
827 ureg_scalar(wpostrans, 1));
828 } else {
829 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
830 */
831 ureg_MAD( ureg,
832 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
833 wpos_input,
834 ureg_scalar(wpostrans, 2),
835 ureg_scalar(wpostrans, 3));
836 }
837
838 /* Use wpos_temp as position input from here on:
839 */
840 t->inputs[t->inputMapping[FRAG_ATTRIB_WPOS]] = ureg_src(wpos_temp);
841 }
842
843
844 /**
845 * Emit fragment position/ooordinate code.
846 */
847 static void
848 emit_wpos(struct st_context *st,
849 struct st_translate *t,
850 const struct gl_program *program,
851 struct ureg_program *ureg)
852 {
853 const struct gl_fragment_program *fp =
854 (const struct gl_fragment_program *) program;
855 struct pipe_screen *pscreen = st->pipe->screen;
856 GLfloat adjX = 0.0f;
857 GLfloat adjY[2] = { 0.0f, 0.0f };
858 boolean invert = FALSE;
859
860 /* Query the pixel center conventions supported by the pipe driver and set
861 * adjX, adjY to help out if it cannot handle the requested one internally.
862 *
863 * The bias of the y-coordinate depends on whether y-inversion takes place
864 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
865 * drawing to an FBO (causes additional inversion), and whether the the pipe
866 * driver origin and the requested origin differ (the latter condition is
867 * stored in the 'invert' variable).
868 *
869 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
870 *
871 * center shift only:
872 * i -> h: +0.5
873 * h -> i: -0.5
874 *
875 * inversion only:
876 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
877 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
878 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
879 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
880 *
881 * inversion and center shift:
882 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
883 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
884 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
885 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
886 */
887 if (fp->OriginUpperLeft) {
888 /* Fragment shader wants origin in upper-left */
889 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
890 /* the driver supports upper-left origin */
891 }
892 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
893 /* the driver supports lower-left origin, need to invert Y */
894 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
895 invert = TRUE;
896 }
897 else
898 assert(0);
899 }
900 else {
901 /* Fragment shader wants origin in lower-left */
902 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
903 /* the driver supports lower-left origin */
904 ureg_property_fs_coord_origin(ureg, TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
905 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
906 /* the driver supports upper-left origin, need to invert Y */
907 invert = TRUE;
908 else
909 assert(0);
910 }
911
912 if (fp->PixelCenterInteger) {
913 /* Fragment shader wants pixel center integer */
914 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
915 /* the driver supports pixel center integer */
916 adjY[1] = 1.0f;
917 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
918 }
919 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
920 /* the driver supports pixel center half integer, need to bias X,Y */
921 adjX = -0.5f;
922 adjY[0] = -0.5f;
923 adjY[1] = 0.5f;
924 }
925 else
926 assert(0);
927 }
928 else {
929 /* Fragment shader wants pixel center half integer */
930 if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
931 /* the driver supports pixel center half integer */
932 }
933 else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
934 /* the driver supports pixel center integer, need to bias X,Y */
935 adjX = adjY[0] = adjY[1] = 0.5f;
936 ureg_property_fs_coord_pixel_center(ureg, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
937 }
938 else
939 assert(0);
940 }
941
942 /* we invert after adjustment so that we avoid the MOV to temporary,
943 * and reuse the adjustment ADD instead */
944 emit_wpos_adjustment(t, program, invert, adjX, adjY);
945 }
946
947
948 /**
949 * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
950 * TGSI uses +1 for front, -1 for back.
951 * This function converts the TGSI value to the GL value. Simply clamping/
952 * saturating the value to [0,1] does the job.
953 */
954 static void
955 emit_face_var( struct st_translate *t,
956 const struct gl_program *program )
957 {
958 struct ureg_program *ureg = t->ureg;
959 struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
960 struct ureg_src face_input = t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]];
961
962 /* MOV_SAT face_temp, input[face]
963 */
964 face_temp = ureg_saturate( face_temp );
965 ureg_MOV( ureg, face_temp, face_input );
966
967 /* Use face_temp as face input from here on:
968 */
969 t->inputs[t->inputMapping[FRAG_ATTRIB_FACE]] = ureg_src(face_temp);
970 }
971
972
973 static void
974 emit_edgeflags( struct st_translate *t,
975 const struct gl_program *program )
976 {
977 struct ureg_program *ureg = t->ureg;
978 struct ureg_dst edge_dst = t->outputs[t->outputMapping[VERT_RESULT_EDGE]];
979 struct ureg_src edge_src = t->inputs[t->inputMapping[VERT_ATTRIB_EDGEFLAG]];
980
981 ureg_MOV( ureg, edge_dst, edge_src );
982 }
983
984
985 /**
986 * Translate Mesa program to TGSI format.
987 * \param program the program to translate
988 * \param numInputs number of input registers used
989 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
990 * input indexes
991 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
992 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
993 * each input
994 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
995 * \param numOutputs number of output registers used
996 * \param outputMapping maps Mesa fragment program outputs to TGSI
997 * generic outputs
998 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
999 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
1000 * each output
1001 *
1002 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
1003 */
1004 enum pipe_error
1005 st_translate_mesa_program(
1006 struct gl_context *ctx,
1007 uint procType,
1008 struct ureg_program *ureg,
1009 const struct gl_program *program,
1010 GLuint numInputs,
1011 const GLuint inputMapping[],
1012 const ubyte inputSemanticName[],
1013 const ubyte inputSemanticIndex[],
1014 const GLuint interpMode[],
1015 GLuint numOutputs,
1016 const GLuint outputMapping[],
1017 const ubyte outputSemanticName[],
1018 const ubyte outputSemanticIndex[],
1019 boolean passthrough_edgeflags )
1020 {
1021 struct st_translate translate, *t;
1022 unsigned i;
1023 enum pipe_error ret = PIPE_OK;
1024
1025 assert(numInputs <= Elements(t->inputs));
1026 assert(numOutputs <= Elements(t->outputs));
1027
1028 t = &translate;
1029 memset(t, 0, sizeof *t);
1030
1031 t->procType = procType;
1032 t->inputMapping = inputMapping;
1033 t->outputMapping = outputMapping;
1034 t->ureg = ureg;
1035 t->pointSizeOutIndex = -1;
1036 t->prevInstWrotePointSize = GL_FALSE;
1037
1038 /*_mesa_print_program(program);*/
1039
1040 /*
1041 * Declare input attributes.
1042 */
1043 if (procType == TGSI_PROCESSOR_FRAGMENT) {
1044 for (i = 0; i < numInputs; i++) {
1045 if (program->InputFlags[0] & PROG_PARAM_BIT_CYL_WRAP) {
1046 t->inputs[i] = ureg_DECL_fs_input_cyl(ureg,
1047 inputSemanticName[i],
1048 inputSemanticIndex[i],
1049 interpMode[i],
1050 TGSI_CYLINDRICAL_WRAP_X);
1051 }
1052 else {
1053 t->inputs[i] = ureg_DECL_fs_input(ureg,
1054 inputSemanticName[i],
1055 inputSemanticIndex[i],
1056 interpMode[i]);
1057 }
1058 }
1059
1060 if (program->InputsRead & FRAG_BIT_WPOS) {
1061 /* Must do this after setting up t->inputs, and before
1062 * emitting constant references, below:
1063 */
1064 emit_wpos(st_context(ctx), t, program, ureg);
1065 }
1066
1067 if (program->InputsRead & FRAG_BIT_FACE) {
1068 emit_face_var( t, program );
1069 }
1070
1071 /*
1072 * Declare output attributes.
1073 */
1074 for (i = 0; i < numOutputs; i++) {
1075 switch (outputSemanticName[i]) {
1076 case TGSI_SEMANTIC_POSITION:
1077 t->outputs[i] = ureg_DECL_output( ureg,
1078 TGSI_SEMANTIC_POSITION, /* Z / Depth */
1079 outputSemanticIndex[i] );
1080
1081 t->outputs[i] = ureg_writemask( t->outputs[i],
1082 TGSI_WRITEMASK_Z );
1083 break;
1084 case TGSI_SEMANTIC_STENCIL:
1085 t->outputs[i] = ureg_DECL_output( ureg,
1086 TGSI_SEMANTIC_STENCIL, /* Stencil */
1087 outputSemanticIndex[i] );
1088 t->outputs[i] = ureg_writemask( t->outputs[i],
1089 TGSI_WRITEMASK_Y );
1090 break;
1091 case TGSI_SEMANTIC_COLOR:
1092 t->outputs[i] = ureg_DECL_output( ureg,
1093 TGSI_SEMANTIC_COLOR,
1094 outputSemanticIndex[i] );
1095 break;
1096 default:
1097 debug_assert(0);
1098 return 0;
1099 }
1100 }
1101 }
1102 else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1103 for (i = 0; i < numInputs; i++) {
1104 t->inputs[i] = ureg_DECL_gs_input(ureg,
1105 i,
1106 inputSemanticName[i],
1107 inputSemanticIndex[i]);
1108 }
1109
1110 for (i = 0; i < numOutputs; i++) {
1111 t->outputs[i] = ureg_DECL_output( ureg,
1112 outputSemanticName[i],
1113 outputSemanticIndex[i] );
1114 }
1115 }
1116 else {
1117 assert(procType == TGSI_PROCESSOR_VERTEX);
1118
1119 for (i = 0; i < numInputs; i++) {
1120 t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1121 }
1122
1123 for (i = 0; i < numOutputs; i++) {
1124 t->outputs[i] = ureg_DECL_output( ureg,
1125 outputSemanticName[i],
1126 outputSemanticIndex[i] );
1127 if ((outputSemanticName[i] == TGSI_SEMANTIC_PSIZE) && program->Id) {
1128 /* Writing to the point size result register requires special
1129 * handling to implement clamping.
1130 */
1131 static const gl_state_index pointSizeClampState[STATE_LENGTH]
1132 = { STATE_INTERNAL, STATE_POINT_SIZE_IMPL_CLAMP, 0, 0, 0 };
1133 /* XXX: note we are modifying the incoming shader here! Need to
1134 * do this before emitting the constant decls below, or this
1135 * will be missed:
1136 */
1137 unsigned pointSizeClampConst =
1138 _mesa_add_state_reference(program->Parameters,
1139 pointSizeClampState);
1140 struct ureg_dst psizregtemp = ureg_DECL_temporary( ureg );
1141 t->pointSizeConst = ureg_DECL_constant( ureg, pointSizeClampConst );
1142 t->pointSizeResult = t->outputs[i];
1143 t->pointSizeOutIndex = i;
1144 t->outputs[i] = psizregtemp;
1145 }
1146 }
1147 if (passthrough_edgeflags)
1148 emit_edgeflags( t, program );
1149 }
1150
1151 /* Declare address register.
1152 */
1153 if (program->NumAddressRegs > 0) {
1154 debug_assert( program->NumAddressRegs == 1 );
1155 t->address[0] = ureg_DECL_address( ureg );
1156 }
1157
1158 /* Declare misc input registers
1159 */
1160 {
1161 GLbitfield sysInputs = program->SystemValuesRead;
1162 unsigned numSys = 0;
1163 for (i = 0; sysInputs; i++) {
1164 if (sysInputs & (1 << i)) {
1165 unsigned semName = mesa_sysval_to_semantic[i];
1166 t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1167 numSys++;
1168 sysInputs &= ~(1 << i);
1169 }
1170 }
1171 }
1172
1173 if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1174 /* If temps are accessed with indirect addressing, declare temporaries
1175 * in sequential order. Else, we declare them on demand elsewhere.
1176 */
1177 for (i = 0; i < program->NumTemporaries; i++) {
1178 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1179 t->temps[i] = ureg_DECL_temporary( t->ureg );
1180 }
1181 }
1182
1183 /* Emit constants and immediates. Mesa uses a single index space
1184 * for these, so we put all the translated regs in t->constants.
1185 */
1186 if (program->Parameters) {
1187 t->constants = CALLOC( program->Parameters->NumParameters,
1188 sizeof t->constants[0] );
1189 if (t->constants == NULL) {
1190 ret = PIPE_ERROR_OUT_OF_MEMORY;
1191 goto out;
1192 }
1193
1194 for (i = 0; i < program->Parameters->NumParameters; i++) {
1195 switch (program->Parameters->Parameters[i].Type) {
1196 case PROGRAM_ENV_PARAM:
1197 case PROGRAM_LOCAL_PARAM:
1198 case PROGRAM_STATE_VAR:
1199 case PROGRAM_NAMED_PARAM:
1200 case PROGRAM_UNIFORM:
1201 t->constants[i] = ureg_DECL_constant( ureg, i );
1202 break;
1203
1204 /* Emit immediates only when there's no indirect addressing of
1205 * the const buffer.
1206 * FIXME: Be smarter and recognize param arrays:
1207 * indirect addressing is only valid within the referenced
1208 * array.
1209 */
1210 case PROGRAM_CONSTANT:
1211 if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1212 t->constants[i] = ureg_DECL_constant( ureg, i );
1213 else
1214 t->constants[i] =
1215 ureg_DECL_immediate( ureg,
1216 (const float*) program->Parameters->ParameterValues[i],
1217 4 );
1218 break;
1219 default:
1220 break;
1221 }
1222 }
1223 }
1224
1225 /* texture samplers */
1226 for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
1227 if (program->SamplersUsed & (1 << i)) {
1228 t->samplers[i] = ureg_DECL_sampler( ureg, i );
1229 }
1230 }
1231
1232 /* Emit each instruction in turn:
1233 */
1234 for (i = 0; i < program->NumInstructions; i++) {
1235 set_insn_start( t, ureg_get_instruction_number( ureg ));
1236 compile_instruction( t, &program->Instructions[i] );
1237
1238 if (t->prevInstWrotePointSize && program->Id) {
1239 /* The previous instruction wrote to the (fake) vertex point size
1240 * result register. Now we need to clamp that value to the min/max
1241 * point size range, putting the result into the real point size
1242 * register.
1243 * Note that we can't do this easily at the end of program due to
1244 * possible early return.
1245 */
1246 set_insn_start( t, ureg_get_instruction_number( ureg ));
1247 ureg_MAX( t->ureg,
1248 ureg_writemask(t->outputs[t->pointSizeOutIndex], WRITEMASK_X),
1249 ureg_src(t->outputs[t->pointSizeOutIndex]),
1250 ureg_swizzle(t->pointSizeConst, 1,1,1,1));
1251 ureg_MIN( t->ureg, ureg_writemask(t->pointSizeResult, WRITEMASK_X),
1252 ureg_src(t->outputs[t->pointSizeOutIndex]),
1253 ureg_swizzle(t->pointSizeConst, 2,2,2,2));
1254 }
1255 t->prevInstWrotePointSize = GL_FALSE;
1256 }
1257
1258 /* Fix up all emitted labels:
1259 */
1260 for (i = 0; i < t->labels_count; i++) {
1261 ureg_fixup_label( ureg,
1262 t->labels[i].token,
1263 t->insn[t->labels[i].branch_target] );
1264 }
1265
1266 out:
1267 FREE(t->insn);
1268 FREE(t->labels);
1269 FREE(t->constants);
1270
1271 if (t->error) {
1272 debug_printf("%s: translate error flag set\n", __FUNCTION__);
1273 }
1274
1275 return ret;
1276 }
1277
1278
1279 /**
1280 * Tokens cannot be free with free otherwise the builtin gallium
1281 * malloc debugging will get confused.
1282 */
1283 void
1284 st_free_tokens(const struct tgsi_token *tokens)
1285 {
1286 FREE((void *)tokens);
1287 }