src/mesa/state_tracker/st_mesa_to_tgsi.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2007-2008 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 /*
  29  * \author
  30  * Michal Krol,
  31  * Keith Whitwell
  32  */
  33
  34 #include "pipe/p_compiler.h"
  35 #include "pipe/p_context.h"
  36 #include "pipe/p_screen.h"
  37 #include "pipe/p_shader_tokens.h"
  38 #include "pipe/p_state.h"
  39 #include "tgsi/tgsi_ureg.h"
  40 #include "st_mesa_to_tgsi.h"
  41 #include "st_context.h"
  42 #include "program/prog_instruction.h"
  43 #include "program/prog_parameter.h"
  44 #include "util/u_debug.h"
  45 #include "util/u_math.h"
  46 #include "util/u_memory.h"
  47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
  48
  49
  50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) |    \
  51                            (1 << PROGRAM_CONSTANT) |     \
  52                            (1 << PROGRAM_UNIFORM))
  53
  54
  55 struct label {
  56    unsigned branch_target;
  57    unsigned token;
  58 };
  59
  60
  61 /**
  62  * Intermediate state used during shader translation.
  63  */
  64 struct st_translate {
  65    struct ureg_program *ureg;
  66
  67    struct ureg_dst temps[MAX_PROGRAM_TEMPS];
  68    struct ureg_src *constants;
  69    struct ureg_dst outputs[PIPE_MAX_SHADER_OUTPUTS];
  70    struct ureg_src inputs[PIPE_MAX_SHADER_INPUTS];
  71    struct ureg_dst address[1];
  72    struct ureg_src samplers[PIPE_MAX_SAMPLERS];
  73    struct ureg_src systemValues[SYSTEM_VALUE_MAX];
  74
  75    const GLuint *inputMapping;
  76    const GLuint *outputMapping;
  77
  78    /* For every instruction that contains a label (eg CALL), keep
  79     * details so that we can go back afterwards and emit the correct
  80     * tgsi instruction number for each label.
  81     */
  82    struct label *labels;
  83    unsigned labels_size;
  84    unsigned labels_count;
  85
  86    /* Keep a record of the tgsi instruction number that each mesa
  87     * instruction starts at, will be used to fix up labels after
  88     * translation.
  89     */
  90    unsigned *insn;
  91    unsigned insn_size;
  92    unsigned insn_count;
  93
  94    unsigned procType;  /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
  95
  96    boolean error;
  97 };
  98
  99
 100 /**
 101  * Make note of a branch to a label in the TGSI code.
 102  * After we've emitted all instructions, we'll go over the list
 103  * of labels built here and patch the TGSI code with the actual
 104  * location of each label.
 105  */
 106 static unsigned *get_label( struct st_translate *t,
 107                             unsigned branch_target )
 108 {
 109    unsigned i;
 110
 111    if (t->labels_count + 1 >= t->labels_size) {
 112       t->labels_size = 1 << (util_logbase2(t->labels_size) + 1);
 113       t->labels = realloc(t->labels, t->labels_size * sizeof t->labels[0]);
 114       if (t->labels == NULL) {
 115          static unsigned dummy;
 116          t->error = TRUE;
 117          return &dummy;
 118       }
 119    }
 120
 121    i = t->labels_count++;
 122    t->labels[i].branch_target = branch_target;
 123    return &t->labels[i].token;
 124 }
 125
 126
 127 /**
 128  * Called prior to emitting the TGSI code for each Mesa instruction.
 129  * Allocate additional space for instructions if needed.
 130  * Update the insn[] array so the next Mesa instruction points to
 131  * the next TGSI instruction.
 132  */
 133 static void set_insn_start( struct st_translate *t,
 134                             unsigned start )
 135 {
 136    if (t->insn_count + 1 >= t->insn_size) {
 137       t->insn_size = 1 << (util_logbase2(t->insn_size) + 1);
 138       t->insn = realloc(t->insn, t->insn_size * sizeof t->insn[0]);
 139       if (t->insn == NULL) {
 140          t->error = TRUE;
 141          return;
 142       }
 143    }
 144
 145    t->insn[t->insn_count++] = start;
 146 }
 147
 148
 149 /**
 150  * Map a Mesa dst register to a TGSI ureg_dst register.
 151  */
 152 static struct ureg_dst
 153 dst_register( struct st_translate *t,
 154               gl_register_file file,
 155               GLuint index )
 156 {
 157    switch( file ) {
 158    case PROGRAM_UNDEFINED:
 159       return ureg_dst_undef();
 160
 161    case PROGRAM_TEMPORARY:
 162       if (ureg_dst_is_undef(t->temps[index]))
 163          t->temps[index] = ureg_DECL_temporary( t->ureg );
 164
 165       return t->temps[index];
 166
 167    case PROGRAM_OUTPUT:
 168       if (t->procType == TGSI_PROCESSOR_VERTEX)
 169          assert(index < VARYING_SLOT_MAX);
 170       else if (t->procType == TGSI_PROCESSOR_FRAGMENT)
 171          assert(index < FRAG_RESULT_MAX);
 172       else
 173          assert(index < VARYING_SLOT_MAX);
 174
 175       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 176
 177       return t->outputs[t->outputMapping[index]];
 178
 179    case PROGRAM_ADDRESS:
 180       return t->address[index];
 181
 182    default:
 183       debug_assert( 0 );
 184       return ureg_dst_undef();
 185    }
 186 }
 187
 188
 189 /**
 190  * Map a Mesa src register to a TGSI ureg_src register.
 191  */
 192 static struct ureg_src
 193 src_register( struct st_translate *t,
 194               gl_register_file file,
 195               GLint index )
 196 {
 197    switch( file ) {
 198    case PROGRAM_UNDEFINED:
 199       return ureg_src_undef();
 200
 201    case PROGRAM_TEMPORARY:
 202       assert(index >= 0);
 203       assert(index < ARRAY_SIZE(t->temps));
 204       if (ureg_dst_is_undef(t->temps[index]))
 205          t->temps[index] = ureg_DECL_temporary( t->ureg );
 206       return ureg_src(t->temps[index]);
 207
 208    case PROGRAM_UNIFORM:
 209       assert(index >= 0);
 210       return t->constants[index];
 211    case PROGRAM_STATE_VAR:
 212    case PROGRAM_CONSTANT:       /* ie, immediate */
 213       if (index < 0)
 214          return ureg_DECL_constant( t->ureg, 0 );
 215       else
 216          return t->constants[index];
 217
 218    case PROGRAM_INPUT:
 219       assert(t->inputMapping[index] < ARRAY_SIZE(t->inputs));
 220       return t->inputs[t->inputMapping[index]];
 221
 222    case PROGRAM_OUTPUT:
 223       assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
 224       return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
 225
 226    case PROGRAM_ADDRESS:
 227       return ureg_src(t->address[index]);
 228
 229    case PROGRAM_SYSTEM_VALUE:
 230       assert(index < ARRAY_SIZE(t->systemValues));
 231       return t->systemValues[index];
 232
 233    default:
 234       debug_assert( 0 );
 235       return ureg_src_undef();
 236    }
 237 }
 238
 239
 240 /**
 241  * Map mesa texture target to TGSI texture target.
 242  */
 243 unsigned
 244 st_translate_texture_target( GLuint textarget,
 245                           GLboolean shadow )
 246 {
 247    if (shadow) {
 248       switch( textarget ) {
 249       case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_SHADOW1D;
 250       case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_SHADOW2D;
 251       case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_SHADOWRECT;
 252       case TEXTURE_1D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW1D_ARRAY;
 253       case TEXTURE_2D_ARRAY_INDEX: return TGSI_TEXTURE_SHADOW2D_ARRAY;
 254       case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_SHADOWCUBE;
 255       case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_SHADOWCUBE_ARRAY;
 256       default: break;
 257       }
 258    }
 259
 260    switch( textarget ) {
 261    case TEXTURE_2D_MULTISAMPLE_INDEX: return TGSI_TEXTURE_2D_MSAA;
 262    case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX: return TGSI_TEXTURE_2D_ARRAY_MSAA;
 263    case TEXTURE_BUFFER_INDEX: return TGSI_TEXTURE_BUFFER;
 264    case TEXTURE_1D_INDEX:   return TGSI_TEXTURE_1D;
 265    case TEXTURE_2D_INDEX:   return TGSI_TEXTURE_2D;
 266    case TEXTURE_3D_INDEX:   return TGSI_TEXTURE_3D;
 267    case TEXTURE_CUBE_INDEX: return TGSI_TEXTURE_CUBE;
 268    case TEXTURE_CUBE_ARRAY_INDEX: return TGSI_TEXTURE_CUBE_ARRAY;
 269    case TEXTURE_RECT_INDEX: return TGSI_TEXTURE_RECT;
 270    case TEXTURE_1D_ARRAY_INDEX:   return TGSI_TEXTURE_1D_ARRAY;
 271    case TEXTURE_2D_ARRAY_INDEX:   return TGSI_TEXTURE_2D_ARRAY;
 272    case TEXTURE_EXTERNAL_INDEX:   return TGSI_TEXTURE_2D;
 273    default:
 274       debug_assert( 0 );
 275       return TGSI_TEXTURE_1D;
 276    }
 277 }
 278
 279
 280 /**
 281  * Create a TGSI ureg_dst register from a Mesa dest register.
 282  */
 283 static struct ureg_dst
 284 translate_dst( struct st_translate *t,
 285                const struct prog_dst_register *DstReg,
 286                boolean saturate)
 287 {
 288    struct ureg_dst dst = dst_register( t,
 289                                        DstReg->File,
 290                                        DstReg->Index );
 291
 292    dst = ureg_writemask( dst,
 293                          DstReg->WriteMask );
 294
 295    if (saturate)
 296       dst = ureg_saturate( dst );
 297
 298    if (DstReg->RelAddr)
 299       dst = ureg_dst_indirect( dst, ureg_src(t->address[0]) );
 300
 301    return dst;
 302 }
 303
 304
 305 /**
 306  * Create a TGSI ureg_src register from a Mesa src register.
 307  */
 308 static struct ureg_src
 309 translate_src( struct st_translate *t,
 310                const struct prog_src_register *SrcReg )
 311 {
 312    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 313
 314    if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
 315       src = src_register( t, SrcReg->File, SrcReg->Index2 );
 316       if (SrcReg->RelAddr2)
 317          src = ureg_src_dimension_indirect( src, ureg_src(t->address[0]),
 318                                             SrcReg->Index);
 319       else
 320          src = ureg_src_dimension( src, SrcReg->Index);
 321    }
 322
 323    src = ureg_swizzle( src,
 324                        GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
 325                        GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
 326                        GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
 327                        GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
 328
 329    if (SrcReg->Negate == NEGATE_XYZW)
 330       src = ureg_negate(src);
 331
 332    if (SrcReg->Abs)
 333       src = ureg_abs(src);
 334
 335    if (SrcReg->RelAddr) {
 336       src = ureg_src_indirect( src, ureg_src(t->address[0]));
 337       if (SrcReg->File != PROGRAM_INPUT &&
 338           SrcReg->File != PROGRAM_OUTPUT) {
 339          /* If SrcReg->Index was negative, it was set to zero in
 340           * src_register().  Reassign it now.  But don't do this
 341           * for input/output regs since they get remapped while
 342           * const buffers don't.
 343           */
 344          src.Index = SrcReg->Index;
 345       }
 346    }
 347
 348    return src;
 349 }
 350
 351
 352 static struct ureg_src swizzle_4v( struct ureg_src src,
 353                                    const unsigned *swz )
 354 {
 355    return ureg_swizzle( src, swz[0], swz[1], swz[2], swz[3] );
 356 }
 357
 358
 359 /**
 360  * Translate a SWZ instruction into a MOV, MUL or MAD instruction.  EG:
 361  *
 362  *   SWZ dst, src.x-y10
 363  *
 364  * becomes:
 365  *
 366  *   MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
 367  */
 368 static void emit_swz( struct st_translate *t,
 369                       struct ureg_dst dst,
 370                       const struct prog_src_register *SrcReg )
 371 {
 372    struct ureg_program *ureg = t->ureg;
 373    struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
 374
 375    unsigned negate_mask =  SrcReg->Negate;
 376
 377    unsigned one_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ONE) << 0 |
 378                         (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ONE) << 1 |
 379                         (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ONE) << 2 |
 380                         (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ONE) << 3);
 381
 382    unsigned zero_mask = ((GET_SWZ(SrcReg->Swizzle, 0) == SWIZZLE_ZERO) << 0 |
 383                          (GET_SWZ(SrcReg->Swizzle, 1) == SWIZZLE_ZERO) << 1 |
 384                          (GET_SWZ(SrcReg->Swizzle, 2) == SWIZZLE_ZERO) << 2 |
 385                          (GET_SWZ(SrcReg->Swizzle, 3) == SWIZZLE_ZERO) << 3);
 386
 387    unsigned negative_one_mask = one_mask & negate_mask;
 388    unsigned positive_one_mask = one_mask & ~negate_mask;
 389
 390    struct ureg_src imm;
 391    unsigned i;
 392    unsigned mul_swizzle[4] = {0,0,0,0};
 393    unsigned add_swizzle[4] = {0,0,0,0};
 394    unsigned src_swizzle[4] = {0,0,0,0};
 395    boolean need_add = FALSE;
 396    boolean need_mul = FALSE;
 397
 398    if (dst.WriteMask == 0)
 399       return;
 400
 401    /* Is this just a MOV?
 402     */
 403    if (zero_mask == 0 &&
 404        one_mask == 0 &&
 405        (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
 406    {
 407       ureg_MOV( ureg, dst, translate_src( t, SrcReg ));
 408       return;
 409    }
 410
 411 #define IMM_ZERO    0
 412 #define IMM_ONE     1
 413 #define IMM_NEG_ONE 2
 414
 415    imm = ureg_imm3f( ureg, 0, 1, -1 );
 416
 417    for (i = 0; i < 4; i++) {
 418       unsigned bit = 1 << i;
 419
 420       if (dst.WriteMask & bit) {
 421          if (positive_one_mask & bit) {
 422             mul_swizzle[i] = IMM_ZERO;
 423             add_swizzle[i] = IMM_ONE;
 424             need_add = TRUE;
 425          }
 426          else if (negative_one_mask & bit) {
 427             mul_swizzle[i] = IMM_ZERO;
 428             add_swizzle[i] = IMM_NEG_ONE;
 429             need_add = TRUE;
 430          }
 431          else if (zero_mask & bit) {
 432             mul_swizzle[i] = IMM_ZERO;
 433             add_swizzle[i] = IMM_ZERO;
 434             need_add = TRUE;
 435          }
 436          else {
 437             add_swizzle[i] = IMM_ZERO;
 438             src_swizzle[i] = GET_SWZ(SrcReg->Swizzle, i);
 439             need_mul = TRUE;
 440             if (negate_mask & bit) {
 441                mul_swizzle[i] = IMM_NEG_ONE;
 442             }
 443             else {
 444                mul_swizzle[i] = IMM_ONE;
 445             }
 446          }
 447       }
 448    }
 449
 450    if (need_mul && need_add) {
 451       ureg_MAD( ureg,
 452                 dst,
 453                 swizzle_4v( src, src_swizzle ),
 454                 swizzle_4v( imm, mul_swizzle ),
 455                 swizzle_4v( imm, add_swizzle ) );
 456    }
 457    else if (need_mul) {
 458       ureg_MUL( ureg,
 459                 dst,
 460                 swizzle_4v( src, src_swizzle ),
 461                 swizzle_4v( imm, mul_swizzle ) );
 462    }
 463    else if (need_add) {
 464       ureg_MOV( ureg,
 465                 dst,
 466                 swizzle_4v( imm, add_swizzle ) );
 467    }
 468    else {
 469       debug_assert(0);
 470    }
 471
 472 #undef IMM_ZERO
 473 #undef IMM_ONE
 474 #undef IMM_NEG_ONE
 475 }
 476
 477
 478 /**
 479  * Negate the value of DDY to match GL semantics where (0,0) is the
 480  * lower-left corner of the window.
 481  * Note that the GL_ARB_fragment_coord_conventions extension will
 482  * effect this someday.
 483  */
 484 static void emit_ddy( struct st_translate *t,
 485                       struct ureg_dst dst,
 486                       const struct prog_src_register *SrcReg )
 487 {
 488    struct ureg_program *ureg = t->ureg;
 489    struct ureg_src src = translate_src( t, SrcReg );
 490    src = ureg_negate( src );
 491    ureg_DDY( ureg, dst, src );
 492 }
 493
 494
 495
 496 static unsigned
 497 translate_opcode( unsigned op )
 498 {
 499    switch( op ) {
 500    case OPCODE_ARL:
 501       return TGSI_OPCODE_ARL;
 502    case OPCODE_ABS:
 503       return TGSI_OPCODE_ABS;
 504    case OPCODE_ADD:
 505       return TGSI_OPCODE_ADD;
 506    case OPCODE_BGNLOOP:
 507       return TGSI_OPCODE_BGNLOOP;
 508    case OPCODE_BGNSUB:
 509       return TGSI_OPCODE_BGNSUB;
 510    case OPCODE_BRK:
 511       return TGSI_OPCODE_BRK;
 512    case OPCODE_CAL:
 513       return TGSI_OPCODE_CAL;
 514    case OPCODE_CMP:
 515       return TGSI_OPCODE_CMP;
 516    case OPCODE_CONT:
 517       return TGSI_OPCODE_CONT;
 518    case OPCODE_COS:
 519       return TGSI_OPCODE_COS;
 520    case OPCODE_DDX:
 521       return TGSI_OPCODE_DDX;
 522    case OPCODE_DDY:
 523       return TGSI_OPCODE_DDY;
 524    case OPCODE_DP2:
 525       return TGSI_OPCODE_DP2;
 526    case OPCODE_DP3:
 527       return TGSI_OPCODE_DP3;
 528    case OPCODE_DP4:
 529       return TGSI_OPCODE_DP4;
 530    case OPCODE_DPH:
 531       return TGSI_OPCODE_DPH;
 532    case OPCODE_DST:
 533       return TGSI_OPCODE_DST;
 534    case OPCODE_ELSE:
 535       return TGSI_OPCODE_ELSE;
 536    case OPCODE_ENDIF:
 537       return TGSI_OPCODE_ENDIF;
 538    case OPCODE_ENDLOOP:
 539       return TGSI_OPCODE_ENDLOOP;
 540    case OPCODE_ENDSUB:
 541       return TGSI_OPCODE_ENDSUB;
 542    case OPCODE_EX2:
 543       return TGSI_OPCODE_EX2;
 544    case OPCODE_EXP:
 545       return TGSI_OPCODE_EXP;
 546    case OPCODE_FLR:
 547       return TGSI_OPCODE_FLR;
 548    case OPCODE_FRC:
 549       return TGSI_OPCODE_FRC;
 550    case OPCODE_IF:
 551       return TGSI_OPCODE_IF;
 552    case OPCODE_TRUNC:
 553       return TGSI_OPCODE_TRUNC;
 554    case OPCODE_KIL:
 555       return TGSI_OPCODE_KILL_IF;
 556    case OPCODE_KIL_NV:
 557       /* XXX we don't support condition codes in TGSI */
 558       return TGSI_OPCODE_KILL;
 559    case OPCODE_LG2:
 560       return TGSI_OPCODE_LG2;
 561    case OPCODE_LOG:
 562       return TGSI_OPCODE_LOG;
 563    case OPCODE_LIT:
 564       return TGSI_OPCODE_LIT;
 565    case OPCODE_LRP:
 566       return TGSI_OPCODE_LRP;
 567    case OPCODE_MAD:
 568       return TGSI_OPCODE_MAD;
 569    case OPCODE_MAX:
 570       return TGSI_OPCODE_MAX;
 571    case OPCODE_MIN:
 572       return TGSI_OPCODE_MIN;
 573    case OPCODE_MOV:
 574       return TGSI_OPCODE_MOV;
 575    case OPCODE_MUL:
 576       return TGSI_OPCODE_MUL;
 577    case OPCODE_NOP:
 578       return TGSI_OPCODE_NOP;
 579    case OPCODE_POW:
 580       return TGSI_OPCODE_POW;
 581    case OPCODE_RCP:
 582       return TGSI_OPCODE_RCP;
 583    case OPCODE_RET:
 584       return TGSI_OPCODE_RET;
 585    case OPCODE_SCS:
 586       return TGSI_OPCODE_SCS;
 587    case OPCODE_SEQ:
 588       return TGSI_OPCODE_SEQ;
 589    case OPCODE_SGE:
 590       return TGSI_OPCODE_SGE;
 591    case OPCODE_SGT:
 592       return TGSI_OPCODE_SGT;
 593    case OPCODE_SIN:
 594       return TGSI_OPCODE_SIN;
 595    case OPCODE_SLE:
 596       return TGSI_OPCODE_SLE;
 597    case OPCODE_SLT:
 598       return TGSI_OPCODE_SLT;
 599    case OPCODE_SNE:
 600       return TGSI_OPCODE_SNE;
 601    case OPCODE_SSG:
 602       return TGSI_OPCODE_SSG;
 603    case OPCODE_SUB:
 604       return TGSI_OPCODE_SUB;
 605    case OPCODE_TEX:
 606       return TGSI_OPCODE_TEX;
 607    case OPCODE_TXB:
 608       return TGSI_OPCODE_TXB;
 609    case OPCODE_TXD:
 610       return TGSI_OPCODE_TXD;
 611    case OPCODE_TXL:
 612       return TGSI_OPCODE_TXL;
 613    case OPCODE_TXP:
 614       return TGSI_OPCODE_TXP;
 615    case OPCODE_XPD:
 616       return TGSI_OPCODE_XPD;
 617    case OPCODE_END:
 618       return TGSI_OPCODE_END;
 619    default:
 620       debug_assert( 0 );
 621       return TGSI_OPCODE_NOP;
 622    }
 623 }
 624
 625
 626 static void
 627 compile_instruction(
 628    struct gl_context *ctx,
 629    struct st_translate *t,
 630    const struct prog_instruction *inst)
 631 {
 632    struct ureg_program *ureg = t->ureg;
 633    GLuint i;
 634    struct ureg_dst dst[1] = { { 0 } };
 635    struct ureg_src src[4];
 636    unsigned num_dst;
 637    unsigned num_src;
 638
 639    num_dst = _mesa_num_inst_dst_regs( inst->Opcode );
 640    num_src = _mesa_num_inst_src_regs( inst->Opcode );
 641
 642    if (num_dst)
 643       dst[0] = translate_dst( t,
 644                               &inst->DstReg,
 645                               inst->Saturate);
 646
 647    for (i = 0; i < num_src; i++)
 648       src[i] = translate_src( t, &inst->SrcReg[i] );
 649
 650    switch( inst->Opcode ) {
 651    case OPCODE_SWZ:
 652       emit_swz( t, dst[0], &inst->SrcReg[0] );
 653       return;
 654
 655    case OPCODE_BGNLOOP:
 656    case OPCODE_CAL:
 657    case OPCODE_ELSE:
 658    case OPCODE_ENDLOOP:
 659       debug_assert(num_dst == 0);
 660       ureg_label_insn( ureg,
 661                        translate_opcode( inst->Opcode ),
 662                        src, num_src,
 663                        get_label( t, inst->BranchTarget ));
 664       return;
 665
 666    case OPCODE_IF:
 667       debug_assert(num_dst == 0);
 668       ureg_label_insn( ureg,
 669                        ctx->Const.NativeIntegers ? TGSI_OPCODE_UIF : TGSI_OPCODE_IF,
 670                        src, num_src,
 671                        get_label( t, inst->BranchTarget ));
 672       return;
 673
 674    case OPCODE_TEX:
 675    case OPCODE_TXB:
 676    case OPCODE_TXD:
 677    case OPCODE_TXL:
 678    case OPCODE_TXP:
 679       src[num_src++] = t->samplers[inst->TexSrcUnit];
 680       ureg_tex_insn( ureg,
 681                      translate_opcode( inst->Opcode ),
 682                      dst, num_dst,
 683                      st_translate_texture_target( inst->TexSrcTarget,
 684                                                inst->TexShadow ),
 685                      NULL, 0,
 686                      src, num_src );
 687       return;
 688
 689    case OPCODE_SCS:
 690       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XY );
 691       ureg_insn( ureg,
 692                  translate_opcode( inst->Opcode ),
 693                  dst, num_dst,
 694                  src, num_src );
 695       break;
 696
 697    case OPCODE_XPD:
 698       dst[0] = ureg_writemask(dst[0], TGSI_WRITEMASK_XYZ );
 699       ureg_insn( ureg,
 700                  translate_opcode( inst->Opcode ),
 701                  dst, num_dst,
 702                  src, num_src );
 703       break;
 704
 705    case OPCODE_NOISE1:
 706    case OPCODE_NOISE2:
 707    case OPCODE_NOISE3:
 708    case OPCODE_NOISE4:
 709       /* At some point, a motivated person could add a better
 710        * implementation of noise.  Currently not even the nvidia
 711        * binary drivers do anything more than this.  In any case, the
 712        * place to do this is in the GL state tracker, not the poor
 713        * driver.
 714        */
 715       ureg_MOV( ureg, dst[0], ureg_imm1f(ureg, 0.5) );
 716       break;
 717
 718    case OPCODE_DDY:
 719       emit_ddy( t, dst[0], &inst->SrcReg[0] );
 720       break;
 721
 722    case OPCODE_RSQ:
 723       ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
 724       break;
 725
 726    default:
 727       ureg_insn( ureg,
 728                  translate_opcode( inst->Opcode ),
 729                  dst, num_dst,
 730                  src, num_src );
 731       break;
 732    }
 733 }
 734
 735
 736 /**
 737  * Emit the TGSI instructions for inverting and adjusting WPOS.
 738  * This code is unavoidable because it also depends on whether
 739  * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
 740  */
 741 static void
 742 emit_wpos_adjustment( struct st_translate *t,
 743                       const struct gl_program *program,
 744                       boolean invert,
 745                       GLfloat adjX, GLfloat adjY[2])
 746 {
 747    struct ureg_program *ureg = t->ureg;
 748
 749    /* Fragment program uses fragment position input.
 750     * Need to replace instances of INPUT[WPOS] with temp T
 751     * where T = INPUT[WPOS] by y is inverted.
 752     */
 753    static const gl_state_index wposTransformState[STATE_LENGTH]
 754       = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0 };
 755
 756    /* XXX: note we are modifying the incoming shader here!  Need to
 757     * do this before emitting the constant decls below, or this
 758     * will be missed:
 759     */
 760    unsigned wposTransConst = _mesa_add_state_reference(program->Parameters,
 761                                                        wposTransformState);
 762
 763    struct ureg_src wpostrans = ureg_DECL_constant( ureg, wposTransConst );
 764    struct ureg_dst wpos_temp = ureg_DECL_temporary( ureg );
 765    struct ureg_src wpos_input = t->inputs[t->inputMapping[VARYING_SLOT_POS]];
 766
 767    /* First, apply the coordinate shift: */
 768    if (adjX || adjY[0] || adjY[1]) {
 769       if (adjY[0] != adjY[1]) {
 770          /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
 771           * depending on whether inversion is actually going to be applied
 772           * or not, which is determined by testing against the inversion
 773           * state variable used below, which will be either +1 or -1.
 774           */
 775          struct ureg_dst adj_temp = ureg_DECL_temporary(ureg);
 776
 777          ureg_CMP(ureg, adj_temp,
 778                   ureg_scalar(wpostrans, invert ? 2 : 0),
 779                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f),
 780                   ureg_imm4f(ureg, adjX, adjY[1], 0.0f, 0.0f));
 781          ureg_ADD(ureg, wpos_temp, wpos_input, ureg_src(adj_temp));
 782       } else {
 783          ureg_ADD(ureg, wpos_temp, wpos_input,
 784                   ureg_imm4f(ureg, adjX, adjY[0], 0.0f, 0.0f));
 785       }
 786       wpos_input = ureg_src(wpos_temp);
 787    } else {
 788       /* MOV wpos_temp, input[wpos]
 789        */
 790       ureg_MOV( ureg, wpos_temp, wpos_input );
 791    }
 792
 793    /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
 794     * inversion/identity, or the other way around if we're drawing to an FBO.
 795     */
 796    if (invert) {
 797       /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
 798        */
 799       ureg_MAD( ureg,
 800                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 801                 wpos_input,
 802                 ureg_scalar(wpostrans, 0),
 803                 ureg_scalar(wpostrans, 1));
 804    } else {
 805       /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
 806        */
 807       ureg_MAD( ureg,
 808                 ureg_writemask(wpos_temp, TGSI_WRITEMASK_Y ),
 809                 wpos_input,
 810                 ureg_scalar(wpostrans, 2),
 811                 ureg_scalar(wpostrans, 3));
 812    }
 813
 814    /* Use wpos_temp as position input from here on:
 815     */
 816    t->inputs[t->inputMapping[VARYING_SLOT_POS]] = ureg_src(wpos_temp);
 817 }
 818
 819
 820 /**
 821  * Emit fragment position/coordinate code.
 822  */
 823 static void
 824 emit_wpos(struct st_context *st,
 825           struct st_translate *t,
 826           const struct gl_program *program,
 827           struct ureg_program *ureg)
 828 {
 829    const struct gl_fragment_program *fp =
 830       (const struct gl_fragment_program *) program;
 831    struct pipe_screen *pscreen = st->pipe->screen;
 832    GLfloat adjX = 0.0f;
 833    GLfloat adjY[2] = { 0.0f, 0.0f };
 834    boolean invert = FALSE;
 835
 836    /* Query the pixel center conventions supported by the pipe driver and set
 837     * adjX, adjY to help out if it cannot handle the requested one internally.
 838     *
 839     * The bias of the y-coordinate depends on whether y-inversion takes place
 840     * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
 841     * drawing to an FBO (causes additional inversion), and whether the the pipe
 842     * driver origin and the requested origin differ (the latter condition is
 843     * stored in the 'invert' variable).
 844     *
 845     * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
 846     *
 847     * center shift only:
 848     * i -> h: +0.5
 849     * h -> i: -0.5
 850     *
 851     * inversion only:
 852     * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
 853     * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
 854     * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
 855     * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
 856     *
 857     * inversion and center shift:
 858     * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
 859     * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
 860     * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
 861     * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
 862     */
 863    if (fp->OriginUpperLeft) {
 864       /* Fragment shader wants origin in upper-left */
 865       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT)) {
 866          /* the driver supports upper-left origin */
 867       }
 868       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT)) {
 869          /* the driver supports lower-left origin, need to invert Y */
 870          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 871                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 872          invert = TRUE;
 873       }
 874       else
 875          assert(0);
 876    }
 877    else {
 878       /* Fragment shader wants origin in lower-left */
 879       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT))
 880          /* the driver supports lower-left origin */
 881          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_ORIGIN,
 882                        TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
 883       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT))
 884          /* the driver supports upper-left origin, need to invert Y */
 885          invert = TRUE;
 886       else
 887          assert(0);
 888    }
 889
 890    if (fp->PixelCenterInteger) {
 891       /* Fragment shader wants pixel center integer */
 892       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 893          /* the driver supports pixel center integer */
 894          adjY[1] = 1.0f;
 895          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 896                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 897       }
 898       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 899          /* the driver supports pixel center half integer, need to bias X,Y */
 900          adjX = -0.5f;
 901          adjY[0] = -0.5f;
 902          adjY[1] = 0.5f;
 903       }
 904       else
 905          assert(0);
 906    }
 907    else {
 908       /* Fragment shader wants pixel center half integer */
 909       if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER)) {
 910          /* the driver supports pixel center half integer */
 911       }
 912       else if (pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER)) {
 913          /* the driver supports pixel center integer, need to bias X,Y */
 914          adjX = adjY[0] = adjY[1] = 0.5f;
 915          ureg_property(ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
 916                        TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 917       }
 918       else
 919          assert(0);
 920    }
 921
 922    /* we invert after adjustment so that we avoid the MOV to temporary,
 923     * and reuse the adjustment ADD instead */
 924    emit_wpos_adjustment(t, program, invert, adjX, adjY);
 925 }
 926
 927
 928 /**
 929  * OpenGL's fragment gl_FrontFace input is 1 for front-facing, 0 for back.
 930  * TGSI uses +1 for front, -1 for back.
 931  * This function converts the TGSI value to the GL value.  Simply clamping/
 932  * saturating the value to [0,1] does the job.
 933  */
 934 static void
 935 emit_face_var( struct st_translate *t,
 936                const struct gl_program *program )
 937 {
 938    struct ureg_program *ureg = t->ureg;
 939    struct ureg_dst face_temp = ureg_DECL_temporary( ureg );
 940    struct ureg_src face_input = t->inputs[t->inputMapping[VARYING_SLOT_FACE]];
 941
 942    /* MOV_SAT face_temp, input[face]
 943     */
 944    face_temp = ureg_saturate( face_temp );
 945    ureg_MOV( ureg, face_temp, face_input );
 946
 947    /* Use face_temp as face input from here on:
 948     */
 949    t->inputs[t->inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
 950 }
 951
 952
 953 /**
 954  * Translate Mesa program to TGSI format.
 955  * \param program  the program to translate
 956  * \param numInputs  number of input registers used
 957  * \param inputMapping  maps Mesa fragment program inputs to TGSI generic
 958  *                      input indexes
 959  * \param inputSemanticName  the TGSI_SEMANTIC flag for each input
 960  * \param inputSemanticIndex  the semantic index (ex: which texcoord) for
 961  *                            each input
 962  * \param interpMode  the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
 963  * \param numOutputs  number of output registers used
 964  * \param outputMapping  maps Mesa fragment program outputs to TGSI
 965  *                       generic outputs
 966  * \param outputSemanticName  the TGSI_SEMANTIC flag for each output
 967  * \param outputSemanticIndex  the semantic index (ex: which texcoord) for
 968  *                             each output
 969  *
 970  * \return  PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
 971  */
 972 enum pipe_error
 973 st_translate_mesa_program(
 974    struct gl_context *ctx,
 975    uint procType,
 976    struct ureg_program *ureg,
 977    const struct gl_program *program,
 978    GLuint numInputs,
 979    const GLuint inputMapping[],
 980    const ubyte inputSemanticName[],
 981    const ubyte inputSemanticIndex[],
 982    const GLuint interpMode[],
 983    GLuint numOutputs,
 984    const GLuint outputMapping[],
 985    const ubyte outputSemanticName[],
 986    const ubyte outputSemanticIndex[])
 987 {
 988    struct st_translate translate, *t;
 989    unsigned i;
 990    enum pipe_error ret = PIPE_OK;
 991
 992    assert(numInputs <= ARRAY_SIZE(t->inputs));
 993    assert(numOutputs <= ARRAY_SIZE(t->outputs));
 994
 995    t = &translate;
 996    memset(t, 0, sizeof *t);
 997
 998    t->procType = procType;
 999    t->inputMapping = inputMapping;
1000    t->outputMapping = outputMapping;
1001    t->ureg = ureg;
1002
1003    /*_mesa_print_program(program);*/
1004
1005    /*
1006     * Declare input attributes.
1007     */
1008    if (procType == TGSI_PROCESSOR_FRAGMENT) {
1009       for (i = 0; i < numInputs; i++) {
1010          t->inputs[i] = ureg_DECL_fs_input(ureg,
1011                                            inputSemanticName[i],
1012                                            inputSemanticIndex[i],
1013                                            interpMode[i]);
1014       }
1015
1016       if (program->InputsRead & VARYING_BIT_POS) {
1017          /* Must do this after setting up t->inputs, and before
1018           * emitting constant references, below:
1019           */
1020          emit_wpos(st_context(ctx), t, program, ureg);
1021       }
1022
1023       if (program->InputsRead & VARYING_BIT_FACE) {
1024          emit_face_var( t, program );
1025       }
1026
1027       /*
1028        * Declare output attributes.
1029        */
1030       for (i = 0; i < numOutputs; i++) {
1031          switch (outputSemanticName[i]) {
1032          case TGSI_SEMANTIC_POSITION:
1033             t->outputs[i] = ureg_DECL_output( ureg,
1034                                               TGSI_SEMANTIC_POSITION, /* Z / Depth */
1035                                               outputSemanticIndex[i] );
1036
1037             t->outputs[i] = ureg_writemask( t->outputs[i],
1038                                             TGSI_WRITEMASK_Z );
1039             break;
1040          case TGSI_SEMANTIC_STENCIL:
1041             t->outputs[i] = ureg_DECL_output( ureg,
1042                                               TGSI_SEMANTIC_STENCIL, /* Stencil */
1043                                               outputSemanticIndex[i] );
1044             t->outputs[i] = ureg_writemask( t->outputs[i],
1045                                             TGSI_WRITEMASK_Y );
1046             break;
1047          case TGSI_SEMANTIC_COLOR:
1048             t->outputs[i] = ureg_DECL_output( ureg,
1049                                               TGSI_SEMANTIC_COLOR,
1050                                               outputSemanticIndex[i] );
1051             break;
1052          default:
1053             debug_assert(0);
1054             return 0;
1055          }
1056       }
1057    }
1058    else if (procType == TGSI_PROCESSOR_GEOMETRY) {
1059       for (i = 0; i < numInputs; i++) {
1060          t->inputs[i] = ureg_DECL_input(ureg,
1061                                         inputSemanticName[i],
1062                                         inputSemanticIndex[i], 0, 1);
1063       }
1064
1065       for (i = 0; i < numOutputs; i++) {
1066          t->outputs[i] = ureg_DECL_output( ureg,
1067                                            outputSemanticName[i],
1068                                            outputSemanticIndex[i] );
1069       }
1070    }
1071    else {
1072       assert(procType == TGSI_PROCESSOR_VERTEX);
1073
1074       for (i = 0; i < numInputs; i++) {
1075          t->inputs[i] = ureg_DECL_vs_input(ureg, i);
1076       }
1077
1078       for (i = 0; i < numOutputs; i++) {
1079          t->outputs[i] = ureg_DECL_output( ureg,
1080                                            outputSemanticName[i],
1081                                            outputSemanticIndex[i] );
1082          if (outputSemanticName[i] == TGSI_SEMANTIC_FOG) {
1083             /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
1084             ureg_MOV(ureg,
1085                      ureg_writemask(t->outputs[i], TGSI_WRITEMASK_YZW),
1086                      ureg_imm4f(ureg, 0.0f, 0.0f, 0.0f, 1.0f));
1087             t->outputs[i] = ureg_writemask(t->outputs[i], TGSI_WRITEMASK_X);
1088          }
1089       }
1090    }
1091
1092    /* Declare address register.
1093     */
1094    if (program->NumAddressRegs > 0) {
1095       debug_assert( program->NumAddressRegs == 1 );
1096       t->address[0] = ureg_DECL_address( ureg );
1097    }
1098
1099    /* Declare misc input registers
1100     */
1101    {
1102       GLbitfield sysInputs = program->SystemValuesRead;
1103       unsigned numSys = 0;
1104       for (i = 0; sysInputs; i++) {
1105          if (sysInputs & (1 << i)) {
1106             unsigned semName = _mesa_sysval_to_semantic[i];
1107             t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
1108             if (semName == TGSI_SEMANTIC_INSTANCEID ||
1109                 semName == TGSI_SEMANTIC_VERTEXID) {
1110                /* From Gallium perspective, these system values are always
1111                 * integer, and require native integer support.  However, if
1112                 * native integer is supported on the vertex stage but not the
1113                 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1114                 * assumes these system values are floats. To resolve the
1115                 * inconsistency, we insert a U2F.
1116                 */
1117                struct st_context *st = st_context(ctx);
1118                struct pipe_screen *pscreen = st->pipe->screen;
1119                assert(procType == TGSI_PROCESSOR_VERTEX);
1120                assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
1121                (void) pscreen;  /* silence non-debug build warnings */
1122                if (!ctx->Const.NativeIntegers) {
1123                   struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
1124                   ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
1125                   t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
1126                }
1127             }
1128             numSys++;
1129             sysInputs &= ~(1 << i);
1130          }
1131       }
1132    }
1133
1134    if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
1135       /* If temps are accessed with indirect addressing, declare temporaries
1136        * in sequential order.  Else, we declare them on demand elsewhere.
1137        */
1138       for (i = 0; i < program->NumTemporaries; i++) {
1139          /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1140          t->temps[i] = ureg_DECL_temporary( t->ureg );
1141       }
1142    }
1143
1144    /* Emit constants and immediates.  Mesa uses a single index space
1145     * for these, so we put all the translated regs in t->constants.
1146     */
1147    if (program->Parameters) {
1148       t->constants = calloc( program->Parameters->NumParameters,
1149                              sizeof t->constants[0] );
1150       if (t->constants == NULL) {
1151          ret = PIPE_ERROR_OUT_OF_MEMORY;
1152          goto out;
1153       }
1154
1155       for (i = 0; i < program->Parameters->NumParameters; i++) {
1156          switch (program->Parameters->Parameters[i].Type) {
1157          case PROGRAM_STATE_VAR:
1158          case PROGRAM_UNIFORM:
1159             t->constants[i] = ureg_DECL_constant( ureg, i );
1160             break;
1161
1162             /* Emit immediates only when there's no indirect addressing of
1163              * the const buffer.
1164              * FIXME: Be smarter and recognize param arrays:
1165              * indirect addressing is only valid within the referenced
1166              * array.
1167              */
1168          case PROGRAM_CONSTANT:
1169             if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
1170                t->constants[i] = ureg_DECL_constant( ureg, i );
1171             else
1172                t->constants[i] =
1173                   ureg_DECL_immediate( ureg,
1174                                        (const float*) program->Parameters->ParameterValues[i],
1175                                        4 );
1176             break;
1177          default:
1178             break;
1179          }
1180       }
1181    }
1182
1183    /* texture samplers */
1184    for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; i++) {
1185       if (program->SamplersUsed & (1 << i)) {
1186          t->samplers[i] = ureg_DECL_sampler( ureg, i );
1187       }
1188    }
1189
1190    /* Emit each instruction in turn:
1191     */
1192    for (i = 0; i < program->NumInstructions; i++) {
1193       set_insn_start( t, ureg_get_instruction_number( ureg ));
1194       compile_instruction(ctx, t, &program->Instructions[i]);
1195    }
1196
1197    /* Fix up all emitted labels:
1198     */
1199    for (i = 0; i < t->labels_count; i++) {
1200       ureg_fixup_label( ureg,
1201                         t->labels[i].token,
1202                         t->insn[t->labels[i].branch_target] );
1203    }
1204
1205 out:
1206    free(t->insn);
1207    free(t->labels);
1208    free(t->constants);
1209
1210    if (t->error) {
1211       debug_printf("%s: translate error flag set\n", __func__);
1212    }
1213
1214    return ret;
1215 }