1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
34 #include "pipe/p_compiler.h"
35 #include "pipe/p_context.h"
36 #include "pipe/p_screen.h"
37 #include "pipe/p_shader_tokens.h"
38 #include "pipe/p_state.h"
39 #include "tgsi/tgsi_ureg.h"
40 #include "st_mesa_to_tgsi.h"
41 #include "st_context.h"
42 #include "program/prog_instruction.h"
43 #include "program/prog_parameter.h"
44 #include "util/u_debug.h"
45 #include "util/u_math.h"
46 #include "util/u_memory.h"
47 #include "st_glsl_to_tgsi.h" /* for _mesa_sysval_to_semantic */
50 #define PROGRAM_ANY_CONST ((1 << PROGRAM_STATE_VAR) | \
51 (1 << PROGRAM_CONSTANT) | \
52 (1 << PROGRAM_UNIFORM))
56 unsigned branch_target
;
62 * Intermediate state used during shader translation.
65 struct ureg_program
*ureg
;
67 struct ureg_dst temps
[MAX_PROGRAM_TEMPS
];
68 struct ureg_src
*constants
;
69 struct ureg_dst outputs
[PIPE_MAX_SHADER_OUTPUTS
];
70 struct ureg_src inputs
[PIPE_MAX_SHADER_INPUTS
];
71 struct ureg_dst address
[1];
72 struct ureg_src samplers
[PIPE_MAX_SAMPLERS
];
73 struct ureg_src systemValues
[SYSTEM_VALUE_MAX
];
75 const GLuint
*inputMapping
;
76 const GLuint
*outputMapping
;
78 /* For every instruction that contains a label (eg CALL), keep
79 * details so that we can go back afterwards and emit the correct
80 * tgsi instruction number for each label.
84 unsigned labels_count
;
86 /* Keep a record of the tgsi instruction number that each mesa
87 * instruction starts at, will be used to fix up labels after
94 unsigned procType
; /**< TGSI_PROCESSOR_VERTEX/FRAGMENT */
101 * Make note of a branch to a label in the TGSI code.
102 * After we've emitted all instructions, we'll go over the list
103 * of labels built here and patch the TGSI code with the actual
104 * location of each label.
106 static unsigned *get_label( struct st_translate
*t
,
107 unsigned branch_target
)
111 if (t
->labels_count
+ 1 >= t
->labels_size
) {
112 t
->labels_size
= 1 << (util_logbase2(t
->labels_size
) + 1);
113 t
->labels
= realloc(t
->labels
, t
->labels_size
* sizeof t
->labels
[0]);
114 if (t
->labels
== NULL
) {
115 static unsigned dummy
;
121 i
= t
->labels_count
++;
122 t
->labels
[i
].branch_target
= branch_target
;
123 return &t
->labels
[i
].token
;
128 * Called prior to emitting the TGSI code for each Mesa instruction.
129 * Allocate additional space for instructions if needed.
130 * Update the insn[] array so the next Mesa instruction points to
131 * the next TGSI instruction.
133 static void set_insn_start( struct st_translate
*t
,
136 if (t
->insn_count
+ 1 >= t
->insn_size
) {
137 t
->insn_size
= 1 << (util_logbase2(t
->insn_size
) + 1);
138 t
->insn
= realloc(t
->insn
, t
->insn_size
* sizeof t
->insn
[0]);
139 if (t
->insn
== NULL
) {
145 t
->insn
[t
->insn_count
++] = start
;
150 * Map a Mesa dst register to a TGSI ureg_dst register.
152 static struct ureg_dst
153 dst_register( struct st_translate
*t
,
154 gl_register_file file
,
158 case PROGRAM_UNDEFINED
:
159 return ureg_dst_undef();
161 case PROGRAM_TEMPORARY
:
162 if (ureg_dst_is_undef(t
->temps
[index
]))
163 t
->temps
[index
] = ureg_DECL_temporary( t
->ureg
);
165 return t
->temps
[index
];
168 if (t
->procType
== TGSI_PROCESSOR_VERTEX
)
169 assert(index
< VARYING_SLOT_MAX
);
170 else if (t
->procType
== TGSI_PROCESSOR_FRAGMENT
)
171 assert(index
< FRAG_RESULT_MAX
);
173 assert(index
< VARYING_SLOT_MAX
);
175 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
177 return t
->outputs
[t
->outputMapping
[index
]];
179 case PROGRAM_ADDRESS
:
180 return t
->address
[index
];
184 return ureg_dst_undef();
190 * Map a Mesa src register to a TGSI ureg_src register.
192 static struct ureg_src
193 src_register( struct st_translate
*t
,
194 gl_register_file file
,
198 case PROGRAM_UNDEFINED
:
199 return ureg_src_undef();
201 case PROGRAM_TEMPORARY
:
203 assert(index
< ARRAY_SIZE(t
->temps
));
204 if (ureg_dst_is_undef(t
->temps
[index
]))
205 t
->temps
[index
] = ureg_DECL_temporary( t
->ureg
);
206 return ureg_src(t
->temps
[index
]);
208 case PROGRAM_UNIFORM
:
210 return t
->constants
[index
];
211 case PROGRAM_STATE_VAR
:
212 case PROGRAM_CONSTANT
: /* ie, immediate */
214 return ureg_DECL_constant( t
->ureg
, 0 );
216 return t
->constants
[index
];
219 assert(t
->inputMapping
[index
] < ARRAY_SIZE(t
->inputs
));
220 return t
->inputs
[t
->inputMapping
[index
]];
223 assert(t
->outputMapping
[index
] < ARRAY_SIZE(t
->outputs
));
224 return ureg_src(t
->outputs
[t
->outputMapping
[index
]]); /* not needed? */
226 case PROGRAM_ADDRESS
:
227 return ureg_src(t
->address
[index
]);
229 case PROGRAM_SYSTEM_VALUE
:
230 assert(index
< ARRAY_SIZE(t
->systemValues
));
231 return t
->systemValues
[index
];
235 return ureg_src_undef();
241 * Map mesa texture target to TGSI texture target.
244 st_translate_texture_target( GLuint textarget
,
248 switch( textarget
) {
249 case TEXTURE_1D_INDEX
: return TGSI_TEXTURE_SHADOW1D
;
250 case TEXTURE_2D_INDEX
: return TGSI_TEXTURE_SHADOW2D
;
251 case TEXTURE_RECT_INDEX
: return TGSI_TEXTURE_SHADOWRECT
;
252 case TEXTURE_1D_ARRAY_INDEX
: return TGSI_TEXTURE_SHADOW1D_ARRAY
;
253 case TEXTURE_2D_ARRAY_INDEX
: return TGSI_TEXTURE_SHADOW2D_ARRAY
;
254 case TEXTURE_CUBE_INDEX
: return TGSI_TEXTURE_SHADOWCUBE
;
255 case TEXTURE_CUBE_ARRAY_INDEX
: return TGSI_TEXTURE_SHADOWCUBE_ARRAY
;
260 switch( textarget
) {
261 case TEXTURE_2D_MULTISAMPLE_INDEX
: return TGSI_TEXTURE_2D_MSAA
;
262 case TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX
: return TGSI_TEXTURE_2D_ARRAY_MSAA
;
263 case TEXTURE_BUFFER_INDEX
: return TGSI_TEXTURE_BUFFER
;
264 case TEXTURE_1D_INDEX
: return TGSI_TEXTURE_1D
;
265 case TEXTURE_2D_INDEX
: return TGSI_TEXTURE_2D
;
266 case TEXTURE_3D_INDEX
: return TGSI_TEXTURE_3D
;
267 case TEXTURE_CUBE_INDEX
: return TGSI_TEXTURE_CUBE
;
268 case TEXTURE_CUBE_ARRAY_INDEX
: return TGSI_TEXTURE_CUBE_ARRAY
;
269 case TEXTURE_RECT_INDEX
: return TGSI_TEXTURE_RECT
;
270 case TEXTURE_1D_ARRAY_INDEX
: return TGSI_TEXTURE_1D_ARRAY
;
271 case TEXTURE_2D_ARRAY_INDEX
: return TGSI_TEXTURE_2D_ARRAY
;
272 case TEXTURE_EXTERNAL_INDEX
: return TGSI_TEXTURE_2D
;
275 return TGSI_TEXTURE_1D
;
281 * Create a TGSI ureg_dst register from a Mesa dest register.
283 static struct ureg_dst
284 translate_dst( struct st_translate
*t
,
285 const struct prog_dst_register
*DstReg
,
288 struct ureg_dst dst
= dst_register( t
,
292 dst
= ureg_writemask( dst
,
296 dst
= ureg_saturate( dst
);
299 dst
= ureg_dst_indirect( dst
, ureg_src(t
->address
[0]) );
306 * Create a TGSI ureg_src register from a Mesa src register.
308 static struct ureg_src
309 translate_src( struct st_translate
*t
,
310 const struct prog_src_register
*SrcReg
)
312 struct ureg_src src
= src_register( t
, SrcReg
->File
, SrcReg
->Index
);
314 src
= ureg_swizzle( src
,
315 GET_SWZ( SrcReg
->Swizzle
, 0 ) & 0x3,
316 GET_SWZ( SrcReg
->Swizzle
, 1 ) & 0x3,
317 GET_SWZ( SrcReg
->Swizzle
, 2 ) & 0x3,
318 GET_SWZ( SrcReg
->Swizzle
, 3 ) & 0x3);
320 if (SrcReg
->Negate
== NEGATE_XYZW
)
321 src
= ureg_negate(src
);
326 if (SrcReg
->RelAddr
) {
327 src
= ureg_src_indirect( src
, ureg_src(t
->address
[0]));
328 if (SrcReg
->File
!= PROGRAM_INPUT
&&
329 SrcReg
->File
!= PROGRAM_OUTPUT
) {
330 /* If SrcReg->Index was negative, it was set to zero in
331 * src_register(). Reassign it now. But don't do this
332 * for input/output regs since they get remapped while
333 * const buffers don't.
335 src
.Index
= SrcReg
->Index
;
343 static struct ureg_src
swizzle_4v( struct ureg_src src
,
344 const unsigned *swz
)
346 return ureg_swizzle( src
, swz
[0], swz
[1], swz
[2], swz
[3] );
351 * Translate a SWZ instruction into a MOV, MUL or MAD instruction. EG:
357 * MAD dst {1,-1,0,0}, src.xyxx, {0,0,1,0}
359 static void emit_swz( struct st_translate
*t
,
361 const struct prog_src_register
*SrcReg
)
363 struct ureg_program
*ureg
= t
->ureg
;
364 struct ureg_src src
= src_register( t
, SrcReg
->File
, SrcReg
->Index
);
366 unsigned negate_mask
= SrcReg
->Negate
;
368 unsigned one_mask
= ((GET_SWZ(SrcReg
->Swizzle
, 0) == SWIZZLE_ONE
) << 0 |
369 (GET_SWZ(SrcReg
->Swizzle
, 1) == SWIZZLE_ONE
) << 1 |
370 (GET_SWZ(SrcReg
->Swizzle
, 2) == SWIZZLE_ONE
) << 2 |
371 (GET_SWZ(SrcReg
->Swizzle
, 3) == SWIZZLE_ONE
) << 3);
373 unsigned zero_mask
= ((GET_SWZ(SrcReg
->Swizzle
, 0) == SWIZZLE_ZERO
) << 0 |
374 (GET_SWZ(SrcReg
->Swizzle
, 1) == SWIZZLE_ZERO
) << 1 |
375 (GET_SWZ(SrcReg
->Swizzle
, 2) == SWIZZLE_ZERO
) << 2 |
376 (GET_SWZ(SrcReg
->Swizzle
, 3) == SWIZZLE_ZERO
) << 3);
378 unsigned negative_one_mask
= one_mask
& negate_mask
;
379 unsigned positive_one_mask
= one_mask
& ~negate_mask
;
383 unsigned mul_swizzle
[4] = {0,0,0,0};
384 unsigned add_swizzle
[4] = {0,0,0,0};
385 unsigned src_swizzle
[4] = {0,0,0,0};
386 boolean need_add
= FALSE
;
387 boolean need_mul
= FALSE
;
389 if (dst
.WriteMask
== 0)
392 /* Is this just a MOV?
394 if (zero_mask
== 0 &&
396 (negate_mask
== 0 || negate_mask
== TGSI_WRITEMASK_XYZW
))
398 ureg_MOV( ureg
, dst
, translate_src( t
, SrcReg
));
404 #define IMM_NEG_ONE 2
406 imm
= ureg_imm3f( ureg
, 0, 1, -1 );
408 for (i
= 0; i
< 4; i
++) {
409 unsigned bit
= 1 << i
;
411 if (dst
.WriteMask
& bit
) {
412 if (positive_one_mask
& bit
) {
413 mul_swizzle
[i
] = IMM_ZERO
;
414 add_swizzle
[i
] = IMM_ONE
;
417 else if (negative_one_mask
& bit
) {
418 mul_swizzle
[i
] = IMM_ZERO
;
419 add_swizzle
[i
] = IMM_NEG_ONE
;
422 else if (zero_mask
& bit
) {
423 mul_swizzle
[i
] = IMM_ZERO
;
424 add_swizzle
[i
] = IMM_ZERO
;
428 add_swizzle
[i
] = IMM_ZERO
;
429 src_swizzle
[i
] = GET_SWZ(SrcReg
->Swizzle
, i
);
431 if (negate_mask
& bit
) {
432 mul_swizzle
[i
] = IMM_NEG_ONE
;
435 mul_swizzle
[i
] = IMM_ONE
;
441 if (need_mul
&& need_add
) {
444 swizzle_4v( src
, src_swizzle
),
445 swizzle_4v( imm
, mul_swizzle
),
446 swizzle_4v( imm
, add_swizzle
) );
451 swizzle_4v( src
, src_swizzle
),
452 swizzle_4v( imm
, mul_swizzle
) );
457 swizzle_4v( imm
, add_swizzle
) );
470 translate_opcode( unsigned op
)
474 return TGSI_OPCODE_ARL
;
476 return TGSI_OPCODE_ABS
;
478 return TGSI_OPCODE_ADD
;
480 return TGSI_OPCODE_BGNLOOP
;
482 return TGSI_OPCODE_BGNSUB
;
484 return TGSI_OPCODE_BRK
;
486 return TGSI_OPCODE_CAL
;
488 return TGSI_OPCODE_CMP
;
490 return TGSI_OPCODE_CONT
;
492 return TGSI_OPCODE_COS
;
494 return TGSI_OPCODE_DDX
;
496 return TGSI_OPCODE_DDY
;
498 return TGSI_OPCODE_DP2
;
500 return TGSI_OPCODE_DP3
;
502 return TGSI_OPCODE_DP4
;
504 return TGSI_OPCODE_DPH
;
506 return TGSI_OPCODE_DST
;
508 return TGSI_OPCODE_ELSE
;
510 return TGSI_OPCODE_ENDIF
;
512 return TGSI_OPCODE_ENDLOOP
;
514 return TGSI_OPCODE_ENDSUB
;
516 return TGSI_OPCODE_EX2
;
518 return TGSI_OPCODE_EXP
;
520 return TGSI_OPCODE_FLR
;
522 return TGSI_OPCODE_FRC
;
524 return TGSI_OPCODE_IF
;
526 return TGSI_OPCODE_TRUNC
;
528 return TGSI_OPCODE_KILL_IF
;
530 /* XXX we don't support condition codes in TGSI */
531 return TGSI_OPCODE_KILL
;
533 return TGSI_OPCODE_LG2
;
535 return TGSI_OPCODE_LOG
;
537 return TGSI_OPCODE_LIT
;
539 return TGSI_OPCODE_LRP
;
541 return TGSI_OPCODE_MAD
;
543 return TGSI_OPCODE_MAX
;
545 return TGSI_OPCODE_MIN
;
547 return TGSI_OPCODE_MOV
;
549 return TGSI_OPCODE_MUL
;
551 return TGSI_OPCODE_NOP
;
553 return TGSI_OPCODE_POW
;
555 return TGSI_OPCODE_RCP
;
557 return TGSI_OPCODE_RET
;
559 return TGSI_OPCODE_SCS
;
561 return TGSI_OPCODE_SEQ
;
563 return TGSI_OPCODE_SGE
;
565 return TGSI_OPCODE_SGT
;
567 return TGSI_OPCODE_SIN
;
569 return TGSI_OPCODE_SLE
;
571 return TGSI_OPCODE_SLT
;
573 return TGSI_OPCODE_SNE
;
575 return TGSI_OPCODE_SSG
;
577 return TGSI_OPCODE_SUB
;
579 return TGSI_OPCODE_TEX
;
581 return TGSI_OPCODE_TXB
;
583 return TGSI_OPCODE_TXD
;
585 return TGSI_OPCODE_TXL
;
587 return TGSI_OPCODE_TXP
;
589 return TGSI_OPCODE_XPD
;
591 return TGSI_OPCODE_END
;
594 return TGSI_OPCODE_NOP
;
601 struct gl_context
*ctx
,
602 struct st_translate
*t
,
603 const struct prog_instruction
*inst
)
605 struct ureg_program
*ureg
= t
->ureg
;
607 struct ureg_dst dst
[1] = { { 0 } };
608 struct ureg_src src
[4];
612 num_dst
= _mesa_num_inst_dst_regs( inst
->Opcode
);
613 num_src
= _mesa_num_inst_src_regs( inst
->Opcode
);
616 dst
[0] = translate_dst( t
,
620 for (i
= 0; i
< num_src
; i
++)
621 src
[i
] = translate_src( t
, &inst
->SrcReg
[i
] );
623 switch( inst
->Opcode
) {
625 emit_swz( t
, dst
[0], &inst
->SrcReg
[0] );
632 debug_assert(num_dst
== 0);
633 ureg_label_insn( ureg
,
634 translate_opcode( inst
->Opcode
),
636 get_label( t
, inst
->BranchTarget
));
640 debug_assert(num_dst
== 0);
641 ureg_label_insn( ureg
,
642 ctx
->Const
.NativeIntegers
? TGSI_OPCODE_UIF
: TGSI_OPCODE_IF
,
644 get_label( t
, inst
->BranchTarget
));
652 src
[num_src
++] = t
->samplers
[inst
->TexSrcUnit
];
654 translate_opcode( inst
->Opcode
),
656 st_translate_texture_target( inst
->TexSrcTarget
,
663 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XY
);
665 translate_opcode( inst
->Opcode
),
671 dst
[0] = ureg_writemask(dst
[0], TGSI_WRITEMASK_XYZ
);
673 translate_opcode( inst
->Opcode
),
682 /* At some point, a motivated person could add a better
683 * implementation of noise. Currently not even the nvidia
684 * binary drivers do anything more than this. In any case, the
685 * place to do this is in the GL state tracker, not the poor
688 ureg_MOV( ureg
, dst
[0], ureg_imm1f(ureg
, 0.5) );
692 ureg_RSQ( ureg
, dst
[0], ureg_abs(src
[0]) );
697 translate_opcode( inst
->Opcode
),
706 * Emit the TGSI instructions for inverting and adjusting WPOS.
707 * This code is unavoidable because it also depends on whether
708 * a FBO is bound (STATE_FB_WPOS_Y_TRANSFORM).
711 emit_wpos_adjustment(struct gl_context
*ctx
,
712 struct st_translate
*t
,
713 const struct gl_program
*program
,
715 GLfloat adjX
, GLfloat adjY
[2])
717 struct ureg_program
*ureg
= t
->ureg
;
719 /* Fragment program uses fragment position input.
720 * Need to replace instances of INPUT[WPOS] with temp T
721 * where T = INPUT[WPOS] by y is inverted.
723 static const gl_state_index wposTransformState
[STATE_LENGTH
]
724 = { STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0 };
726 /* XXX: note we are modifying the incoming shader here! Need to
727 * do this before emitting the constant decls below, or this
730 unsigned wposTransConst
= _mesa_add_state_reference(program
->Parameters
,
733 struct ureg_src wpostrans
= ureg_DECL_constant( ureg
, wposTransConst
);
734 struct ureg_dst wpos_temp
= ureg_DECL_temporary( ureg
);
735 struct ureg_src
*wpos
=
736 ctx
->Const
.GLSLFragCoordIsSysVal
?
737 &t
->systemValues
[SYSTEM_VALUE_FRAG_COORD
] :
738 &t
->inputs
[t
->inputMapping
[VARYING_SLOT_POS
]];
739 struct ureg_src wpos_input
= *wpos
;
741 /* First, apply the coordinate shift: */
742 if (adjX
|| adjY
[0] || adjY
[1]) {
743 if (adjY
[0] != adjY
[1]) {
744 /* Adjust the y coordinate by adjY[1] or adjY[0] respectively
745 * depending on whether inversion is actually going to be applied
746 * or not, which is determined by testing against the inversion
747 * state variable used below, which will be either +1 or -1.
749 struct ureg_dst adj_temp
= ureg_DECL_temporary(ureg
);
751 ureg_CMP(ureg
, adj_temp
,
752 ureg_scalar(wpostrans
, invert
? 2 : 0),
753 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
),
754 ureg_imm4f(ureg
, adjX
, adjY
[1], 0.0f
, 0.0f
));
755 ureg_ADD(ureg
, wpos_temp
, wpos_input
, ureg_src(adj_temp
));
757 ureg_ADD(ureg
, wpos_temp
, wpos_input
,
758 ureg_imm4f(ureg
, adjX
, adjY
[0], 0.0f
, 0.0f
));
760 wpos_input
= ureg_src(wpos_temp
);
762 /* MOV wpos_temp, input[wpos]
764 ureg_MOV( ureg
, wpos_temp
, wpos_input
);
767 /* Now the conditional y flip: STATE_FB_WPOS_Y_TRANSFORM.xy/zw will be
768 * inversion/identity, or the other way around if we're drawing to an FBO.
771 /* MAD wpos_temp.y, wpos_input, wpostrans.xxxx, wpostrans.yyyy
774 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
776 ureg_scalar(wpostrans
, 0),
777 ureg_scalar(wpostrans
, 1));
779 /* MAD wpos_temp.y, wpos_input, wpostrans.zzzz, wpostrans.wwww
782 ureg_writemask(wpos_temp
, TGSI_WRITEMASK_Y
),
784 ureg_scalar(wpostrans
, 2),
785 ureg_scalar(wpostrans
, 3));
788 /* Use wpos_temp as position input from here on:
790 *wpos
= ureg_src(wpos_temp
);
795 * Emit fragment position/coordinate code.
798 emit_wpos(struct st_context
*st
,
799 struct st_translate
*t
,
800 const struct gl_program
*program
,
801 struct ureg_program
*ureg
)
803 const struct gl_fragment_program
*fp
=
804 (const struct gl_fragment_program
*) program
;
805 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
807 GLfloat adjY
[2] = { 0.0f
, 0.0f
};
808 boolean invert
= FALSE
;
810 /* Query the pixel center conventions supported by the pipe driver and set
811 * adjX, adjY to help out if it cannot handle the requested one internally.
813 * The bias of the y-coordinate depends on whether y-inversion takes place
814 * (adjY[1]) or not (adjY[0]), which is in turn dependent on whether we are
815 * drawing to an FBO (causes additional inversion), and whether the the pipe
816 * driver origin and the requested origin differ (the latter condition is
817 * stored in the 'invert' variable).
819 * For height = 100 (i = integer, h = half-integer, l = lower, u = upper):
826 * l,i -> u,i: ( 0.0 + 1.0) * -1 + 100 = 99
827 * l,h -> u,h: ( 0.5 + 0.0) * -1 + 100 = 99.5
828 * u,i -> l,i: (99.0 + 1.0) * -1 + 100 = 0
829 * u,h -> l,h: (99.5 + 0.0) * -1 + 100 = 0.5
831 * inversion and center shift:
832 * l,i -> u,h: ( 0.0 + 0.5) * -1 + 100 = 99.5
833 * l,h -> u,i: ( 0.5 + 0.5) * -1 + 100 = 99
834 * u,i -> l,h: (99.0 + 0.5) * -1 + 100 = 0.5
835 * u,h -> l,i: (99.5 + 0.5) * -1 + 100 = 0
837 if (fp
->OriginUpperLeft
) {
838 /* Fragment shader wants origin in upper-left */
839 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
)) {
840 /* the driver supports upper-left origin */
842 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
)) {
843 /* the driver supports lower-left origin, need to invert Y */
844 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
845 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
852 /* Fragment shader wants origin in lower-left */
853 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
))
854 /* the driver supports lower-left origin */
855 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_ORIGIN
,
856 TGSI_FS_COORD_ORIGIN_LOWER_LEFT
);
857 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
))
858 /* the driver supports upper-left origin, need to invert Y */
864 if (fp
->PixelCenterInteger
) {
865 /* Fragment shader wants pixel center integer */
866 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
867 /* the driver supports pixel center integer */
869 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
870 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
872 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
873 /* the driver supports pixel center half integer, need to bias X,Y */
882 /* Fragment shader wants pixel center half integer */
883 if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
)) {
884 /* the driver supports pixel center half integer */
886 else if (pscreen
->get_param(pscreen
, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)) {
887 /* the driver supports pixel center integer, need to bias X,Y */
888 adjX
= adjY
[0] = adjY
[1] = 0.5f
;
889 ureg_property(ureg
, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
,
890 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
);
896 /* we invert after adjustment so that we avoid the MOV to temporary,
897 * and reuse the adjustment ADD instead */
898 emit_wpos_adjustment(st
->ctx
, t
, program
, invert
, adjX
, adjY
);
903 * Translate Mesa program to TGSI format.
904 * \param program the program to translate
905 * \param numInputs number of input registers used
906 * \param inputMapping maps Mesa fragment program inputs to TGSI generic
908 * \param inputSemanticName the TGSI_SEMANTIC flag for each input
909 * \param inputSemanticIndex the semantic index (ex: which texcoord) for
911 * \param interpMode the TGSI_INTERPOLATE_LINEAR/PERSP mode for each input
912 * \param numOutputs number of output registers used
913 * \param outputMapping maps Mesa fragment program outputs to TGSI
915 * \param outputSemanticName the TGSI_SEMANTIC flag for each output
916 * \param outputSemanticIndex the semantic index (ex: which texcoord) for
919 * \return PIPE_OK or PIPE_ERROR_OUT_OF_MEMORY
922 st_translate_mesa_program(
923 struct gl_context
*ctx
,
925 struct ureg_program
*ureg
,
926 const struct gl_program
*program
,
928 const GLuint inputMapping
[],
929 const ubyte inputSemanticName
[],
930 const ubyte inputSemanticIndex
[],
931 const GLuint interpMode
[],
933 const GLuint outputMapping
[],
934 const ubyte outputSemanticName
[],
935 const ubyte outputSemanticIndex
[])
937 struct st_translate translate
, *t
;
939 enum pipe_error ret
= PIPE_OK
;
941 assert(numInputs
<= ARRAY_SIZE(t
->inputs
));
942 assert(numOutputs
<= ARRAY_SIZE(t
->outputs
));
945 memset(t
, 0, sizeof *t
);
947 t
->procType
= procType
;
948 t
->inputMapping
= inputMapping
;
949 t
->outputMapping
= outputMapping
;
952 /*_mesa_print_program(program);*/
955 * Declare input attributes.
957 if (procType
== TGSI_PROCESSOR_FRAGMENT
) {
958 for (i
= 0; i
< numInputs
; i
++) {
959 t
->inputs
[i
] = ureg_DECL_fs_input(ureg
,
960 inputSemanticName
[i
],
961 inputSemanticIndex
[i
],
965 if (program
->InputsRead
& VARYING_BIT_POS
) {
966 /* Must do this after setting up t->inputs, and before
967 * emitting constant references, below:
969 emit_wpos(st_context(ctx
), t
, program
, ureg
);
973 * Declare output attributes.
975 for (i
= 0; i
< numOutputs
; i
++) {
976 switch (outputSemanticName
[i
]) {
977 case TGSI_SEMANTIC_POSITION
:
978 t
->outputs
[i
] = ureg_DECL_output( ureg
,
979 TGSI_SEMANTIC_POSITION
, /* Z / Depth */
980 outputSemanticIndex
[i
] );
982 t
->outputs
[i
] = ureg_writemask( t
->outputs
[i
],
985 case TGSI_SEMANTIC_STENCIL
:
986 t
->outputs
[i
] = ureg_DECL_output( ureg
,
987 TGSI_SEMANTIC_STENCIL
, /* Stencil */
988 outputSemanticIndex
[i
] );
989 t
->outputs
[i
] = ureg_writemask( t
->outputs
[i
],
992 case TGSI_SEMANTIC_COLOR
:
993 t
->outputs
[i
] = ureg_DECL_output( ureg
,
995 outputSemanticIndex
[i
] );
1003 else if (procType
== TGSI_PROCESSOR_GEOMETRY
) {
1004 for (i
= 0; i
< numInputs
; i
++) {
1005 t
->inputs
[i
] = ureg_DECL_input(ureg
,
1006 inputSemanticName
[i
],
1007 inputSemanticIndex
[i
], 0, 1);
1010 for (i
= 0; i
< numOutputs
; i
++) {
1011 t
->outputs
[i
] = ureg_DECL_output( ureg
,
1012 outputSemanticName
[i
],
1013 outputSemanticIndex
[i
] );
1017 assert(procType
== TGSI_PROCESSOR_VERTEX
);
1019 for (i
= 0; i
< numInputs
; i
++) {
1020 t
->inputs
[i
] = ureg_DECL_vs_input(ureg
, i
);
1023 for (i
= 0; i
< numOutputs
; i
++) {
1024 t
->outputs
[i
] = ureg_DECL_output( ureg
,
1025 outputSemanticName
[i
],
1026 outputSemanticIndex
[i
] );
1027 if (outputSemanticName
[i
] == TGSI_SEMANTIC_FOG
) {
1028 /* force register to contain a fog coordinate in the form (F, 0, 0, 1). */
1030 ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_YZW
),
1031 ureg_imm4f(ureg
, 0.0f
, 0.0f
, 0.0f
, 1.0f
));
1032 t
->outputs
[i
] = ureg_writemask(t
->outputs
[i
], TGSI_WRITEMASK_X
);
1037 /* Declare address register.
1039 if (program
->NumAddressRegs
> 0) {
1040 debug_assert( program
->NumAddressRegs
== 1 );
1041 t
->address
[0] = ureg_DECL_address( ureg
);
1044 /* Declare misc input registers
1047 GLbitfield sysInputs
= program
->SystemValuesRead
;
1049 for (i
= 0; sysInputs
; i
++) {
1050 if (sysInputs
& (1 << i
)) {
1051 unsigned semName
= _mesa_sysval_to_semantic
[i
];
1053 t
->systemValues
[i
] = ureg_DECL_system_value(ureg
, semName
, 0);
1055 if (semName
== TGSI_SEMANTIC_INSTANCEID
||
1056 semName
== TGSI_SEMANTIC_VERTEXID
) {
1057 /* From Gallium perspective, these system values are always
1058 * integer, and require native integer support. However, if
1059 * native integer is supported on the vertex stage but not the
1060 * pixel stage (e.g, i915g + draw), Mesa will generate IR that
1061 * assumes these system values are floats. To resolve the
1062 * inconsistency, we insert a U2F.
1064 struct st_context
*st
= st_context(ctx
);
1065 struct pipe_screen
*pscreen
= st
->pipe
->screen
;
1066 assert(procType
== TGSI_PROCESSOR_VERTEX
);
1067 assert(pscreen
->get_shader_param(pscreen
, PIPE_SHADER_VERTEX
, PIPE_SHADER_CAP_INTEGERS
));
1068 (void) pscreen
; /* silence non-debug build warnings */
1069 if (!ctx
->Const
.NativeIntegers
) {
1070 struct ureg_dst temp
= ureg_DECL_local_temporary(t
->ureg
);
1071 ureg_U2F( t
->ureg
, ureg_writemask(temp
, TGSI_WRITEMASK_X
), t
->systemValues
[i
]);
1072 t
->systemValues
[i
] = ureg_scalar(ureg_src(temp
), 0);
1076 if (procType
== TGSI_PROCESSOR_FRAGMENT
&&
1077 semName
== TGSI_SEMANTIC_POSITION
)
1078 emit_wpos(st_context(ctx
), t
, program
, ureg
);
1080 sysInputs
&= ~(1 << i
);
1085 if (program
->IndirectRegisterFiles
& (1 << PROGRAM_TEMPORARY
)) {
1086 /* If temps are accessed with indirect addressing, declare temporaries
1087 * in sequential order. Else, we declare them on demand elsewhere.
1089 for (i
= 0; i
< program
->NumTemporaries
; i
++) {
1090 /* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
1091 t
->temps
[i
] = ureg_DECL_temporary( t
->ureg
);
1095 /* Emit constants and immediates. Mesa uses a single index space
1096 * for these, so we put all the translated regs in t->constants.
1098 if (program
->Parameters
) {
1099 t
->constants
= calloc( program
->Parameters
->NumParameters
,
1100 sizeof t
->constants
[0] );
1101 if (t
->constants
== NULL
) {
1102 ret
= PIPE_ERROR_OUT_OF_MEMORY
;
1106 for (i
= 0; i
< program
->Parameters
->NumParameters
; i
++) {
1107 switch (program
->Parameters
->Parameters
[i
].Type
) {
1108 case PROGRAM_STATE_VAR
:
1109 case PROGRAM_UNIFORM
:
1110 t
->constants
[i
] = ureg_DECL_constant( ureg
, i
);
1113 /* Emit immediates only when there's no indirect addressing of
1115 * FIXME: Be smarter and recognize param arrays:
1116 * indirect addressing is only valid within the referenced
1119 case PROGRAM_CONSTANT
:
1120 if (program
->IndirectRegisterFiles
& PROGRAM_ANY_CONST
)
1121 t
->constants
[i
] = ureg_DECL_constant( ureg
, i
);
1124 ureg_DECL_immediate( ureg
,
1125 (const float*) program
->Parameters
->ParameterValues
[i
],
1134 /* texture samplers */
1135 for (i
= 0; i
< ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
; i
++) {
1136 if (program
->SamplersUsed
& (1 << i
)) {
1137 t
->samplers
[i
] = ureg_DECL_sampler( ureg
, i
);
1141 /* Emit each instruction in turn:
1143 for (i
= 0; i
< program
->NumInstructions
; i
++) {
1144 set_insn_start( t
, ureg_get_instruction_number( ureg
));
1145 compile_instruction(ctx
, t
, &program
->Instructions
[i
]);
1148 /* Fix up all emitted labels:
1150 for (i
= 0; i
< t
->labels_count
; i
++) {
1151 ureg_fixup_label( ureg
,
1153 t
->insn
[t
->labels
[i
].branch_target
] );
1162 debug_printf("%s: translate error flag set\n", __func__
);