2 * Mesa 3-D graphics library
5 * Copyright (C) 1999-2005 Brian Paul All Rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 * \file t_arb_program.c
27 * Compile vertex programs to an intermediate representation.
28 * Execute vertex programs over a buffer of vertices.
29 * \author Keith Whitwell, Brian Paul
37 #include "arbprogparse.h"
40 #include "math/m_matrix.h"
41 #include "math/m_translate.h"
42 #include "t_context.h"
43 #include "t_pipeline.h"
44 #include "t_vb_arbprogram.h"
46 #include "program_instruction.h"
54 union instruction
*csr
;
58 #define ARB_VP_MACHINE(stage) ((struct arb_vp_machine *)(stage->privatePtr))
60 #define PUFF(x) ((x)[1] = (x)[2] = (x)[3] = (x)[0])
64 /* Lower precision functions for the EXP, LOG and LIT opcodes. The
65 * LOG2() implementation is probably not accurate enough, and the
66 * attempted optimization for Exp2 is definitely not accurate
67 * enough - it discards all of t's fractional bits!
69 static GLfloat
RoughApproxLog2(GLfloat t
)
74 static GLfloat
RoughApproxExp2(GLfloat t
)
79 fi
.i
= (fi
.i
<< 23) + 0x3f800000;
82 return (GLfloat
) _mesa_pow(2.0, t
);
86 static GLfloat
RoughApproxPower(GLfloat x
, GLfloat y
)
88 if (x
== 0.0 && y
== 0.0)
89 return 1.0; /* spec requires this */
91 return RoughApproxExp2(y
* RoughApproxLog2(x
));
95 /* Higher precision functions for the EX2, LG2 and POW opcodes:
97 static GLfloat
ApproxLog2(GLfloat t
)
99 return (GLfloat
) (LOGF(t
) * 1.442695F
);
102 static GLfloat
ApproxExp2(GLfloat t
)
104 return (GLfloat
) _mesa_pow(2.0, t
);
107 static GLfloat
ApproxPower(GLfloat x
, GLfloat y
)
109 return (GLfloat
) _mesa_pow(x
, y
);
112 static GLfloat
rough_approx_log2_0_1(GLfloat x
)
121 * Perform a reduced swizzle:
123 static void do_RSW( struct arb_vp_machine
*m
, union instruction op
)
125 GLfloat
*result
= m
->File
[0][op
.rsw
.dst
];
126 const GLfloat
*arg0
= m
->File
[op
.rsw
.file0
][op
.rsw
.idx0
];
127 GLuint swz
= op
.rsw
.swz
;
128 GLuint neg
= op
.rsw
.neg
;
131 /* Need a temporary to be correct in the case where result == arg0.
135 result
[0] = tmp
[GET_RSW(swz
, 0)];
136 result
[1] = tmp
[GET_RSW(swz
, 1)];
137 result
[2] = tmp
[GET_RSW(swz
, 2)];
138 result
[3] = tmp
[GET_RSW(swz
, 3)];
141 if (neg
& 0x1) result
[0] = -result
[0];
142 if (neg
& 0x2) result
[1] = -result
[1];
143 if (neg
& 0x4) result
[2] = -result
[2];
144 if (neg
& 0x8) result
[3] = -result
[3];
148 /* Used to implement write masking. To make things easier for the sse
149 * generator I've gone back to a 1 argument version of this function
150 * (dst.msk = arg), rather than the semantically cleaner (dst = SEL
153 * That means this is the only instruction which doesn't write a full
154 * 4 dwords out. This would make such a program harder to analyse,
155 * but it looks like analysis is going to take place on a higher level
158 static void do_MSK( struct arb_vp_machine
*m
, union instruction op
)
160 GLfloat
*dst
= m
->File
[0][op
.msk
.dst
];
161 const GLfloat
*arg
= m
->File
[op
.msk
.file
][op
.msk
.idx
];
163 if (op
.msk
.mask
& 0x1) dst
[0] = arg
[0];
164 if (op
.msk
.mask
& 0x2) dst
[1] = arg
[1];
165 if (op
.msk
.mask
& 0x4) dst
[2] = arg
[2];
166 if (op
.msk
.mask
& 0x8) dst
[3] = arg
[3];
170 static void do_PRT( struct arb_vp_machine
*m
, union instruction op
)
172 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
174 _mesa_printf("%d: %f %f %f %f\n", m
->vtx_nr
,
175 arg0
[0], arg0
[1], arg0
[2], arg0
[3]);
180 * The traditional ALU and texturing instructions. All operate on
181 * internal registers and ignore write masks and swizzling issues.
184 static void do_ABS( struct arb_vp_machine
*m
, union instruction op
)
186 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
187 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
189 result
[0] = (arg0
[0] < 0.0) ? -arg0
[0] : arg0
[0];
190 result
[1] = (arg0
[1] < 0.0) ? -arg0
[1] : arg0
[1];
191 result
[2] = (arg0
[2] < 0.0) ? -arg0
[2] : arg0
[2];
192 result
[3] = (arg0
[3] < 0.0) ? -arg0
[3] : arg0
[3];
195 static void do_ADD( struct arb_vp_machine
*m
, union instruction op
)
197 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
198 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
199 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
201 result
[0] = arg0
[0] + arg1
[0];
202 result
[1] = arg0
[1] + arg1
[1];
203 result
[2] = arg0
[2] + arg1
[2];
204 result
[3] = arg0
[3] + arg1
[3];
208 static void do_DP3( struct arb_vp_machine
*m
, union instruction op
)
210 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
211 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
212 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
214 result
[0] = (arg0
[0] * arg1
[0] +
223 static void do_DP4( struct arb_vp_machine
*m
, union instruction op
)
225 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
226 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
227 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
229 result
[0] = (arg0
[0] * arg1
[0] +
237 static void do_DPH( struct arb_vp_machine
*m
, union instruction op
)
239 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
240 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
241 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
243 result
[0] = (arg0
[0] * arg1
[0] +
251 static void do_DST( struct arb_vp_machine
*m
, union instruction op
)
253 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
254 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
255 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
257 /* This should be ok even if result == arg0 or result == arg1.
260 result
[1] = arg0
[1] * arg1
[1];
266 /* Intended to be high precision:
268 static void do_EX2( struct arb_vp_machine
*m
, union instruction op
)
270 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
271 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
273 result
[0] = (GLfloat
)ApproxExp2(arg0
[0]);
278 /* Allowed to be lower precision:
280 static void do_EXP( struct arb_vp_machine
*m
, union instruction op
)
282 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
283 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
284 GLfloat tmp
= arg0
[0];
285 GLfloat flr_tmp
= FLOORF(tmp
);
286 GLfloat frac_tmp
= tmp
- flr_tmp
;
288 result
[0] = LDEXPF(1.0, (int)flr_tmp
);
289 result
[1] = frac_tmp
;
290 result
[2] = LDEXPF(rough_approx_log2_0_1(frac_tmp
), (int)flr_tmp
);
294 static void do_FLR( struct arb_vp_machine
*m
, union instruction op
)
296 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
297 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
299 result
[0] = FLOORF(arg0
[0]);
300 result
[1] = FLOORF(arg0
[1]);
301 result
[2] = FLOORF(arg0
[2]);
302 result
[3] = FLOORF(arg0
[3]);
305 static void do_FRC( struct arb_vp_machine
*m
, union instruction op
)
307 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
308 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
310 result
[0] = arg0
[0] - FLOORF(arg0
[0]);
311 result
[1] = arg0
[1] - FLOORF(arg0
[1]);
312 result
[2] = arg0
[2] - FLOORF(arg0
[2]);
313 result
[3] = arg0
[3] - FLOORF(arg0
[3]);
316 /* High precision log base 2:
318 static void do_LG2( struct arb_vp_machine
*m
, union instruction op
)
320 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
321 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
323 result
[0] = ApproxLog2(arg0
[0]);
329 static void do_LIT( struct arb_vp_machine
*m
, union instruction op
)
331 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
332 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
338 tmp
[2] = RoughApproxPower(arg0
[1], arg0
[3]);
346 COPY_4V(result
, tmp
);
350 /* Intended to allow a lower precision than required for LG2 above.
352 static void do_LOG( struct arb_vp_machine
*m
, union instruction op
)
354 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
355 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
356 GLfloat tmp
= FABSF(arg0
[0]);
358 GLfloat mantissa
= FREXPF(tmp
, &exponent
);
360 result
[0] = (GLfloat
) (exponent
- 1);
361 result
[1] = 2.0 * mantissa
; /* map [.5, 1) -> [1, 2) */
362 result
[2] = exponent
+ LOG2(mantissa
);
366 static void do_MAX( struct arb_vp_machine
*m
, union instruction op
)
368 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
369 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
370 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
372 result
[0] = (arg0
[0] > arg1
[0]) ? arg0
[0] : arg1
[0];
373 result
[1] = (arg0
[1] > arg1
[1]) ? arg0
[1] : arg1
[1];
374 result
[2] = (arg0
[2] > arg1
[2]) ? arg0
[2] : arg1
[2];
375 result
[3] = (arg0
[3] > arg1
[3]) ? arg0
[3] : arg1
[3];
379 static void do_MIN( struct arb_vp_machine
*m
, union instruction op
)
381 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
382 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
383 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
385 result
[0] = (arg0
[0] < arg1
[0]) ? arg0
[0] : arg1
[0];
386 result
[1] = (arg0
[1] < arg1
[1]) ? arg0
[1] : arg1
[1];
387 result
[2] = (arg0
[2] < arg1
[2]) ? arg0
[2] : arg1
[2];
388 result
[3] = (arg0
[3] < arg1
[3]) ? arg0
[3] : arg1
[3];
391 static void do_MOV( struct arb_vp_machine
*m
, union instruction op
)
393 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
394 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
402 static void do_MUL( struct arb_vp_machine
*m
, union instruction op
)
404 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
405 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
406 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
408 result
[0] = arg0
[0] * arg1
[0];
409 result
[1] = arg0
[1] * arg1
[1];
410 result
[2] = arg0
[2] * arg1
[2];
411 result
[3] = arg0
[3] * arg1
[3];
415 /* Intended to be "high" precision
417 static void do_POW( struct arb_vp_machine
*m
, union instruction op
)
419 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
420 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
421 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
423 result
[0] = (GLfloat
)ApproxPower(arg0
[0], arg1
[0]);
427 static void do_REL( struct arb_vp_machine
*m
, union instruction op
)
429 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
430 GLuint idx
= (op
.alu
.idx0
+ (GLint
)m
->File
[0][REG_ADDR
][0]) & (MAX_NV_VERTEX_PROGRAM_PARAMS
-1);
431 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][idx
];
439 static void do_RCP( struct arb_vp_machine
*m
, union instruction op
)
441 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
442 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
444 result
[0] = 1.0F
/ arg0
[0];
448 static void do_RSQ( struct arb_vp_machine
*m
, union instruction op
)
450 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
451 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
453 result
[0] = INV_SQRTF(FABSF(arg0
[0]));
458 static void do_SGE( struct arb_vp_machine
*m
, union instruction op
)
460 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
461 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
462 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
464 result
[0] = (arg0
[0] >= arg1
[0]) ? 1.0F
: 0.0F
;
465 result
[1] = (arg0
[1] >= arg1
[1]) ? 1.0F
: 0.0F
;
466 result
[2] = (arg0
[2] >= arg1
[2]) ? 1.0F
: 0.0F
;
467 result
[3] = (arg0
[3] >= arg1
[3]) ? 1.0F
: 0.0F
;
471 static void do_SLT( struct arb_vp_machine
*m
, union instruction op
)
473 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
474 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
475 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
477 result
[0] = (arg0
[0] < arg1
[0]) ? 1.0F
: 0.0F
;
478 result
[1] = (arg0
[1] < arg1
[1]) ? 1.0F
: 0.0F
;
479 result
[2] = (arg0
[2] < arg1
[2]) ? 1.0F
: 0.0F
;
480 result
[3] = (arg0
[3] < arg1
[3]) ? 1.0F
: 0.0F
;
483 static void do_SUB( struct arb_vp_machine
*m
, union instruction op
)
485 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
486 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
487 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
489 result
[0] = arg0
[0] - arg1
[0];
490 result
[1] = arg0
[1] - arg1
[1];
491 result
[2] = arg0
[2] - arg1
[2];
492 result
[3] = arg0
[3] - arg1
[3];
496 static void do_XPD( struct arb_vp_machine
*m
, union instruction op
)
498 GLfloat
*result
= m
->File
[0][op
.alu
.dst
];
499 const GLfloat
*arg0
= m
->File
[op
.alu
.file0
][op
.alu
.idx0
];
500 const GLfloat
*arg1
= m
->File
[op
.alu
.file1
][op
.alu
.idx1
];
503 tmp
[0] = arg0
[1] * arg1
[2] - arg0
[2] * arg1
[1];
504 tmp
[1] = arg0
[2] * arg1
[0] - arg0
[0] * arg1
[2];
505 tmp
[2] = arg0
[0] * arg1
[1] - arg0
[1] * arg1
[0];
507 /* Need a temporary to be correct in the case where result == arg0
515 static void do_NOP( struct arb_vp_machine
*m
, union instruction op
)
519 /* Some useful debugging functions:
521 static void print_mask( GLuint mask
)
524 if (mask
&0x1) _mesa_printf("x");
525 if (mask
&0x2) _mesa_printf("y");
526 if (mask
&0x4) _mesa_printf("z");
527 if (mask
&0x8) _mesa_printf("w");
530 static void print_reg( GLuint file
, GLuint reg
)
532 static const char *reg_file
[] = {
542 else if (reg
>= REG_ARG0
&& reg
<= REG_ARG1
)
543 _mesa_printf("ARG%d", reg
- REG_ARG0
);
544 else if (reg
>= REG_TMP0
&& reg
<= REG_TMP11
)
545 _mesa_printf("TMP%d", reg
- REG_TMP0
);
546 else if (reg
>= REG_IN0
&& reg
<= REG_IN31
)
547 _mesa_printf("IN%d", reg
- REG_IN0
);
548 else if (reg
>= REG_OUT0
&& reg
<= REG_OUT14
)
549 _mesa_printf("OUT%d", reg
- REG_OUT0
);
550 else if (reg
== REG_ADDR
)
551 _mesa_printf("ADDR");
552 else if (reg
== REG_ID
)
555 _mesa_printf("REG%d", reg
);
558 _mesa_printf("%s:%d", reg_file
[file
], reg
);
562 static void print_RSW( union instruction op
)
564 GLuint swz
= op
.rsw
.swz
;
565 GLuint neg
= op
.rsw
.neg
;
568 _mesa_printf("RSW ");
569 print_reg(0, op
.rsw
.dst
);
571 print_reg(op
.rsw
.file0
, op
.rsw
.idx0
);
573 for (i
= 0; i
< 4; i
++, swz
>>= 2) {
574 const char *cswz
= "xyzw";
577 _mesa_printf("%c", cswz
[swz
&0x3]);
583 static void print_ALU( union instruction op
)
585 _mesa_printf("%s ", _mesa_opcode_string(op
.alu
.opcode
));
586 print_reg(0, op
.alu
.dst
);
588 print_reg(op
.alu
.file0
, op
.alu
.idx0
);
589 if (_mesa_num_inst_src_regs(op
.alu
.opcode
) > 1) {
591 print_reg(op
.alu
.file1
, op
.alu
.idx1
);
596 static void print_MSK( union instruction op
)
598 _mesa_printf("MSK ");
599 print_reg(0, op
.msk
.dst
);
600 print_mask(op
.msk
.mask
);
602 print_reg(op
.msk
.file
, op
.msk
.idx
);
606 static void print_NOP( union instruction op
)
611 _tnl_disassem_vba_insn( union instruction op
)
613 switch (op
.alu
.opcode
) {
667 _mesa_problem(NULL
, "Bad opcode in _tnl_disassem_vba_insn()");
672 static void (* const opcode_func
[MAX_OPCODE
+3])(struct arb_vp_machine
*, union instruction
) =
749 static union instruction
*cvp_next_instruction( struct compilation
*cp
)
751 union instruction
*op
= cp
->csr
++;
756 static struct reg
cvp_make_reg( GLuint file
, GLuint idx
)
764 static struct reg
cvp_emit_rel( struct compilation
*cp
,
768 union instruction
*op
= cvp_next_instruction(cp
);
769 op
->alu
.opcode
= REL
;
770 op
->alu
.file0
= reg
.file
;
771 op
->alu
.idx0
= reg
.idx
;
772 op
->alu
.dst
= tmpreg
.idx
;
777 static struct reg
cvp_load_reg( struct compilation
*cp
,
783 struct reg tmpreg
= cvp_make_reg(FILE_REG
, tmpidx
);
787 case PROGRAM_TEMPORARY
:
788 return cvp_make_reg(FILE_REG
, REG_TMP0
+ index
);
791 return cvp_make_reg(FILE_REG
, REG_IN0
+ index
);
794 return cvp_make_reg(FILE_REG
, REG_OUT0
+ index
);
796 /* These two aren't populated by the parser?
798 case PROGRAM_LOCAL_PARAM
:
799 reg
= cvp_make_reg(FILE_LOCAL_PARAM
, index
);
801 return cvp_emit_rel(cp
, reg
, tmpreg
);
805 case PROGRAM_ENV_PARAM
:
806 reg
= cvp_make_reg(FILE_ENV_PARAM
, index
);
808 return cvp_emit_rel(cp
, reg
, tmpreg
);
812 case PROGRAM_STATE_VAR
:
813 reg
= cvp_make_reg(FILE_STATE_PARAM
, index
);
815 return cvp_emit_rel(cp
, reg
, tmpreg
);
821 case PROGRAM_WRITE_ONLY
:
822 case PROGRAM_ADDRESS
:
824 _mesa_problem(NULL
, "Invalid register file %d in cvp_load_reg()");
826 return tmpreg
; /* can't happen */
830 static struct reg
cvp_emit_arg( struct compilation
*cp
,
831 const struct prog_src_register
*src
,
834 struct reg reg
= cvp_load_reg( cp
, src
->File
, src
->Index
, src
->RelAddr
, arg
);
835 union instruction rsw
, noop
;
837 /* Emit any necessary swizzling.
840 rsw
.rsw
.neg
= src
->NegateBase
? WRITEMASK_XYZW
: 0;
842 /* we're expecting 2-bit swizzles below... */
843 ASSERT(GET_SWZ(src
->Swizzle
, 0) < 4);
844 ASSERT(GET_SWZ(src
->Swizzle
, 1) < 4);
845 ASSERT(GET_SWZ(src
->Swizzle
, 2) < 4);
846 ASSERT(GET_SWZ(src
->Swizzle
, 3) < 4);
848 rsw
.rsw
.swz
= ((GET_SWZ(src
->Swizzle
, 0) << 0) |
849 (GET_SWZ(src
->Swizzle
, 1) << 2) |
850 (GET_SWZ(src
->Swizzle
, 2) << 4) |
851 (GET_SWZ(src
->Swizzle
, 3) << 6));
855 noop
.rsw
.swz
= RSW_NOOP
;
857 if (rsw
.dword
!= noop
.dword
) {
858 union instruction
*op
= cvp_next_instruction(cp
);
859 struct reg rsw_reg
= cvp_make_reg(FILE_REG
, REG_ARG0
+ arg
);
860 op
->dword
= rsw
.dword
;
861 op
->rsw
.opcode
= RSW
;
862 op
->rsw
.file0
= reg
.file
;
863 op
->rsw
.idx0
= reg
.idx
;
864 op
->rsw
.dst
= rsw_reg
.idx
;
871 static GLuint
cvp_choose_result( struct compilation
*cp
,
872 const struct prog_dst_register
*dst
,
873 union instruction
*fixup
)
875 GLuint mask
= dst
->WriteMask
;
879 case PROGRAM_TEMPORARY
:
880 idx
= REG_TMP0
+ dst
->Index
;
883 idx
= REG_OUT0
+ dst
->Index
;
887 return REG_RES
; /* can't happen */
890 /* Optimization: When writing (with a writemask) to an undefined
891 * value for the first time, the writemask may be ignored.
893 if (mask
!= WRITEMASK_XYZW
&& (cp
->reg_active
& (1 << idx
))) {
894 fixup
->msk
.opcode
= MSK
;
895 fixup
->msk
.dst
= idx
;
896 fixup
->msk
.file
= FILE_REG
;
897 fixup
->msk
.idx
= REG_RES
;
898 fixup
->msk
.mask
= mask
;
899 cp
->reg_active
|= 1 << idx
;
904 cp
->reg_active
|= 1 << idx
;
909 static struct reg
cvp_emit_rsw( struct compilation
*cp
,
918 if (swz
!= RSW_NOOP
|| neg
!= 0) {
919 union instruction
*op
= cvp_next_instruction(cp
);
920 op
->rsw
.opcode
= RSW
;
922 op
->rsw
.file0
= src
.file
;
923 op
->rsw
.idx0
= src
.idx
;
927 retval
.file
= FILE_REG
;
932 /* Oops. Degenerate case:
934 union instruction
*op
= cvp_next_instruction(cp
);
935 op
->alu
.opcode
= OPCODE_MOV
;
937 op
->alu
.file0
= src
.file
;
938 op
->alu
.idx0
= src
.idx
;
940 retval
.file
= FILE_REG
;
950 static void cvp_emit_inst( struct compilation
*cp
,
951 const struct prog_instruction
*inst
)
953 union instruction
*op
;
954 union instruction fixup
;
956 GLuint result
, nr_args
, i
;
958 assert(sizeof(*op
) == sizeof(long long));
960 /* Need to handle SWZ, ARL specially.
962 switch (inst
->Opcode
) {
963 /* Split into mul and add:
966 result
= cvp_choose_result( cp
, &inst
->DstReg
, &fixup
);
967 for (i
= 0; i
< 3; i
++)
968 reg
[i
] = cvp_emit_arg( cp
, &inst
->SrcReg
[i
], REG_ARG0
+i
);
970 op
= cvp_next_instruction(cp
);
971 op
->alu
.opcode
= OPCODE_MUL
;
972 op
->alu
.file0
= reg
[0].file
;
973 op
->alu
.idx0
= reg
[0].idx
;
974 op
->alu
.file1
= reg
[1].file
;
975 op
->alu
.idx1
= reg
[1].idx
;
976 op
->alu
.dst
= REG_ARG0
;
978 op
= cvp_next_instruction(cp
);
979 op
->alu
.opcode
= OPCODE_ADD
;
980 op
->alu
.file0
= FILE_REG
;
981 op
->alu
.idx0
= REG_ARG0
;
982 op
->alu
.file1
= reg
[2].file
;
983 op
->alu
.idx1
= reg
[2].idx
;
984 op
->alu
.dst
= result
;
986 if (result
== REG_RES
) {
987 op
= cvp_next_instruction(cp
);
988 op
->dword
= fixup
.dword
;
993 reg
[0] = cvp_emit_arg( cp
, &inst
->SrcReg
[0], REG_ARG0
);
995 op
= cvp_next_instruction(cp
);
996 op
->alu
.opcode
= OPCODE_FLR
;
997 op
->alu
.dst
= REG_ADDR
;
998 op
->alu
.file0
= reg
[0].file
;
999 op
->alu
.idx0
= reg
[0].idx
;
1003 GLuint swz0
= 0, swz1
= 0;
1004 GLuint neg0
= 0, neg1
= 0;
1007 /* Translate 3-bit-per-element swizzle into two 2-bit swizzles,
1008 * one from the source register the other from a constant
1011 for (i
= 0; i
< 4; i
++) {
1012 GLuint swzelt
= GET_SWZ(inst
->SrcReg
[0].Swizzle
, i
);
1013 if (swzelt
>= SWIZZLE_ZERO
) {
1014 neg0
|= inst
->SrcReg
[0].NegateBase
& (1<<i
);
1015 if (swzelt
== SWIZZLE_ONE
)
1016 swz0
|= SWIZZLE_W
<< (i
*2);
1017 else if (i
< SWIZZLE_W
)
1022 neg1
|= inst
->SrcReg
[0].NegateBase
& (1<<i
);
1023 swz1
|= swzelt
<< (i
*2);
1027 result
= cvp_choose_result( cp
, &inst
->DstReg
, &fixup
);
1028 reg
[0].file
= FILE_REG
;
1029 reg
[0].idx
= REG_ID
;
1030 reg
[1] = cvp_emit_arg( cp
, &inst
->SrcReg
[0], REG_ARG0
);
1032 if (mask
== WRITEMASK_XYZW
) {
1033 cvp_emit_rsw(cp
, result
, reg
[0], neg0
, swz0
, GL_TRUE
);
1036 else if (mask
== 0) {
1037 cvp_emit_rsw(cp
, result
, reg
[1], neg1
, swz1
, GL_TRUE
);
1040 cvp_emit_rsw(cp
, result
, reg
[0], neg0
, swz0
, GL_TRUE
);
1041 reg
[1] = cvp_emit_rsw(cp
, REG_ARG0
, reg
[1], neg1
, swz1
, GL_FALSE
);
1043 op
= cvp_next_instruction(cp
);
1044 op
->msk
.opcode
= MSK
;
1045 op
->msk
.dst
= result
;
1046 op
->msk
.file
= reg
[1].file
;
1047 op
->msk
.idx
= reg
[1].idx
;
1048 op
->msk
.mask
= mask
;
1051 if (result
== REG_RES
) {
1052 op
= cvp_next_instruction(cp
);
1053 op
->dword
= fixup
.dword
;
1062 result
= cvp_choose_result( cp
, &inst
->DstReg
, &fixup
);
1063 nr_args
= _mesa_num_inst_src_regs(inst
->Opcode
);
1064 for (i
= 0; i
< nr_args
; i
++)
1065 reg
[i
] = cvp_emit_arg( cp
, &inst
->SrcReg
[i
], REG_ARG0
+ i
);
1067 op
= cvp_next_instruction(cp
);
1068 op
->alu
.opcode
= inst
->Opcode
;
1069 op
->alu
.file0
= reg
[0].file
;
1070 op
->alu
.idx0
= reg
[0].idx
;
1071 op
->alu
.file1
= reg
[1].file
;
1072 op
->alu
.idx1
= reg
[1].idx
;
1073 op
->alu
.dst
= result
;
1075 if (result
== REG_RES
) {
1076 op
= cvp_next_instruction(cp
);
1077 op
->dword
= fixup
.dword
;
1083 static void free_tnl_data( struct vertex_program
*program
)
1085 struct tnl_compiled_program
*p
= program
->TnlData
;
1086 if (p
->compiled_func
)
1087 _mesa_free((void *)p
->compiled_func
);
1089 program
->TnlData
= NULL
;
1092 static void compile_vertex_program( struct vertex_program
*program
,
1093 GLboolean try_codegen
)
1095 struct compilation cp
;
1096 struct tnl_compiled_program
*p
= CALLOC_STRUCT(tnl_compiled_program
);
1099 if (program
->TnlData
)
1100 free_tnl_data( program
);
1102 program
->TnlData
= p
;
1104 /* Initialize cp. Note that ctx and VB aren't used in compilation
1105 * so we don't have to worry about statechanges:
1107 _mesa_memset(&cp
, 0, sizeof(cp
));
1108 cp
.csr
= p
->instructions
;
1110 /* Compile instructions:
1112 for (i
= 0; i
< program
->Base
.NumInstructions
; i
++) {
1113 cvp_emit_inst(&cp
, &program
->Base
.Instructions
[i
]);
1118 p
->nr_instructions
= cp
.csr
- p
->instructions
;
1120 /* Print/disassemble:
1123 for (i
= 0; i
< p
->nr_instructions
; i
++) {
1124 _tnl_disassem_vba_insn(p
->instructions
[i
]);
1126 _mesa_printf("\n\n");
1131 _tnl_sse_codegen_vertex_program(p
);
1139 /* ----------------------------------------------------------------------
1142 static void userclip( GLcontext
*ctx
,
1145 GLubyte
*clipormask
,
1146 GLubyte
*clipandmask
)
1150 for (p
= 0; p
< ctx
->Const
.MaxClipPlanes
; p
++) {
1151 if (ctx
->Transform
.ClipPlanesEnabled
& (1 << p
)) {
1153 const GLfloat a
= ctx
->Transform
._ClipUserPlane
[p
][0];
1154 const GLfloat b
= ctx
->Transform
._ClipUserPlane
[p
][1];
1155 const GLfloat c
= ctx
->Transform
._ClipUserPlane
[p
][2];
1156 const GLfloat d
= ctx
->Transform
._ClipUserPlane
[p
][3];
1157 GLfloat
*coord
= (GLfloat
*)clip
->data
;
1158 GLuint stride
= clip
->stride
;
1159 GLuint count
= clip
->count
;
1161 for (nr
= 0, i
= 0 ; i
< count
; i
++) {
1162 GLfloat dp
= (coord
[0] * a
+
1169 clipmask
[i
] |= CLIP_USER_BIT
;
1172 STRIDE_F(coord
, stride
);
1176 *clipormask
|= CLIP_USER_BIT
;
1178 *clipandmask
|= CLIP_USER_BIT
;
1188 do_ndc_cliptest(GLcontext
*ctx
, struct arb_vp_machine
*m
)
1190 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
1191 struct vertex_buffer
*VB
= m
->VB
;
1193 /* Cliptest and perspective divide. Clip functions must clear
1197 m
->andmask
= CLIP_ALL_BITS
;
1199 if (tnl
->NeedNdcCoords
) {
1201 _mesa_clip_tab
[VB
->ClipPtr
->size
]( VB
->ClipPtr
,
1209 _mesa_clip_np_tab
[VB
->ClipPtr
->size
]( VB
->ClipPtr
,
1217 /* All vertices are outside the frustum */
1221 /* Test userclip planes. This contributes to VB->ClipMask.
1223 if (ctx
->Transform
.ClipPlanesEnabled
&& !ctx
->VertexProgram
._Enabled
) {
1235 VB
->ClipAndMask
= m
->andmask
;
1236 VB
->ClipOrMask
= m
->ormask
;
1237 VB
->ClipMask
= m
->clipmask
;
1243 static INLINE
void call_func( struct tnl_compiled_program
*p
,
1244 struct arb_vp_machine
*m
)
1246 p
->compiled_func(m
);
1250 * Execute the given vertex program.
1252 * TODO: Integrate the t_vertex.c code here, to build machine vertices
1253 * directly at this point.
1255 * TODO: Eliminate the VB struct entirely and just use
1256 * struct arb_vertex_machine.
1259 run_arb_vertex_program(GLcontext
*ctx
, struct tnl_pipeline_stage
*stage
)
1261 struct vertex_program
*program
= (ctx
->VertexProgram
._Enabled
?
1262 ctx
->VertexProgram
.Current
:
1264 struct vertex_buffer
*VB
= &TNL_CONTEXT(ctx
)->vb
;
1265 struct arb_vp_machine
*m
= ARB_VP_MACHINE(stage
);
1266 struct tnl_compiled_program
*p
;
1270 if (!program
|| program
->IsNVProgram
)
1273 if (program
->Base
.Parameters
) {
1274 _mesa_load_state_parameters(ctx
, program
->Base
.Parameters
);
1277 p
= (struct tnl_compiled_program
*)program
->TnlData
;
1281 m
->nr_inputs
= m
->nr_outputs
= 0;
1283 for (i
= 0; i
< _TNL_ATTRIB_MAX
; i
++) {
1284 if (program
->Base
.InputsRead
& (1<<i
)) {
1285 GLuint j
= m
->nr_inputs
++;
1286 m
->input
[j
].idx
= i
;
1287 m
->input
[j
].data
= (GLfloat
*)m
->VB
->AttribPtr
[i
]->data
;
1288 m
->input
[j
].stride
= m
->VB
->AttribPtr
[i
]->stride
;
1289 m
->input
[j
].size
= m
->VB
->AttribPtr
[i
]->size
;
1290 ASSIGN_4V(m
->File
[0][REG_IN0
+ i
], 0, 0, 0, 1);
1294 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
1295 if (program
->Base
.OutputsWritten
& (1 << i
)) {
1296 GLuint j
= m
->nr_outputs
++;
1297 m
->output
[j
].idx
= i
;
1298 m
->output
[j
].data
= (GLfloat
*)m
->attribs
[i
].data
;
1303 /* Run the actual program:
1305 for (m
->vtx_nr
= 0; m
->vtx_nr
< VB
->Count
; m
->vtx_nr
++) {
1306 for (j
= 0; j
< m
->nr_inputs
; j
++) {
1307 GLuint idx
= REG_IN0
+ m
->input
[j
].idx
;
1308 switch (m
->input
[j
].size
) {
1309 case 4: m
->File
[0][idx
][3] = m
->input
[j
].data
[3];
1310 case 3: m
->File
[0][idx
][2] = m
->input
[j
].data
[2];
1311 case 2: m
->File
[0][idx
][1] = m
->input
[j
].data
[1];
1312 case 1: m
->File
[0][idx
][0] = m
->input
[j
].data
[0];
1315 STRIDE_F(m
->input
[j
].data
, m
->input
[j
].stride
);
1318 if (p
->compiled_func
) {
1322 for (j
= 0; j
< p
->nr_instructions
; j
++) {
1323 union instruction inst
= p
->instructions
[j
];
1324 opcode_func
[inst
.alu
.opcode
]( m
, inst
);
1328 for (j
= 0; j
< m
->nr_outputs
; j
++) {
1329 GLuint idx
= REG_OUT0
+ m
->output
[j
].idx
;
1330 m
->output
[j
].data
[0] = m
->File
[0][idx
][0];
1331 m
->output
[j
].data
[1] = m
->File
[0][idx
][1];
1332 m
->output
[j
].data
[2] = m
->File
[0][idx
][2];
1333 m
->output
[j
].data
[3] = m
->File
[0][idx
][3];
1334 m
->output
[j
].data
+= 4;
1338 /* Setup the VB pointers so that the next pipeline stages get
1339 * their data from the right place (the program output arrays).
1341 * TODO: 1) Have tnl use these RESULT values for outputs rather
1342 * than trying to shoe-horn inputs and outputs into one set of
1345 * TODO: 2) Integrate t_vertex.c so that we just go straight ahead
1346 * and build machine vertices here.
1348 VB
->ClipPtr
= &m
->attribs
[VERT_RESULT_HPOS
];
1349 VB
->ClipPtr
->count
= VB
->Count
;
1351 outputs
= program
->Base
.OutputsWritten
;
1353 if (outputs
& (1<<VERT_RESULT_COL0
)) {
1354 VB
->ColorPtr
[0] = &m
->attribs
[VERT_RESULT_COL0
];
1355 VB
->AttribPtr
[VERT_ATTRIB_COLOR0
] = VB
->ColorPtr
[0];
1358 if (outputs
& (1<<VERT_RESULT_BFC0
)) {
1359 VB
->ColorPtr
[1] = &m
->attribs
[VERT_RESULT_BFC0
];
1362 if (outputs
& (1<<VERT_RESULT_COL1
)) {
1363 VB
->SecondaryColorPtr
[0] = &m
->attribs
[VERT_RESULT_COL1
];
1364 VB
->AttribPtr
[VERT_ATTRIB_COLOR1
] = VB
->SecondaryColorPtr
[0];
1367 if (outputs
& (1<<VERT_RESULT_BFC1
)) {
1368 VB
->SecondaryColorPtr
[1] = &m
->attribs
[VERT_RESULT_BFC1
];
1371 if (outputs
& (1<<VERT_RESULT_FOGC
)) {
1372 VB
->FogCoordPtr
= &m
->attribs
[VERT_RESULT_FOGC
];
1373 VB
->AttribPtr
[VERT_ATTRIB_FOG
] = VB
->FogCoordPtr
;
1376 if (outputs
& (1<<VERT_RESULT_PSIZ
)) {
1377 VB
->PointSizePtr
= &m
->attribs
[VERT_RESULT_PSIZ
];
1378 VB
->AttribPtr
[_TNL_ATTRIB_POINTSIZE
] = &m
->attribs
[VERT_RESULT_PSIZ
];
1381 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
1382 if (outputs
& (1<<(VERT_RESULT_TEX0
+i
))) {
1383 VB
->TexCoordPtr
[i
] = &m
->attribs
[VERT_RESULT_TEX0
+ i
];
1384 VB
->AttribPtr
[VERT_ATTRIB_TEX0
+i
] = VB
->TexCoordPtr
[i
];
1389 for (i
= 0; i
< VB
->Count
; i
++) {
1390 printf("Out %d: %f %f %f %f %f %f %f %f\n", i
,
1391 VEC_ELT(VB
->ClipPtr
, GLfloat
, i
)[0],
1392 VEC_ELT(VB
->ClipPtr
, GLfloat
, i
)[1],
1393 VEC_ELT(VB
->ClipPtr
, GLfloat
, i
)[2],
1394 VEC_ELT(VB
->ClipPtr
, GLfloat
, i
)[3],
1395 VEC_ELT(VB
->TexCoordPtr
[0], GLfloat
, i
)[0],
1396 VEC_ELT(VB
->TexCoordPtr
[0], GLfloat
, i
)[1],
1397 VEC_ELT(VB
->TexCoordPtr
[0], GLfloat
, i
)[2],
1398 VEC_ELT(VB
->TexCoordPtr
[0], GLfloat
, i
)[3]);
1402 /* Perform NDC and cliptest operations:
1404 return do_ndc_cliptest(ctx
, m
);
1409 validate_vertex_program( GLcontext
*ctx
, struct tnl_pipeline_stage
*stage
)
1411 struct arb_vp_machine
*m
= ARB_VP_MACHINE(stage
);
1412 struct vertex_program
*program
=
1413 (ctx
->VertexProgram
._Enabled
? ctx
->VertexProgram
.Current
: 0);
1415 if (!program
&& ctx
->_MaintainTnlProgram
) {
1416 program
= ctx
->_TnlProgram
;
1420 if (!program
->TnlData
)
1421 compile_vertex_program( program
, m
->try_codegen
);
1423 /* Grab the state GL state and put into registers:
1425 m
->File
[FILE_LOCAL_PARAM
] = program
->Base
.LocalParams
;
1426 m
->File
[FILE_ENV_PARAM
] = ctx
->VertexProgram
.Parameters
;
1427 /* GL_NV_vertex_programs can't reference GL state */
1428 if (program
->Base
.Parameters
)
1429 m
->File
[FILE_STATE_PARAM
] = program
->Base
.Parameters
->ParameterValues
;
1431 m
->File
[FILE_STATE_PARAM
] = NULL
;
1442 * Called the first time stage->run is called. In effect, don't
1443 * allocate data until the first time the stage is run.
1445 static GLboolean
init_vertex_program( GLcontext
*ctx
,
1446 struct tnl_pipeline_stage
*stage
)
1448 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
1449 struct vertex_buffer
*VB
= &(tnl
->vb
);
1450 struct arb_vp_machine
*m
;
1451 const GLuint size
= VB
->Size
;
1454 stage
->privatePtr
= _mesa_malloc(sizeof(*m
));
1455 m
= ARB_VP_MACHINE(stage
);
1459 /* arb_vertex_machine struct should subsume the VB:
1463 m
->File
[0] = ALIGN_MALLOC(REG_MAX
* sizeof(GLfloat
) * 4, 16);
1465 /* Initialize regs where necessary:
1467 ASSIGN_4V(m
->File
[0][REG_ID
], 0, 0, 0, 1);
1468 ASSIGN_4V(m
->File
[0][REG_ONES
], 1, 1, 1, 1);
1469 ASSIGN_4V(m
->File
[0][REG_SWZ
], -1, 1, 0, 0);
1470 ASSIGN_4V(m
->File
[0][REG_NEG
], -1, -1, -1, -1);
1471 ASSIGN_4V(m
->File
[0][REG_LIT
], 1, 0, 0, 1);
1472 ASSIGN_4V(m
->File
[0][REG_LIT2
], 1, .5, .2, 1); /* debug value */
1474 if (_mesa_getenv("MESA_EXPERIMENTAL"))
1477 /* Allocate arrays of vertex output values */
1478 for (i
= 0; i
< VERT_RESULT_MAX
; i
++) {
1479 _mesa_vector4f_alloc( &m
->attribs
[i
], 0, size
, 32 );
1480 m
->attribs
[i
].size
= 4;
1483 /* a few other misc allocations */
1484 _mesa_vector4f_alloc( &m
->ndcCoords
, 0, size
, 32 );
1485 m
->clipmask
= (GLubyte
*) ALIGN_MALLOC(sizeof(GLubyte
)*size
, 32 );
1487 if (ctx
->_MaintainTnlProgram
)
1488 _mesa_allow_light_in_model( ctx
, GL_FALSE
);
1490 m
->fpucntl_rnd_neg
= RND_NEG_FPU
; /* const value */
1491 m
->fpucntl_restore
= RESTORE_FPU
; /* const value */
1500 * Destructor for this pipeline stage.
1502 static void dtr( struct tnl_pipeline_stage
*stage
)
1504 struct arb_vp_machine
*m
= ARB_VP_MACHINE(stage
);
1509 /* free the vertex program result arrays */
1510 for (i
= 0; i
< VERT_RESULT_MAX
; i
++)
1511 _mesa_vector4f_free( &m
->attribs
[i
] );
1513 /* free misc arrays */
1514 _mesa_vector4f_free( &m
->ndcCoords
);
1515 ALIGN_FREE( m
->clipmask
);
1516 ALIGN_FREE( m
->File
[0] );
1519 stage
->privatePtr
= NULL
;
1524 * Public description of this pipeline stage.
1526 const struct tnl_pipeline_stage _tnl_arb_vertex_program_stage
=
1529 NULL
, /* private_data */
1530 init_vertex_program
, /* create */
1532 validate_vertex_program
, /* validate */
1533 run_arb_vertex_program
/* run */
1538 * Called via ctx->Driver.ProgramStringNotify() after a new vertex program
1539 * string has been parsed.
1542 _tnl_program_string(GLcontext
*ctx
, GLenum target
, struct program
*program
)
1544 if (program
->Target
== GL_VERTEX_PROGRAM_ARB
) {
1545 /* free any existing tnl data hanging off the program */
1546 struct vertex_program
*vprog
= (struct vertex_program
*) program
;
1547 if (vprog
->TnlData
) {
1548 free_tnl_data(vprog
);