3 * Mesa 3-D graphics library
6 * Copyright (C) 1999-2002 Brian Paul All Rights Reserved.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included
16 * in all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * Check CPU capabilities & initialize optimized funtions for this particular
30 * Written by Holger Waechtler <holger@akaflieg.extern.tu-berlin.de>
31 * Changed by Andre Werthmann <wertmann@cs.uni-potsdam.de> for using the
32 * new Katmai functions.
37 #if defined(USE_SSE_ASM) && defined(__linux__)
40 #if defined(USE_SSE_ASM) && defined(__FreeBSD__)
41 #include <sys/types.h>
42 #include <sys/sysctl.h>
45 #include "common_x86_asm.h"
49 int _mesa_x86_cpu_features
= 0;
51 /* No reason for this to be public.
53 extern GLuint _ASMAPI
_mesa_x86_has_cpuid(void);
54 extern void _ASMAPI
_mesa_x86_cpuid(GLuint op
, GLuint
*reg_eax
, GLuint
*reg_ebx
, GLuint
*reg_ecx
, GLuint
*reg_edx
);
55 extern GLuint _ASMAPI
_mesa_x86_cpuid_eax(GLuint op
);
56 extern GLuint _ASMAPI
_mesa_x86_cpuid_ebx(GLuint op
);
57 extern GLuint _ASMAPI
_mesa_x86_cpuid_ecx(GLuint op
);
58 extern GLuint _ASMAPI
_mesa_x86_cpuid_edx(GLuint op
);
60 static void message( const char *msg
)
66 if ( getenv( "MESA_DEBUG" ) ) {
73 fprintf( stderr
, "%s", msg
);
77 #if defined(USE_SSE_ASM)
79 * We must verify that the Streaming SIMD Extensions are truly supported
80 * on this processor before we go ahead and hook out the optimized code.
81 * Unfortunately, the CPUID bit isn't enough, as the OS must set the
82 * OSFXSR bit in CR4 if it supports the extended FPU save and restore
83 * required to use SSE. Unfortunately, we can't just go ahead and read
84 * this register, as only the kernel can do that. Similarly, we must
85 * verify that the OSXMMEXCPT bit in CR4 has been set by the OS,
86 * signifying that it supports unmasked SIMD FPU exceptions. If we take
87 * an unmasked exception and the OS doesn't correctly support them, the
88 * best we'll get is a SIGILL and the worst we'll get is an infinite
89 * loop in the signal delivery from the kernel as we can't interact with
90 * the SIMD FPU state to clear the exception bits. Either way, this is
94 extern void _mesa_test_os_sse_support( void );
95 extern void _mesa_test_os_sse_exception_support( void );
97 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
98 static void sigill_handler( int signal
, struct sigcontext sc
)
100 message( "SIGILL, " );
102 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
103 * instructions are 3 bytes long. We must increment the instruction
104 * pointer manually to avoid repeated execution of the offending
107 * If the SIGILL is caused by a divide-by-zero when unmasked
108 * exceptions aren't supported, the SIMD FPU status and control
109 * word will be restored at the end of the test, so we don't need
110 * to worry about doing it here. Besides, we may not be able to...
114 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);
117 static void sigfpe_handler( int signal
, struct sigcontext sc
)
119 message( "SIGFPE, " );
121 if ( sc
.fpstate
->magic
!= 0xffff ) {
122 /* Our signal context has the extended FPU state, so reset the
123 * divide-by-zero exception mask and clear the divide-by-zero
126 sc
.fpstate
->mxcsr
|= 0x00000200;
127 sc
.fpstate
->mxcsr
&= 0xfffffffb;
129 /* If we ever get here, we're completely hosed.
132 _mesa_problem( NULL
, "SSE enabling test failed badly!" );
135 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
137 /* If we're running on a processor that can do SSE, let's see if we
138 * are allowed to or not. This will catch 2.4.0 or later kernels that
139 * haven't been configured for a Pentium III but are running on one,
140 * and RedHat patched 2.2 kernels that have broken exception handling
141 * support for user space apps that do SSE.
143 * GH: Isn't this just awful?
145 static void check_os_sse_support( void )
147 #if defined(__linux__)
148 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
149 struct sigaction saved_sigill
;
150 struct sigaction saved_sigfpe
;
152 /* Save the original signal handlers.
154 sigaction( SIGILL
, NULL
, &saved_sigill
);
155 sigaction( SIGFPE
, NULL
, &saved_sigfpe
);
157 signal( SIGILL
, (void (*)(int))sigill_handler
);
158 signal( SIGFPE
, (void (*)(int))sigfpe_handler
);
160 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
161 * supports the extended FPU save and restore required for SSE. If
162 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
163 * doesn't support Streaming SIMD Exceptions, even if the processor
167 message( "Testing OS support for SSE... " );
169 _mesa_test_os_sse_support();
178 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
179 * it supports unmasked SIMD FPU exceptions. If we unmask the
180 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
181 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
182 * as expected, we're okay but we need to clean up after it.
184 * Are we being too stringent in our requirement that the OS support
185 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
186 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
187 * doesn't even support them. We at least know the user-space SSE
188 * support is good in kernels that do support unmasked exceptions,
189 * and therefore to be safe I'm going to leave this test in here.
192 message( "Testing OS support for SSE unmasked exceptions... " );
194 _mesa_test_os_sse_exception_support();
203 /* Restore the original signal handlers.
205 sigaction( SIGILL
, &saved_sigill
, NULL
);
206 sigaction( SIGFPE
, &saved_sigfpe
, NULL
);
208 /* If we've gotten to here and the XMM CPUID bit is still set, we're
209 * safe to go ahead and hook out the SSE code throughout Mesa.
212 message( "Tests of OS support for SSE passed.\n" );
214 message( "Tests of OS support for SSE failed!\n" );
217 /* We can't use POSIX signal handling to test the availability of
218 * SSE, so we disable it by default.
220 message( "Cannot test OS support for SSE, disabling to be safe.\n" );
221 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);
222 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
223 #elif defined(__FreeBSD__)
225 int ret
, len
, enabled
;
226 len
= sizeof(enabled
);
227 ret
= sysctlbyname("hw.instruction_sse", &enabled
, &len
, NULL
, 0);
229 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);
232 /* Do nothing on other platforms for now.
234 message( "Not testing OS support for SSE, leaving enabled.\n" );
235 #endif /* __linux__ */
238 #endif /* USE_SSE_ASM */
241 void _mesa_init_all_x86_transform_asm( void )
243 (void) message
; /* silence warning */
245 _mesa_x86_cpu_features
= 0;
247 if (!_mesa_x86_has_cpuid()) {
248 message("CPUID not detected");
252 GLuint cpu_ext_features
;
257 /* get vendor name */
258 _mesa_x86_cpuid(0, &result
, (GLuint
*)(cpu_vendor
+ 0), (GLuint
*)(cpu_vendor
+ 8), (GLuint
*)(cpu_vendor
+ 4));
259 cpu_vendor
[12] = '\0';
261 message("cpu vendor: ");
265 /* get cpu features */
266 cpu_features
= _mesa_x86_cpuid_edx(1);
268 if (cpu_features
& X86_CPU_FPU
)
269 _mesa_x86_cpu_features
|= X86_FEATURE_FPU
;
270 if (cpu_features
& X86_CPU_CMOV
)
271 _mesa_x86_cpu_features
|= X86_FEATURE_CMOV
;
274 if (cpu_features
& X86_CPU_MMX
)
275 _mesa_x86_cpu_features
|= X86_FEATURE_MMX
;
279 if (cpu_features
& X86_CPU_XMM
)
280 _mesa_x86_cpu_features
|= X86_FEATURE_XMM
;
281 if (cpu_features
& X86_CPU_XMM2
)
282 _mesa_x86_cpu_features
|= X86_FEATURE_XMM2
;
285 /* query extended cpu features */
286 if ((cpu_ext_info
= _mesa_x86_cpuid_eax(0x80000000)) > 0x80000000) {
287 if (cpu_ext_info
>= 0x80000001) {
289 cpu_ext_features
= _mesa_x86_cpuid_edx(0x80000001);
291 if (cpu_features
& X86_CPU_MMX
) {
294 if (cpu_ext_features
& X86_CPUEXT_3DNOW
)
295 _mesa_x86_cpu_features
|= X86_FEATURE_3DNOW
;
296 if (cpu_ext_features
& X86_CPUEXT_3DNOW_EXT
)
297 _mesa_x86_cpu_features
|= X86_FEATURE_3DNOWEXT
;
301 if (cpu_ext_features
& X86_CPUEXT_MMX_EXT
)
302 _mesa_x86_cpu_features
|= X86_FEATURE_MMXEXT
;
308 if (cpu_ext_info
>= 0x80000002) {
311 for (ofs
= 0; ofs
< 3; ofs
++)
312 _mesa_x86_cpuid(0x80000002+ofs
, (GLuint
*)(cpu_name
+ (16*ofs
)+0), (GLuint
*)(cpu_name
+ (16*ofs
)+4), (GLuint
*)(cpu_name
+ (16*ofs
)+8), (GLuint
*)(cpu_name
+ (16*ofs
)+12));
313 cpu_name
[48] = '\0'; /* the name should be NULL terminated, but just to be sure */
315 message("cpu name: ");
323 if ( getenv( "MESA_NO_ASM" ) ) {
324 _mesa_x86_cpu_features
= 0;
327 if ( _mesa_x86_cpu_features
) {
328 _mesa_init_x86_transform_asm();
333 if ( getenv( "MESA_NO_MMX" ) == 0 ) {
334 message( "MMX cpu detected.\n" );
336 _mesa_x86_cpu_features
&= ~(X86_FEATURE_MMX
);
342 if ( cpu_has_3dnow
) {
343 if ( getenv( "MESA_NO_3DNOW" ) == 0 ) {
344 message( "3DNow! cpu detected.\n" );
345 _mesa_init_3dnow_transform_asm();
347 _mesa_x86_cpu_features
&= ~(X86_FEATURE_3DNOW
);
353 if ( cpu_has_xmm
&& getenv( "MESA_FORCE_SSE" ) == 0 ) {
354 check_os_sse_support();
357 if (getenv( "MESA_NO_SSE" ) == 0 ) {
358 message( "SSE cpu detected.\n" );
359 _mesa_init_sse_transform_asm();
361 message( "SSE cpu detected, but switched off by user.\n" );
362 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);