2 * Mesa 3-D graphics library
5 * Copyright (C) 1999-2004 Brian Paul All Rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 * Check CPU capabilities & initialize optimized funtions for this particular
31 * Changed by Andre Werthmann for using the new SSE functions.
33 * \author Holger Waechtler <holger@akaflieg.extern.tu-berlin.de>
34 * \author Andre Werthmann <wertmann@cs.uni-potsdam.de>
37 /* XXX these includes should probably go into imports.h or glheader.h */
38 #if defined(USE_SSE_ASM) && defined(__linux__)
41 #if defined(USE_SSE_ASM) && defined(__FreeBSD__)
42 #include <sys/types.h>
43 #include <sys/sysctl.h>
46 #include "common_x86_asm.h"
50 int _mesa_x86_cpu_features
= 0;
52 /* No reason for this to be public.
54 extern GLuint _ASMAPI
_mesa_x86_has_cpuid(void);
55 extern void _ASMAPI
_mesa_x86_cpuid(GLuint op
, GLuint
*reg_eax
, GLuint
*reg_ebx
, GLuint
*reg_ecx
, GLuint
*reg_edx
);
56 extern GLuint _ASMAPI
_mesa_x86_cpuid_eax(GLuint op
);
57 extern GLuint _ASMAPI
_mesa_x86_cpuid_ebx(GLuint op
);
58 extern GLuint _ASMAPI
_mesa_x86_cpuid_ecx(GLuint op
);
59 extern GLuint _ASMAPI
_mesa_x86_cpuid_edx(GLuint op
);
61 static void message( const char *msg
)
67 if ( _mesa_getenv( "MESA_DEBUG" ) ) {
74 fprintf( stderr
, "%s", msg
);
78 #if defined(USE_SSE_ASM)
80 * We must verify that the Streaming SIMD Extensions are truly supported
81 * on this processor before we go ahead and hook out the optimized code.
82 * Unfortunately, the CPUID bit isn't enough, as the OS must set the
83 * OSFXSR bit in CR4 if it supports the extended FPU save and restore
84 * required to use SSE. Unfortunately, we can't just go ahead and read
85 * this register, as only the kernel can do that. Similarly, we must
86 * verify that the OSXMMEXCPT bit in CR4 has been set by the OS,
87 * signifying that it supports unmasked SIMD FPU exceptions. If we take
88 * an unmasked exception and the OS doesn't correctly support them, the
89 * best we'll get is a SIGILL and the worst we'll get is an infinite
90 * loop in the signal delivery from the kernel as we can't interact with
91 * the SIMD FPU state to clear the exception bits. Either way, this is
94 * However, I have been told by Alan Cox that all 2.4 (and later) Linux
95 * kernels provide full SSE support on all processors that expose SSE via
96 * the CPUID mechanism. It just so happens that this is the exact set of
97 * kernels supported DRI. Therefore, when building for DRI the funky SSE
98 * exception test is omitted.
101 extern void _mesa_test_os_sse_support( void );
102 extern void _mesa_test_os_sse_exception_support( void );
104 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) \
105 && !defined(DRI_NEW_INTERFACE_ONLY)
106 static void sigill_handler( int signal
, struct sigcontext sc
)
108 message( "SIGILL, " );
110 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
111 * instructions are 3 bytes long. We must increment the instruction
112 * pointer manually to avoid repeated execution of the offending
115 * If the SIGILL is caused by a divide-by-zero when unmasked
116 * exceptions aren't supported, the SIMD FPU status and control
117 * word will be restored at the end of the test, so we don't need
118 * to worry about doing it here. Besides, we may not be able to...
122 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);
125 static void sigfpe_handler( int signal
, struct sigcontext sc
)
127 message( "SIGFPE, " );
129 if ( sc
.fpstate
->magic
!= 0xffff ) {
130 /* Our signal context has the extended FPU state, so reset the
131 * divide-by-zero exception mask and clear the divide-by-zero
134 sc
.fpstate
->mxcsr
|= 0x00000200;
135 sc
.fpstate
->mxcsr
&= 0xfffffffb;
137 /* If we ever get here, we're completely hosed.
140 _mesa_problem( NULL
, "SSE enabling test failed badly!" );
143 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
146 #ifndef STATUS_FLOAT_MULTIPLE_TRAPS
147 # define STATUS_FLOAT_MULTIPLE_TRAPS (0xC00002B5L)
149 static LONG WINAPI
ExceptionFilter(LPEXCEPTION_POINTERS exp
)
151 PEXCEPTION_RECORD rec
= exp
->ExceptionRecord
;
152 PCONTEXT ctx
= exp
->ContextRecord
;
154 if ( rec
->ExceptionCode
== EXCEPTION_ILLEGAL_INSTRUCTION
) {
155 message( "EXCEPTION_ILLEGAL_INSTRUCTION, " );
156 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);
157 } else if ( rec
->ExceptionCode
== STATUS_FLOAT_MULTIPLE_TRAPS
) {
158 message( "STATUS_FLOAT_MULTIPLE_TRAPS, " );
159 /* Windows seems to clear the exception flag itself, we just have to increment Eip */
161 message( "UNEXPECTED EXCEPTION (0x%08x), terminating!" );
162 return EXCEPTION_EXECUTE_HANDLER
;
165 if ( (ctx
->ContextFlags
& CONTEXT_CONTROL
) != CONTEXT_CONTROL
) {
166 message( "Context does not contain control registers, terminating!" );
167 return EXCEPTION_EXECUTE_HANDLER
;
171 return EXCEPTION_CONTINUE_EXECUTION
;
176 /* If we're running on a processor that can do SSE, let's see if we
177 * are allowed to or not. This will catch 2.4.0 or later kernels that
178 * haven't been configured for a Pentium III but are running on one,
179 * and RedHat patched 2.2 kernels that have broken exception handling
180 * support for user space apps that do SSE.
182 * GH: Isn't this just awful?
184 static void check_os_sse_support( void )
186 #if defined(__linux__) && !defined(DRI_NEW_INTERFACE_ONLY)
187 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
188 struct sigaction saved_sigill
;
189 struct sigaction saved_sigfpe
;
191 /* Save the original signal handlers.
193 sigaction( SIGILL
, NULL
, &saved_sigill
);
194 sigaction( SIGFPE
, NULL
, &saved_sigfpe
);
196 signal( SIGILL
, (void (*)(int))sigill_handler
);
197 signal( SIGFPE
, (void (*)(int))sigfpe_handler
);
199 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
200 * supports the extended FPU save and restore required for SSE. If
201 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
202 * doesn't support Streaming SIMD Exceptions, even if the processor
206 message( "Testing OS support for SSE... " );
208 _mesa_test_os_sse_support();
217 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
218 * it supports unmasked SIMD FPU exceptions. If we unmask the
219 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
220 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
221 * as expected, we're okay but we need to clean up after it.
223 * Are we being too stringent in our requirement that the OS support
224 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
225 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
226 * doesn't even support them. We at least know the user-space SSE
227 * support is good in kernels that do support unmasked exceptions,
228 * and therefore to be safe I'm going to leave this test in here.
231 message( "Testing OS support for SSE unmasked exceptions... " );
233 _mesa_test_os_sse_exception_support();
242 /* Restore the original signal handlers.
244 sigaction( SIGILL
, &saved_sigill
, NULL
);
245 sigaction( SIGFPE
, &saved_sigfpe
, NULL
);
247 /* If we've gotten to here and the XMM CPUID bit is still set, we're
248 * safe to go ahead and hook out the SSE code throughout Mesa.
251 message( "Tests of OS support for SSE passed.\n" );
253 message( "Tests of OS support for SSE failed!\n" );
256 /* We can't use POSIX signal handling to test the availability of
257 * SSE, so we disable it by default.
259 message( "Cannot test OS support for SSE, disabling to be safe.\n" );
260 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);
261 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
262 #elif defined(__FreeBSD__)
266 len
= sizeof(enabled
);
267 ret
= sysctlbyname("hw.instruction_sse", &enabled
, &len
, NULL
, 0);
269 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);
272 LPTOP_LEVEL_EXCEPTION_FILTER oldFilter
;
274 /* Install our ExceptionFilter */
275 oldFilter
= SetUnhandledExceptionFilter( ExceptionFilter
);
278 message( "Testing OS support for SSE... " );
280 _mesa_test_os_sse_support();
290 message( "Testing OS support for SSE unmasked exceptions... " );
292 _mesa_test_os_sse_exception_support();
301 /* Restore previous exception filter */
302 SetUnhandledExceptionFilter( oldFilter
);
305 message( "Tests of OS support for SSE passed.\n" );
307 message( "Tests of OS support for SSE failed!\n" );
310 /* Do nothing on other platforms for now.
312 message( "Not testing OS support for SSE, leaving enabled.\n" );
313 #endif /* __linux__ */
316 #endif /* USE_SSE_ASM */
319 void _mesa_init_all_x86_transform_asm( void )
321 (void) message
; /* silence warning */
323 _mesa_x86_cpu_features
= 0;
325 if (!_mesa_x86_has_cpuid()) {
326 message("CPUID not detected");
330 GLuint cpu_ext_features
;
335 /* get vendor name */
336 _mesa_x86_cpuid(0, &result
, (GLuint
*)(cpu_vendor
+ 0), (GLuint
*)(cpu_vendor
+ 8), (GLuint
*)(cpu_vendor
+ 4));
337 cpu_vendor
[12] = '\0';
339 message("cpu vendor: ");
343 /* get cpu features */
344 cpu_features
= _mesa_x86_cpuid_edx(1);
346 if (cpu_features
& X86_CPU_FPU
)
347 _mesa_x86_cpu_features
|= X86_FEATURE_FPU
;
348 if (cpu_features
& X86_CPU_CMOV
)
349 _mesa_x86_cpu_features
|= X86_FEATURE_CMOV
;
352 if (cpu_features
& X86_CPU_MMX
)
353 _mesa_x86_cpu_features
|= X86_FEATURE_MMX
;
357 if (cpu_features
& X86_CPU_XMM
)
358 _mesa_x86_cpu_features
|= X86_FEATURE_XMM
;
359 if (cpu_features
& X86_CPU_XMM2
)
360 _mesa_x86_cpu_features
|= X86_FEATURE_XMM2
;
363 /* query extended cpu features */
364 if ((cpu_ext_info
= _mesa_x86_cpuid_eax(0x80000000)) > 0x80000000) {
365 if (cpu_ext_info
>= 0x80000001) {
367 cpu_ext_features
= _mesa_x86_cpuid_edx(0x80000001);
369 if (cpu_features
& X86_CPU_MMX
) {
372 if (cpu_ext_features
& X86_CPUEXT_3DNOW
)
373 _mesa_x86_cpu_features
|= X86_FEATURE_3DNOW
;
374 if (cpu_ext_features
& X86_CPUEXT_3DNOW_EXT
)
375 _mesa_x86_cpu_features
|= X86_FEATURE_3DNOWEXT
;
379 if (cpu_ext_features
& X86_CPUEXT_MMX_EXT
)
380 _mesa_x86_cpu_features
|= X86_FEATURE_MMXEXT
;
386 if (cpu_ext_info
>= 0x80000002) {
389 for (ofs
= 0; ofs
< 3; ofs
++)
390 _mesa_x86_cpuid(0x80000002+ofs
, (GLuint
*)(cpu_name
+ (16*ofs
)+0), (GLuint
*)(cpu_name
+ (16*ofs
)+4), (GLuint
*)(cpu_name
+ (16*ofs
)+8), (GLuint
*)(cpu_name
+ (16*ofs
)+12));
391 cpu_name
[48] = '\0'; /* the name should be NULL terminated, but just to be sure */
393 message("cpu name: ");
401 if ( _mesa_getenv( "MESA_NO_ASM" ) ) {
402 _mesa_x86_cpu_features
= 0;
405 if ( _mesa_x86_cpu_features
) {
406 _mesa_init_x86_transform_asm();
411 if ( _mesa_getenv( "MESA_NO_MMX" ) == 0 ) {
412 message( "MMX cpu detected.\n" );
414 _mesa_x86_cpu_features
&= ~(X86_FEATURE_MMX
);
420 if ( cpu_has_3dnow
) {
421 if ( _mesa_getenv( "MESA_NO_3DNOW" ) == 0 ) {
422 message( "3DNow! cpu detected.\n" );
423 _mesa_init_3dnow_transform_asm();
425 _mesa_x86_cpu_features
&= ~(X86_FEATURE_3DNOW
);
432 if ( _mesa_getenv( "MESA_NO_SSE" ) == 0 ) {
433 message( "SSE cpu detected.\n" );
434 if ( _mesa_getenv( "MESA_FORCE_SSE" ) == 0 ) {
435 check_os_sse_support();
438 _mesa_init_sse_transform_asm();
441 message( "SSE cpu detected, but switched off by user.\n" );
442 _mesa_x86_cpu_features
&= ~(X86_FEATURE_XMM
);