src/mesa/x86/common_x86.c

   1 /* $Id: common_x86.c,v 1.21 2003/01/21 16:13:55 brianp Exp $ */
   2
   3 /*
   4  * Mesa 3-D graphics library
   5  * Version:  5.0
   6  *
   7  * Copyright (C) 1999-2002  Brian Paul   All Rights Reserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included
  17  * in all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  23  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  24  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 /*
  28  * Check CPU capabilities & initialize optimized funtions for this particular
  29  * processor.
  30  *
  31  * Written by Holger Waechtler <holger@akaflieg.extern.tu-berlin.de>
  32  * Changed by Andre Werthmann <wertmann@cs.uni-potsdam.de> for using the
  33  * new Katmai functions.
  34  */
  35
  36 #include <stdlib.h>
  37 #include <stdio.h>
  38 #if defined(USE_SSE_ASM) && defined(__linux__)
  39 #include <signal.h>
  40 #endif
  41 #if defined(USE_SSE_ASM) && defined(__FreeBSD__)
  42 #include <sys/types.h>
  43 #include <sys/sysctl.h>
  44 #endif
  45
  46 #include "context.h"
  47 #include "common_x86_asm.h"
  48 #include "imports.h"
  49
  50
  51 int _mesa_x86_cpu_features = 0;
  52
  53 /* No reason for this to be public.
  54  */
  55 extern int      _mesa_identify_x86_cpu_features(void);
  56
  57 extern GLuint   _mesa_x86_has_cpuid(void);
  58 extern void     _mesa_x86_cpuid(GLuint op, GLuint *reg_eax, GLuint *reg_ebx, GLuint *reg_ecx, GLuint *reg_edx);
  59 extern GLuint   _mesa_x86_cpuid_eax(GLuint op);
  60 extern GLuint   _mesa_x86_cpuid_ebx(GLuint op);
  61 extern GLuint   _mesa_x86_cpuid_ecx(GLuint op);
  62 extern GLuint   _mesa_x86_cpuid_edx(GLuint op);
  63
  64 static void message( const char *msg )
  65 {
  66    GLboolean debug;
  67 #ifdef DEBUG
  68    debug = GL_TRUE;
  69 #else
  70    if ( getenv( "MESA_DEBUG" ) ) {
  71       debug = GL_TRUE;
  72    } else {
  73       debug = GL_FALSE;
  74    }
  75 #endif
  76    if ( debug ) {
  77       fprintf( stderr, "%s", msg );
  78    }
  79 }
  80
  81 #if defined(USE_SSE_ASM)
  82 /*
  83  * We must verify that the Streaming SIMD Extensions are truly supported
  84  * on this processor before we go ahead and hook out the optimized code.
  85  * Unfortunately, the CPUID bit isn't enough, as the OS must set the
  86  * OSFXSR bit in CR4 if it supports the extended FPU save and restore
  87  * required to use SSE.  Unfortunately, we can't just go ahead and read
  88  * this register, as only the kernel can do that.  Similarly, we must
  89  * verify that the OSXMMEXCPT bit in CR4 has been set by the OS,
  90  * signifying that it supports unmasked SIMD FPU exceptions.  If we take
  91  * an unmasked exception and the OS doesn't correctly support them, the
  92  * best we'll get is a SIGILL and the worst we'll get is an infinite
  93  * loop in the signal delivery from the kernel as we can't interact with
  94  * the SIMD FPU state to clear the exception bits.  Either way, this is
  95  * not good.
  96  */
  97
  98 extern void _mesa_test_os_sse_support( void );
  99 extern void _mesa_test_os_sse_exception_support( void );
 100
 101 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 102 static void sigill_handler( int signal, struct sigcontext sc )
 103 {
 104    message( "SIGILL, " );
 105
 106    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 107     * instructions are 3 bytes long.  We must increment the instruction
 108     * pointer manually to avoid repeated execution of the offending
 109     * instruction.
 110     *
 111     * If the SIGILL is caused by a divide-by-zero when unmasked
 112     * exceptions aren't supported, the SIMD FPU status and control
 113     * word will be restored at the end of the test, so we don't need
 114     * to worry about doing it here.  Besides, we may not be able to...
 115     */
 116    sc.eip += 3;
 117
 118    _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 119 }
 120
 121 static void sigfpe_handler( int signal, struct sigcontext sc )
 122 {
 123    message( "SIGFPE, " );
 124
 125    if ( sc.fpstate->magic != 0xffff ) {
 126       /* Our signal context has the extended FPU state, so reset the
 127        * divide-by-zero exception mask and clear the divide-by-zero
 128        * exception bit.
 129        */
 130       sc.fpstate->mxcsr |= 0x00000200;
 131       sc.fpstate->mxcsr &= 0xfffffffb;
 132    } else {
 133       /* If we ever get here, we're completely hosed.
 134        */
 135       message( "\n\n" );
 136       _mesa_problem( NULL, "SSE enabling test failed badly!" );
 137    }
 138 }
 139 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 140
 141 /* If we're running on a processor that can do SSE, let's see if we
 142  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 143  * haven't been configured for a Pentium III but are running on one,
 144  * and RedHat patched 2.2 kernels that have broken exception handling
 145  * support for user space apps that do SSE.
 146  *
 147  * GH: Isn't this just awful?
 148  */
 149 static void check_os_sse_support( void )
 150 {
 151 #if defined(__linux__)
 152 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 153    struct sigaction saved_sigill;
 154    struct sigaction saved_sigfpe;
 155
 156    /* Save the original signal handlers.
 157     */
 158    sigaction( SIGILL, NULL, &saved_sigill );
 159    sigaction( SIGFPE, NULL, &saved_sigfpe );
 160
 161    signal( SIGILL, (void (*)(int))sigill_handler );
 162    signal( SIGFPE, (void (*)(int))sigfpe_handler );
 163
 164    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 165     * supports the extended FPU save and restore required for SSE.  If
 166     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 167     * doesn't support Streaming SIMD Exceptions, even if the processor
 168     * does.
 169     */
 170    if ( cpu_has_xmm ) {
 171       message( "Testing OS support for SSE... " );
 172
 173       _mesa_test_os_sse_support();
 174
 175       if ( cpu_has_xmm ) {
 176          message( "yes.\n" );
 177       } else {
 178          message( "no!\n" );
 179       }
 180    }
 181
 182    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 183     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 184     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 185     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 186     * as expected, we're okay but we need to clean up after it.
 187     *
 188     * Are we being too stringent in our requirement that the OS support
 189     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 190     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 191     * doesn't even support them.  We at least know the user-space SSE
 192     * support is good in kernels that do support unmasked exceptions,
 193     * and therefore to be safe I'm going to leave this test in here.
 194     */
 195    if ( cpu_has_xmm ) {
 196       message( "Testing OS support for SSE unmasked exceptions... " );
 197
 198       _mesa_test_os_sse_exception_support();
 199
 200       if ( cpu_has_xmm ) {
 201          message( "yes.\n" );
 202       } else {
 203          message( "no!\n" );
 204       }
 205    }
 206
 207    /* Restore the original signal handlers.
 208     */
 209    sigaction( SIGILL, &saved_sigill, NULL );
 210    sigaction( SIGFPE, &saved_sigfpe, NULL );
 211
 212    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 213     * safe to go ahead and hook out the SSE code throughout Mesa.
 214     */
 215    if ( cpu_has_xmm ) {
 216       message( "Tests of OS support for SSE passed.\n" );
 217    } else {
 218       message( "Tests of OS support for SSE failed!\n" );
 219    }
 220 #else
 221    /* We can't use POSIX signal handling to test the availability of
 222     * SSE, so we disable it by default.
 223     */
 224    message( "Cannot test OS support for SSE, disabling to be safe.\n" );
 225    _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 226 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 227 #elif defined(__FreeBSD__)
 228    {
 229       int ret, len, enabled;
 230       len = sizeof(enabled);
 231       ret = sysctlbyname("hw.instruction_sse", &enabled, &len, NULL, 0);
 232       if (ret || !enabled)
 233          _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 234    }
 235 #else
 236    /* Do nothing on other platforms for now.
 237     */
 238    message( "Not testing OS support for SSE, leaving enabled.\n" );
 239 #endif /* __linux__ */
 240 }
 241
 242 #endif /* USE_SSE_ASM */
 243
 244
 245 void _mesa_init_all_x86_transform_asm( void )
 246 {
 247    (void) message; /* silence warning */
 248 #ifdef USE_X86_ASM
 249    _mesa_x86_cpu_features = 0;
 250
 251    if (!_mesa_x86_has_cpuid()) {
 252        message("CPUID not detected");
 253    }
 254    else {
 255        GLuint cpu_features;
 256        GLuint cpu_ext_features;
 257        GLuint cpu_ext_info;
 258        char cpu_vendor[13];
 259        GLuint result;
 260
 261        /* get vendor name */
 262        _mesa_x86_cpuid(0, &result, (GLuint *)(cpu_vendor + 0), (GLuint *)(cpu_vendor + 8), (GLuint *)(cpu_vendor + 4));
 263        cpu_vendor[12] = '\0';
 264
 265        message("cpu vendor: ");
 266        message(cpu_vendor);
 267        message("\n");
 268
 269        /* get cpu features */
 270        cpu_features = _mesa_x86_cpuid_edx(1);
 271
 272        if (cpu_features & X86_CPU_FPU)
 273            _mesa_x86_cpu_features |= X86_FEATURE_FPU;
 274        if (cpu_features & X86_CPU_CMOV)
 275            _mesa_x86_cpu_features |= X86_FEATURE_CMOV;
 276
 277 #ifdef USE_MMX_ASM
 278        if (cpu_features & X86_CPU_MMX)
 279            _mesa_x86_cpu_features |= X86_FEATURE_MMX;
 280 #endif
 281
 282 #ifdef USE_SSE_ASM
 283        if (cpu_features & X86_CPU_XMM)
 284            _mesa_x86_cpu_features |= X86_FEATURE_XMM;
 285        if (cpu_features & X86_CPU_XMM2)
 286            _mesa_x86_cpu_features |= X86_FEATURE_XMM2;
 287 #endif
 288
 289        /* query extended cpu features */
 290        if ((cpu_ext_info = _mesa_x86_cpuid_eax(0x80000000)) > 0x80000000) {
 291            if (cpu_ext_info >= 0x80000001) {
 292
 293                cpu_ext_features = _mesa_x86_cpuid_edx(0x80000001);
 294
 295                if (cpu_features & X86_CPU_MMX) {
 296
 297 #ifdef USE_3DNOW_ASM
 298                    if (cpu_ext_features & X86_CPUEXT_3DNOW)
 299                        _mesa_x86_cpu_features |= X86_FEATURE_3DNOW;
 300                    if (cpu_ext_features & X86_CPUEXT_3DNOW_EXT)
 301                        _mesa_x86_cpu_features |= X86_FEATURE_3DNOWEXT;
 302 #endif
 303
 304 #ifdef USE_MMX_ASM
 305                    if (cpu_ext_features & X86_CPUEXT_MMX_EXT)
 306                        _mesa_x86_cpu_features |= X86_FEATURE_MMXEXT;
 307 #endif
 308                }
 309            }
 310
 311            /* query cpu name */
 312            if (cpu_ext_info >= 0x80000002) {
 313                GLuint ofs;
 314                char cpu_name[49];
 315                for (ofs = 0; ofs < 3; ofs++)
 316                    _mesa_x86_cpuid(0x80000002+ofs, (GLuint *)(cpu_name + (16*ofs)+0), (GLuint *)(cpu_name + (16*ofs)+4), (GLuint *)(cpu_name + (16*ofs)+8), (GLuint *)(cpu_name + (16*ofs)+12));
 317                cpu_name[48] = '\0'; /* the name should be NULL terminated, but just to be sure */
 318
 319                message("cpu name: ");
 320                message(cpu_name);
 321                message("\n");
 322            }
 323        }
 324
 325    }
 326
 327    if ( getenv( "MESA_NO_ASM" ) ) {
 328       _mesa_x86_cpu_features = 0;
 329    }
 330
 331    if ( _mesa_x86_cpu_features ) {
 332       _mesa_init_x86_transform_asm();
 333    }
 334
 335 #ifdef USE_MMX_ASM
 336    if ( cpu_has_mmx ) {
 337       if ( getenv( "MESA_NO_MMX" ) == 0 ) {
 338          message( "MMX cpu detected.\n" );
 339       } else {
 340          _mesa_x86_cpu_features &= ~(X86_FEATURE_MMX);
 341       }
 342    }
 343 #endif
 344
 345 #ifdef USE_3DNOW_ASM
 346    if ( cpu_has_3dnow ) {
 347       if ( getenv( "MESA_NO_3DNOW" ) == 0 ) {
 348          message( "3DNow! cpu detected.\n" );
 349          _mesa_init_3dnow_transform_asm();
 350       } else {
 351          _mesa_x86_cpu_features &= ~(X86_FEATURE_3DNOW);
 352       }
 353    }
 354 #endif
 355
 356 #ifdef USE_SSE_ASM
 357    if ( cpu_has_xmm && getenv( "MESA_FORCE_SSE" ) == 0 ) {
 358       check_os_sse_support();
 359    }
 360    if ( cpu_has_xmm ) {
 361       if ( getenv( "MESA_NO_SSE" ) == 0 ) {
 362          message( "SSE cpu detected.\n" );
 363          _mesa_init_sse_transform_asm();
 364       } else {
 365          _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 366       }
 367    }
 368 #endif
 369 #endif
 370 }
 371