src/mesa/x86/common_x86.c

   1 /*
   2  * Mesa 3-D graphics library
   3  * Version:  6.5.1
   4  *
   5  * Copyright (C) 1999-2006  Brian Paul   All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included
  15  * in all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  21  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file common_x86.c
  27  *
  28  * Check CPU capabilities & initialize optimized funtions for this particular
  29  * processor.
  30  *
  31  * Changed by Andre Werthmann for using the new SSE functions.
  32  *
  33  * \author Holger Waechtler <holger@akaflieg.extern.tu-berlin.de>
  34  * \author Andre Werthmann <wertmann@cs.uni-potsdam.de>
  35  */
  36
  37 /* XXX these includes should probably go into imports.h or glheader.h */
  38 #if defined(USE_SSE_ASM) && defined(__linux__)
  39 #include <signal.h>
  40 #endif
  41 #if defined(USE_SSE_ASM) && defined(__FreeBSD__)
  42 #include <sys/types.h>
  43 #include <sys/sysctl.h>
  44 #endif
  45
  46 #include "common_x86_asm.h"
  47 #include "imports.h"
  48
  49
  50 int _mesa_x86_cpu_features = 0;
  51
  52 /* No reason for this to be public.
  53  */
  54 extern GLuint   _ASMAPI _mesa_x86_has_cpuid(void);
  55 extern void     _ASMAPI _mesa_x86_cpuid(GLuint op, GLuint *reg_eax, GLuint *reg_ebx, GLuint *reg_ecx, GLuint *reg_edx);
  56 extern GLuint   _ASMAPI _mesa_x86_cpuid_eax(GLuint op);
  57 extern GLuint   _ASMAPI _mesa_x86_cpuid_ebx(GLuint op);
  58 extern GLuint   _ASMAPI _mesa_x86_cpuid_ecx(GLuint op);
  59 extern GLuint   _ASMAPI _mesa_x86_cpuid_edx(GLuint op);
  60
  61
  62 #if defined(USE_SSE_ASM)
  63 /*
  64  * We must verify that the Streaming SIMD Extensions are truly supported
  65  * on this processor before we go ahead and hook out the optimized code.
  66  * Unfortunately, the CPUID bit isn't enough, as the OS must set the
  67  * OSFXSR bit in CR4 if it supports the extended FPU save and restore
  68  * required to use SSE.  Unfortunately, we can't just go ahead and read
  69  * this register, as only the kernel can do that.  Similarly, we must
  70  * verify that the OSXMMEXCPT bit in CR4 has been set by the OS,
  71  * signifying that it supports unmasked SIMD FPU exceptions.  If we take
  72  * an unmasked exception and the OS doesn't correctly support them, the
  73  * best we'll get is a SIGILL and the worst we'll get is an infinite
  74  * loop in the signal delivery from the kernel as we can't interact with
  75  * the SIMD FPU state to clear the exception bits.  Either way, this is
  76  * not good.
  77  *
  78  * However, I have been told by Alan Cox that all 2.4 (and later) Linux
  79  * kernels provide full SSE support on all processors that expose SSE via
  80  * the CPUID mechanism.  It just so happens that this is the exact set of
  81  * kernels supported DRI.  Therefore, when building for DRI the funky SSE
  82  * exception test is omitted.
  83  */
  84
  85 extern void _mesa_test_os_sse_support( void );
  86 extern void _mesa_test_os_sse_exception_support( void );
  87
  88 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) \
  89    && !defined(IN_DRI_DRIVER)
  90 static void sigill_handler( int signal, struct sigcontext sc )
  91 {
  92    /*message( "SIGILL, " );*/
  93
  94    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
  95     * instructions are 3 bytes long.  We must increment the instruction
  96     * pointer manually to avoid repeated execution of the offending
  97     * instruction.
  98     *
  99     * If the SIGILL is caused by a divide-by-zero when unmasked
 100     * exceptions aren't supported, the SIMD FPU status and control
 101     * word will be restored at the end of the test, so we don't need
 102     * to worry about doing it here.  Besides, we may not be able to...
 103     */
 104    sc.eip += 3;
 105
 106    _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 107 }
 108
 109 static void sigfpe_handler( int signal, struct sigcontext sc )
 110 {
 111    /*message( "SIGFPE, " );*/
 112
 113    if ( sc.fpstate->magic != 0xffff ) {
 114       /* Our signal context has the extended FPU state, so reset the
 115        * divide-by-zero exception mask and clear the divide-by-zero
 116        * exception bit.
 117        */
 118       sc.fpstate->mxcsr |= 0x00000200;
 119       sc.fpstate->mxcsr &= 0xfffffffb;
 120    } else {
 121       /* If we ever get here, we're completely hosed.
 122        */
 123       /*message( "\n\n" );*/
 124       _mesa_problem( NULL, "SSE enabling test failed badly!" );
 125    }
 126 }
 127 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 128
 129 #if defined(WIN32)
 130 #ifndef STATUS_FLOAT_MULTIPLE_TRAPS
 131 # define STATUS_FLOAT_MULTIPLE_TRAPS (0xC00002B5L)
 132 #endif
 133 static LONG WINAPI ExceptionFilter(LPEXCEPTION_POINTERS exp)
 134 {
 135    PEXCEPTION_RECORD rec = exp->ExceptionRecord;
 136    PCONTEXT ctx = exp->ContextRecord;
 137
 138    if ( rec->ExceptionCode == EXCEPTION_ILLEGAL_INSTRUCTION ) {
 139       _mesa_debug(NULL, "EXCEPTION_ILLEGAL_INSTRUCTION\n" );
 140       _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 141    } else if ( rec->ExceptionCode == STATUS_FLOAT_MULTIPLE_TRAPS ) {
 142       _mesa_debug(NULL, "STATUS_FLOAT_MULTIPLE_TRAPS\n");
 143       /* Windows seems to clear the exception flag itself, we just have to increment Eip */
 144    } else {
 145       _mesa_debug(NULL, "UNEXPECTED EXCEPTION (0x%08x), terminating!\n" );
 146       return EXCEPTION_EXECUTE_HANDLER;
 147    }
 148
 149    if ( (ctx->ContextFlags & CONTEXT_CONTROL) != CONTEXT_CONTROL ) {
 150       _mesa_debug(NULL, "Context does not contain control registers, terminating!\n");
 151       return EXCEPTION_EXECUTE_HANDLER;
 152    }
 153    ctx->Eip += 3;
 154
 155    return EXCEPTION_CONTINUE_EXECUTION;
 156 }
 157 #endif /* WIN32 */
 158
 159
 160 /* If we're running on a processor that can do SSE, let's see if we
 161  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 162  * haven't been configured for a Pentium III but are running on one,
 163  * and RedHat patched 2.2 kernels that have broken exception handling
 164  * support for user space apps that do SSE.
 165  *
 166  * GH: Isn't this just awful?
 167  */
 168 static void check_os_sse_support( void )
 169 {
 170 #if defined(__linux__) && !defined(IN_DRI_DRIVER)
 171 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 172    struct sigaction saved_sigill;
 173    struct sigaction saved_sigfpe;
 174
 175    /* Save the original signal handlers.
 176     */
 177    sigaction( SIGILL, NULL, &saved_sigill );
 178    sigaction( SIGFPE, NULL, &saved_sigfpe );
 179
 180    signal( SIGILL, (void (*)(int))sigill_handler );
 181    signal( SIGFPE, (void (*)(int))sigfpe_handler );
 182
 183    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 184     * supports the extended FPU save and restore required for SSE.  If
 185     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 186     * doesn't support Streaming SIMD Exceptions, even if the processor
 187     * does.
 188     */
 189    if ( cpu_has_xmm ) {
 190       _mesa_debug(NULL, "Testing OS support for SSE...\n");
 191
 192       _mesa_test_os_sse_support();
 193
 194       if ( cpu_has_xmm ) {
 195          _mesa_debug(NULL, "Yes\n");
 196       } else {
 197          _mesa_debug(NULL, "No\n");
 198       }
 199    }
 200
 201    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 202     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 203     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 204     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 205     * as expected, we're okay but we need to clean up after it.
 206     *
 207     * Are we being too stringent in our requirement that the OS support
 208     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 209     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 210     * doesn't even support them.  We at least know the user-space SSE
 211     * support is good in kernels that do support unmasked exceptions,
 212     * and therefore to be safe I'm going to leave this test in here.
 213     */
 214    if ( cpu_has_xmm ) {
 215       _mesa_debug(NULL, "Testing OS support for SSE unmasked exceptions...\n");
 216
 217       _mesa_test_os_sse_exception_support();
 218
 219       if ( cpu_has_xmm ) {
 220          _mesa_debug(NULL, "Yes.\n");
 221       } else {
 222          _mesa_debug(NULL, "No!\n");
 223       }
 224    }
 225
 226    /* Restore the original signal handlers.
 227     */
 228    sigaction( SIGILL, &saved_sigill, NULL );
 229    sigaction( SIGFPE, &saved_sigfpe, NULL );
 230
 231    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 232     * safe to go ahead and hook out the SSE code throughout Mesa.
 233     */
 234    if ( cpu_has_xmm ) {
 235       _mesa_debug(NULL, "Tests of OS support for SSE passed.\n");
 236    } else {
 237       _mesa_debug(NULL, "Tests of OS support for SSE failed!\n");
 238    }
 239 #else
 240    /* We can't use POSIX signal handling to test the availability of
 241     * SSE, so we disable it by default.
 242     */
 243    _mesa_debug(NULL, "Cannot test OS support for SSE, disabling to be safe.\n");
 244    _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 245 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 246 #elif defined(__FreeBSD__)
 247    {
 248       int ret, enabled;
 249       unsigned int len;
 250       len = sizeof(enabled);
 251       ret = sysctlbyname("hw.instruction_sse", &enabled, &len, NULL, 0);
 252       if (ret || !enabled)
 253          _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 254    }
 255 #elif defined(WIN32)
 256    LPTOP_LEVEL_EXCEPTION_FILTER oldFilter;
 257
 258    /* Install our ExceptionFilter */
 259    oldFilter = SetUnhandledExceptionFilter( ExceptionFilter );
 260
 261    if ( cpu_has_xmm ) {
 262       _mesa_debug(NULL, "Testing OS support for SSE...\n");
 263
 264       _mesa_test_os_sse_support();
 265
 266       if ( cpu_has_xmm ) {
 267          _mesa_debug(NULL, "Yes.\n");
 268       } else {
 269          _mesa_debug(NULL, "No!\n");
 270       }
 271    }
 272
 273    if ( cpu_has_xmm ) {
 274       _mesa_debug(NULL, "Testing OS support for SSE unmasked exceptions...\n");
 275
 276       _mesa_test_os_sse_exception_support();
 277
 278       if ( cpu_has_xmm ) {
 279          _mesa_debug(NULL, "Yes.\n");
 280       } else {
 281          _mesa_debug(NULL, "No!\n");
 282       }
 283    }
 284
 285    /* Restore previous exception filter */
 286    SetUnhandledExceptionFilter( oldFilter );
 287
 288    if ( cpu_has_xmm ) {
 289       _mesa_debug(NULL, "Tests of OS support for SSE passed.\n");
 290    } else {
 291       _mesa_debug(NULL, "Tests of OS support for SSE failed!\n");
 292    }
 293 #else
 294    /* Do nothing on other platforms for now.
 295     */
 296    _mesa_debug(NULL, "Not testing OS support for SSE, leaving enabled.\n");
 297 #endif /* __linux__ */
 298 }
 299
 300 #endif /* USE_SSE_ASM */
 301
 302
 303 void _mesa_init_all_x86_transform_asm( void )
 304 {
 305 #ifdef USE_X86_ASM
 306    _mesa_x86_cpu_features = 0;
 307
 308    if (!_mesa_x86_has_cpuid()) {
 309        _mesa_debug(NULL, "CPUID not detected\n");
 310    }
 311    else {
 312        GLuint cpu_features;
 313        GLuint cpu_ext_features;
 314        GLuint cpu_ext_info;
 315        char cpu_vendor[13];
 316        GLuint result;
 317
 318        /* get vendor name */
 319        _mesa_x86_cpuid(0, &result, (GLuint *)(cpu_vendor + 0), (GLuint *)(cpu_vendor + 8), (GLuint *)(cpu_vendor + 4));
 320        cpu_vendor[12] = '\0';
 321
 322        _mesa_debug(NULL, "CPU vendor: %s\n", cpu_vendor);
 323
 324        /* get cpu features */
 325        cpu_features = _mesa_x86_cpuid_edx(1);
 326
 327        if (cpu_features & X86_CPU_FPU)
 328            _mesa_x86_cpu_features |= X86_FEATURE_FPU;
 329        if (cpu_features & X86_CPU_CMOV)
 330            _mesa_x86_cpu_features |= X86_FEATURE_CMOV;
 331
 332 #ifdef USE_MMX_ASM
 333        if (cpu_features & X86_CPU_MMX)
 334            _mesa_x86_cpu_features |= X86_FEATURE_MMX;
 335 #endif
 336
 337 #ifdef USE_SSE_ASM
 338        if (cpu_features & X86_CPU_XMM)
 339            _mesa_x86_cpu_features |= X86_FEATURE_XMM;
 340        if (cpu_features & X86_CPU_XMM2)
 341            _mesa_x86_cpu_features |= X86_FEATURE_XMM2;
 342 #endif
 343
 344        /* query extended cpu features */
 345        if ((cpu_ext_info = _mesa_x86_cpuid_eax(0x80000000)) > 0x80000000) {
 346            if (cpu_ext_info >= 0x80000001) {
 347
 348                cpu_ext_features = _mesa_x86_cpuid_edx(0x80000001);
 349
 350                if (cpu_features & X86_CPU_MMX) {
 351
 352 #ifdef USE_3DNOW_ASM
 353                    if (cpu_ext_features & X86_CPUEXT_3DNOW)
 354                        _mesa_x86_cpu_features |= X86_FEATURE_3DNOW;
 355                    if (cpu_ext_features & X86_CPUEXT_3DNOW_EXT)
 356                        _mesa_x86_cpu_features |= X86_FEATURE_3DNOWEXT;
 357 #endif
 358
 359 #ifdef USE_MMX_ASM
 360                    if (cpu_ext_features & X86_CPUEXT_MMX_EXT)
 361                        _mesa_x86_cpu_features |= X86_FEATURE_MMXEXT;
 362 #endif
 363                }
 364            }
 365
 366            /* query cpu name */
 367            if (cpu_ext_info >= 0x80000002) {
 368                GLuint ofs;
 369                char cpu_name[49];
 370                for (ofs = 0; ofs < 3; ofs++)
 371                    _mesa_x86_cpuid(0x80000002+ofs, (GLuint *)(cpu_name + (16*ofs)+0), (GLuint *)(cpu_name + (16*ofs)+4), (GLuint *)(cpu_name + (16*ofs)+8), (GLuint *)(cpu_name + (16*ofs)+12));
 372                cpu_name[48] = '\0'; /* the name should be NULL terminated, but just to be sure */
 373
 374                _mesa_debug(NULL, "CPU name: %s\n", cpu_name);
 375            }
 376        }
 377
 378    }
 379
 380    if ( _mesa_getenv( "MESA_NO_ASM" ) ) {
 381       _mesa_x86_cpu_features = 0;
 382    }
 383
 384    if ( _mesa_x86_cpu_features ) {
 385       _mesa_init_x86_transform_asm();
 386    }
 387
 388 #ifdef USE_MMX_ASM
 389    if ( cpu_has_mmx ) {
 390       if ( _mesa_getenv( "MESA_NO_MMX" ) == 0 ) {
 391          _mesa_debug(NULL, "MMX cpu detected.\n");
 392       } else {
 393          _mesa_x86_cpu_features &= ~(X86_FEATURE_MMX);
 394       }
 395    }
 396 #endif
 397
 398 #ifdef USE_3DNOW_ASM
 399    if ( cpu_has_3dnow ) {
 400       if ( _mesa_getenv( "MESA_NO_3DNOW" ) == 0 ) {
 401          _mesa_debug(NULL, "3DNow! cpu detected.\n");
 402          _mesa_init_3dnow_transform_asm();
 403       } else {
 404          _mesa_x86_cpu_features &= ~(X86_FEATURE_3DNOW);
 405       }
 406    }
 407 #endif
 408
 409 #ifdef USE_SSE_ASM
 410    if ( cpu_has_xmm ) {
 411       if ( _mesa_getenv( "MESA_NO_SSE" ) == 0 ) {
 412          _mesa_debug(NULL, "SSE cpu detected.\n");
 413          if ( _mesa_getenv( "MESA_FORCE_SSE" ) == 0 ) {
 414             check_os_sse_support();
 415          }
 416          if ( cpu_has_xmm ) {
 417             _mesa_init_sse_transform_asm();
 418          }
 419       } else {
 420          _mesa_debug(NULL, "SSE cpu detected, but switched off by user.\n");
 421          _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
 422       }
 423    }
 424 #endif
 425 #endif
 426 }
 427