1 """ key strategic example showing how to do multi-input fan-in into a
2 multi-stage pipeline, then multi-output fanout.
4 the multiplex ID from the fan-in is passed in to the pipeline, preserved,
5 and used as a routing ID on the fanout.
8 from random
import randint
10 from nmigen
import Module
, Signal
, Cat
, Value
, Elaboratable
11 from nmigen
.compat
.sim
import run_simulation
12 from nmigen
.cli
import verilog
, rtlil
14 from nmutil
.multipipe
import CombMultiOutPipeline
, CombMuxOutPipe
15 from nmutil
.multipipe
import PriorityCombMuxInPipe
16 from nmutil
.singlepipe
import SimpleHandshake
, RecordObject
, Object
19 class PassData2(RecordObject
):
21 RecordObject
.__init
__(self
)
22 self
.mid
= Signal(2, reset_less
=True)
23 self
.idx
= Signal(8, reset_less
=True)
24 self
.data
= Signal(16, reset_less
=True)
27 class PassData(Object
):
30 self
.mid
= Signal(2, reset_less
=True)
31 self
.idx
= Signal(8, reset_less
=True)
32 self
.data
= Signal(16, reset_less
=True)
36 class PassThroughStage
:
40 return self
.ispec() # same as ospec
43 return i
# pass-through
47 class PassThroughPipe(SimpleHandshake
):
49 SimpleHandshake
.__init
__(self
, PassThroughStage())
53 def __init__(self
, dut
):
58 for mid
in range(dut
.num_rows
):
61 for i
in range(self
.tlen
):
62 self
.di
[mid
][i
] = randint(0, 255) + (mid
<<8)
63 self
.do
[mid
][i
] = self
.di
[mid
][i
]
66 for i
in range(self
.tlen
):
69 yield rs
.valid_i
.eq(1)
70 yield rs
.data_i
.data
.eq(op2
)
71 yield rs
.data_i
.idx
.eq(i
)
72 yield rs
.data_i
.mid
.eq(mid
)
74 o_p_ready
= yield rs
.ready_o
77 o_p_ready
= yield rs
.ready_o
79 print ("send", mid
, i
, hex(op2
))
81 yield rs
.valid_i
.eq(0)
82 # wait random period of time before queueing another value
83 for i
in range(randint(0, 3)):
86 yield rs
.valid_i
.eq(0)
89 print ("send ended", mid
)
91 ## wait random period of time before queueing another value
92 #for i in range(randint(0, 3)):
95 #send_range = randint(0, 3)
99 # send = randint(0, send_range) != 0
103 #stall_range = randint(0, 3)
104 #for j in range(randint(1,10)):
105 # stall = randint(0, stall_range) != 0
106 # yield self.dut.n[0].ready_i.eq(stall)
109 yield n
.ready_i
.eq(1)
111 o_n_valid
= yield n
.valid_o
112 i_n_ready
= yield n
.ready_i
113 if not o_n_valid
or not i_n_ready
:
116 out_mid
= yield n
.data_o
.mid
117 out_i
= yield n
.data_o
.idx
118 out_v
= yield n
.data_o
.data
120 print ("recv", out_mid
, out_i
, hex(out_v
))
122 # see if this output has occurred already, delete it if it has
123 assert mid
== out_mid
, "out_mid %d not correct %d" % (out_mid
, mid
)
124 assert out_i
in self
.do
[mid
], "out_i %d not in array %s" % \
125 (out_i
, repr(self
.do
[mid
]))
126 assert self
.do
[mid
][out_i
] == out_v
# pass-through data
127 del self
.do
[mid
][out_i
]
129 # check if there's any more outputs
130 if len(self
.do
[mid
]) == 0:
132 print ("recv ended", mid
)
135 class TestPriorityMuxPipe(PriorityCombMuxInPipe
):
136 def __init__(self
, num_rows
):
137 self
.num_rows
= num_rows
138 stage
= PassThroughStage()
139 PriorityCombMuxInPipe
.__init
__(self
, stage
, p_len
=self
.num_rows
)
143 def __init__(self
, dut
):
148 for i
in range(self
.tlen
* dut
.num_rows
):
152 mid
= randint(0, dut
.num_rows
-1)
153 data
= randint(0, 255) + (mid
<<8)
156 for i
in range(self
.tlen
* dut
.num_rows
):
160 yield rs
.valid_i
.eq(1)
161 yield rs
.data_i
.data
.eq(op2
)
162 yield rs
.data_i
.mid
.eq(mid
)
164 o_p_ready
= yield rs
.ready_o
167 o_p_ready
= yield rs
.ready_o
169 print ("send", mid
, i
, hex(op2
))
171 yield rs
.valid_i
.eq(0)
172 # wait random period of time before queueing another value
173 for i
in range(randint(0, 3)):
176 yield rs
.valid_i
.eq(0)
179 class TestMuxOutPipe(CombMuxOutPipe
):
180 def __init__(self
, num_rows
):
181 self
.num_rows
= num_rows
182 stage
= PassThroughStage()
183 CombMuxOutPipe
.__init
__(self
, stage
, n_len
=self
.num_rows
)
186 class TestInOutPipe(Elaboratable
):
187 def __init__(self
, num_rows
=4):
188 self
.num_rows
= num_rows
189 self
.inpipe
= TestPriorityMuxPipe(num_rows
) # fan-in (combinatorial)
190 self
.pipe1
= PassThroughPipe() # stage 1 (clock-sync)
191 self
.pipe2
= PassThroughPipe() # stage 2 (clock-sync)
192 self
.outpipe
= TestMuxOutPipe(num_rows
) # fan-out (combinatorial)
194 self
.p
= self
.inpipe
.p
# kinda annoying,
195 self
.n
= self
.outpipe
.n
# use pipe in/out as this class in/out
196 self
._ports
= self
.inpipe
.ports() + self
.outpipe
.ports()
198 def elaborate(self
, platform
):
200 m
.submodules
.inpipe
= self
.inpipe
201 m
.submodules
.pipe1
= self
.pipe1
202 m
.submodules
.pipe2
= self
.pipe2
203 m
.submodules
.outpipe
= self
.outpipe
205 m
.d
.comb
+= self
.inpipe
.n
.connect_to_next(self
.pipe1
.p
)
206 m
.d
.comb
+= self
.pipe1
.connect_to_next(self
.pipe2
)
207 m
.d
.comb
+= self
.pipe2
.connect_to_next(self
.outpipe
)
215 if __name__
== '__main__':
216 dut
= TestInOutPipe()
217 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
218 with
open("test_inoutmux_pipe.il", "w") as f
:
220 #run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
222 test
= InputTest(dut
)
223 run_simulation(dut
, [test
.rcv(1), test
.rcv(0),
224 test
.rcv(3), test
.rcv(2),
225 test
.send(0), test
.send(1),
226 test
.send(3), test
.send(2),
228 vcd_name
="test_inoutmux_pipe.vcd")