08b9a6112bf22b668e0f1270af2cedf001cba9ca
1 # just... don't ask. MSB0 is a massive pain in the neck.
2 # this module, aside from creating various field constants,
3 # helps out by creating alternative (identical) classes with
4 # a "b" name to indicate "MSB0 big-endian".
7 # sigh create little-ended versions of bitfield flags
8 def botchify(bekls
, lekls
, msb
=63):
9 for attr
in dir(bekls
):
12 setattr(lekls
, attr
, msb
-getattr(bekls
, attr
))
15 # Can't think of a better place to put these functions.
16 # Return an arbitrary subfield of a larger field.
17 def field_slice(msb0_start
, msb0_end
, field_width
=64):
20 Answers with a subfield slice of the signal r ("register"),
21 where the start and end bits use IBM "MSB 0" conventions.
23 see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
25 * assertion: msb0_start < msb0_end.
26 * The range specified is inclusive on both ends.
27 * field_width specifies the total number of bits (note: not bits-1)
29 if msb0_start
>= msb0_end
:
31 "start ({}) must be less than end ({})".format(msb0_start
, msb0_end
)
33 # sigh. MSB0 (IBM numbering) is inverted. converting to python
34 # we *swap names* so as not to get confused by having "end, start"
35 lsb0_end
= (field_width
-1) - msb0_start
36 lsb0_start
= (field_width
-1) - msb0_end
38 return slice(lsb0_start
, lsb0_end
+ 1)
41 def field(r
, msb0_start
, msb0_end
=None, field_width
=64):
42 """Answers with a subfield of the signal r ("register"), where
43 the start and end bits use IBM conventions. start < end, if
44 end is provided. The range specified is inclusive on both ends.
46 Answers with a subfield of the signal r ("register"),
47 where the start and end bits use IBM "MSB 0" conventions.
48 If end is not provided, a single bit subfield is returned.
50 see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
52 * assertion: msb0_start < msb0_end.
53 * The range specified is inclusive on both ends.
54 * field_width specifies the total number of bits (note: not bits-1)
58 comb += field(insn, 0, 6, field_width=32).eq(17)
59 # NOTE: NEVER DIRECTLY ACCESS OPCODE FIELDS IN INSTRUCTIONS.
60 # This example is purely for illustrative purposes only.
61 # Use self.fields.FormXYZ.etcetc instead.
63 comb += field(msr, MSRb.TEs, MSRb.TEe).eq(0)
65 Proof by substitution:
67 field(insn, 0, 6, field_width=32).eq(17)
68 == insn[field_slice(0, 6, field_width=32)].eq(17)
69 == insn[slice((31-6), (31-0)+1)].eq(17)
70 == insn[slice(25, 32)].eq(17)
73 field(msr, MSRb.TEs, MSRb.TEe).eq(0)
74 == field(msr, 53, 54).eq(0)
75 == msr[field_slice(53, 54)].eq(0)
76 == msr[slice((63-54), (63-53)+1)].eq(0) # note cross-over!
77 == msr[slice(9, 11)].eq(0)
81 return r
[(field_width
- 1) - msb0_start
]
83 return r
[field_slice(msb0_start
, msb0_end
, field_width
)]
86 # Listed in V3.0B Book III Chap 4.2.1
87 # MSR bit numbers, *bigendian* order (PowerISA format)
88 # use this in the simulator
90 SF
= 0 # Sixty-Four bit mode
91 HV
= 3 # Hypervisor state
92 UND
= 5 # Undefined behavior state (see Bk 2, Sect. 3.2.1)
93 TSs
= 29 # Transactional State (subfield)
94 TSe
= 30 # Transactional State (subfield)
95 TM
= 31 # Transactional Memory Available
96 VEC
= 38 # Vector Available
97 VSX
= 40 # VSX Available
99 EE
= 48 # External interrupt Enable
100 PR
= 49 # PRoblem state
101 FP
= 50 # FP available
102 ME
= 51 # Machine Check int enable
103 FE0
= 52 # Floating-Point Exception Mode 0
104 TEs
= 53 # Trace Enable (subfield)
105 TEe
= 54 # Trace Enable (subfield)
106 FE1
= 55 # Floating-Point Exception Mode 1
107 IR
= 58 # Instruction Relocation
108 DR
= 59 # Data Relocation
109 PMM
= 60 # Performance Monitor Mark
110 RI
= 62 # Recoverable Interrupt
111 LE
= 63 # Little Endian
113 # use this inside the HDL (where everything is little-endian)
119 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
121 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
123 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
124 # to expand traptype to cope with the increased range
126 # use this in the simulator
128 INVALID
= 33 # 1 for an invalid mem err
129 PERMERR
= 35 # 1 for an permanent mem err
130 TM_BAD_THING
= 42 # 1 for a TM Bad Thing type interrupt
131 FP
= 43 # 1 if FP exception
132 ILLEG
= 44 # 1 if illegal instruction (not doing hypervisor)
133 PRIV
= 45 # 1 if privileged interrupt
134 TRAP
= 46 # 1 if exception is "trap" type
135 ADR
= 47 # 0 if SRR0 = address of instruction causing exception
137 # and use this in the HDL
143 # see traptype (and trap main_stage.py)
144 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
145 # to expand traptype to cope with the increased range
152 EINT
= 1<<4 # external interrupt
153 DEC
= 1<<5 # decrement counter
154 MEMEXC
= 1<<6 # LD/ST exception
155 ILLEG
= 1<<7 # currently the max
156 # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
157 size
= 8 # MUST update this to contain the full number of Trap Types
160 # EXTRA3 3-bit subfield (spec)
162 VEC
= 0 # 1 for vector, 0 for scalar
163 MSB
= 1 # augmented register number, MSB
164 LSB
= 2 # augmented register number, LSB
168 SPEC_AUG_SIZE
= 2 # augmented subfield size (MSB+LSB above)
171 botchify(SPECb
, SPEC
, SPEC_SIZE
-1)
174 # EXTRA field, with EXTRA2 subfield encoding
190 botchify(EXTRA2b
, EXTRA2
, EXTRA2_SIZE
-1)
193 # EXTRA field, with EXTRA3 subfield encoding
204 # SVP64 ReMapped Field (from v3.1 EXT001 Prefix)
208 RM
= [6, 8] + list(range(10, 32))
216 CR0
= 0 # TODO: increase when CRs are expanded to 128
217 CR1
= 1 # TODO: increase when CRs are expanded to 128
218 CRPred
= 4 # TODO: increase when CRs are expanded to 128
225 LDST_SHIFT
= 2 # set =1 for shift mode
226 # when predicate not set: 0=ignore/skip 1=zero
227 DZ
= 3 # for destination
229 # for branch-conditional
230 BC_SNZ
= 3 # for branch-conditional mode
231 BC_VLI
= 2 # for VL include/exclude on VLSET mode
233 REDUCE
= 2 # 0=normal predication 1=reduce mode
234 PARALLEL
= 3 # 1=parallel reduce, 0=scalar reduce
235 SVM
= 3 # subvector reduce mode 0=independent 1=horizontal
236 CRM
= 4 # CR mode on reduce (Rc=1) 0=some 1=all
237 RG
= 4 # Reverse-gear on reduce
239 N
= 2 # saturation signed mode 0=signed 1=unsigned
240 # ffirst and predicate result modes
241 INV
= 2 # invert CR sense 0=set 1=unset
242 CR_MSB
= 3 # CR bit to update (with Rc=1)
244 RC1
= 4 # update CR as if Rc=1 (when Rc=0)
245 # LD immediate els (element-stride) locations, depending on mode
261 botchify(SVP64MODEb
, SVP64MODE
, SVP64MODE_SIZE
-1)
263 # add subfields to use with nmutil.sel
264 SVP64MODE
.MOD2
= [0, 1]
265 SVP64MODE
.CR
= [3, 4]
283 botchify(CRb
, CR
, CR_SIZE
-1)
286 # POWER9 Register Files
287 # XXX these are specific to Libre-SOC's decoder. really, they
288 # should be in libre-soc. however... long story: because the
289 # PowerDecoder2 has been moved to openpower-isa, and its decoding
290 # depends on that, then... whoops.
297 N_REGS
= 3 # maximum number of regs
306 XER
= 5 # non-XER bits
310 N_REGS
= 9 # maximum number of regs
314 SO
=0 # this is actually 2-bit but we ignore 1 bit of it
317 N_REGS
= 3 # maximum number of regs