src/openpower/decoder/decode2execute1.py

   1 """Decode2ToExecute1Type
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Signal, Record
   7 from nmutil.iocontrol import RecordObject
   8 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
   9                                      SPRfull, SPRreduced, LDSTMode)
  10 from openpower.consts import TT
  11 from openpower.exceptions import LDSTException
  12 from openpower.decoder.power_svp64_rm import sv_input_record_layout
  13
  14 from openpower.util import log
  15
  16 class Data(Record):
  17
  18     def __init__(self, width, name):
  19         name_ok = "%s_ok" % name
  20         layout = ((name, width), (name_ok, 1))
  21         Record.__init__(self, layout)
  22         self.data = getattr(self, name) # convenience
  23         self.ok = getattr(self, name_ok) # convenience
  24         self.data.reset_less = True # grrr
  25         self.reset_less = True # grrr
  26
  27     def ports(self):
  28         return [self.data, self.ok]
  29
  30
  31 class IssuerDecode2ToOperand(RecordObject):
  32     """IssuerDecode2ToOperand
  33
  34     contains the subset of fields needed for Issuer to decode the instruction
  35     and get register rdflags signals set up.  it also doubles up as the
  36     "Trap" temporary store, because part of the Decoder's job is to
  37     identify whether a trap / interrupt / exception should occur.
  38     """
  39
  40     def __init__(self, name=None):
  41
  42         RecordObject.__init__(self, layout=sv_input_record_layout,
  43                                     name=name)
  44
  45         # current "state" (TODO: this in its own Record)
  46         self.msr = Signal(64, reset_less=True)
  47         self.cia = Signal(64, reset_less=True)
  48         self.svstate = Signal(32, reset_less=True)
  49
  50         # instruction, type and decoded information
  51         self.insn = Signal(32, reset_less=True) # original instruction
  52         self.insn_type = Signal(MicrOp, reset_less=True)
  53         self.fn_unit = Signal(Function, reset_less=True)
  54         self.lk = Signal(reset_less=True)
  55         self.rc = Data(1, "rc")
  56         self.oe = Data(1, "oe")
  57         self.input_carry = Signal(CryIn, reset_less=True)
  58         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
  59         self.ldst_exc  = LDSTException("exc")
  60         self.trapaddr  = Signal(13, reset_less=True)
  61         self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
  62         self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
  63         self.is_32bit = Signal(reset_less=True)
  64
  65
  66 class Decode2ToOperand(IssuerDecode2ToOperand):
  67
  68     def __init__(self, name=None):
  69
  70         IssuerDecode2ToOperand.__init__(self, name=name)
  71
  72         # instruction, type and decoded information
  73         self.imm_data = Data(64, name="imm")
  74         self.invert_in = Signal(reset_less=True)
  75         self.zero_a = Signal(reset_less=True)
  76         self.output_carry = Signal(reset_less=True)
  77         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
  78         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
  79         self.invert_out = Signal(reset_less=True)
  80         self.is_32bit = Signal(reset_less=True)
  81         self.is_signed = Signal(reset_less=True)
  82         self.data_len = Signal(4, reset_less=True) # bytes
  83         self.byte_reverse  = Signal(reset_less=True)
  84         self.sign_extend  = Signal(reset_less=True)# do we need this?
  85         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
  86         self.write_cr0 = Signal(reset_less=True)
  87
  88
  89 class Decode2ToExecute1Type(RecordObject):
  90
  91     def __init__(self, name=None, asmcode=True, opkls=None, do=None,
  92                        regreduce_en=False):
  93
  94         if regreduce_en:
  95             SPR = SPRreduced
  96         else:
  97             SPR = SPRfull
  98
  99         if do is None and opkls is None:
 100             opkls = Decode2ToOperand
 101
 102         RecordObject.__init__(self, name=name)
 103
 104         if asmcode:
 105             self.asmcode = Signal(8, reset_less=True) # only for simulator
 106         self.write_reg = Data(7, name="rego")
 107         self.write_ea = Data(7, name="ea") # for LD/ST in update mode
 108         self.read_reg1 = Data(7, name="reg1")
 109         self.read_reg2 = Data(7, name="reg2")
 110         self.read_reg3 = Data(7, name="reg3")
 111         self.write_spr = Data(SPR, name="spro")
 112         self.read_spr1 = Data(SPR, name="spr1")
 113         #self.read_spr2 = Data(SPR, name="spr2") # only one needed
 114
 115         self.xer_in = Signal(3, reset_less=True)   # xer might be read
 116         self.xer_out = Signal(reset_less=True)  # xer might be written
 117
 118         # for the FAST regs (SRR1, SRR2, SVSRR0, CTR, LR etc.)
 119         self.read_fast1 = Data(3, name="fast1")
 120         self.read_fast2 = Data(3, name="fast2")
 121         self.read_fast3 = Data(3, name="fast3")   # really only for SVSRR0
 122         self.write_fast1 = Data(3, name="fasto1")
 123         self.write_fast2 = Data(3, name="fasto2")
 124         self.write_fast3 = Data(3, name="fasto3") # likewise
 125
 126         self.read_cr1 = Data(7, name="cr_in1")
 127         self.read_cr2 = Data(7, name="cr_in2")
 128         self.read_cr3 = Data(7, name="cr_in2")
 129         self.write_cr = Data(7, name="cr_out")
 130
 131         # decode operand data
 132         log ("decode2execute init", name, opkls, do)
 133         #assert name is not None, str(opkls)
 134         if do is not None:
 135             self.do = do
 136         else:
 137             self.do = opkls(name)