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[openpower-isa.git] / src / openpower / decoder / isa / caller.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020 Michael Nolan
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
14 """
15
16 from collections import namedtuple
17 from copy import deepcopy
18 from functools import wraps
19 import os
20 import errno
21 import struct
22 from openpower.syscalls import ppc_flags
23 import sys
24 from elftools.elf.elffile import ELFFile # for isinstance
25
26 from nmigen.sim import Settle
27 import openpower.syscalls
28 from openpower.consts import (MSRb, PIb, # big-endian (PowerISA versions)
29 SVP64CROffs, SVP64MODEb)
30 from openpower.decoder.helpers import (ISACallerHelper, ISAFPHelpers, exts,
31 gtu, undefined, copy_assign_rhs)
32 from openpower.decoder.isa.mem import Mem, MemMMap, MemException, LoadedELF
33 from openpower.decoder.isa.radixmmu import RADIX
34 from openpower.decoder.isa.svshape import SVSHAPE
35 from openpower.decoder.isa.svstate import SVP64State
36 from openpower.decoder.orderedset import OrderedSet
37 from openpower.decoder.power_enums import (FPTRANS_INSNS, CRInSel, CROutSel,
38 In1Sel, In2Sel, In3Sel, LDSTMode,
39 MicrOp, OutSel, SVMode,
40 SVP64LDSTmode, SVP64PredCR,
41 SVP64PredInt, SVP64PredMode,
42 SVP64RMMode, SVPType, XER_bits,
43 insns, spr_byname, spr_dict,
44 BFP_FLAG_NAMES)
45 from openpower.insndb.core import SVP64Instruction
46 from openpower.decoder.power_svp64 import SVP64RM, decode_extra
47 from openpower.decoder.selectable_int import (FieldSelectableInt,
48 SelectableInt, selectconcat,
49 EFFECTIVELY_UNLIMITED)
50 from openpower.consts import DEFAULT_MSR
51 from openpower.fpscr import FPSCRState
52 from openpower.xer import XERState
53 from openpower.util import LogType, log
54
55 LDST_UPDATE_INSNS = ['ldu', 'lwzu', 'lbzu', 'lhzu', 'lhau', 'lfsu', 'lfdu',
56 'stwu', 'stbu', 'sthu', 'stfsu', 'stfdu', 'stdu',
57 ]
58
59
60 instruction_info = namedtuple('instruction_info',
61 'func read_regs uninit_regs write_regs ' +
62 'special_regs op_fields form asmregs')
63
64 special_sprs = {
65 'LR': 8,
66 'CTR': 9,
67 'TAR': 815,
68 'XER': 1,
69 'VRSAVE': 256}
70
71
72 # rrright. this is here basically because the compiler pywriter returns
73 # results in a specific priority order. to make sure regs match up they
74 # need partial sorting. sigh.
75 REG_SORT_ORDER = {
76 # TODO (lkcl): adjust other registers that should be in a particular order
77 # probably CA, CA32, and CR
78 "FRT": 0,
79 "FRA": 0,
80 "FRB": 0,
81 "FRC": 0,
82 "FRS": 0,
83 "RT": 0,
84 "RA": 0,
85 "RB": 0,
86 "RC": 0,
87 "RS": 0,
88 "BI": 0,
89 "CR": 0,
90 "LR": 0,
91 "CTR": 0,
92 "TAR": 0,
93 "MSR": 0,
94 "SVSTATE": 0,
95 "SVSHAPE0": 0,
96 "SVSHAPE1": 0,
97 "SVSHAPE2": 0,
98 "SVSHAPE3": 0,
99
100 "CA": 0,
101 "CA32": 0,
102
103 "FPSCR": 1,
104
105 "overflow": 7, # should definitely be last
106 "CR0": 8, # likewise
107 }
108
109 fregs = ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
110
111
112 def get_masked_reg(regs, base, offs, ew_bits):
113 # rrrright. start by breaking down into row/col, based on elwidth
114 gpr_offs = offs // (64 // ew_bits)
115 gpr_col = offs % (64 // ew_bits)
116 # compute the mask based on ew_bits
117 mask = (1 << ew_bits) - 1
118 # now select the 64-bit register, but get its value (easier)
119 val = regs[base + gpr_offs]
120 # shift down so element we want is at LSB
121 val >>= gpr_col * ew_bits
122 # mask so we only return the LSB element
123 return val & mask
124
125
126 def set_masked_reg(regs, base, offs, ew_bits, value):
127 # rrrright. start by breaking down into row/col, based on elwidth
128 gpr_offs = offs // (64//ew_bits)
129 gpr_col = offs % (64//ew_bits)
130 # compute the mask based on ew_bits
131 mask = (1 << ew_bits)-1
132 # now select the 64-bit register, but get its value (easier)
133 val = regs[base+gpr_offs]
134 # now mask out the bit we don't want
135 val = val & ~(mask << (gpr_col*ew_bits))
136 # then wipe the bit we don't want from the value
137 value = value & mask
138 # OR the new value in, shifted up
139 val |= value << (gpr_col*ew_bits)
140 regs[base+gpr_offs] = val
141
142
143 def create_args(reglist, extra=None):
144 retval = list(OrderedSet(reglist))
145 retval.sort(key=lambda reg: REG_SORT_ORDER.get(reg, 0))
146 if extra is not None:
147 return [extra] + retval
148 return retval
149
150
151 def create_full_args(*, read_regs, special_regs, uninit_regs, write_regs,
152 extra=None):
153 return create_args([
154 *read_regs, *uninit_regs, *write_regs, *special_regs], extra=extra)
155
156
157 def is_ffirst_mode(dec2):
158 rm_mode = yield dec2.rm_dec.mode
159 return rm_mode == SVP64RMMode.FFIRST.value
160
161
162 class GPR(dict):
163 def __init__(self, decoder, isacaller, svstate, regfile):
164 dict.__init__(self)
165 self.sd = decoder
166 self.isacaller = isacaller
167 self.svstate = svstate
168 for i in range(len(regfile)):
169 self[i] = SelectableInt(regfile[i], 64)
170
171 def __call__(self, ridx, is_vec=False, offs=0, elwidth=64):
172 if isinstance(ridx, SelectableInt):
173 ridx = ridx.value
174 if elwidth == 64:
175 return self[ridx+offs]
176 # rrrright. start by breaking down into row/col, based on elwidth
177 gpr_offs = offs // (64//elwidth)
178 gpr_col = offs % (64//elwidth)
179 # now select the 64-bit register, but get its value (easier)
180 val = self[ridx+gpr_offs].value
181 # now shift down and mask out
182 val = val >> (gpr_col*elwidth) & ((1 << elwidth)-1)
183 # finally, return a SelectableInt at the required elwidth
184 log("GPR call", ridx, "isvec", is_vec, "offs", offs,
185 "elwid", elwidth, "offs/col", gpr_offs, gpr_col, "val", hex(val))
186 return SelectableInt(val, elwidth)
187
188 def set_form(self, form):
189 self.form = form
190
191 def write(self, rnum, value, is_vec=False, elwidth=64):
192 # get internal value
193 if isinstance(rnum, SelectableInt):
194 rnum = rnum.value
195 if isinstance(value, SelectableInt):
196 value = value.value
197 # compatibility...
198 if isinstance(rnum, tuple):
199 rnum, base, offs = rnum
200 else:
201 base, offs = rnum, 0
202 # rrrright. start by breaking down into row/col, based on elwidth
203 gpr_offs = offs // (64//elwidth)
204 gpr_col = offs % (64//elwidth)
205 # compute the mask based on elwidth
206 mask = (1 << elwidth)-1
207 # now select the 64-bit register, but get its value (easier)
208 val = self[base+gpr_offs].value
209 # now mask out the bit we don't want
210 val = val & ~(mask << (gpr_col*elwidth))
211 # then wipe the bit we don't want from the value
212 value = value & mask
213 # OR the new value in, shifted up
214 val |= value << (gpr_col*elwidth)
215 # finally put the damn value into the regfile
216 log("GPR write", base, "isvec", is_vec, "offs", offs,
217 "elwid", elwidth, "offs/col", gpr_offs, gpr_col, "val", hex(val),
218 "@", base+gpr_offs)
219 dict.__setitem__(self, base+gpr_offs, SelectableInt(val, 64))
220
221 def __setitem__(self, rnum, value):
222 # rnum = rnum.value # only SelectableInt allowed
223 log("GPR setitem", rnum, value)
224 if isinstance(rnum, SelectableInt):
225 rnum = rnum.value
226 dict.__setitem__(self, rnum, value)
227
228 def getz(self, rnum, rvalue=None):
229 # rnum = rnum.value # only SelectableInt allowed
230 log("GPR getzero?", rnum, rvalue)
231 if rvalue is not None:
232 if rnum == 0:
233 return SelectableInt(0, rvalue.bits)
234 return rvalue
235 if rnum == 0:
236 return SelectableInt(0, 64)
237 return self[rnum]
238
239 def _get_regnum(self, attr):
240 getform = self.sd.sigforms[self.form]
241 rnum = getattr(getform, attr)
242 return rnum
243
244 def ___getitem__(self, attr):
245 """ XXX currently not used
246 """
247 rnum = self._get_regnum(attr)
248 log("GPR getitem", attr, rnum)
249 return self.regfile[rnum]
250
251 def dump(self, printout=True):
252 res = []
253 for i in range(len(self)):
254 res.append(self[i].value)
255 if printout:
256 for i in range(0, len(res), 8):
257 s = []
258 for j in range(8):
259 s.append("%08x" % res[i+j])
260 s = ' '.join(s)
261 log("reg", "%2d" % i, s, kind=LogType.InstrInOuts)
262 return res
263
264
265 class SPR(dict):
266 def __init__(self, dec2, initial_sprs={}, gpr=None):
267 self.sd = dec2
268 self.gpr = gpr # for SVSHAPE[0-3]
269 dict.__init__(self)
270 for key, v in initial_sprs.items():
271 if isinstance(key, SelectableInt):
272 key = key.value
273 key = special_sprs.get(key, key)
274 if isinstance(key, int):
275 info = spr_dict[key]
276 else:
277 info = spr_byname[key]
278 if not isinstance(v, SelectableInt):
279 v = SelectableInt(v, info.length)
280 self[key] = v
281
282 def __getitem__(self, key):
283 #log("get spr", key)
284 #log("dict", self.items())
285 # if key in special_sprs get the special spr, otherwise return key
286 if isinstance(key, SelectableInt):
287 key = key.value
288 if isinstance(key, int):
289 key = spr_dict[key].SPR
290 key = special_sprs.get(key, key)
291 if key == 'HSRR0': # HACK!
292 key = 'SRR0'
293 if key == 'HSRR1': # HACK!
294 key = 'SRR1'
295 if key in self:
296 res = dict.__getitem__(self, key)
297 else:
298 if isinstance(key, int):
299 info = spr_dict[key]
300 else:
301 info = spr_byname[key]
302 self[key] = SelectableInt(0, info.length)
303 res = dict.__getitem__(self, key)
304 #log("spr returning", key, res)
305 return res
306
307 def __setitem__(self, key, value):
308 if isinstance(key, SelectableInt):
309 key = key.value
310 if isinstance(key, int):
311 key = spr_dict[key].SPR
312 log("spr key", key)
313 key = special_sprs.get(key, key)
314 if key == 'HSRR0': # HACK!
315 self.__setitem__('SRR0', value)
316 if key == 'HSRR1': # HACK!
317 self.__setitem__('SRR1', value)
318 if key == 1:
319 value = XERState(value)
320 if key in ('SVSHAPE0', 'SVSHAPE1', 'SVSHAPE2', 'SVSHAPE3'):
321 value = SVSHAPE(value, self.gpr)
322 log("setting spr", key, value)
323 dict.__setitem__(self, key, value)
324
325 def __call__(self, ridx):
326 return self[ridx]
327
328 def dump(self, printout=True):
329 res = []
330 keys = list(self.keys())
331 # keys.sort()
332 for k in keys:
333 sprname = spr_dict.get(k, None)
334 if sprname is None:
335 sprname = k
336 else:
337 sprname = sprname.SPR
338 res.append((sprname, self[k].value))
339 if printout:
340 for sprname, value in res:
341 print(" ", sprname, hex(value))
342 return res
343
344
345 class PC:
346 def __init__(self, pc_init=0):
347 self.CIA = SelectableInt(pc_init, 64)
348 self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
349
350 def update_nia(self, is_svp64):
351 increment = 8 if is_svp64 else 4
352 self.NIA = self.CIA + SelectableInt(increment, 64)
353
354 def update(self, namespace, is_svp64):
355 """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
356 """
357 self.CIA = namespace['NIA'].narrow(64)
358 self.update_nia(is_svp64)
359 namespace['CIA'] = self.CIA
360 namespace['NIA'] = self.NIA
361
362
363 # CR register fields
364 # See PowerISA Version 3.0 B Book 1
365 # Section 2.3.1 Condition Register pages 30 - 31
366 class CRFields:
367 LT = FL = 0 # negative, less than, floating-point less than
368 GT = FG = 1 # positive, greater than, floating-point greater than
369 EQ = FE = 2 # equal, floating-point equal
370 SO = FU = 3 # summary overflow, floating-point unordered
371
372 def __init__(self, init=0):
373 # rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
374 # self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
375 self.cr = SelectableInt(init, 64) # underlying reg
376 # field-selectable versions of Condition Register TODO check bitranges?
377 self.crl = []
378 for i in range(8):
379 bits = tuple(range(i*4+32, (i+1)*4+32))
380 _cr = FieldSelectableInt(self.cr, bits)
381 self.crl.append(_cr)
382
383
384 # decode SVP64 predicate integer to reg number and invert
385 def get_predint(gpr, mask):
386 r3 = gpr(3)
387 r10 = gpr(10)
388 r30 = gpr(30)
389 log("get_predint", mask, SVP64PredInt.ALWAYS.value)
390 if mask == SVP64PredInt.ALWAYS.value:
391 return 0xffff_ffff_ffff_ffff # 64 bits of 1
392 if mask == SVP64PredInt.R3_UNARY.value:
393 return 1 << (r3.value & 0b111111)
394 if mask == SVP64PredInt.R3.value:
395 return r3.value
396 if mask == SVP64PredInt.R3_N.value:
397 return ~r3.value
398 if mask == SVP64PredInt.R10.value:
399 return r10.value
400 if mask == SVP64PredInt.R10_N.value:
401 return ~r10.value
402 if mask == SVP64PredInt.R30.value:
403 return r30.value
404 if mask == SVP64PredInt.R30_N.value:
405 return ~r30.value
406
407
408 # decode SVP64 predicate CR to reg number and invert status
409 def _get_predcr(mask):
410 if mask == SVP64PredCR.LT.value:
411 return 0, 1
412 if mask == SVP64PredCR.GE.value:
413 return 0, 0
414 if mask == SVP64PredCR.GT.value:
415 return 1, 1
416 if mask == SVP64PredCR.LE.value:
417 return 1, 0
418 if mask == SVP64PredCR.EQ.value:
419 return 2, 1
420 if mask == SVP64PredCR.NE.value:
421 return 2, 0
422 if mask == SVP64PredCR.SO.value:
423 return 3, 1
424 if mask == SVP64PredCR.NS.value:
425 return 3, 0
426
427
428 # read individual CR fields (0..VL-1), extract the required bit
429 # and construct the mask
430 def get_predcr(crl, mask, vl):
431 idx, noninv = _get_predcr(mask)
432 mask = 0
433 for i in range(vl):
434 cr = crl[i+SVP64CROffs.CRPred]
435 if cr[idx].value == noninv:
436 mask |= (1 << i)
437 return mask
438
439
440 # TODO, really should just be using PowerDecoder2
441 def get_idx_map(dec2, name):
442 op = dec2.dec.op
443 in1_sel = yield op.in1_sel
444 in2_sel = yield op.in2_sel
445 in3_sel = yield op.in3_sel
446 in1 = yield dec2.e.read_reg1.data
447 # identify which regnames map to in1/2/3
448 if name == 'RA' or name == 'RA_OR_ZERO':
449 if (in1_sel == In1Sel.RA.value or
450 (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
451 return 1
452 if in1_sel == In1Sel.RA_OR_ZERO.value:
453 return 1
454 elif name == 'RB':
455 if in2_sel == In2Sel.RB.value:
456 return 2
457 if in3_sel == In3Sel.RB.value:
458 return 3
459 # XXX TODO, RC doesn't exist yet!
460 elif name == 'RC':
461 if in3_sel == In3Sel.RC.value:
462 return 3
463 elif name in ['EA', 'RS']:
464 if in1_sel == In1Sel.RS.value:
465 return 1
466 if in2_sel == In2Sel.RS.value:
467 return 2
468 if in3_sel == In3Sel.RS.value:
469 return 3
470 elif name == 'FRA':
471 if in1_sel == In1Sel.FRA.value:
472 return 1
473 if in3_sel == In3Sel.FRA.value:
474 return 3
475 elif name == 'FRB':
476 if in2_sel == In2Sel.FRB.value:
477 return 2
478 elif name == 'FRC':
479 if in3_sel == In3Sel.FRC.value:
480 return 3
481 elif name == 'FRS':
482 if in1_sel == In1Sel.FRS.value:
483 return 1
484 if in3_sel == In3Sel.FRS.value:
485 return 3
486 elif name == 'FRT':
487 if in1_sel == In1Sel.FRT.value:
488 return 1
489 elif name == 'RT':
490 if in1_sel == In1Sel.RT.value:
491 return 1
492 return None
493
494
495 # TODO, really should just be using PowerDecoder2
496 def get_idx_in(dec2, name, ewmode=False):
497 idx = yield from get_idx_map(dec2, name)
498 if idx is None:
499 return None, False
500 op = dec2.dec.op
501 in1_sel = yield op.in1_sel
502 in2_sel = yield op.in2_sel
503 in3_sel = yield op.in3_sel
504 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
505 in1 = yield dec2.e.read_reg1.data
506 in2 = yield dec2.e.read_reg2.data
507 in3 = yield dec2.e.read_reg3.data
508 if ewmode:
509 in1_base = yield dec2.e.read_reg1.base
510 in2_base = yield dec2.e.read_reg2.base
511 in3_base = yield dec2.e.read_reg3.base
512 in1_offs = yield dec2.e.read_reg1.offs
513 in2_offs = yield dec2.e.read_reg2.offs
514 in3_offs = yield dec2.e.read_reg3.offs
515 in1 = (in1, in1_base, in1_offs)
516 in2 = (in2, in2_base, in2_offs)
517 in3 = (in3, in3_base, in3_offs)
518
519 in1_isvec = yield dec2.in1_isvec
520 in2_isvec = yield dec2.in2_isvec
521 in3_isvec = yield dec2.in3_isvec
522 log("get_idx_in in1", name, in1_sel, In1Sel.RA.value,
523 in1, in1_isvec)
524 log("get_idx_in in2", name, in2_sel, In2Sel.RB.value,
525 in2, in2_isvec)
526 log("get_idx_in in3", name, in3_sel, In3Sel.RS.value,
527 in3, in3_isvec)
528 log("get_idx_in FRS in3", name, in3_sel, In3Sel.FRS.value,
529 in3, in3_isvec)
530 log("get_idx_in FRB in2", name, in2_sel, In2Sel.FRB.value,
531 in2, in2_isvec)
532 log("get_idx_in FRC in3", name, in3_sel, In3Sel.FRC.value,
533 in3, in3_isvec)
534 if idx == 1:
535 return in1, in1_isvec
536 if idx == 2:
537 return in2, in2_isvec
538 if idx == 3:
539 return in3, in3_isvec
540 return None, False
541
542
543 # TODO, really should just be using PowerDecoder2
544 def get_cr_in(dec2, name):
545 op = dec2.dec.op
546 in_sel = yield op.cr_in
547 in_bitfield = yield dec2.dec_cr_in.cr_bitfield.data
548 sv_cr_in = yield op.sv_cr_in
549 spec = yield dec2.crin_svdec.spec
550 sv_override = yield dec2.dec_cr_in.sv_override
551 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
552 in1 = yield dec2.e.read_cr1.data
553 cr_isvec = yield dec2.cr_in_isvec
554 log("get_cr_in", in_sel, CROutSel.CR0.value, in1, cr_isvec)
555 log(" sv_cr_in", sv_cr_in)
556 log(" cr_bf", in_bitfield)
557 log(" spec", spec)
558 log(" override", sv_override)
559 # identify which regnames map to in / o2
560 if name == 'BI':
561 if in_sel == CRInSel.BI.value:
562 return in1, cr_isvec
563 log("get_cr_in not found", name)
564 return None, False
565
566
567 # TODO, really should just be using PowerDecoder2
568 def get_cr_out(dec2, name):
569 op = dec2.dec.op
570 out_sel = yield op.cr_out
571 out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
572 sv_cr_out = yield op.sv_cr_out
573 spec = yield dec2.crout_svdec.spec
574 sv_override = yield dec2.dec_cr_out.sv_override
575 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
576 out = yield dec2.e.write_cr.data
577 o_isvec = yield dec2.cr_out_isvec
578 log("get_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
579 log(" sv_cr_out", sv_cr_out)
580 log(" cr_bf", out_bitfield)
581 log(" spec", spec)
582 log(" override", sv_override)
583 # identify which regnames map to out / o2
584 if name == 'BF':
585 if out_sel == CROutSel.BF.value:
586 return out, o_isvec
587 if name == 'CR0':
588 if out_sel == CROutSel.CR0.value:
589 return out, o_isvec
590 if name == 'CR1': # these are not actually calculated correctly
591 if out_sel == CROutSel.CR1.value:
592 return out, o_isvec
593 # check RC1 set? if so return implicit vector, this is a REAL bad hack
594 RC1 = yield dec2.rm_dec.RC1
595 if RC1:
596 log("get_cr_out RC1 mode")
597 if name == 'CR0':
598 return 0, True # XXX TODO: offset CR0 from SVSTATE SPR
599 if name == 'CR1':
600 return 1, True # XXX TODO: offset CR1 from SVSTATE SPR
601 # nope - not found.
602 log("get_cr_out not found", name)
603 return None, False
604
605
606 # TODO, really should just be using PowerDecoder2
607 def get_out_map(dec2, name):
608 op = dec2.dec.op
609 out_sel = yield op.out_sel
610 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
611 out = yield dec2.e.write_reg.data
612 # identify which regnames map to out / o2
613 if name == 'RA':
614 if out_sel == OutSel.RA.value:
615 return True
616 elif name == 'RT':
617 if out_sel == OutSel.RT.value:
618 return True
619 if out_sel == OutSel.RT_OR_ZERO.value and out != 0:
620 return True
621 elif name == 'RT_OR_ZERO':
622 if out_sel == OutSel.RT_OR_ZERO.value:
623 return True
624 elif name == 'FRA':
625 if out_sel == OutSel.FRA.value:
626 return True
627 elif name == 'FRS':
628 if out_sel == OutSel.FRS.value:
629 return True
630 elif name == 'FRT':
631 if out_sel == OutSel.FRT.value:
632 return True
633 return False
634
635
636 # TODO, really should just be using PowerDecoder2
637 def get_idx_out(dec2, name, ewmode=False):
638 op = dec2.dec.op
639 out_sel = yield op.out_sel
640 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
641 out = yield dec2.e.write_reg.data
642 o_isvec = yield dec2.o_isvec
643 if ewmode:
644 offs = yield dec2.e.write_reg.offs
645 base = yield dec2.e.write_reg.base
646 out = (out, base, offs)
647 # identify which regnames map to out / o2
648 ismap = yield from get_out_map(dec2, name)
649 if ismap:
650 log("get_idx_out", name, out_sel, out, o_isvec)
651 return out, o_isvec
652 log("get_idx_out not found", name, out_sel, out, o_isvec)
653 return None, False
654
655
656 # TODO, really should just be using PowerDecoder2
657 def get_out2_map(dec2, name):
658 # check first if register is activated for write
659 op = dec2.dec.op
660 out_sel = yield op.out_sel
661 out = yield dec2.e.write_ea.data
662 out_ok = yield dec2.e.write_ea.ok
663 if not out_ok:
664 return False
665
666 if name in ['EA', 'RA']:
667 if hasattr(op, "upd"):
668 # update mode LD/ST uses read-reg A also as an output
669 upd = yield op.upd
670 log("get_idx_out2", upd, LDSTMode.update.value,
671 out_sel, OutSel.RA.value,
672 out)
673 if upd == LDSTMode.update.value:
674 return True
675 if name == 'RS':
676 fft_en = yield dec2.implicit_rs
677 if fft_en:
678 log("get_idx_out2", out_sel, OutSel.RS.value,
679 out)
680 return True
681 if name == 'FRS':
682 fft_en = yield dec2.implicit_rs
683 if fft_en:
684 log("get_idx_out2", out_sel, OutSel.FRS.value,
685 out)
686 return True
687 return False
688
689
690 # TODO, really should just be using PowerDecoder2
691 def get_idx_out2(dec2, name, ewmode=False):
692 # check first if register is activated for write
693 op = dec2.dec.op
694 out_sel = yield op.out_sel
695 out = yield dec2.e.write_ea.data
696 if ewmode:
697 offs = yield dec2.e.write_ea.offs
698 base = yield dec2.e.write_ea.base
699 out = (out, base, offs)
700 o_isvec = yield dec2.o2_isvec
701 ismap = yield from get_out2_map(dec2, name)
702 if ismap:
703 log("get_idx_out2", name, out_sel, out, o_isvec)
704 return out, o_isvec
705 return None, False
706
707
708 class StepLoop:
709 """deals with svstate looping.
710 """
711
712 def __init__(self, svstate):
713 self.svstate = svstate
714 self.new_iterators()
715
716 def new_iterators(self):
717 self.src_it = self.src_iterator()
718 self.dst_it = self.dst_iterator()
719 self.loopend = False
720 self.new_srcstep = 0
721 self.new_dststep = 0
722 self.new_ssubstep = 0
723 self.new_dsubstep = 0
724 self.pred_dst_zero = 0
725 self.pred_src_zero = 0
726
727 def src_iterator(self):
728 """source-stepping iterator
729 """
730 pack = self.svstate.pack
731
732 # source step
733 if pack:
734 # pack advances subvl in *outer* loop
735 while True: # outer subvl loop
736 while True: # inner vl loop
737 vl = self.svstate.vl
738 subvl = self.subvl
739 srcmask = self.srcmask
740 srcstep = self.svstate.srcstep
741 pred_src_zero = ((1 << srcstep) & srcmask) != 0
742 if self.pred_sz or pred_src_zero:
743 self.pred_src_zero = not pred_src_zero
744 log(" advance src", srcstep, vl,
745 self.svstate.ssubstep, subvl)
746 # yield actual substep/srcstep
747 yield (self.svstate.ssubstep, srcstep)
748 # the way yield works these could have been modified.
749 vl = self.svstate.vl
750 subvl = self.subvl
751 srcstep = self.svstate.srcstep
752 log(" advance src check", srcstep, vl,
753 self.svstate.ssubstep, subvl, srcstep == vl-1,
754 self.svstate.ssubstep == subvl)
755 if srcstep == vl-1: # end-point
756 self.svstate.srcstep = SelectableInt(0, 7) # reset
757 if self.svstate.ssubstep == subvl: # end-point
758 log(" advance pack stop")
759 return
760 break # exit inner loop
761 self.svstate.srcstep += SelectableInt(1, 7) # advance ss
762 subvl = self.subvl
763 if self.svstate.ssubstep == subvl: # end-point
764 self.svstate.ssubstep = SelectableInt(0, 2) # reset
765 log(" advance pack stop")
766 return
767 self.svstate.ssubstep += SelectableInt(1, 2)
768
769 else:
770 # these cannot be done as for-loops because SVSTATE may change
771 # (srcstep/substep may be modified, interrupted, subvl/vl change)
772 # but they *can* be done as while-loops as long as every SVSTATE
773 # "thing" is re-read every single time a yield gives indices
774 while True: # outer vl loop
775 while True: # inner subvl loop
776 vl = self.svstate.vl
777 subvl = self.subvl
778 srcmask = self.srcmask
779 srcstep = self.svstate.srcstep
780 pred_src_zero = ((1 << srcstep) & srcmask) != 0
781 if self.pred_sz or pred_src_zero:
782 self.pred_src_zero = not pred_src_zero
783 log(" advance src", srcstep, vl,
784 self.svstate.ssubstep, subvl)
785 # yield actual substep/srcstep
786 yield (self.svstate.ssubstep, srcstep)
787 if self.svstate.ssubstep == subvl: # end-point
788 self.svstate.ssubstep = SelectableInt(0, 2) # reset
789 break # exit inner loop
790 self.svstate.ssubstep += SelectableInt(1, 2)
791 vl = self.svstate.vl
792 if srcstep == vl-1: # end-point
793 self.svstate.srcstep = SelectableInt(0, 7) # reset
794 self.loopend = True
795 return
796 self.svstate.srcstep += SelectableInt(1, 7) # advance srcstep
797
798 def dst_iterator(self):
799 """dest-stepping iterator
800 """
801 unpack = self.svstate.unpack
802
803 # dest step
804 if unpack:
805 # pack advances subvl in *outer* loop
806 while True: # outer subvl loop
807 while True: # inner vl loop
808 vl = self.svstate.vl
809 subvl = self.subvl
810 dstmask = self.dstmask
811 dststep = self.svstate.dststep
812 pred_dst_zero = ((1 << dststep) & dstmask) != 0
813 if self.pred_dz or pred_dst_zero:
814 self.pred_dst_zero = not pred_dst_zero
815 log(" advance dst", dststep, vl,
816 self.svstate.dsubstep, subvl)
817 # yield actual substep/dststep
818 yield (self.svstate.dsubstep, dststep)
819 # the way yield works these could have been modified.
820 vl = self.svstate.vl
821 dststep = self.svstate.dststep
822 log(" advance dst check", dststep, vl,
823 self.svstate.ssubstep, subvl)
824 if dststep == vl-1: # end-point
825 self.svstate.dststep = SelectableInt(0, 7) # reset
826 if self.svstate.dsubstep == subvl: # end-point
827 log(" advance unpack stop")
828 return
829 break
830 self.svstate.dststep += SelectableInt(1, 7) # advance ds
831 subvl = self.subvl
832 if self.svstate.dsubstep == subvl: # end-point
833 self.svstate.dsubstep = SelectableInt(0, 2) # reset
834 log(" advance unpack stop")
835 return
836 self.svstate.dsubstep += SelectableInt(1, 2)
837 else:
838 # these cannot be done as for-loops because SVSTATE may change
839 # (dststep/substep may be modified, interrupted, subvl/vl change)
840 # but they *can* be done as while-loops as long as every SVSTATE
841 # "thing" is re-read every single time a yield gives indices
842 while True: # outer vl loop
843 while True: # inner subvl loop
844 subvl = self.subvl
845 dstmask = self.dstmask
846 dststep = self.svstate.dststep
847 pred_dst_zero = ((1 << dststep) & dstmask) != 0
848 if self.pred_dz or pred_dst_zero:
849 self.pred_dst_zero = not pred_dst_zero
850 log(" advance dst", dststep, self.svstate.vl,
851 self.svstate.dsubstep, subvl)
852 # yield actual substep/dststep
853 yield (self.svstate.dsubstep, dststep)
854 if self.svstate.dsubstep == subvl: # end-point
855 self.svstate.dsubstep = SelectableInt(0, 2) # reset
856 break
857 self.svstate.dsubstep += SelectableInt(1, 2)
858 subvl = self.subvl
859 vl = self.svstate.vl
860 if dststep == vl-1: # end-point
861 self.svstate.dststep = SelectableInt(0, 7) # reset
862 return
863 self.svstate.dststep += SelectableInt(1, 7) # advance dststep
864
865 def src_iterate(self):
866 """source-stepping iterator
867 """
868 subvl = self.subvl
869 vl = self.svstate.vl
870 pack = self.svstate.pack
871 unpack = self.svstate.unpack
872 ssubstep = self.svstate.ssubstep
873 end_ssub = ssubstep == subvl
874 end_src = self.svstate.srcstep == vl-1
875 log(" pack/unpack/subvl", pack, unpack, subvl,
876 "end", end_src,
877 "sub", end_ssub)
878 # first source step
879 srcstep = self.svstate.srcstep
880 srcmask = self.srcmask
881 if pack:
882 # pack advances subvl in *outer* loop
883 while True:
884 assert srcstep <= vl-1
885 end_src = srcstep == vl-1
886 if end_src:
887 if end_ssub:
888 self.loopend = True
889 else:
890 self.svstate.ssubstep += SelectableInt(1, 2)
891 srcstep = 0 # reset
892 break
893 else:
894 srcstep += 1 # advance srcstep
895 if not self.srcstep_skip:
896 break
897 if ((1 << srcstep) & srcmask) != 0:
898 break
899 else:
900 log(" sskip", bin(srcmask), bin(1 << srcstep))
901 else:
902 # advance subvl in *inner* loop
903 if end_ssub:
904 while True:
905 assert srcstep <= vl-1
906 end_src = srcstep == vl-1
907 if end_src: # end-point
908 self.loopend = True
909 srcstep = 0
910 break
911 else:
912 srcstep += 1
913 if not self.srcstep_skip:
914 break
915 if ((1 << srcstep) & srcmask) != 0:
916 break
917 else:
918 log(" sskip", bin(srcmask), bin(1 << srcstep))
919 self.svstate.ssubstep = SelectableInt(0, 2) # reset
920 else:
921 # advance ssubstep
922 self.svstate.ssubstep += SelectableInt(1, 2)
923
924 self.svstate.srcstep = SelectableInt(srcstep, 7)
925 log(" advance src", self.svstate.srcstep, self.svstate.ssubstep,
926 self.loopend)
927
928 def dst_iterate(self):
929 """dest step iterator
930 """
931 vl = self.svstate.vl
932 subvl = self.subvl
933 pack = self.svstate.pack
934 unpack = self.svstate.unpack
935 dsubstep = self.svstate.dsubstep
936 end_dsub = dsubstep == subvl
937 dststep = self.svstate.dststep
938 end_dst = dststep == vl-1
939 dstmask = self.dstmask
940 log(" pack/unpack/subvl", pack, unpack, subvl,
941 "end", end_dst,
942 "sub", end_dsub)
943 # now dest step
944 if unpack:
945 # unpack advances subvl in *outer* loop
946 while True:
947 assert dststep <= vl-1
948 end_dst = dststep == vl-1
949 if end_dst:
950 if end_dsub:
951 self.loopend = True
952 else:
953 self.svstate.dsubstep += SelectableInt(1, 2)
954 dststep = 0 # reset
955 break
956 else:
957 dststep += 1 # advance dststep
958 if not self.dststep_skip:
959 break
960 if ((1 << dststep) & dstmask) != 0:
961 break
962 else:
963 log(" dskip", bin(dstmask), bin(1 << dststep))
964 else:
965 # advance subvl in *inner* loop
966 if end_dsub:
967 while True:
968 assert dststep <= vl-1
969 end_dst = dststep == vl-1
970 if end_dst: # end-point
971 self.loopend = True
972 dststep = 0
973 break
974 else:
975 dststep += 1
976 if not self.dststep_skip:
977 break
978 if ((1 << dststep) & dstmask) != 0:
979 break
980 else:
981 log(" dskip", bin(dstmask), bin(1 << dststep))
982 self.svstate.dsubstep = SelectableInt(0, 2) # reset
983 else:
984 # advance ssubstep
985 self.svstate.dsubstep += SelectableInt(1, 2)
986
987 self.svstate.dststep = SelectableInt(dststep, 7)
988 log(" advance dst", self.svstate.dststep, self.svstate.dsubstep,
989 self.loopend)
990
991 def at_loopend(self):
992 """tells if this is the last possible element. uses the cached values
993 for src/dst-step and sub-steps
994 """
995 subvl = self.subvl
996 vl = self.svstate.vl
997 srcstep, dststep = self.new_srcstep, self.new_dststep
998 ssubstep, dsubstep = self.new_ssubstep, self.new_dsubstep
999 end_ssub = ssubstep == subvl
1000 end_dsub = dsubstep == subvl
1001 if srcstep == vl-1 and end_ssub:
1002 return True
1003 if dststep == vl-1 and end_dsub:
1004 return True
1005 return False
1006
1007 def advance_svstate_steps(self):
1008 """ advance sub/steps. note that Pack/Unpack *INVERTS* the order.
1009 TODO when Pack/Unpack is set, substep becomes the *outer* loop
1010 """
1011 self.subvl = yield self.dec2.rm_dec.rm_in.subvl
1012 if self.loopend: # huhn??
1013 return
1014 self.src_iterate()
1015 self.dst_iterate()
1016
1017 def read_src_mask(self):
1018 """read/update pred_sz and src mask
1019 """
1020 # get SVSTATE VL (oh and print out some debug stuff)
1021 vl = self.svstate.vl
1022 srcstep = self.svstate.srcstep
1023 ssubstep = self.svstate.ssubstep
1024
1025 # get predicate mask (all 64 bits)
1026 srcmask = 0xffff_ffff_ffff_ffff
1027
1028 pmode = yield self.dec2.rm_dec.predmode
1029 sv_ptype = yield self.dec2.dec.op.SV_Ptype
1030 srcpred = yield self.dec2.rm_dec.srcpred
1031 dstpred = yield self.dec2.rm_dec.dstpred
1032 pred_sz = yield self.dec2.rm_dec.pred_sz
1033 if pmode == SVP64PredMode.INT.value:
1034 srcmask = dstmask = get_predint(self.gpr, dstpred)
1035 if sv_ptype == SVPType.P2.value:
1036 srcmask = get_predint(self.gpr, srcpred)
1037 elif pmode == SVP64PredMode.CR.value:
1038 srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
1039 if sv_ptype == SVPType.P2.value:
1040 srcmask = get_predcr(self.crl, srcpred, vl)
1041 # work out if the ssubsteps are completed
1042 ssubstart = ssubstep == 0
1043 log(" pmode", pmode)
1044 log(" ptype", sv_ptype)
1045 log(" srcpred", bin(srcpred))
1046 log(" srcmask", bin(srcmask))
1047 log(" pred_sz", bin(pred_sz))
1048 log(" ssubstart", ssubstart)
1049
1050 # store all that above
1051 self.srcstep_skip = False
1052 self.srcmask = srcmask
1053 self.pred_sz = pred_sz
1054 self.new_ssubstep = ssubstep
1055 log(" new ssubstep", ssubstep)
1056 # until the predicate mask has a "1" bit... or we run out of VL
1057 # let srcstep==VL be the indicator to move to next instruction
1058 if not pred_sz:
1059 self.srcstep_skip = True
1060
1061 def read_dst_mask(self):
1062 """same as read_src_mask - check and record everything needed
1063 """
1064 # get SVSTATE VL (oh and print out some debug stuff)
1065 # yield Delay(1e-10) # make changes visible
1066 vl = self.svstate.vl
1067 dststep = self.svstate.dststep
1068 dsubstep = self.svstate.dsubstep
1069
1070 # get predicate mask (all 64 bits)
1071 dstmask = 0xffff_ffff_ffff_ffff
1072
1073 pmode = yield self.dec2.rm_dec.predmode
1074 reverse_gear = yield self.dec2.rm_dec.reverse_gear
1075 sv_ptype = yield self.dec2.dec.op.SV_Ptype
1076 dstpred = yield self.dec2.rm_dec.dstpred
1077 pred_dz = yield self.dec2.rm_dec.pred_dz
1078 if pmode == SVP64PredMode.INT.value:
1079 dstmask = get_predint(self.gpr, dstpred)
1080 elif pmode == SVP64PredMode.CR.value:
1081 dstmask = get_predcr(self.crl, dstpred, vl)
1082 # work out if the ssubsteps are completed
1083 dsubstart = dsubstep == 0
1084 log(" pmode", pmode)
1085 log(" ptype", sv_ptype)
1086 log(" dstpred", bin(dstpred))
1087 log(" dstmask", bin(dstmask))
1088 log(" pred_dz", bin(pred_dz))
1089 log(" dsubstart", dsubstart)
1090
1091 self.dststep_skip = False
1092 self.dstmask = dstmask
1093 self.pred_dz = pred_dz
1094 self.new_dsubstep = dsubstep
1095 log(" new dsubstep", dsubstep)
1096 if not pred_dz:
1097 self.dststep_skip = True
1098
1099 def svstate_pre_inc(self):
1100 """check if srcstep/dststep need to skip over masked-out predicate bits
1101 note that this is not supposed to do anything to substep,
1102 it is purely for skipping masked-out bits
1103 """
1104
1105 self.subvl = yield self.dec2.rm_dec.rm_in.subvl
1106 yield from self.read_src_mask()
1107 yield from self.read_dst_mask()
1108
1109 self.skip_src()
1110 self.skip_dst()
1111
1112 def skip_src(self):
1113
1114 srcstep = self.svstate.srcstep
1115 srcmask = self.srcmask
1116 pred_src_zero = self.pred_sz
1117 vl = self.svstate.vl
1118 # srcstep-skipping opportunity identified
1119 if self.srcstep_skip:
1120 # cannot do this with sv.bc - XXX TODO
1121 if srcmask == 0:
1122 self.loopend = True
1123 while (((1 << srcstep) & srcmask) == 0) and (srcstep != vl):
1124 log(" sskip", bin(1 << srcstep))
1125 srcstep += 1
1126
1127 # now work out if the relevant mask bits require zeroing
1128 if pred_src_zero:
1129 pred_src_zero = ((1 << srcstep) & srcmask) == 0
1130
1131 # store new srcstep / dststep
1132 self.new_srcstep = srcstep
1133 self.pred_src_zero = pred_src_zero
1134 log(" new srcstep", srcstep)
1135
1136 def skip_dst(self):
1137 # dststep-skipping opportunity identified
1138 dststep = self.svstate.dststep
1139 dstmask = self.dstmask
1140 pred_dst_zero = self.pred_dz
1141 vl = self.svstate.vl
1142 if self.dststep_skip:
1143 # cannot do this with sv.bc - XXX TODO
1144 if dstmask == 0:
1145 self.loopend = True
1146 while (((1 << dststep) & dstmask) == 0) and (dststep != vl):
1147 log(" dskip", bin(1 << dststep))
1148 dststep += 1
1149
1150 # now work out if the relevant mask bits require zeroing
1151 if pred_dst_zero:
1152 pred_dst_zero = ((1 << dststep) & dstmask) == 0
1153
1154 # store new srcstep / dststep
1155 self.new_dststep = dststep
1156 self.pred_dst_zero = pred_dst_zero
1157 log(" new dststep", dststep)
1158
1159
1160 class ExitSyscallCalled(Exception):
1161 pass
1162
1163
1164 class SyscallEmulator(openpower.syscalls.Dispatcher):
1165 def __init__(self, isacaller):
1166 self.__isacaller = isacaller
1167
1168 host = os.uname().machine
1169 bits = (64 if (sys.maxsize > (2**32)) else 32)
1170 host = openpower.syscalls.architecture(arch=host, bits=bits)
1171
1172 return super().__init__(guest="ppc64", host=host)
1173
1174 def __call__(self, identifier, *arguments):
1175 (identifier, *arguments) = map(int, (identifier, *arguments))
1176 return super().__call__(identifier, *arguments)
1177
1178 def sys_exit_group(self, status, *rest):
1179 self.__isacaller.halted = True
1180 raise ExitSyscallCalled(status)
1181
1182 def sys_write(self, fd, buf, count, *rest):
1183 buf = self.__isacaller.mem.get_ctypes(buf, count, is_write=False)
1184 try:
1185 return os.write(fd, buf)
1186 except OSError as e:
1187 return -e.errno
1188
1189 def sys_read(self, fd, buf, count, *rest):
1190 buf = self.__isacaller.mem.get_ctypes(buf, count, is_write=True)
1191 try:
1192 return os.readv(fd, [buf])
1193 except OSError as e:
1194 return -e.errno
1195
1196 def sys_mmap(self, addr, length, prot, flags, fd, offset, *rest):
1197 return self.__isacaller.mem.mmap_syscall(
1198 addr, length, prot, flags, fd, offset, is_mmap2=False)
1199
1200 def sys_mmap2(self, addr, length, prot, flags, fd, offset, *rest):
1201 return self.__isacaller.mem.mmap_syscall(
1202 addr, length, prot, flags, fd, offset, is_mmap2=True)
1203
1204 def sys_brk(self, addr, *rest):
1205 return self.__isacaller.mem.brk_syscall(addr)
1206
1207 def sys_munmap(self, addr, length, *rest):
1208 return -errno.ENOSYS # TODO: implement
1209
1210 def sys_mprotect(self, addr, length, prot, *rest):
1211 return -errno.ENOSYS # TODO: implement
1212
1213 def sys_pkey_mprotect(self, addr, length, prot, pkey, *rest):
1214 return -errno.ENOSYS # TODO: implement
1215
1216 def sys_openat(self, dirfd, pathname, flags, mode, *rest):
1217 try:
1218 path = self.__isacaller.mem.read_cstr(pathname)
1219 except (ValueError, MemException):
1220 return -errno.EFAULT
1221 try:
1222 if dirfd == ppc_flags.AT_FDCWD:
1223 return os.open(path, flags, mode)
1224 else:
1225 return os.open(path, flags, mode, dir_fd=dirfd)
1226 except OSError as e:
1227 return -e.errno
1228
1229 def _uname(self):
1230 uname = os.uname()
1231 sysname = b'Linux'
1232 nodename = uname.nodename.encode()
1233 release = b'5.6.0-1-powerpc64le'
1234 version = b'#1 SMP Debian 5.6.7-1 (2020-04-29)'
1235 machine = b'ppc64le'
1236 domainname = b''
1237 return sysname, nodename, release, version, machine, domainname
1238
1239 def sys_uname(self, buf, *rest):
1240 s = struct.Struct("<65s65s65s65s65s")
1241 try:
1242 buf = self.__isacaller.mem.get_ctypes(buf, s.size, is_write=True)
1243 except (ValueError, MemException):
1244 return -errno.EFAULT
1245 sysname, nodename, release, version, machine, domainname = \
1246 self._uname()
1247 s.pack_into(buf, 0, sysname, nodename, release, version, machine)
1248 return 0
1249
1250 def sys_newuname(self, buf, *rest):
1251 name_len = ppc_flags.__NEW_UTS_LEN + 1
1252 s = struct.Struct("<%ds%ds%ds%ds%ds%ds" % ((name_len,) * 6))
1253 try:
1254 buf = self.__isacaller.mem.get_ctypes(buf, s.size, is_write=True)
1255 except (ValueError, MemException):
1256 return -errno.EFAULT
1257 sysname, nodename, release, version, machine, domainname = \
1258 self._uname()
1259 s.pack_into(buf, 0,
1260 sysname, nodename, release, version, machine, domainname)
1261 return 0
1262
1263 def sys_readlink(self, pathname, buf, bufsiz, *rest):
1264 dirfd = ppc_flags.AT_FDCWD
1265 return self.sys_readlinkat(dirfd, pathname, buf, bufsiz)
1266
1267 def sys_readlinkat(self, dirfd, pathname, buf, bufsiz, *rest):
1268 try:
1269 path = self.__isacaller.mem.read_cstr(pathname)
1270 buf = self.__isacaller.mem.get_ctypes(buf, bufsiz, is_write=True)
1271 except (ValueError, MemException):
1272 return -errno.EFAULT
1273 try:
1274 if dirfd == ppc_flags.AT_FDCWD:
1275 result = os.readlink(path)
1276 else:
1277 result = os.readlink(path, dir_fd=dirfd)
1278 retval = min(len(result), len(buf))
1279 buf[:retval] = result[:retval]
1280 return retval
1281 except OSError as e:
1282 return -e.errno
1283
1284
1285 class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
1286 # decoder2 - an instance of power_decoder2
1287 # regfile - a list of initial values for the registers
1288 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
1289 # respect_pc - tracks the program counter. requires initial_insns
1290 def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
1291 initial_mem=None, initial_msr=0,
1292 initial_svstate=0,
1293 initial_insns=None,
1294 fpregfile=None,
1295 respect_pc=False,
1296 disassembly=None,
1297 initial_pc=0,
1298 bigendian=False,
1299 mmu=False,
1300 icachemmu=False,
1301 initial_fpscr=0,
1302 insnlog=None,
1303 use_mmap_mem=False,
1304 use_syscall_emu=False,
1305 emulating_mmap=False):
1306 if use_syscall_emu:
1307 self.syscall = SyscallEmulator(isacaller=self)
1308 if not use_mmap_mem:
1309 log("forcing use_mmap_mem due to use_syscall_emu active")
1310 use_mmap_mem = True
1311 else:
1312 self.syscall = None
1313
1314 # we will eventually be able to load ELF files without use_syscall_emu
1315 # (e.g. the linux kernel), so do it in a separate if block
1316 if isinstance(initial_insns, ELFFile):
1317 if not use_mmap_mem:
1318 log("forcing use_mmap_mem due to loading an ELF file")
1319 use_mmap_mem = True
1320 if not emulating_mmap:
1321 log("forcing emulating_mmap due to loading an ELF file")
1322 emulating_mmap = True
1323
1324 # trace log file for model output. if None do nothing
1325 self.insnlog = insnlog
1326 self.insnlog_is_file = hasattr(insnlog, "write")
1327 if not self.insnlog_is_file and self.insnlog:
1328 self.insnlog = open(self.insnlog, "w")
1329
1330 self.bigendian = bigendian
1331 self.halted = False
1332 self.is_svp64_mode = False
1333 self.respect_pc = respect_pc
1334 if initial_sprs is None:
1335 initial_sprs = {}
1336 if initial_mem is None:
1337 initial_mem = {}
1338 if fpregfile is None:
1339 fpregfile = [0] * 32
1340 if initial_insns is None:
1341 initial_insns = {}
1342 assert self.respect_pc == False, "instructions required to honor pc"
1343 if initial_msr is None:
1344 initial_msr = DEFAULT_MSR
1345
1346 log("ISACaller insns", respect_pc, initial_insns, disassembly)
1347 log("ISACaller initial_msr", initial_msr)
1348
1349 # "fake program counter" mode (for unit testing)
1350 self.fake_pc = 0
1351 disasm_start = 0
1352 if not respect_pc:
1353 if isinstance(initial_mem, tuple):
1354 self.fake_pc = initial_mem[0]
1355 disasm_start = self.fake_pc
1356 else:
1357 disasm_start = initial_pc
1358
1359 # disassembly: we need this for now (not given from the decoder)
1360 self.disassembly = {}
1361 if disassembly:
1362 for i, code in enumerate(disassembly):
1363 self.disassembly[i*4 + disasm_start] = code
1364
1365 # set up registers, instruction memory, data memory, PC, SPRs, MSR, CR
1366 self.svp64rm = SVP64RM()
1367 if initial_svstate is None:
1368 initial_svstate = 0
1369 if isinstance(initial_svstate, int):
1370 initial_svstate = SVP64State(initial_svstate)
1371 # SVSTATE, MSR and PC
1372 StepLoop.__init__(self, initial_svstate)
1373 self.msr = SelectableInt(initial_msr, 64) # underlying reg
1374 self.pc = PC()
1375 # GPR FPR SPR registers
1376 initial_sprs = deepcopy(initial_sprs) # so as not to get modified
1377 self.gpr = GPR(decoder2, self, self.svstate, regfile)
1378 self.fpr = GPR(decoder2, self, self.svstate, fpregfile)
1379 # initialise SPRs before MMU
1380 self.spr = SPR(decoder2, initial_sprs, gpr=self.gpr)
1381
1382 # set up 4 dummy SVSHAPEs if they aren't already set up
1383 for i in range(4):
1384 sname = 'SVSHAPE%d' % i
1385 val = self.spr.get(sname, 0)
1386 # make sure it's an SVSHAPE -- conversion done by SPR.__setitem__
1387 self.spr[sname] = val
1388 self.last_op_svshape = False
1389
1390 # "raw" memory
1391 if use_mmap_mem:
1392 self.mem = MemMMap(row_bytes=8,
1393 initial_mem=initial_mem,
1394 misaligned_ok=True,
1395 emulating_mmap=emulating_mmap)
1396 self.imem = self.mem
1397 lelf = self.mem.initialize(row_bytes=4, initial_mem=initial_insns)
1398 if isinstance(lelf, LoadedELF): # stuff parsed from ELF
1399 initial_pc = lelf.pc
1400 for k, v in lelf.gprs.items():
1401 self.gpr[k] = SelectableInt(v, 64)
1402 initial_fpscr = lelf.fpscr
1403 self.mem.log_fancy(kind=LogType.InstrInOuts)
1404 else:
1405 self.mem = Mem(row_bytes=8, initial_mem=initial_mem,
1406 misaligned_ok=True)
1407 self.mem.log_fancy(kind=LogType.InstrInOuts)
1408 self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
1409 # MMU mode, redirect underlying Mem through RADIX
1410 if mmu:
1411 self.mem = RADIX(self.mem, self)
1412 if icachemmu:
1413 self.imem = RADIX(self.imem, self)
1414
1415 # TODO, needed here:
1416 # FPR (same as GPR except for FP nums)
1417 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
1418 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
1419 self.fpscr = FPSCRState(initial_fpscr)
1420
1421 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
1422 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
1423 # -- Done
1424 # 2.3.2 LR (actually SPR #8) -- Done
1425 # 2.3.3 CTR (actually SPR #9) -- Done
1426 # 2.3.4 TAR (actually SPR #815)
1427 # 3.2.2 p45 XER (actually SPR #1) -- Done
1428 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
1429
1430 # create CR then allow portions of it to be "selectable" (below)
1431 self.cr_fields = CRFields(initial_cr)
1432 self.cr = self.cr_fields.cr
1433 self.cr_backup = 0 # sigh, dreadful hack: for fail-first (VLi)
1434
1435 # "undefined", just set to variable-bit-width int (use exts "max")
1436 # self.undefined = SelectableInt(0, EFFECTIVELY_UNLIMITED)
1437
1438 self.namespace = {}
1439 self.namespace.update(self.spr)
1440 self.namespace.update({'GPR': self.gpr,
1441 'FPR': self.fpr,
1442 'MEM': self.mem,
1443 'SPR': self.spr,
1444 'memassign': self.memassign,
1445 'NIA': self.pc.NIA,
1446 'CIA': self.pc.CIA,
1447 'SVSTATE': self.svstate,
1448 'SVSHAPE0': self.spr['SVSHAPE0'],
1449 'SVSHAPE1': self.spr['SVSHAPE1'],
1450 'SVSHAPE2': self.spr['SVSHAPE2'],
1451 'SVSHAPE3': self.spr['SVSHAPE3'],
1452 'CR': self.cr,
1453 'MSR': self.msr,
1454 'FPSCR': self.fpscr,
1455 'undefined': undefined,
1456 'mode_is_64bit': True,
1457 'SO': XER_bits['SO'],
1458 'XLEN': 64 # elwidth overrides
1459 })
1460
1461 for name in BFP_FLAG_NAMES:
1462 setattr(self, name, 0)
1463
1464 # update pc to requested start point
1465 self.set_pc(initial_pc)
1466
1467 # field-selectable versions of Condition Register
1468 self.crl = self.cr_fields.crl
1469 for i in range(8):
1470 self.namespace["CR%d" % i] = self.crl[i]
1471
1472 self.decoder = decoder2.dec
1473 self.dec2 = decoder2
1474
1475 super().__init__(XLEN=self.namespace["XLEN"], FPSCR=self.fpscr)
1476
1477 def trace(self, out):
1478 if self.insnlog is None:
1479 return
1480 self.insnlog.write(out)
1481
1482 @property
1483 def XLEN(self):
1484 return self.namespace["XLEN"]
1485
1486 @property
1487 def FPSCR(self):
1488 return self.fpscr
1489
1490 def call_trap(self, trap_addr, trap_bit):
1491 """calls TRAP and sets up NIA to the new execution location.
1492 next instruction will begin at trap_addr.
1493 """
1494 self.TRAP(trap_addr, trap_bit)
1495 self.namespace['NIA'] = self.trap_nia
1496 self.pc.update(self.namespace, self.is_svp64_mode)
1497
1498 def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
1499 """TRAP> saves PC, MSR (and TODO SVSTATE), and updates MSR
1500
1501 TRAP function is callable from inside the pseudocode itself,
1502 hence the default arguments. when calling from inside ISACaller
1503 it is best to use call_trap()
1504
1505 trap_addr: int | SelectableInt
1506 the address to go to (before any modifications from `KAIVB`)
1507 trap_bit: int | None
1508 the bit in `SRR1` to set, `None` means don't set any bits.
1509 """
1510 if isinstance(trap_addr, SelectableInt):
1511 trap_addr = trap_addr.value
1512 # https://bugs.libre-soc.org/show_bug.cgi?id=859
1513 kaivb = self.spr['KAIVB'].value
1514 msr = self.namespace['MSR'].value
1515 log("TRAP:", hex(trap_addr), hex(msr), "kaivb", hex(kaivb))
1516 # store CIA(+4?) in SRR0, set NIA to 0x700
1517 # store MSR in SRR1, set MSR to um errr something, have to check spec
1518 # store SVSTATE (if enabled) in SVSRR0
1519 self.spr['SRR0'].value = self.pc.CIA.value
1520 self.spr['SRR1'].value = msr
1521 if self.is_svp64_mode:
1522 self.spr['SVSRR0'] = self.namespace['SVSTATE'].value
1523 self.trap_nia = SelectableInt(trap_addr | (kaivb & ~0x1fff), 64)
1524 if trap_bit is not None:
1525 self.spr['SRR1'][trap_bit] = 1 # change *copy* of MSR in SRR1
1526
1527 # set exception bits. TODO: this should, based on the address
1528 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
1529 # bits appropriately. however it turns out that *for now* in all
1530 # cases (all trap_addrs) the exact same thing is needed.
1531 self.msr[MSRb.IR] = 0
1532 self.msr[MSRb.DR] = 0
1533 self.msr[MSRb.FE0] = 0
1534 self.msr[MSRb.FE1] = 0
1535 self.msr[MSRb.EE] = 0
1536 self.msr[MSRb.RI] = 0
1537 self.msr[MSRb.SF] = 1
1538 self.msr[MSRb.TM] = 0
1539 self.msr[MSRb.VEC] = 0
1540 self.msr[MSRb.VSX] = 0
1541 self.msr[MSRb.PR] = 0
1542 self.msr[MSRb.FP] = 0
1543 self.msr[MSRb.PMM] = 0
1544 self.msr[MSRb.TEs] = 0
1545 self.msr[MSRb.TEe] = 0
1546 self.msr[MSRb.UND] = 0
1547 self.msr[MSRb.LE] = 1
1548
1549 def memassign(self, ea, sz, val):
1550 self.mem.memassign(ea, sz, val)
1551
1552 def prep_namespace(self, insn_name, formname, op_fields, xlen):
1553 # TODO: get field names from form in decoder*1* (not decoder2)
1554 # decoder2 is hand-created, and decoder1.sigform is auto-generated
1555 # from spec
1556 # then "yield" fields only from op_fields rather than hard-coded
1557 # list, here.
1558 fields = self.decoder.sigforms[formname]
1559 log("prep_namespace", formname, op_fields, insn_name)
1560 for name in op_fields:
1561 # CR immediates. deal with separately. needs modifying
1562 # pseudocode
1563 if self.is_svp64_mode and name in ['BI']: # TODO, more CRs
1564 # BI is a 5-bit, must reconstruct the value
1565 regnum, is_vec = yield from get_cr_in(self.dec2, name)
1566 sig = getattr(fields, name)
1567 val = yield sig
1568 # low 2 LSBs (CR field selector) remain same, CR num extended
1569 assert regnum <= 7, "sigh, TODO, 128 CR fields"
1570 val = (val & 0b11) | (regnum << 2)
1571 elif self.is_svp64_mode and name in ['BF']: # TODO, more CRs
1572 regnum, is_vec = yield from get_cr_out(self.dec2, "BF")
1573 log('hack %s' % name, regnum, is_vec)
1574 val = regnum
1575 else:
1576 sig = getattr(fields, name)
1577 val = yield sig
1578 # these are all opcode fields involved in index-selection of CR,
1579 # and need to do "standard" arithmetic. CR[BA+32] for example
1580 # would, if using SelectableInt, only be 5-bit.
1581 if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
1582 self.namespace[name] = val
1583 else:
1584 self.namespace[name] = SelectableInt(val, sig.width)
1585
1586 self.namespace['XER'] = self.spr['XER']
1587 self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
1588 self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
1589 self.namespace['OV'] = self.spr['XER'][XER_bits['OV']].value
1590 self.namespace['OV32'] = self.spr['XER'][XER_bits['OV32']].value
1591 self.namespace['XLEN'] = xlen
1592
1593 # add some SVSTATE convenience variables
1594 vl = self.svstate.vl
1595 srcstep = self.svstate.srcstep
1596 self.namespace['VL'] = vl
1597 self.namespace['srcstep'] = srcstep
1598
1599 # take a copy of the CR field value: if non-VLi fail-first fails
1600 # this is because the pseudocode writes *directly* to CR. sigh
1601 self.cr_backup = self.cr.value
1602
1603 # sv.bc* need some extra fields
1604 if not self.is_svp64_mode or not insn_name.startswith("sv.bc"):
1605 return
1606
1607 # blegh grab bits manually
1608 mode = yield self.dec2.rm_dec.rm_in.mode
1609 # convert to SelectableInt before test
1610 mode = SelectableInt(mode, 5)
1611 bc_vlset = mode[SVP64MODEb.BC_VLSET] != 0
1612 bc_vli = mode[SVP64MODEb.BC_VLI] != 0
1613 bc_snz = mode[SVP64MODEb.BC_SNZ] != 0
1614 bc_vsb = yield self.dec2.rm_dec.bc_vsb
1615 bc_ctrtest = yield self.dec2.rm_dec.bc_ctrtest
1616 bc_lru = yield self.dec2.rm_dec.bc_lru
1617 bc_gate = yield self.dec2.rm_dec.bc_gate
1618 sz = yield self.dec2.rm_dec.pred_sz
1619 self.namespace['mode'] = SelectableInt(mode, 5)
1620 self.namespace['ALL'] = SelectableInt(bc_gate, 1)
1621 self.namespace['VSb'] = SelectableInt(bc_vsb, 1)
1622 self.namespace['LRu'] = SelectableInt(bc_lru, 1)
1623 self.namespace['CTRtest'] = SelectableInt(bc_ctrtest, 1)
1624 self.namespace['VLSET'] = SelectableInt(bc_vlset, 1)
1625 self.namespace['VLI'] = SelectableInt(bc_vli, 1)
1626 self.namespace['sz'] = SelectableInt(sz, 1)
1627 self.namespace['SNZ'] = SelectableInt(bc_snz, 1)
1628
1629 def get_kludged_op_add_ca_ov(self, inputs, inp_ca_ov):
1630 """ this was not at all necessary to do. this function massively
1631 duplicates - in a laborious and complex fashion - the contents of
1632 the CSV files that were extracted two years ago from microwatt's
1633 source code. A-inversion is the "inv A" column, output inversion
1634 is the "inv out" column, carry-in equal to 0 or 1 or CA is the
1635 "cry in" column
1636
1637 all of that information is available in
1638 self.instrs[ins_name].op_fields
1639 where info is usually assigned to self.instrs[ins_name]
1640
1641 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/minor_31.csv;hb=HEAD
1642
1643 the immediate constants are *also* decoded correctly and placed
1644 usually by DecodeIn2Imm into operand2, as part of power_decoder2.py
1645 """
1646 def ca(a, b, ca_in, width):
1647 mask = (1 << width) - 1
1648 y = (a & mask) + (b & mask) + ca_in
1649 return y >> width
1650
1651 asmcode = yield self.dec2.dec.op.asmcode
1652 insn = insns.get(asmcode)
1653 SI = yield self.dec2.dec.SI
1654 SI &= 0xFFFF
1655 CA, OV = inp_ca_ov
1656 inputs = [i.value for i in inputs]
1657 if SI & 0x8000:
1658 SI -= 0x10000
1659 if insn in ("add", "addo", "addc", "addco"):
1660 a = inputs[0]
1661 b = inputs[1]
1662 ca_in = 0
1663 elif insn == "addic" or insn == "addic.":
1664 a = inputs[0]
1665 b = SI
1666 ca_in = 0
1667 elif insn in ("subf", "subfo", "subfc", "subfco"):
1668 a = ~inputs[0]
1669 b = inputs[1]
1670 ca_in = 1
1671 elif insn == "subfic":
1672 a = ~inputs[0]
1673 b = SI
1674 ca_in = 1
1675 elif insn == "adde" or insn == "addeo":
1676 a = inputs[0]
1677 b = inputs[1]
1678 ca_in = CA
1679 elif insn == "subfe" or insn == "subfeo":
1680 a = ~inputs[0]
1681 b = inputs[1]
1682 ca_in = CA
1683 elif insn == "addme" or insn == "addmeo":
1684 a = inputs[0]
1685 b = ~0
1686 ca_in = CA
1687 elif insn == "addze" or insn == "addzeo":
1688 a = inputs[0]
1689 b = 0
1690 ca_in = CA
1691 elif insn == "subfme" or insn == "subfmeo":
1692 a = ~inputs[0]
1693 b = ~0
1694 ca_in = CA
1695 elif insn == "subfze" or insn == "subfzeo":
1696 a = ~inputs[0]
1697 b = 0
1698 ca_in = CA
1699 elif insn == "addex":
1700 # CA[32] aren't actually written, just generate so we have
1701 # something to return
1702 ca64 = ov64 = ca(inputs[0], inputs[1], OV, 64)
1703 ca32 = ov32 = ca(inputs[0], inputs[1], OV, 32)
1704 return ca64, ca32, ov64, ov32
1705 elif insn == "neg" or insn == "nego":
1706 a = ~inputs[0]
1707 b = 0
1708 ca_in = 1
1709 else:
1710 raise NotImplementedError(
1711 "op_add kludge unimplemented instruction: ", asmcode, insn)
1712
1713 ca64 = ca(a, b, ca_in, 64)
1714 ca32 = ca(a, b, ca_in, 32)
1715 ov64 = ca64 != ca(a, b, ca_in, 63)
1716 ov32 = ca32 != ca(a, b, ca_in, 31)
1717 return ca64, ca32, ov64, ov32
1718
1719 def handle_carry_(self, inputs, output, ca, ca32, inp_ca_ov):
1720 if ca is not None and ca32 is not None:
1721 return
1722 op = yield self.dec2.e.do.insn_type
1723 if op == MicrOp.OP_ADD.value and ca is None and ca32 is None:
1724 retval = yield from self.get_kludged_op_add_ca_ov(
1725 inputs, inp_ca_ov)
1726 ca, ca32, ov, ov32 = retval
1727 asmcode = yield self.dec2.dec.op.asmcode
1728 if insns.get(asmcode) == 'addex':
1729 # TODO: if 32-bit mode, set ov to ov32
1730 self.spr['XER'][XER_bits['OV']] = ov
1731 self.spr['XER'][XER_bits['OV32']] = ov32
1732 log(f"write OV/OV32 OV={ov} OV32={ov32}",
1733 kind=LogType.InstrInOuts)
1734 else:
1735 # TODO: if 32-bit mode, set ca to ca32
1736 self.spr['XER'][XER_bits['CA']] = ca
1737 self.spr['XER'][XER_bits['CA32']] = ca32
1738 log(f"write CA/CA32 CA={ca} CA32={ca32}",
1739 kind=LogType.InstrInOuts)
1740 return
1741 inv_a = yield self.dec2.e.do.invert_in
1742 if inv_a:
1743 inputs[0] = ~inputs[0]
1744
1745 imm_ok = yield self.dec2.e.do.imm_data.ok
1746 if imm_ok:
1747 imm = yield self.dec2.e.do.imm_data.data
1748 inputs.append(SelectableInt(imm, 64))
1749 gts = []
1750 for x in inputs:
1751 log("gt input", x, output)
1752 gt = (gtu(x, output))
1753 gts.append(gt)
1754 log(gts)
1755 cy = 1 if any(gts) else 0
1756 log("CA", cy, gts)
1757 if ca is None: # already written
1758 self.spr['XER'][XER_bits['CA']] = cy
1759
1760 # 32 bit carry
1761 # ARGH... different for OP_ADD... *sigh*...
1762 op = yield self.dec2.e.do.insn_type
1763 if op == MicrOp.OP_ADD.value:
1764 res32 = (output.value & (1 << 32)) != 0
1765 a32 = (inputs[0].value & (1 << 32)) != 0
1766 if len(inputs) >= 2:
1767 b32 = (inputs[1].value & (1 << 32)) != 0
1768 else:
1769 b32 = False
1770 cy32 = res32 ^ a32 ^ b32
1771 log("CA32 ADD", cy32)
1772 else:
1773 gts = []
1774 for x in inputs:
1775 log("input", x, output)
1776 log(" x[32:64]", x, x[32:64])
1777 log(" o[32:64]", output, output[32:64])
1778 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
1779 gts.append(gt)
1780 cy32 = 1 if any(gts) else 0
1781 log("CA32", cy32, gts)
1782 if ca32 is None: # already written
1783 self.spr['XER'][XER_bits['CA32']] = cy32
1784
1785 def handle_overflow(self, inputs, output, div_overflow, inp_ca_ov):
1786 op = yield self.dec2.e.do.insn_type
1787 if op == MicrOp.OP_ADD.value:
1788 retval = yield from self.get_kludged_op_add_ca_ov(
1789 inputs, inp_ca_ov)
1790 ca, ca32, ov, ov32 = retval
1791 # TODO: if 32-bit mode, set ov to ov32
1792 self.spr['XER'][XER_bits['OV']] = ov
1793 self.spr['XER'][XER_bits['OV32']] = ov32
1794 self.spr['XER'][XER_bits['SO']] |= ov
1795 return
1796 if hasattr(self.dec2.e.do, "invert_in"):
1797 inv_a = yield self.dec2.e.do.invert_in
1798 if inv_a:
1799 inputs[0] = ~inputs[0]
1800
1801 imm_ok = yield self.dec2.e.do.imm_data.ok
1802 if imm_ok:
1803 imm = yield self.dec2.e.do.imm_data.data
1804 inputs.append(SelectableInt(imm, 64))
1805 log("handle_overflow", inputs, output, div_overflow)
1806 if len(inputs) < 2 and div_overflow is None:
1807 return
1808
1809 # div overflow is different: it's returned by the pseudo-code
1810 # because it's more complex than can be done by analysing the output
1811 if div_overflow is not None:
1812 ov, ov32 = div_overflow, div_overflow
1813 # arithmetic overflow can be done by analysing the input and output
1814 elif len(inputs) >= 2:
1815 # OV (64-bit)
1816 input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
1817 output_sgn = exts(output.value, output.bits) < 0
1818 ov = 1 if input_sgn[0] == input_sgn[1] and \
1819 output_sgn != input_sgn[0] else 0
1820
1821 # OV (32-bit)
1822 input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
1823 output32_sgn = exts(output.value, 32) < 0
1824 ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
1825 output32_sgn != input32_sgn[0] else 0
1826
1827 # now update XER OV/OV32/SO
1828 so = self.spr['XER'][XER_bits['SO']]
1829 new_so = so | ov # sticky overflow ORs in old with new
1830 self.spr['XER'][XER_bits['OV']] = ov
1831 self.spr['XER'][XER_bits['OV32']] = ov32
1832 self.spr['XER'][XER_bits['SO']] = new_so
1833 log(" set overflow", ov, ov32, so, new_so)
1834
1835 def handle_comparison(self, out, cr_idx=0, overflow=None, no_so=False):
1836 assert isinstance(out, SelectableInt), \
1837 "out zero not a SelectableInt %s" % repr(outputs)
1838 log("handle_comparison", out.bits, hex(out.value))
1839 # TODO - XXX *processor* in 32-bit mode
1840 # https://bugs.libre-soc.org/show_bug.cgi?id=424
1841 # if is_32bit:
1842 # o32 = exts(out.value, 32)
1843 # print ("handle_comparison exts 32 bit", hex(o32))
1844 out = exts(out.value, out.bits)
1845 log("handle_comparison exts", hex(out))
1846 # create the three main CR flags, EQ GT LT
1847 zero = SelectableInt(out == 0, 1)
1848 positive = SelectableInt(out > 0, 1)
1849 negative = SelectableInt(out < 0, 1)
1850 # get (or not) XER.SO. for setvl this is important *not* to read SO
1851 if no_so:
1852 SO = SelectableInt(1, 0)
1853 else:
1854 SO = self.spr['XER'][XER_bits['SO']]
1855 log("handle_comparison SO", SO.value,
1856 "overflow", overflow,
1857 "zero", zero.value,
1858 "+ve", positive.value,
1859 "-ve", negative.value)
1860 # alternative overflow checking (setvl mainly at the moment)
1861 if overflow is not None and overflow == 1:
1862 SO = SelectableInt(1, 1)
1863 # create the four CR field values and set the required CR field
1864 cr_field = selectconcat(negative, positive, zero, SO)
1865 log("handle_comparison cr_field", self.cr, cr_idx, cr_field)
1866 self.crl[cr_idx].eq(cr_field)
1867 return cr_field
1868
1869 def set_pc(self, pc_val):
1870 self.namespace['NIA'] = SelectableInt(pc_val, 64)
1871 self.pc.update(self.namespace, self.is_svp64_mode)
1872
1873 def get_next_insn(self):
1874 """check instruction
1875 """
1876 if self.respect_pc:
1877 pc = self.pc.CIA.value
1878 else:
1879 pc = self.fake_pc
1880 ins = self.imem.ld(pc, 4, False, True, instr_fetch=True)
1881 if ins is None:
1882 raise KeyError("no instruction at 0x%x" % pc)
1883 return pc, ins
1884
1885 def setup_one(self):
1886 """set up one instruction
1887 """
1888 pc, insn = self.get_next_insn()
1889 yield from self.setup_next_insn(pc, insn)
1890
1891 # cache since it's really slow to construct
1892 __PREFIX_CACHE = SVP64Instruction.Prefix(SelectableInt(value=0, bits=32))
1893
1894 def __decode_prefix(self, opcode):
1895 pfx = self.__PREFIX_CACHE
1896 pfx.storage.eq(opcode)
1897 return pfx
1898
1899 def setup_next_insn(self, pc, ins):
1900 """set up next instruction
1901 """
1902 self._pc = pc
1903 log("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
1904 log("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
1905
1906 yield self.dec2.sv_rm.eq(0)
1907 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
1908 yield self.dec2.dec.bigendian.eq(self.bigendian)
1909 yield self.dec2.state.msr.eq(self.msr.value)
1910 yield self.dec2.state.pc.eq(pc)
1911 if self.svstate is not None:
1912 yield self.dec2.state.svstate.eq(self.svstate.value)
1913
1914 # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
1915 yield Settle()
1916 opcode = yield self.dec2.dec.opcode_in
1917 opcode = SelectableInt(value=opcode, bits=32)
1918 pfx = self.__decode_prefix(opcode)
1919 log("prefix test: opcode:", pfx.PO, bin(pfx.PO), pfx.id)
1920 self.is_svp64_mode = bool((pfx.PO == 0b000001) and (pfx.id == 0b11))
1921 self.pc.update_nia(self.is_svp64_mode)
1922 # set SVP64 decode
1923 yield self.dec2.is_svp64_mode.eq(self.is_svp64_mode)
1924 self.namespace['NIA'] = self.pc.NIA
1925 self.namespace['SVSTATE'] = self.svstate
1926 if not self.is_svp64_mode:
1927 return
1928
1929 # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
1930 log("svp64.rm", bin(pfx.rm))
1931 log(" svstate.vl", self.svstate.vl)
1932 log(" svstate.mvl", self.svstate.maxvl)
1933 ins = self.imem.ld(pc+4, 4, False, True, instr_fetch=True)
1934 log(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
1935 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
1936 yield self.dec2.sv_rm.eq(int(pfx.rm)) # svp64 prefix
1937 yield Settle()
1938
1939 def execute_one(self):
1940 """execute one instruction
1941 """
1942 # get the disassembly code for this instruction
1943 if not self.disassembly:
1944 code = yield from self.get_assembly_name()
1945 else:
1946 offs, dbg = 0, ""
1947 if self.is_svp64_mode:
1948 offs, dbg = 4, "svp64 "
1949 code = self.disassembly[self._pc+offs]
1950 log(" %s sim-execute" % dbg, hex(self._pc), code)
1951 opname = code.split(' ')[0]
1952 try:
1953 yield from self.call(opname) # execute the instruction
1954 except MemException as e: # check for memory errors
1955 if e.args[0] == 'unaligned': # alignment error
1956 # run a Trap but set DAR first
1957 print("memory unaligned exception, DAR", e.dar, repr(e))
1958 self.spr['DAR'] = SelectableInt(e.dar, 64)
1959 self.call_trap(0x600, PIb.PRIV) # 0x600, privileged
1960 return
1961 elif e.args[0] == 'invalid': # invalid
1962 # run a Trap but set DAR first
1963 log("RADIX MMU memory invalid error, mode %s" % e.mode)
1964 if e.mode == 'EXECUTE':
1965 # XXX TODO: must set a few bits in SRR1,
1966 # see microwatt loadstore1.vhdl
1967 # if m_in.segerr = '0' then
1968 # v.srr1(47 - 33) := m_in.invalid;
1969 # v.srr1(47 - 35) := m_in.perm_error; -- noexec fault
1970 # v.srr1(47 - 44) := m_in.badtree;
1971 # v.srr1(47 - 45) := m_in.rc_error;
1972 # v.intr_vec := 16#400#;
1973 # else
1974 # v.intr_vec := 16#480#;
1975 self.call_trap(0x400, PIb.PRIV) # 0x400, privileged
1976 else:
1977 self.call_trap(0x300, PIb.PRIV) # 0x300, privileged
1978 return
1979 # not supported yet:
1980 raise e # ... re-raise
1981
1982 # append to the trace log file
1983 self.trace(" # %s\n" % code)
1984
1985 log("gprs after code", code)
1986 self.gpr.dump()
1987 crs = []
1988 for i in range(len(self.crl)):
1989 crs.append(bin(self.crl[i].asint()))
1990 log("crs", " ".join(crs))
1991 log("vl,maxvl", self.svstate.vl, self.svstate.maxvl)
1992
1993 # don't use this except in special circumstances
1994 if not self.respect_pc:
1995 self.fake_pc += 4
1996
1997 log("execute one, CIA NIA", hex(self.pc.CIA.value),
1998 hex(self.pc.NIA.value))
1999
2000 def get_assembly_name(self):
2001 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
2002 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
2003 dec_insn = yield self.dec2.e.do.insn
2004 insn_1_11 = yield self.dec2.e.do.insn[1:11]
2005 asmcode = yield self.dec2.dec.op.asmcode
2006 int_op = yield self.dec2.dec.op.internal_op
2007 log("get assembly name asmcode", asmcode, int_op,
2008 hex(dec_insn), bin(insn_1_11))
2009 asmop = insns.get(asmcode, None)
2010
2011 # sigh reconstruct the assembly instruction name
2012 if hasattr(self.dec2.e.do, "oe"):
2013 ov_en = yield self.dec2.e.do.oe.oe
2014 ov_ok = yield self.dec2.e.do.oe.ok
2015 else:
2016 ov_en = False
2017 ov_ok = False
2018 if hasattr(self.dec2.e.do, "rc"):
2019 rc_en = yield self.dec2.e.do.rc.rc
2020 rc_ok = yield self.dec2.e.do.rc.ok
2021 else:
2022 rc_en = False
2023 rc_ok = False
2024 # annoying: ignore rc_ok if RC1 is set (for creating *assembly name*)
2025 RC1 = yield self.dec2.rm_dec.RC1
2026 if RC1:
2027 rc_en = False
2028 rc_ok = False
2029 # grrrr have to special-case MUL op (see DecodeOE)
2030 log("ov %d en %d rc %d en %d op %d" %
2031 (ov_ok, ov_en, rc_ok, rc_en, int_op))
2032 if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
2033 log("mul op")
2034 if rc_en & rc_ok:
2035 asmop += "."
2036 else:
2037 if not asmop.endswith("."): # don't add "." to "andis."
2038 if rc_en & rc_ok:
2039 asmop += "."
2040 if hasattr(self.dec2.e.do, "lk"):
2041 lk = yield self.dec2.e.do.lk
2042 if lk:
2043 asmop += "l"
2044 log("int_op", int_op)
2045 if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
2046 AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
2047 log("AA", AA)
2048 if AA:
2049 asmop += "a"
2050 spr_msb = yield from self.get_spr_msb()
2051 if int_op == MicrOp.OP_MFCR.value:
2052 if spr_msb:
2053 asmop = 'mfocrf'
2054 else:
2055 asmop = 'mfcr'
2056 # XXX TODO: for whatever weird reason this doesn't work
2057 # https://bugs.libre-soc.org/show_bug.cgi?id=390
2058 if int_op == MicrOp.OP_MTCRF.value:
2059 if spr_msb:
2060 asmop = 'mtocrf'
2061 else:
2062 asmop = 'mtcrf'
2063 return asmop
2064
2065 def reset_remaps(self):
2066 self.remap_loopends = [0] * 4
2067 self.remap_idxs = [0, 1, 2, 3]
2068
2069 def get_remap_indices(self):
2070 """WARNING, this function stores remap_idxs and remap_loopends
2071 in the class for later use. this to avoid problems with yield
2072 """
2073 # go through all iterators in lock-step, advance to next remap_idx
2074 srcstep, dststep, ssubstep, dsubstep = self.get_src_dststeps()
2075 # get four SVSHAPEs. here we are hard-coding
2076 self.reset_remaps()
2077 SVSHAPE0 = self.spr['SVSHAPE0']
2078 SVSHAPE1 = self.spr['SVSHAPE1']
2079 SVSHAPE2 = self.spr['SVSHAPE2']
2080 SVSHAPE3 = self.spr['SVSHAPE3']
2081 # set up the iterators
2082 remaps = [(SVSHAPE0, SVSHAPE0.get_iterator()),
2083 (SVSHAPE1, SVSHAPE1.get_iterator()),
2084 (SVSHAPE2, SVSHAPE2.get_iterator()),
2085 (SVSHAPE3, SVSHAPE3.get_iterator()),
2086 ]
2087
2088 dbg = []
2089 for i, (shape, remap) in enumerate(remaps):
2090 # zero is "disabled"
2091 if shape.value == 0x0:
2092 self.remap_idxs[i] = 0
2093 # pick src or dststep depending on reg num (0-2=in, 3-4=out)
2094 step = dststep if (i in [3, 4]) else srcstep
2095 # this is terrible. O(N^2) looking for the match. but hey.
2096 for idx, (remap_idx, loopends) in enumerate(remap):
2097 if idx == step:
2098 break
2099 self.remap_idxs[i] = remap_idx
2100 self.remap_loopends[i] = loopends
2101 dbg.append((i, step, remap_idx, loopends))
2102 for (i, step, remap_idx, loopends) in dbg:
2103 log("SVSHAPE %d idx, end" % i, step, remap_idx, bin(loopends))
2104 return remaps
2105
2106 def get_spr_msb(self):
2107 dec_insn = yield self.dec2.e.do.insn
2108 return dec_insn & (1 << 20) != 0 # sigh - XFF.spr[-1]?
2109
2110 def call(self, name, syscall_emu_active=False):
2111 """call(opcode) - the primary execution point for instructions
2112 """
2113 self.last_st_addr = None # reset the last known store address
2114 self.last_ld_addr = None # etc.
2115
2116 ins_name = name.strip() # remove spaces if not already done so
2117 if self.halted:
2118 log("halted - not executing", ins_name)
2119 return
2120
2121 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
2122 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
2123 asmop = yield from self.get_assembly_name()
2124 log("call", ins_name, asmop,
2125 kind=LogType.InstrInOuts)
2126
2127 # sv.setvl is *not* a loop-function. sigh
2128 log("is_svp64_mode", self.is_svp64_mode, asmop)
2129
2130 # check privileged
2131 int_op = yield self.dec2.dec.op.internal_op
2132 spr_msb = yield from self.get_spr_msb()
2133
2134 instr_is_privileged = False
2135 if int_op in [MicrOp.OP_ATTN.value,
2136 MicrOp.OP_MFMSR.value,
2137 MicrOp.OP_MTMSR.value,
2138 MicrOp.OP_MTMSRD.value,
2139 # TODO: OP_TLBIE
2140 MicrOp.OP_RFID.value]:
2141 instr_is_privileged = True
2142 if int_op in [MicrOp.OP_MFSPR.value,
2143 MicrOp.OP_MTSPR.value] and spr_msb:
2144 instr_is_privileged = True
2145
2146 log("is priv", instr_is_privileged, hex(self.msr.value),
2147 self.msr[MSRb.PR])
2148 # check MSR priv bit and whether op is privileged: if so, throw trap
2149 if instr_is_privileged and self.msr[MSRb.PR] == 1:
2150 self.call_trap(0x700, PIb.PRIV)
2151 return
2152
2153 # check halted condition
2154 if ins_name == 'attn':
2155 self.halted = True
2156 return
2157
2158 # User mode system call emulation consists of several steps:
2159 # 1. Detect whether instruction is sc or scv.
2160 # 2. Call the HDL implementation which invokes trap.
2161 # 3. Reroute the guest system call to host system call.
2162 # 4. Force return from the interrupt as if we had guest OS.
2163 if ((asmop in ("sc", "scv")) and
2164 (self.syscall is not None) and
2165 not syscall_emu_active):
2166 # Memoize PC and trigger an interrupt
2167 if self.respect_pc:
2168 pc = self.pc.CIA.value
2169 else:
2170 pc = self.fake_pc
2171 yield from self.call(asmop, syscall_emu_active=True)
2172
2173 # Reroute the syscall to host OS
2174 identifier = self.gpr(0)
2175 arguments = map(self.gpr, range(3, 9))
2176 result = self.syscall(identifier, *arguments)
2177 self.gpr.write(3, result, False, self.namespace["XLEN"])
2178
2179 # Return from interrupt
2180 yield from self.call("rfid", syscall_emu_active=True)
2181 return
2182 elif ((name in ("rfid", "hrfid")) and syscall_emu_active):
2183 asmop = "rfid"
2184
2185 # check illegal instruction
2186 illegal = False
2187 if ins_name not in ['mtcrf', 'mtocrf']:
2188 illegal = ins_name != asmop
2189
2190 # list of instructions not being supported by binutils (.long)
2191 dotstrp = asmop[:-1] if asmop[-1] == '.' else asmop
2192 if dotstrp in [*FPTRANS_INSNS,
2193 *LDST_UPDATE_INSNS,
2194 'ffmadds', 'fdmadds', 'ffadds',
2195 'minmax',
2196 "brh", "brw", "brd",
2197 'setvl', 'svindex', 'svremap', 'svstep',
2198 'svshape', 'svshape2',
2199 'ternlogi', 'bmask', 'cprop', 'gbbd',
2200 'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
2201 'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
2202 "dsld", "dsrd", "maddedus",
2203 "sadd", "saddw", "sadduw",
2204 "cffpr", "cffpro",
2205 "mffpr", "mffprs",
2206 "ctfpr", "ctfprs",
2207 "mtfpr", "mtfprs",
2208 "maddsubrs", "maddrs", "msubrs",
2209 "cfuged", "cntlzdm", "cnttzdm", "pdepd", "pextd",
2210 "setbc", "setbcr", "setnbc", "setnbcr",
2211 ]:
2212 illegal = False
2213 ins_name = dotstrp
2214
2215 # match against instructions treated as nop, see nop below
2216 if asmop.startswith("dcbt"):
2217 illegal = False
2218 ins_name = "nop"
2219
2220 # branch-conditional redirects to sv.bc
2221 if asmop.startswith('bc') and self.is_svp64_mode:
2222 ins_name = 'sv.%s' % ins_name
2223
2224 # ld-immediate-with-pi mode redirects to ld-with-postinc
2225 ldst_imm_postinc = False
2226 if 'u' in ins_name and self.is_svp64_mode:
2227 ldst_pi = yield self.dec2.rm_dec.ldst_postinc
2228 if ldst_pi:
2229 ins_name = ins_name.replace("u", "up")
2230 ldst_imm_postinc = True
2231 log(" enable ld/st postinc", ins_name)
2232
2233 log(" post-processed name", dotstrp, ins_name, asmop)
2234
2235 # illegal instructions call TRAP at 0x700
2236 if illegal:
2237 print("illegal", ins_name, asmop)
2238 self.call_trap(0x700, PIb.ILLEG)
2239 print("name %s != %s - calling ILLEGAL trap, PC: %x" %
2240 (ins_name, asmop, self.pc.CIA.value))
2241 return
2242
2243 # this is for setvl "Vertical" mode: if set true,
2244 # srcstep/dststep is explicitly advanced. mode says which SVSTATE to
2245 # test for Rc=1 end condition. 3 bits of all 3 loops are put into CR0
2246 self.allow_next_step_inc = False
2247 self.svstate_next_mode = 0
2248
2249 # nop has to be supported, we could let the actual op calculate
2250 # but PowerDecoder has a pattern for nop
2251 if ins_name == 'nop':
2252 self.update_pc_next()
2253 return
2254
2255 # get elwidths, defaults to 64
2256 xlen = 64
2257 ew_src = 64
2258 ew_dst = 64
2259 if self.is_svp64_mode:
2260 ew_src = yield self.dec2.rm_dec.ew_src
2261 ew_dst = yield self.dec2.rm_dec.ew_dst
2262 ew_src = 8 << (3-int(ew_src)) # convert to bitlength
2263 ew_dst = 8 << (3-int(ew_dst)) # convert to bitlength
2264 xlen = max(ew_src, ew_dst)
2265 log("elwidth", ew_src, ew_dst)
2266 log("XLEN:", self.is_svp64_mode, xlen)
2267
2268 # look up instruction in ISA.instrs, prepare namespace
2269 if ins_name == 'pcdec': # grrrr yes there are others ("stbcx." etc.)
2270 info = self.instrs[ins_name+"."]
2271 elif asmop[-1] == '.' and asmop in self.instrs:
2272 info = self.instrs[asmop]
2273 else:
2274 info = self.instrs[ins_name]
2275 yield from self.prep_namespace(ins_name, info.form, info.op_fields,
2276 xlen)
2277
2278 # dict retains order
2279 inputs = dict.fromkeys(create_full_args(
2280 read_regs=info.read_regs, special_regs=info.special_regs,
2281 uninit_regs=info.uninit_regs, write_regs=info.write_regs))
2282
2283 # preserve order of register names
2284 write_without_special_regs = OrderedSet(info.write_regs)
2285 write_without_special_regs -= OrderedSet(info.special_regs)
2286 input_names = create_args([
2287 *info.read_regs, *info.uninit_regs, *write_without_special_regs])
2288 log("input names", input_names)
2289
2290 # get SVP64 entry for the current instruction
2291 sv_rm = self.svp64rm.instrs.get(ins_name)
2292 if sv_rm is not None:
2293 dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
2294 else:
2295 dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
2296 log("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
2297
2298 # see if srcstep/dststep need skipping over masked-out predicate bits
2299 # svstep also needs advancement because it calls SVSTATE_NEXT.
2300 # bit the remaps get computed just after pre_inc moves them on
2301 # with remap_set_steps substituting for PowerDecider2 not doing it,
2302 # and SVSTATE_NEXT not being able to.use yield, the preinc on
2303 # svstep is necessary for now.
2304 self.reset_remaps()
2305 if (self.is_svp64_mode or ins_name in ['svstep']):
2306 yield from self.svstate_pre_inc()
2307 if self.is_svp64_mode:
2308 pre = yield from self.update_new_svstate_steps()
2309 if pre:
2310 self.svp64_reset_loop()
2311 self.update_nia()
2312 self.update_pc_next()
2313 return
2314 srcstep, dststep, ssubstep, dsubstep = self.get_src_dststeps()
2315 pred_dst_zero = self.pred_dst_zero
2316 pred_src_zero = self.pred_src_zero
2317 vl = self.svstate.vl
2318 subvl = yield self.dec2.rm_dec.rm_in.subvl
2319
2320 # VL=0 in SVP64 mode means "do nothing: skip instruction"
2321 if self.is_svp64_mode and vl == 0:
2322 self.pc.update(self.namespace, self.is_svp64_mode)
2323 log("SVP64: VL=0, end of call", self.namespace['CIA'],
2324 self.namespace['NIA'], kind=LogType.InstrInOuts)
2325 return
2326
2327 # for when SVREMAP is active, using pre-arranged schedule.
2328 # note: modifying PowerDecoder2 needs to "settle"
2329 remap_en = self.svstate.SVme
2330 persist = self.svstate.RMpst
2331 active = (persist or self.last_op_svshape) and remap_en != 0
2332 if self.is_svp64_mode:
2333 yield self.dec2.remap_active.eq(remap_en if active else 0)
2334 yield Settle()
2335 if persist or self.last_op_svshape:
2336 remaps = self.get_remap_indices()
2337 if self.is_svp64_mode and (persist or self.last_op_svshape):
2338 yield from self.remap_set_steps(remaps)
2339 # after that, settle down (combinatorial) to let Vector reg numbers
2340 # work themselves out
2341 yield Settle()
2342 if self.is_svp64_mode:
2343 remap_active = yield self.dec2.remap_active
2344 else:
2345 remap_active = False
2346 log("remap active", bin(remap_active), self.is_svp64_mode)
2347
2348 # LDST does *not* allow elwidth overrides on RA (Effective Address).
2349 # this has to be detected. XXX TODO: RB for ldst-idx *may* need
2350 # conversion (to 64-bit) also.
2351 # see write reg this *HAS* to also override XLEN to 64 on LDST/Update
2352 sv_mode = yield self.dec2.rm_dec.sv_mode
2353 is_ldst = (sv_mode in [SVMode.LDST_IDX.value, SVMode.LDST_IMM.value] \
2354 and self.is_svp64_mode)
2355 log("is_ldst", sv_mode, is_ldst)
2356
2357 # main input registers (RT, RA ...)
2358 for name in input_names:
2359 if name == "overflow":
2360 inputs[name] = SelectableInt(0, 1)
2361 elif name == "FPSCR":
2362 inputs[name] = self.FPSCR
2363 elif name in ("CA", "CA32", "OV", "OV32"):
2364 inputs[name] = self.spr['XER'][XER_bits[name]]
2365 elif name in "CR0":
2366 inputs[name] = self.crl[0]
2367 elif name in spr_byname:
2368 inputs[name] = self.spr[name]
2369 elif is_ldst and name == 'RA':
2370 regval = (yield from self.get_input(name, ew_src, 64))
2371 log("EA (RA) regval name", name, regval)
2372 inputs[name] = regval
2373 else:
2374 regval = (yield from self.get_input(name, ew_src, xlen))
2375 log("regval name", name, regval)
2376 inputs[name] = regval
2377
2378 # arrrrgh, awful hack, to get _RT into namespace
2379 if ins_name in ['setvl', 'svstep']:
2380 regname = "_RT"
2381 RT = yield self.dec2.dec.RT
2382 self.namespace[regname] = SelectableInt(RT, 5)
2383 if RT == 0:
2384 self.namespace["RT"] = SelectableInt(0, 5)
2385 regnum, is_vec = yield from get_idx_out(self.dec2, "RT")
2386 log('hack input reg %s %s' % (name, str(regnum)), is_vec)
2387
2388 # in SVP64 mode for LD/ST work out immediate
2389 # XXX TODO: replace_ds for DS-Form rather than D-Form.
2390 # use info.form to detect
2391 if self.is_svp64_mode and not ldst_imm_postinc:
2392 yield from self.check_replace_d(info, remap_active)
2393
2394 # "special" registers
2395 for special in info.special_regs:
2396 if special in special_sprs:
2397 inputs[special] = self.spr[special]
2398 else:
2399 inputs[special] = self.namespace[special]
2400
2401 # clear trap (trap) NIA
2402 self.trap_nia = None
2403
2404 # check if this was an sv.bc* and create an indicator that
2405 # this is the last check to be made as a loop. combined with
2406 # the ALL/ANY mode we can early-exit. note that BI (to test)
2407 # is an input so there is no termination if BI is scalar
2408 # (because early-termination is for *output* scalars)
2409 if self.is_svp64_mode and ins_name.startswith("sv.bc"):
2410 end_loop = srcstep == vl-1 or dststep == vl-1
2411 self.namespace['end_loop'] = SelectableInt(end_loop, 1)
2412
2413 inp_ca_ov = (self.spr['XER'][XER_bits['CA']].value,
2414 self.spr['XER'][XER_bits['OV']].value)
2415
2416 for k, v in inputs.items():
2417 if v is None:
2418 v = SelectableInt(0, self.XLEN)
2419 # prevent pseudo-code from modifying input registers
2420 v = copy_assign_rhs(v)
2421 if isinstance(v, SelectableInt):
2422 v.ok = False
2423 inputs[k] = v
2424
2425 # execute actual instruction here (finally)
2426 log("inputs", inputs)
2427 inputs = list(inputs.values())
2428 results = info.func(self, *inputs)
2429 output_names = create_args(info.write_regs)
2430 outs = {}
2431 # record .ok before anything after the pseudo-code can modify it
2432 outs_ok = {}
2433 for out, n in zip(results or [], output_names):
2434 outs[n] = out
2435 outs_ok[n] = True
2436 if isinstance(out, SelectableInt):
2437 outs_ok[n] = out.ok
2438 log("results", outs)
2439 log("results ok", outs_ok)
2440
2441 # "inject" decorator takes namespace from function locals: we need to
2442 # overwrite NIA being overwritten (sigh)
2443 if self.trap_nia is not None:
2444 self.namespace['NIA'] = self.trap_nia
2445
2446 log("after func", self.namespace['CIA'], self.namespace['NIA'])
2447
2448 # check if op was a LD/ST so that debugging can check the
2449 # address
2450 if int_op in [MicrOp.OP_STORE.value,
2451 ]:
2452 self.last_st_addr = self.mem.last_st_addr
2453 if int_op in [MicrOp.OP_LOAD.value,
2454 ]:
2455 self.last_ld_addr = self.mem.last_ld_addr
2456 log("op", int_op, MicrOp.OP_STORE.value, MicrOp.OP_LOAD.value,
2457 self.last_st_addr, self.last_ld_addr)
2458
2459 # detect if CA/CA32 already in outputs (sra*, basically)
2460 ca = outs.get("CA")
2461 ca32 = outs.get("CA32")
2462
2463 log("carry already done?", ca, ca32, output_names)
2464 # soc test_pipe_caller tests don't have output_carry
2465 has_output_carry = hasattr(self.dec2.e.do, "output_carry")
2466 carry_en = has_output_carry and (yield self.dec2.e.do.output_carry)
2467 if carry_en:
2468 yield from self.handle_carry_(
2469 inputs, results[0], ca, ca32, inp_ca_ov=inp_ca_ov)
2470
2471 # get output named "overflow" and "CR0"
2472 overflow = outs.get('overflow')
2473 cr0 = outs.get('CR0')
2474 cr1 = outs.get('CR1')
2475
2476 # soc test_pipe_caller tests don't have oe
2477 has_oe = hasattr(self.dec2.e.do, "oe")
2478 # yeah just no. not in parallel processing
2479 if has_oe and not self.is_svp64_mode:
2480 # detect if overflow was in return result
2481 ov_en = yield self.dec2.e.do.oe.oe
2482 ov_ok = yield self.dec2.e.do.oe.ok
2483 log("internal overflow", ins_name, overflow, "en?", ov_en, ov_ok)
2484 if ov_en & ov_ok:
2485 yield from self.handle_overflow(
2486 inputs, results[0], overflow, inp_ca_ov=inp_ca_ov)
2487
2488 # only do SVP64 dest predicated Rc=1 if dest-pred is not enabled
2489 rc_en = False
2490 if not self.is_svp64_mode or not pred_dst_zero:
2491 if hasattr(self.dec2.e.do, "rc"):
2492 rc_en = yield self.dec2.e.do.rc.rc
2493 # don't do Rc=1 for svstep it is handled explicitly.
2494 # XXX TODO: now that CR0 is supported, sort out svstep's pseudocode
2495 # to write directly to CR0 instead of in ISACaller. hooyahh.
2496 if rc_en and ins_name not in ['svstep']:
2497 if outs_ok.get('FPSCR', False):
2498 FPSCR = outs['FPSCR']
2499 else:
2500 FPSCR = self.FPSCR
2501 yield from self.do_rc_ov(
2502 ins_name, results[0], overflow, cr0, cr1, FPSCR)
2503
2504 # check failfirst
2505 ffirst_hit = False, False
2506 if self.is_svp64_mode:
2507 sv_mode = yield self.dec2.rm_dec.sv_mode
2508 is_cr = sv_mode == SVMode.CROP.value
2509 chk = rc_en or is_cr
2510 if outs_ok.get('CR', False):
2511 # early write so check_ffirst can see value
2512 self.namespace['CR'].eq(outs['CR'])
2513 ffirst_hit = (yield from self.check_ffirst(info, chk, srcstep))
2514
2515 # any modified return results?
2516 yield from self.do_outregs(
2517 info, outs, carry_en, ffirst_hit, ew_dst, outs_ok)
2518
2519 # check if a FP Exception occurred. TODO for DD-FFirst, check VLi
2520 # and raise the exception *after* if VLi=1 but if VLi=0 then
2521 # truncate and make the exception "disappear".
2522 if self.FPSCR.FEX and (self.msr[MSRb.FE0] or self.msr[MSRb.FE1]):
2523 self.call_trap(0x700, PIb.FP)
2524 return
2525
2526 yield from self.do_nia(asmop, ins_name, rc_en, ffirst_hit)
2527
2528 def check_ffirst(self, info, rc_en, srcstep):
2529 """fail-first mode: checks a bit of Rc Vector, truncates VL
2530 """
2531 rm_mode = yield self.dec2.rm_dec.mode
2532 ff_inv = yield self.dec2.rm_dec.inv
2533 cr_bit = yield self.dec2.rm_dec.cr_sel
2534 RC1 = yield self.dec2.rm_dec.RC1
2535 vli_ = yield self.dec2.rm_dec.vli # VL inclusive if truncated
2536 log(" ff rm_mode", rc_en, rm_mode, SVP64RMMode.FFIRST.value)
2537 log(" inv", ff_inv)
2538 log(" RC1", RC1)
2539 log(" vli", vli_)
2540 log(" cr_bit", cr_bit)
2541 log(" rc_en", rc_en)
2542 ffirst = yield from is_ffirst_mode(self.dec2)
2543 if not rc_en or not ffirst:
2544 return False, False
2545 # get the CR vevtor, do BO-test
2546 crf = "CR0"
2547 log("asmregs", info.asmregs[0], info.write_regs)
2548 if 'CR' in info.write_regs and 'BF' in info.asmregs[0]:
2549 crf = 'BF'
2550 regnum, is_vec = yield from get_cr_out(self.dec2, crf)
2551 crtest = self.crl[regnum]
2552 ffirst_hit = crtest[cr_bit] != ff_inv
2553 log("cr test", crf, regnum, int(crtest), crtest, cr_bit, ff_inv)
2554 log("cr test?", ffirst_hit)
2555 if not ffirst_hit:
2556 return False, False
2557 # Fail-first activated, truncate VL
2558 vli = SelectableInt(int(vli_), 7)
2559 self.svstate.vl = srcstep + vli
2560 yield self.dec2.state.svstate.eq(self.svstate.value)
2561 yield Settle() # let decoder update
2562 return True, vli_
2563
2564 def do_rc_ov(self, ins_name, result, overflow, cr0, cr1, FPSCR):
2565 cr_out = yield self.dec2.op.cr_out
2566 if cr_out == CROutSel.CR1.value:
2567 rc_reg = "CR1"
2568 else:
2569 rc_reg = "CR0"
2570 regnum, is_vec = yield from get_cr_out(self.dec2, rc_reg)
2571 # hang on... for `setvl` actually you want to test SVSTATE.VL
2572 is_setvl = ins_name in ('svstep', 'setvl')
2573 if is_setvl:
2574 result = SelectableInt(result.vl, 64)
2575 # else:
2576 # overflow = None # do not override overflow except in setvl
2577
2578 if rc_reg == "CR1":
2579 if cr1 is None:
2580 cr1 = int(FPSCR.FX) << 3
2581 cr1 |= int(FPSCR.FEX) << 2
2582 cr1 |= int(FPSCR.VX) << 1
2583 cr1 |= int(FPSCR.OX)
2584 log("default fp cr1", cr1)
2585 else:
2586 log("explicit cr1", cr1)
2587 self.crl[regnum].eq(cr1)
2588 elif cr0 is None:
2589 # if there was not an explicit CR0 in the pseudocode,
2590 # do implicit Rc=1
2591 c = self.handle_comparison(result, regnum, overflow, no_so=is_setvl)
2592 log("implicit cr0", c)
2593 else:
2594 # otherwise we just blat CR0 into the required regnum
2595 log("explicit cr0", cr0)
2596 self.crl[regnum].eq(cr0)
2597
2598 def do_outregs(self, info, outs, ca_en, ffirst_hit, ew_dst, outs_ok):
2599 ffirst_hit, vli = ffirst_hit
2600 # write out any regs for this instruction, but only if fail-first is ok
2601 # XXX TODO: allow CR-vector to be written out even if ffirst fails
2602 if not ffirst_hit or vli:
2603 for name, output in outs.items():
2604 if not outs_ok[name]:
2605 log("skipping writing output with .ok=False", name, output)
2606 continue
2607 yield from self.check_write(info, name, output, ca_en, ew_dst)
2608 # restore the CR value on non-VLI failfirst (from sv.cmp and others
2609 # which write directly to CR in the pseudocode (gah, what a mess)
2610 # if ffirst_hit and not vli:
2611 # self.cr.value = self.cr_backup
2612
2613 def do_nia(self, asmop, ins_name, rc_en, ffirst_hit):
2614 ffirst_hit, vli = ffirst_hit
2615 if ffirst_hit:
2616 self.svp64_reset_loop()
2617 nia_update = True
2618 else:
2619 # check advancement of src/dst/sub-steps and if PC needs updating
2620 nia_update = (yield from self.check_step_increment(
2621 rc_en, asmop, ins_name))
2622 if nia_update:
2623 self.update_pc_next()
2624
2625 def check_replace_d(self, info, remap_active):
2626 replace_d = False # update / replace constant in pseudocode
2627 ldstmode = yield self.dec2.rm_dec.ldstmode
2628 vl = self.svstate.vl
2629 subvl = yield self.dec2.rm_dec.rm_in.subvl
2630 srcstep, dststep = self.new_srcstep, self.new_dststep
2631 ssubstep, dsubstep = self.new_ssubstep, self.new_dsubstep
2632 if info.form == 'DS':
2633 # DS-Form, multiply by 4 then knock 2 bits off after
2634 imm = yield self.dec2.dec.fields.FormDS.DS[0:14] * 4
2635 else:
2636 imm = yield self.dec2.dec.fields.FormD.D[0:16]
2637 imm = exts(imm, 16) # sign-extend to integer
2638 # get the right step. LD is from srcstep, ST is dststep
2639 op = yield self.dec2.e.do.insn_type
2640 offsmul = 0
2641 if op == MicrOp.OP_LOAD.value:
2642 if remap_active:
2643 offsmul = yield self.dec2.in1_step
2644 log("D-field REMAP src", imm, offsmul, ldstmode)
2645 else:
2646 offsmul = (srcstep * (subvl+1)) + ssubstep
2647 log("D-field src", imm, offsmul, ldstmode)
2648 elif op == MicrOp.OP_STORE.value:
2649 # XXX NOTE! no bit-reversed STORE! this should not ever be used
2650 offsmul = (dststep * (subvl+1)) + dsubstep
2651 log("D-field dst", imm, offsmul, ldstmode)
2652 # Unit-Strided LD/ST adds offset*width to immediate
2653 if ldstmode == SVP64LDSTmode.UNITSTRIDE.value:
2654 ldst_len = yield self.dec2.e.do.data_len
2655 imm = SelectableInt(imm + offsmul * ldst_len, 32)
2656 replace_d = True
2657 # Element-strided multiplies the immediate by element step
2658 elif ldstmode == SVP64LDSTmode.ELSTRIDE.value:
2659 imm = SelectableInt(imm * offsmul, 32)
2660 replace_d = True
2661 if replace_d:
2662 ldst_ra_vec = yield self.dec2.rm_dec.ldst_ra_vec
2663 ldst_imz_in = yield self.dec2.rm_dec.ldst_imz_in
2664 log("LDSTmode", SVP64LDSTmode(ldstmode),
2665 offsmul, imm, ldst_ra_vec, ldst_imz_in)
2666 # new replacement D... errr.. DS
2667 if replace_d:
2668 if info.form == 'DS':
2669 # TODO: assert 2 LSBs are zero?
2670 log("DS-Form, TODO, assert 2 LSBs zero?", bin(imm.value))
2671 imm.value = imm.value >> 2
2672 self.namespace['DS'] = imm
2673 else:
2674 self.namespace['D'] = imm
2675
2676 def get_input(self, name, ew_src, xlen):
2677 # using PowerDecoder2, first, find the decoder index.
2678 # (mapping name RA RB RC RS to in1, in2, in3)
2679 regnum, is_vec = yield from get_idx_in(self.dec2, name, True)
2680 if regnum is None:
2681 # doing this is not part of svp64, it's because output
2682 # registers, to be modified, need to be in the namespace.
2683 regnum, is_vec = yield from get_idx_out(self.dec2, name, True)
2684 if regnum is None:
2685 regnum, is_vec = yield from get_idx_out2(self.dec2, name, True)
2686
2687 if isinstance(regnum, tuple):
2688 (regnum, base, offs) = regnum
2689 else:
2690 base, offs = regnum, 0 # temporary HACK
2691
2692 # in case getting the register number is needed, _RA, _RB
2693 # (HACK: only in straight non-svp64-mode for now, or elwidth == 64)
2694 regname = "_" + name
2695 if not self.is_svp64_mode or ew_src == 64:
2696 self.namespace[regname] = regnum
2697 else:
2698 # FIXME: we're trying to access a sub-register, plain register
2699 # numbers don't work for that. for now, just pass something that
2700 # can be compared to 0 and probably will cause an error if misused.
2701 # see https://bugs.libre-soc.org/show_bug.cgi?id=1221
2702 self.namespace[regname] = regnum * 10000
2703
2704 if not self.is_svp64_mode or not self.pred_src_zero:
2705 log('reading reg %s %s' % (name, str(regnum)), is_vec)
2706 if name in fregs:
2707 fval = self.fpr(base, is_vec, offs, ew_src)
2708 reg_val = SelectableInt(fval)
2709 assert ew_src == self.XLEN, "TODO fix elwidth conversion"
2710 self.trace("r:FPR:%d:%d:%d " % (base, offs, ew_src))
2711 log("read fp reg %d/%d: 0x%x" % (base, offs, reg_val.value),
2712 kind=LogType.InstrInOuts)
2713 elif name is not None:
2714 gval = self.gpr(base, is_vec, offs, ew_src)
2715 reg_val = SelectableInt(gval.value, bits=xlen)
2716 self.trace("r:GPR:%d:%d:%d " % (base, offs, ew_src))
2717 log("read int reg %d/%d: 0x%x" % (base, offs, reg_val.value),
2718 kind=LogType.InstrInOuts)
2719 else:
2720 log('zero input reg %s %s' % (name, str(regnum)), is_vec)
2721 reg_val = SelectableInt(0, ew_src)
2722 return reg_val
2723
2724 def remap_set_steps(self, remaps):
2725 """remap_set_steps sets up the in1/2/3 and out1/2 steps.
2726 they work in concert with PowerDecoder2 at the moment,
2727 there is no HDL implementation of REMAP. therefore this
2728 function, because ISACaller still uses PowerDecoder2,
2729 will *explicitly* write the dec2.XX_step values. this has
2730 to get sorted out.
2731 """
2732 # just some convenient debug info
2733 for i in range(4):
2734 sname = 'SVSHAPE%d' % i
2735 shape = self.spr[sname]
2736 log(sname, bin(shape.value))
2737 log(" lims", shape.lims)
2738 log(" mode", shape.mode)
2739 log(" skip", shape.skip)
2740
2741 # set up the list of steps to remap
2742 mi0 = self.svstate.mi0
2743 mi1 = self.svstate.mi1
2744 mi2 = self.svstate.mi2
2745 mo0 = self.svstate.mo0
2746 mo1 = self.svstate.mo1
2747 steps = [[self.dec2.in1_step, mi0], # RA
2748 [self.dec2.in2_step, mi1], # RB
2749 [self.dec2.in3_step, mi2], # RC
2750 [self.dec2.o_step, mo0], # RT
2751 [self.dec2.o2_step, mo1], # EA
2752 ]
2753 if False: # TODO
2754 rnames = ['RA', 'RB', 'RC', 'RT', 'RS']
2755 for i, reg in enumerate(rnames):
2756 idx = yield from get_idx_map(self.dec2, reg)
2757 if idx is None:
2758 idx = yield from get_idx_map(self.dec2, "F"+reg)
2759 if idx == 1: # RA
2760 steps[i][0] = self.dec2.in1_step
2761 elif idx == 2: # RB
2762 steps[i][0] = self.dec2.in2_step
2763 elif idx == 3: # RC
2764 steps[i][0] = self.dec2.in3_step
2765 log("remap step", i, reg, idx, steps[i][1])
2766 remap_idxs = self.remap_idxs
2767 rremaps = []
2768 # now cross-index the required SHAPE for each of 3-in 2-out regs
2769 rnames = ['RA', 'RB', 'RC', 'RT', 'EA']
2770 for i, (dstep, shape_idx) in enumerate(steps):
2771 (shape, remap) = remaps[shape_idx]
2772 remap_idx = remap_idxs[shape_idx]
2773 # zero is "disabled"
2774 if shape.value == 0x0:
2775 continue
2776 # now set the actual requested step to the current index
2777 if dstep is not None:
2778 yield dstep.eq(remap_idx)
2779
2780 # debug printout info
2781 rremaps.append((shape.mode, hex(shape.value), dstep,
2782 i, rnames[i], shape_idx, remap_idx))
2783 for x in rremaps:
2784 log("shape remap", x)
2785
2786 def check_write(self, info, name, output, carry_en, ew_dst):
2787 if name == 'overflow': # ignore, done already (above)
2788 return
2789 if name == 'CR0': # ignore, done already (above)
2790 return
2791 if isinstance(output, int):
2792 output = SelectableInt(output, EFFECTIVELY_UNLIMITED)
2793 # write FPSCR
2794 if name in ['FPSCR', ]:
2795 log("write FPSCR 0x%x" % (output.value))
2796 self.FPSCR.eq(output)
2797 return
2798 # write carry flags
2799 if name in ['CA', 'CA32']:
2800 if carry_en:
2801 log("writing %s to XER" % name, output)
2802 log("write XER %s 0x%x" % (name, output.value))
2803 self.spr['XER'][XER_bits[name]] = output.value
2804 else:
2805 log("NOT writing %s to XER" % name, output)
2806 return
2807 # write special SPRs
2808 if name in info.special_regs:
2809 log('writing special %s' % name, output, special_sprs)
2810 log("write reg %s 0x%x" % (name, output.value),
2811 kind=LogType.InstrInOuts)
2812 if name in special_sprs:
2813 self.spr[name] = output
2814 else:
2815 self.namespace[name].eq(output)
2816 if name == 'MSR':
2817 log('msr written', hex(self.msr.value))
2818 return
2819 # find out1/out2 PR/FPR
2820 regnum, is_vec = yield from get_idx_out(self.dec2, name, True)
2821 if regnum is None:
2822 regnum, is_vec = yield from get_idx_out2(self.dec2, name, True)
2823 if regnum is None:
2824 # temporary hack for not having 2nd output
2825 regnum = yield getattr(self.decoder, name)
2826 is_vec = False
2827 # convenient debug prefix
2828 if name in fregs:
2829 reg_prefix = 'f'
2830 else:
2831 reg_prefix = 'r'
2832 # check zeroing due to predicate bit being zero
2833 if self.is_svp64_mode and self.pred_dst_zero:
2834 log('zeroing reg %s %s' % (str(regnum), str(output)), is_vec)
2835 output = SelectableInt(0, EFFECTIVELY_UNLIMITED)
2836 log("write reg %s%s 0x%x ew %d" % (reg_prefix, str(regnum),
2837 output.value, ew_dst),
2838 kind=LogType.InstrInOuts)
2839 # zero-extend tov64 bit begore storing (should use EXT oh well)
2840 if output.bits > 64:
2841 output = SelectableInt(output.value, 64)
2842 rnum, base, offset = regnum
2843 if name in fregs:
2844 self.fpr.write(regnum, output, is_vec, ew_dst)
2845 self.trace("w:FPR:%d:%d:%d " % (rnum, offset, ew_dst))
2846 return
2847
2848 # LDST/Update does *not* allow elwidths on RA (Effective Address).
2849 # this has to be detected, and overridden. see get_input (related)
2850 sv_mode = yield self.dec2.rm_dec.sv_mode
2851 is_ldst = (sv_mode in [SVMode.LDST_IDX.value, SVMode.LDST_IMM.value] \
2852 and self.is_svp64_mode)
2853 if is_ldst and name in ['EA', 'RA']:
2854 op = self.dec2.dec.op
2855 if hasattr(op, "upd"):
2856 # update mode LD/ST uses read-reg A also as an output
2857 upd = yield op.upd
2858 log("write is_ldst is_update", sv_mode, is_ldst, upd)
2859 if upd == LDSTMode.update.value:
2860 ew_dst = 64 # override for RA (EA) to 64-bit
2861
2862 self.gpr.write(regnum, output, is_vec, ew_dst)
2863 self.trace("w:GPR:%d:%d:%d " % (rnum, offset, ew_dst))
2864
2865 def check_step_increment(self, rc_en, asmop, ins_name):
2866 # check if it is the SVSTATE.src/dest step that needs incrementing
2867 # this is our Sub-Program-Counter loop from 0 to VL-1
2868 if not self.allow_next_step_inc:
2869 if self.is_svp64_mode:
2870 return (yield from self.svstate_post_inc(ins_name))
2871
2872 # XXX only in non-SVP64 mode!
2873 # record state of whether the current operation was an svshape,
2874 # OR svindex!
2875 # to be able to know if it should apply in the next instruction.
2876 # also (if going to use this instruction) should disable ability
2877 # to interrupt in between. sigh.
2878 self.last_op_svshape = asmop in ['svremap', 'svindex',
2879 'svshape2']
2880 return True
2881
2882 pre = False
2883 post = False
2884 nia_update = True
2885 log("SVSTATE_NEXT: inc requested, mode",
2886 self.svstate_next_mode, self.allow_next_step_inc)
2887 yield from self.svstate_pre_inc()
2888 pre = yield from self.update_new_svstate_steps()
2889 if pre:
2890 # reset at end of loop including exit Vertical Mode
2891 log("SVSTATE_NEXT: end of loop, reset")
2892 self.svp64_reset_loop()
2893 self.svstate.vfirst = 0
2894 self.update_nia()
2895 if not rc_en:
2896 return True
2897 self.handle_comparison(SelectableInt(0, 64)) # CR0
2898 return True
2899 if self.allow_next_step_inc == 2:
2900 log("SVSTATE_NEXT: read")
2901 nia_update = (yield from self.svstate_post_inc(ins_name))
2902 else:
2903 log("SVSTATE_NEXT: post-inc")
2904 # use actual (cached) src/dst-step here to check end
2905 remaps = self.get_remap_indices()
2906 remap_idxs = self.remap_idxs
2907 vl = self.svstate.vl
2908 subvl = yield self.dec2.rm_dec.rm_in.subvl
2909 if self.allow_next_step_inc != 2:
2910 yield from self.advance_svstate_steps()
2911 #self.namespace['SVSTATE'] = self.svstate.spr
2912 # set CR0 (if Rc=1) based on end
2913 endtest = 1 if self.at_loopend() else 0
2914 if rc_en:
2915 #results = [SelectableInt(endtest, 64)]
2916 # self.handle_comparison(results) # CR0
2917
2918 # see if svstep was requested, if so, which SVSTATE
2919 endings = 0b111
2920 if self.svstate_next_mode > 0:
2921 shape_idx = self.svstate_next_mode.value-1
2922 endings = self.remap_loopends[shape_idx]
2923 cr_field = SelectableInt((~endings) << 1 | endtest, 4)
2924 log("svstep Rc=1, CR0", cr_field, endtest)
2925 self.crl[0].eq(cr_field) # CR0
2926 if endtest:
2927 # reset at end of loop including exit Vertical Mode
2928 log("SVSTATE_NEXT: after increments, reset")
2929 self.svp64_reset_loop()
2930 self.svstate.vfirst = 0
2931 return nia_update
2932
2933 def SVSTATE_NEXT(self, mode, submode):
2934 """explicitly moves srcstep/dststep on to next element, for
2935 "Vertical-First" mode. this function is called from
2936 setvl pseudo-code, as a pseudo-op "svstep"
2937
2938 WARNING: this function uses information that was created EARLIER
2939 due to it being in the middle of a yield, but this function is
2940 *NOT* called from yield (it's called from compiled pseudocode).
2941 """
2942 self.allow_next_step_inc = submode.value + 1
2943 log("SVSTATE_NEXT mode", mode, submode, self.allow_next_step_inc)
2944 self.svstate_next_mode = mode
2945 if self.svstate_next_mode > 0 and self.svstate_next_mode < 5:
2946 shape_idx = self.svstate_next_mode.value-1
2947 return SelectableInt(self.remap_idxs[shape_idx], 7)
2948 if self.svstate_next_mode == 5:
2949 self.svstate_next_mode = 0
2950 return SelectableInt(self.svstate.srcstep, 7)
2951 if self.svstate_next_mode == 6:
2952 self.svstate_next_mode = 0
2953 return SelectableInt(self.svstate.dststep, 7)
2954 if self.svstate_next_mode == 7:
2955 self.svstate_next_mode = 0
2956 return SelectableInt(self.svstate.ssubstep, 7)
2957 if self.svstate_next_mode == 8:
2958 self.svstate_next_mode = 0
2959 return SelectableInt(self.svstate.dsubstep, 7)
2960 return SelectableInt(0, 7)
2961
2962 def get_src_dststeps(self):
2963 """gets srcstep, dststep, and ssubstep, dsubstep
2964 """
2965 return (self.new_srcstep, self.new_dststep,
2966 self.new_ssubstep, self.new_dsubstep)
2967
2968 def update_svstate_namespace(self, overwrite_svstate=True):
2969 if overwrite_svstate:
2970 # note, do not get the bit-reversed srcstep here!
2971 srcstep, dststep = self.new_srcstep, self.new_dststep
2972 ssubstep, dsubstep = self.new_ssubstep, self.new_dsubstep
2973
2974 # update SVSTATE with new srcstep
2975 self.svstate.srcstep = srcstep
2976 self.svstate.dststep = dststep
2977 self.svstate.ssubstep = ssubstep
2978 self.svstate.dsubstep = dsubstep
2979 self.namespace['SVSTATE'] = self.svstate
2980 yield self.dec2.state.svstate.eq(self.svstate.value)
2981 yield Settle() # let decoder update
2982
2983 def update_new_svstate_steps(self, overwrite_svstate=True):
2984 yield from self.update_svstate_namespace(overwrite_svstate)
2985 srcstep = self.svstate.srcstep
2986 dststep = self.svstate.dststep
2987 ssubstep = self.svstate.ssubstep
2988 dsubstep = self.svstate.dsubstep
2989 pack = self.svstate.pack
2990 unpack = self.svstate.unpack
2991 vl = self.svstate.vl
2992 sv_mode = yield self.dec2.rm_dec.sv_mode
2993 subvl = yield self.dec2.rm_dec.rm_in.subvl
2994 rm_mode = yield self.dec2.rm_dec.mode
2995 ff_inv = yield self.dec2.rm_dec.inv
2996 cr_bit = yield self.dec2.rm_dec.cr_sel
2997 log(" srcstep", srcstep)
2998 log(" dststep", dststep)
2999 log(" pack", pack)
3000 log(" unpack", unpack)
3001 log(" ssubstep", ssubstep)
3002 log(" dsubstep", dsubstep)
3003 log(" vl", vl)
3004 log(" subvl", subvl)
3005 log(" rm_mode", rm_mode)
3006 log(" sv_mode", sv_mode)
3007 log(" inv", ff_inv)
3008 log(" cr_bit", cr_bit)
3009
3010 # check if end reached (we let srcstep overrun, above)
3011 # nothing needs doing (TODO zeroing): just do next instruction
3012 if self.loopend:
3013 return True
3014 return ((ssubstep == subvl and srcstep == vl) or
3015 (dsubstep == subvl and dststep == vl))
3016
3017 def svstate_post_inc(self, insn_name, vf=0):
3018 # check if SV "Vertical First" mode is enabled
3019 vfirst = self.svstate.vfirst
3020 log(" SV Vertical First", vf, vfirst)
3021 if not vf and vfirst == 1:
3022 # SV Branch-Conditional required to be as-if-vector
3023 # because there *is* no destination register
3024 # (SV normally only terminates on 1st scalar reg written
3025 # except in [slightly-misnamed] mapreduce mode)
3026 ffirst = yield from is_ffirst_mode(self.dec2)
3027 if insn_name.startswith("sv.bc") or ffirst:
3028 self.update_pc_next()
3029 return False
3030 self.update_nia()
3031 return True
3032
3033 # check if it is the SVSTATE.src/dest step that needs incrementing
3034 # this is our Sub-Program-Counter loop from 0 to VL-1
3035 # XXX twin predication TODO
3036 vl = self.svstate.vl
3037 subvl = yield self.dec2.rm_dec.rm_in.subvl
3038 mvl = self.svstate.maxvl
3039 srcstep = self.svstate.srcstep
3040 dststep = self.svstate.dststep
3041 ssubstep = self.svstate.ssubstep
3042 dsubstep = self.svstate.dsubstep
3043 pack = self.svstate.pack
3044 unpack = self.svstate.unpack
3045 rm_mode = yield self.dec2.rm_dec.mode
3046 reverse_gear = yield self.dec2.rm_dec.reverse_gear
3047 sv_ptype = yield self.dec2.dec.op.SV_Ptype
3048 out_vec = not (yield self.dec2.no_out_vec)
3049 in_vec = not (yield self.dec2.no_in_vec)
3050 rm_mode = yield self.dec2.rm_dec.mode
3051 log(" svstate.vl", vl)
3052 log(" svstate.mvl", mvl)
3053 log(" rm.subvl", subvl)
3054 log(" svstate.srcstep", srcstep)
3055 log(" svstate.dststep", dststep)
3056 log(" svstate.ssubstep", ssubstep)
3057 log(" svstate.dsubstep", dsubstep)
3058 log(" svstate.pack", pack)
3059 log(" svstate.unpack", unpack)
3060 log(" mode", rm_mode)
3061 log(" reverse", reverse_gear)
3062 log(" out_vec", out_vec)
3063 log(" in_vec", in_vec)
3064 log(" sv_ptype", sv_ptype, sv_ptype == SVPType.P2.value)
3065 log(" rm_mode", rm_mode)
3066 # check if this was an sv.bc* and if so did it succeed
3067 if self.is_svp64_mode and insn_name.startswith("sv.bc"):
3068 end_loop = self.namespace['end_loop']
3069 log("branch %s end_loop" % insn_name, end_loop)
3070 if end_loop.value:
3071 self.svp64_reset_loop()
3072 self.update_pc_next()
3073 return False
3074 # check if srcstep needs incrementing by one, stop PC advancing
3075 # but for 2-pred both src/dest have to be checked.
3076 # XXX this might not be true! it may just be LD/ST
3077 if sv_ptype == SVPType.P2.value:
3078 svp64_is_vector = (out_vec or in_vec)
3079 else:
3080 svp64_is_vector = out_vec
3081 # also if data-dependent fail-first is used, only in_vec is tested,
3082 # allowing *scalar destinations* to be used as an accumulator.
3083 # effectively this implies /mr (mapreduce mode) is 100% on with ddffirst
3084 # see https://bugs.libre-soc.org/show_bug.cgi?id=1183#c16
3085 ffirst = yield from is_ffirst_mode(self.dec2)
3086 if ffirst:
3087 svp64_is_vector = in_vec
3088
3089 # loops end at the first "hit" (source or dest)
3090 yield from self.advance_svstate_steps()
3091 loopend = self.loopend
3092 log("loopend", svp64_is_vector, loopend)
3093 if not svp64_is_vector or loopend:
3094 # reset loop to zero and update NIA
3095 self.svp64_reset_loop()
3096 self.update_nia()
3097
3098 return True
3099
3100 # still looping, advance and update NIA
3101 self.namespace['SVSTATE'] = self.svstate
3102
3103 # not an SVP64 branch, so fix PC (NIA==CIA) for next loop
3104 # (by default, NIA is CIA+4 if v3.0B or CIA+8 if SVP64)
3105 # this way we keep repeating the same instruction (with new steps)
3106 self.pc.NIA.eq(self.pc.CIA)
3107 self.namespace['NIA'] = self.pc.NIA
3108 log("end of sub-pc call", self.namespace['CIA'], self.namespace['NIA'])
3109 return False # DO NOT allow PC update whilst Sub-PC loop running
3110
3111 def update_pc_next(self):
3112 # UPDATE program counter
3113 self.pc.update(self.namespace, self.is_svp64_mode)
3114 #self.svstate.spr = self.namespace['SVSTATE']
3115 log("end of call", self.namespace['CIA'],
3116 self.namespace['NIA'],
3117 self.namespace['SVSTATE'])
3118
3119 def svp64_reset_loop(self):
3120 self.svstate.srcstep = 0
3121 self.svstate.dststep = 0
3122 self.svstate.ssubstep = 0
3123 self.svstate.dsubstep = 0
3124 self.loopend = False
3125 log(" svstate.srcstep loop end (PC to update)")
3126 self.namespace['SVSTATE'] = self.svstate
3127
3128 def update_nia(self):
3129 self.pc.update_nia(self.is_svp64_mode)
3130 self.namespace['NIA'] = self.pc.NIA
3131
3132
3133 def inject():
3134 """Decorator factory.
3135
3136 this decorator will "inject" variables into the function's namespace,
3137 from the *dictionary* in self.namespace. it therefore becomes possible
3138 to make it look like a whole stack of variables which would otherwise
3139 need "self." inserted in front of them (*and* for those variables to be
3140 added to the instance) "appear" in the function.
3141
3142 "self.namespace['SI']" for example becomes accessible as just "SI" but
3143 *only* inside the function, when decorated.
3144 """
3145 def variable_injector(func):
3146 @wraps(func)
3147 def decorator(*args, **kwargs):
3148 try:
3149 func_globals = func.__globals__ # Python 2.6+
3150 except AttributeError:
3151 func_globals = func.func_globals # Earlier versions.
3152
3153 context = args[0].namespace # variables to be injected
3154 saved_values = func_globals.copy() # Shallow copy of dict.
3155 log("globals before", context.keys())
3156 func_globals.update(context)
3157 result = func(*args, **kwargs)
3158 log("globals after", func_globals['CIA'], func_globals['NIA'])
3159 log("args[0]", args[0].namespace['CIA'],
3160 args[0].namespace['NIA'],
3161 args[0].namespace['SVSTATE'])
3162 if 'end_loop' in func_globals:
3163 log("args[0] end_loop", func_globals['end_loop'])
3164 args[0].namespace = func_globals
3165 #exec (func.__code__, func_globals)
3166
3167 # finally:
3168 # func_globals = saved_values # Undo changes.
3169
3170 return result
3171
3172 return decorator
3173
3174 return variable_injector