94ac7c008366d5edc9a7fadd34e8033e135084df
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020 Michael Nolan
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
17 from nmigen
.sim
import Settle
, Delay
18 from functools
import wraps
19 from copy
import copy
, deepcopy
20 from openpower
.decoder
.orderedset
import OrderedSet
21 from openpower
.decoder
.selectable_int
import (
26 from openpower
.decoder
.power_insn
import SVP64Instruction
27 from openpower
.decoder
.power_enums
import (spr_dict
, spr_byname
, XER_bits
,
29 In1Sel
, In2Sel
, In3Sel
,
30 OutSel
, CRInSel
, CROutSel
, LDSTMode
,
31 SVP64RMMode
, SVP64PredMode
,
32 SVP64PredInt
, SVP64PredCR
,
33 SVP64LDSTmode
, FPTRANS_INSNS
)
35 from openpower
.decoder
.power_enums
import SVPtype
37 from openpower
.decoder
.helpers
import (exts
, gtu
, ltu
, undefined
,
38 ISACallerHelper
, ISAFPHelpers
)
39 from openpower
.consts
import PIb
, MSRb
# big-endian (PowerISA versions)
40 from openpower
.consts
import (SVP64MODE
, SVP64MODEb
,
43 from openpower
.decoder
.power_svp64
import SVP64RM
, decode_extra
45 from openpower
.decoder
.isa
.radixmmu
import RADIX
46 from openpower
.decoder
.isa
.mem
import Mem
, swap_order
, MemException
47 from openpower
.decoder
.isa
.svshape
import SVSHAPE
48 from openpower
.decoder
.isa
.svstate
import SVP64State
51 from openpower
.util
import LogKind
, log
53 from collections
import namedtuple
57 instruction_info
= namedtuple('instruction_info',
58 'func read_regs uninit_regs write_regs ' +
59 'special_regs op_fields form asmregs')
69 # rrright. this is here basically because the compiler pywriter returns
70 # results in a specific priority order. to make sure regs match up they
71 # need partial sorting. sigh.
73 # TODO (lkcl): adjust other registers that should be in a particular order
74 # probably CA, CA32, and CR
100 "overflow": 7, # should definitely be last
104 fregs
= ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
107 def create_args(reglist
, extra
=None):
108 retval
= list(OrderedSet(reglist
))
109 retval
.sort(key
=lambda reg
: REG_SORT_ORDER
.get(reg
, 0))
110 if extra
is not None:
111 return [extra
] + retval
116 def __init__(self
, decoder
, isacaller
, svstate
, regfile
):
119 self
.isacaller
= isacaller
120 self
.svstate
= svstate
121 for i
in range(len(regfile
)):
122 self
[i
] = SelectableInt(regfile
[i
], 64)
124 def __call__(self
, ridx
):
125 if isinstance(ridx
, SelectableInt
):
129 def set_form(self
, form
):
132 def __setitem__(self
, rnum
, value
):
133 # rnum = rnum.value # only SelectableInt allowed
134 log("GPR setitem", rnum
, value
)
135 if isinstance(rnum
, SelectableInt
):
137 dict.__setitem
__(self
, rnum
, value
)
139 def getz(self
, rnum
):
140 # rnum = rnum.value # only SelectableInt allowed
141 log("GPR getzero?", rnum
)
143 return SelectableInt(0, 64)
146 def _get_regnum(self
, attr
):
147 getform
= self
.sd
.sigforms
[self
.form
]
148 rnum
= getattr(getform
, attr
)
151 def ___getitem__(self
, attr
):
152 """ XXX currently not used
154 rnum
= self
._get
_regnum
(attr
)
155 log("GPR getitem", attr
, rnum
)
156 return self
.regfile
[rnum
]
158 def dump(self
, printout
=True):
160 for i
in range(len(self
)):
161 res
.append(self
[i
].value
)
163 for i
in range(0, len(res
), 8):
166 s
.append("%08x" % res
[i
+j
])
168 print("reg", "%2d" % i
, s
)
173 def __init__(self
, dec2
, initial_sprs
={}):
176 for key
, v
in initial_sprs
.items():
177 if isinstance(key
, SelectableInt
):
179 key
= special_sprs
.get(key
, key
)
180 if isinstance(key
, int):
183 info
= spr_byname
[key
]
184 if not isinstance(v
, SelectableInt
):
185 v
= SelectableInt(v
, info
.length
)
188 def __getitem__(self
, key
):
190 log("dict", self
.items())
191 # if key in special_sprs get the special spr, otherwise return key
192 if isinstance(key
, SelectableInt
):
194 if isinstance(key
, int):
195 key
= spr_dict
[key
].SPR
196 key
= special_sprs
.get(key
, key
)
197 if key
== 'HSRR0': # HACK!
199 if key
== 'HSRR1': # HACK!
202 res
= dict.__getitem
__(self
, key
)
204 if isinstance(key
, int):
207 info
= spr_byname
[key
]
208 dict.__setitem
__(self
, key
, SelectableInt(0, info
.length
))
209 res
= dict.__getitem
__(self
, key
)
210 log("spr returning", key
, res
)
213 def __setitem__(self
, key
, value
):
214 if isinstance(key
, SelectableInt
):
216 if isinstance(key
, int):
217 key
= spr_dict
[key
].SPR
219 key
= special_sprs
.get(key
, key
)
220 if key
== 'HSRR0': # HACK!
221 self
.__setitem
__('SRR0', value
)
222 if key
== 'HSRR1': # HACK!
223 self
.__setitem
__('SRR1', value
)
224 log("setting spr", key
, value
)
225 dict.__setitem
__(self
, key
, value
)
227 def __call__(self
, ridx
):
230 def dump(self
, printout
=True):
232 keys
= list(self
.keys())
235 sprname
= spr_dict
.get(k
, None)
239 sprname
= sprname
.SPR
240 res
.append((sprname
, self
[k
].value
))
242 for sprname
, value
in res
:
243 print(" ", sprname
, hex(value
))
248 def __init__(self
, pc_init
=0):
249 self
.CIA
= SelectableInt(pc_init
, 64)
250 self
.NIA
= self
.CIA
+ SelectableInt(4, 64) # only true for v3.0B!
252 def update_nia(self
, is_svp64
):
253 increment
= 8 if is_svp64
else 4
254 self
.NIA
= self
.CIA
+ SelectableInt(increment
, 64)
256 def update(self
, namespace
, is_svp64
):
257 """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
259 self
.CIA
= namespace
['NIA'].narrow(64)
260 self
.update_nia(is_svp64
)
261 namespace
['CIA'] = self
.CIA
262 namespace
['NIA'] = self
.NIA
266 # See PowerISA Version 3.0 B Book 1
267 # Section 2.3.1 Condition Register pages 30 - 31
269 LT
= FL
= 0 # negative, less than, floating-point less than
270 GT
= FG
= 1 # positive, greater than, floating-point greater than
271 EQ
= FE
= 2 # equal, floating-point equal
272 SO
= FU
= 3 # summary overflow, floating-point unordered
274 def __init__(self
, init
=0):
275 # rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
276 # self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
277 self
.cr
= SelectableInt(init
, 64) # underlying reg
278 # field-selectable versions of Condition Register TODO check bitranges?
281 bits
= tuple(range(i
*4+32, (i
+1)*4+32))
282 _cr
= FieldSelectableInt(self
.cr
, bits
)
286 # decode SVP64 predicate integer to reg number and invert
287 def get_predint(gpr
, mask
):
291 log("get_predint", mask
, SVP64PredInt
.ALWAYS
.value
)
292 if mask
== SVP64PredInt
.ALWAYS
.value
:
293 return 0xffff_ffff_ffff_ffff # 64 bits of 1
294 if mask
== SVP64PredInt
.R3_UNARY
.value
:
295 return 1 << (r3
.value
& 0b111111)
296 if mask
== SVP64PredInt
.R3
.value
:
298 if mask
== SVP64PredInt
.R3_N
.value
:
300 if mask
== SVP64PredInt
.R10
.value
:
302 if mask
== SVP64PredInt
.R10_N
.value
:
304 if mask
== SVP64PredInt
.R30
.value
:
306 if mask
== SVP64PredInt
.R30_N
.value
:
310 # decode SVP64 predicate CR to reg number and invert status
311 def _get_predcr(mask
):
312 if mask
== SVP64PredCR
.LT
.value
:
314 if mask
== SVP64PredCR
.GE
.value
:
316 if mask
== SVP64PredCR
.GT
.value
:
318 if mask
== SVP64PredCR
.LE
.value
:
320 if mask
== SVP64PredCR
.EQ
.value
:
322 if mask
== SVP64PredCR
.NE
.value
:
324 if mask
== SVP64PredCR
.SO
.value
:
326 if mask
== SVP64PredCR
.NS
.value
:
330 # read individual CR fields (0..VL-1), extract the required bit
331 # and construct the mask
332 def get_predcr(crl
, mask
, vl
):
333 idx
, noninv
= _get_predcr(mask
)
336 cr
= crl
[i
+SVP64CROffs
.CRPred
]
337 if cr
[idx
].value
== noninv
:
342 # TODO, really should just be using PowerDecoder2
343 def get_pdecode_idx_in(dec2
, name
):
345 in1_sel
= yield op
.in1_sel
346 in2_sel
= yield op
.in2_sel
347 in3_sel
= yield op
.in3_sel
348 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
349 in1
= yield dec2
.e
.read_reg1
.data
350 in2
= yield dec2
.e
.read_reg2
.data
351 in3
= yield dec2
.e
.read_reg3
.data
352 in1_isvec
= yield dec2
.in1_isvec
353 in2_isvec
= yield dec2
.in2_isvec
354 in3_isvec
= yield dec2
.in3_isvec
355 log("get_pdecode_idx_in in1", name
, in1_sel
, In1Sel
.RA
.value
,
357 log("get_pdecode_idx_in in2", name
, in2_sel
, In2Sel
.RB
.value
,
359 log("get_pdecode_idx_in in3", name
, in3_sel
, In3Sel
.RS
.value
,
361 log("get_pdecode_idx_in FRS in3", name
, in3_sel
, In3Sel
.FRS
.value
,
363 log("get_pdecode_idx_in FRB in2", name
, in2_sel
, In2Sel
.FRB
.value
,
365 log("get_pdecode_idx_in FRC in3", name
, in3_sel
, In3Sel
.FRC
.value
,
367 # identify which regnames map to in1/2/3
368 if name
== 'RA' or name
== 'RA_OR_ZERO':
369 if (in1_sel
== In1Sel
.RA
.value
or
370 (in1_sel
== In1Sel
.RA_OR_ZERO
.value
and in1
!= 0)):
371 return in1
, in1_isvec
372 if in1_sel
== In1Sel
.RA_OR_ZERO
.value
:
373 return in1
, in1_isvec
375 if in2_sel
== In2Sel
.RB
.value
:
376 return in2
, in2_isvec
377 if in3_sel
== In3Sel
.RB
.value
:
378 return in3
, in3_isvec
379 # XXX TODO, RC doesn't exist yet!
381 if in3_sel
== In3Sel
.RC
.value
:
382 return in3
, in3_isvec
383 assert False, "RC does not exist yet"
385 if in1_sel
== In1Sel
.RS
.value
:
386 return in1
, in1_isvec
387 if in2_sel
== In2Sel
.RS
.value
:
388 return in2
, in2_isvec
389 if in3_sel
== In3Sel
.RS
.value
:
390 return in3
, in3_isvec
392 if in1_sel
== In1Sel
.FRA
.value
:
393 return in1
, in1_isvec
395 if in2_sel
== In2Sel
.FRB
.value
:
396 return in2
, in2_isvec
398 if in3_sel
== In3Sel
.FRC
.value
:
399 return in3
, in3_isvec
401 if in1_sel
== In1Sel
.FRS
.value
:
402 return in1
, in1_isvec
403 if in3_sel
== In3Sel
.FRS
.value
:
404 return in3
, in3_isvec
408 # TODO, really should just be using PowerDecoder2
409 def get_pdecode_cr_in(dec2
, name
):
411 in_sel
= yield op
.cr_in
412 in_bitfield
= yield dec2
.dec_cr_in
.cr_bitfield
.data
413 sv_cr_in
= yield op
.sv_cr_in
414 spec
= yield dec2
.crin_svdec
.spec
415 sv_override
= yield dec2
.dec_cr_in
.sv_override
416 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
417 in1
= yield dec2
.e
.read_cr1
.data
418 cr_isvec
= yield dec2
.cr_in_isvec
419 log("get_pdecode_cr_in", in_sel
, CROutSel
.CR0
.value
, in1
, cr_isvec
)
420 log(" sv_cr_in", sv_cr_in
)
421 log(" cr_bf", in_bitfield
)
423 log(" override", sv_override
)
424 # identify which regnames map to in / o2
426 if in_sel
== CRInSel
.BI
.value
:
428 log("get_pdecode_cr_in not found", name
)
432 # TODO, really should just be using PowerDecoder2
433 def get_pdecode_cr_out(dec2
, name
):
435 out_sel
= yield op
.cr_out
436 out_bitfield
= yield dec2
.dec_cr_out
.cr_bitfield
.data
437 sv_cr_out
= yield op
.sv_cr_out
438 spec
= yield dec2
.crout_svdec
.spec
439 sv_override
= yield dec2
.dec_cr_out
.sv_override
440 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
441 out
= yield dec2
.e
.write_cr
.data
442 o_isvec
= yield dec2
.o_isvec
443 log("get_pdecode_cr_out", out_sel
, CROutSel
.CR0
.value
, out
, o_isvec
)
444 log(" sv_cr_out", sv_cr_out
)
445 log(" cr_bf", out_bitfield
)
447 log(" override", sv_override
)
448 # identify which regnames map to out / o2
450 if out_sel
== CROutSel
.CR0
.value
:
452 if name
== 'CR1': # these are not actually calculated correctly
453 if out_sel
== CROutSel
.CR1
.value
:
455 log("get_pdecode_cr_out not found", name
)
459 # TODO, really should just be using PowerDecoder2
460 def get_pdecode_idx_out(dec2
, name
):
462 out_sel
= yield op
.out_sel
463 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
464 out
= yield dec2
.e
.write_reg
.data
465 o_isvec
= yield dec2
.o_isvec
466 # identify which regnames map to out / o2
468 log("get_pdecode_idx_out", out_sel
, OutSel
.RA
.value
, out
, o_isvec
)
469 if out_sel
== OutSel
.RA
.value
:
472 log("get_pdecode_idx_out", out_sel
, OutSel
.RT
.value
,
473 OutSel
.RT_OR_ZERO
.value
, out
, o_isvec
,
475 if out_sel
== OutSel
.RT
.value
:
477 if out_sel
== OutSel
.RT_OR_ZERO
.value
and out
!= 0:
479 elif name
== 'RT_OR_ZERO':
480 log("get_pdecode_idx_out", out_sel
, OutSel
.RT
.value
,
481 OutSel
.RT_OR_ZERO
.value
, out
, o_isvec
,
483 if out_sel
== OutSel
.RT_OR_ZERO
.value
:
486 log("get_pdecode_idx_out", out_sel
, OutSel
.FRA
.value
, out
, o_isvec
)
487 if out_sel
== OutSel
.FRA
.value
:
490 log("get_pdecode_idx_out", out_sel
, OutSel
.FRT
.value
,
491 OutSel
.FRT
.value
, out
, o_isvec
)
492 if out_sel
== OutSel
.FRT
.value
:
494 log("get_pdecode_idx_out not found", name
, out_sel
, out
, o_isvec
)
498 # TODO, really should just be using PowerDecoder2
499 def get_pdecode_idx_out2(dec2
, name
):
500 # check first if register is activated for write
502 out_sel
= yield op
.out_sel
503 out
= yield dec2
.e
.write_ea
.data
504 o_isvec
= yield dec2
.o2_isvec
505 out_ok
= yield dec2
.e
.write_ea
.ok
506 log("get_pdecode_idx_out2", name
, out_sel
, out
, out_ok
, o_isvec
)
511 if hasattr(op
, "upd"):
512 # update mode LD/ST uses read-reg A also as an output
514 log("get_pdecode_idx_out2", upd
, LDSTMode
.update
.value
,
515 out_sel
, OutSel
.RA
.value
,
517 if upd
== LDSTMode
.update
.value
:
520 fft_en
= yield dec2
.implicit_rs
522 log("get_pdecode_idx_out2", out_sel
, OutSel
.RS
.value
,
526 fft_en
= yield dec2
.implicit_rs
528 log("get_pdecode_idx_out2", out_sel
, OutSel
.FRS
.value
,
535 """deals with svstate looping.
538 def __init__(self
, svstate
):
539 self
.svstate
= svstate
542 def new_iterators(self
):
543 self
.src_it
= self
.src_iterator()
544 self
.dst_it
= self
.dst_iterator()
548 self
.new_ssubstep
= 0
549 self
.new_dsubstep
= 0
550 self
.pred_dst_zero
= 0
551 self
.pred_src_zero
= 0
553 def src_iterator(self
):
554 """source-stepping iterator
556 pack
= self
.svstate
.pack
560 # pack advances subvl in *outer* loop
561 while True: # outer subvl loop
562 while True: # inner vl loop
565 srcmask
= self
.srcmask
566 srcstep
= self
.svstate
.srcstep
567 pred_src_zero
= ((1 << srcstep
) & srcmask
) != 0
568 if self
.pred_sz
or pred_src_zero
:
569 self
.pred_src_zero
= not pred_src_zero
570 log(" advance src", srcstep
, vl
,
571 self
.svstate
.ssubstep
, subvl
)
572 # yield actual substep/srcstep
573 yield (self
.svstate
.ssubstep
, srcstep
)
574 # the way yield works these could have been modified.
577 srcstep
= self
.svstate
.srcstep
578 log(" advance src check", srcstep
, vl
,
579 self
.svstate
.ssubstep
, subvl
, srcstep
== vl
-1,
580 self
.svstate
.ssubstep
== subvl
)
581 if srcstep
== vl
-1: # end-point
582 self
.svstate
.srcstep
= SelectableInt(0, 7) # reset
583 if self
.svstate
.ssubstep
== subvl
: # end-point
584 log(" advance pack stop")
586 break # exit inner loop
587 self
.svstate
.srcstep
+= SelectableInt(1, 7) # advance ss
589 if self
.svstate
.ssubstep
== subvl
: # end-point
590 self
.svstate
.ssubstep
= SelectableInt(0, 2) # reset
591 log(" advance pack stop")
593 self
.svstate
.ssubstep
+= SelectableInt(1, 2)
596 # these cannot be done as for-loops because SVSTATE may change
597 # (srcstep/substep may be modified, interrupted, subvl/vl change)
598 # but they *can* be done as while-loops as long as every SVSTATE
599 # "thing" is re-read every single time a yield gives indices
600 while True: # outer vl loop
601 while True: # inner subvl loop
604 srcmask
= self
.srcmask
605 srcstep
= self
.svstate
.srcstep
606 pred_src_zero
= ((1 << srcstep
) & srcmask
) != 0
607 if self
.pred_sz
or pred_src_zero
:
608 self
.pred_src_zero
= not pred_src_zero
609 log(" advance src", srcstep
, vl
,
610 self
.svstate
.ssubstep
, subvl
)
611 # yield actual substep/srcstep
612 yield (self
.svstate
.ssubstep
, srcstep
)
613 if self
.svstate
.ssubstep
== subvl
: # end-point
614 self
.svstate
.ssubstep
= SelectableInt(0, 2) # reset
615 break # exit inner loop
616 self
.svstate
.ssubstep
+= SelectableInt(1, 2)
618 if srcstep
== vl
-1: # end-point
619 self
.svstate
.srcstep
= SelectableInt(0, 7) # reset
622 self
.svstate
.srcstep
+= SelectableInt(1, 7) # advance srcstep
624 def dst_iterator(self
):
625 """dest-stepping iterator
627 unpack
= self
.svstate
.unpack
631 # pack advances subvl in *outer* loop
632 while True: # outer subvl loop
633 while True: # inner vl loop
636 dstmask
= self
.dstmask
637 dststep
= self
.svstate
.dststep
638 pred_dst_zero
= ((1 << dststep
) & dstmask
) != 0
639 if self
.pred_dz
or pred_dst_zero
:
640 self
.pred_dst_zero
= not pred_dst_zero
641 log(" advance dst", dststep
, vl
,
642 self
.svstate
.dsubstep
, subvl
)
643 # yield actual substep/dststep
644 yield (self
.svstate
.dsubstep
, dststep
)
645 # the way yield works these could have been modified.
647 dststep
= self
.svstate
.dststep
648 log(" advance dst check", dststep
, vl
,
649 self
.svstate
.ssubstep
, subvl
)
650 if dststep
== vl
-1: # end-point
651 self
.svstate
.dststep
= SelectableInt(0, 7) # reset
652 if self
.svstate
.dsubstep
== subvl
: # end-point
653 log(" advance unpack stop")
656 self
.svstate
.dststep
+= SelectableInt(1, 7) # advance ds
658 if self
.svstate
.dsubstep
== subvl
: # end-point
659 self
.svstate
.dsubstep
= SelectableInt(0, 2) # reset
660 log(" advance unpack stop")
662 self
.svstate
.dsubstep
+= SelectableInt(1, 2)
664 # these cannot be done as for-loops because SVSTATE may change
665 # (dststep/substep may be modified, interrupted, subvl/vl change)
666 # but they *can* be done as while-loops as long as every SVSTATE
667 # "thing" is re-read every single time a yield gives indices
668 while True: # outer vl loop
669 while True: # inner subvl loop
671 dstmask
= self
.dstmask
672 dststep
= self
.svstate
.dststep
673 pred_dst_zero
= ((1 << dststep
) & dstmask
) != 0
674 if self
.pred_dz
or pred_dst_zero
:
675 self
.pred_dst_zero
= not pred_dst_zero
676 log(" advance dst", dststep
, self
.svstate
.vl
,
677 self
.svstate
.dsubstep
, subvl
)
678 # yield actual substep/dststep
679 yield (self
.svstate
.dsubstep
, dststep
)
680 if self
.svstate
.dsubstep
== subvl
: # end-point
681 self
.svstate
.dsubstep
= SelectableInt(0, 2) # reset
683 self
.svstate
.dsubstep
+= SelectableInt(1, 2)
686 if dststep
== vl
-1: # end-point
687 self
.svstate
.dststep
= SelectableInt(0, 7) # reset
689 self
.svstate
.dststep
+= SelectableInt(1, 7) # advance dststep
691 def src_iterate(self
):
692 """source-stepping iterator
696 pack
= self
.svstate
.pack
697 unpack
= self
.svstate
.unpack
698 ssubstep
= self
.svstate
.ssubstep
699 end_ssub
= ssubstep
== subvl
700 end_src
= self
.svstate
.srcstep
== vl
-1
701 log(" pack/unpack/subvl", pack
, unpack
, subvl
,
705 srcstep
= self
.svstate
.srcstep
706 srcmask
= self
.srcmask
708 # pack advances subvl in *outer* loop
710 assert srcstep
<= vl
-1
711 end_src
= srcstep
== vl
-1
716 self
.svstate
.ssubstep
+= SelectableInt(1, 2)
720 srcstep
+= 1 # advance srcstep
721 if not self
.srcstep_skip
:
723 if ((1 << srcstep
) & srcmask
) != 0:
726 log(" sskip", bin(srcmask
), bin(1 << srcstep
))
728 # advance subvl in *inner* loop
731 assert srcstep
<= vl
-1
732 end_src
= srcstep
== vl
-1
733 if end_src
: # end-point
739 if not self
.srcstep_skip
:
741 if ((1 << srcstep
) & srcmask
) != 0:
744 log(" sskip", bin(srcmask
), bin(1 << srcstep
))
745 self
.svstate
.ssubstep
= SelectableInt(0, 2) # reset
748 self
.svstate
.ssubstep
+= SelectableInt(1, 2)
750 self
.svstate
.srcstep
= SelectableInt(srcstep
, 7)
751 log(" advance src", self
.svstate
.srcstep
, self
.svstate
.ssubstep
,
754 def dst_iterate(self
):
755 """dest step iterator
759 pack
= self
.svstate
.pack
760 unpack
= self
.svstate
.unpack
761 dsubstep
= self
.svstate
.dsubstep
762 end_dsub
= dsubstep
== subvl
763 dststep
= self
.svstate
.dststep
764 end_dst
= dststep
== vl
-1
765 dstmask
= self
.dstmask
766 log(" pack/unpack/subvl", pack
, unpack
, subvl
,
771 # unpack advances subvl in *outer* loop
773 assert dststep
<= vl
-1
774 end_dst
= dststep
== vl
-1
779 self
.svstate
.dsubstep
+= SelectableInt(1, 2)
783 dststep
+= 1 # advance dststep
784 if not self
.dststep_skip
:
786 if ((1 << dststep
) & dstmask
) != 0:
789 log(" dskip", bin(dstmask
), bin(1 << dststep
))
791 # advance subvl in *inner* loop
794 assert dststep
<= vl
-1
795 end_dst
= dststep
== vl
-1
796 if end_dst
: # end-point
802 if not self
.dststep_skip
:
804 if ((1 << dststep
) & dstmask
) != 0:
807 log(" dskip", bin(dstmask
), bin(1 << dststep
))
808 self
.svstate
.dsubstep
= SelectableInt(0, 2) # reset
811 self
.svstate
.dsubstep
+= SelectableInt(1, 2)
813 self
.svstate
.dststep
= SelectableInt(dststep
, 7)
814 log(" advance dst", self
.svstate
.dststep
, self
.svstate
.dsubstep
,
817 def at_loopend(self
):
818 """tells if this is the last possible element. uses the cached values
819 for src/dst-step and sub-steps
823 srcstep
, dststep
= self
.new_srcstep
, self
.new_dststep
824 ssubstep
, dsubstep
= self
.new_ssubstep
, self
.new_dsubstep
825 end_ssub
= ssubstep
== subvl
826 end_dsub
= dsubstep
== subvl
827 if srcstep
== vl
-1 and end_ssub
:
829 if dststep
== vl
-1 and end_dsub
:
833 def advance_svstate_steps(self
):
834 """ advance sub/steps. note that Pack/Unpack *INVERTS* the order.
835 TODO when Pack/Unpack is set, substep becomes the *outer* loop
837 self
.subvl
= yield self
.dec2
.rm_dec
.rm_in
.subvl
838 if self
.loopend
: # huhn??
843 def read_src_mask(self
):
844 """read/update pred_sz and src mask
846 # get SVSTATE VL (oh and print out some debug stuff)
848 srcstep
= self
.svstate
.srcstep
849 ssubstep
= self
.svstate
.ssubstep
851 # get predicate mask (all 64 bits)
852 srcmask
= 0xffff_ffff_ffff_ffff
854 pmode
= yield self
.dec2
.rm_dec
.predmode
855 sv_ptype
= yield self
.dec2
.dec
.op
.SV_Ptype
856 srcpred
= yield self
.dec2
.rm_dec
.srcpred
857 dstpred
= yield self
.dec2
.rm_dec
.dstpred
858 pred_sz
= yield self
.dec2
.rm_dec
.pred_sz
859 if pmode
== SVP64PredMode
.INT
.value
:
860 srcmask
= dstmask
= get_predint(self
.gpr
, dstpred
)
861 if sv_ptype
== SVPtype
.P2
.value
:
862 srcmask
= get_predint(self
.gpr
, srcpred
)
863 elif pmode
== SVP64PredMode
.CR
.value
:
864 srcmask
= dstmask
= get_predcr(self
.crl
, dstpred
, vl
)
865 if sv_ptype
== SVPtype
.P2
.value
:
866 srcmask
= get_predcr(self
.crl
, srcpred
, vl
)
867 # work out if the ssubsteps are completed
868 ssubstart
= ssubstep
== 0
870 log(" ptype", sv_ptype
)
871 log(" srcpred", bin(srcpred
))
872 log(" srcmask", bin(srcmask
))
873 log(" pred_sz", bin(pred_sz
))
874 log(" ssubstart", ssubstart
)
876 # store all that above
877 self
.srcstep_skip
= False
878 self
.srcmask
= srcmask
879 self
.pred_sz
= pred_sz
880 self
.new_ssubstep
= ssubstep
881 log(" new ssubstep", ssubstep
)
882 # until the predicate mask has a "1" bit... or we run out of VL
883 # let srcstep==VL be the indicator to move to next instruction
885 self
.srcstep_skip
= True
887 def read_dst_mask(self
):
888 """same as read_src_mask - check and record everything needed
890 # get SVSTATE VL (oh and print out some debug stuff)
891 # yield Delay(1e-10) # make changes visible
893 dststep
= self
.svstate
.dststep
894 dsubstep
= self
.svstate
.dsubstep
896 # get predicate mask (all 64 bits)
897 dstmask
= 0xffff_ffff_ffff_ffff
899 pmode
= yield self
.dec2
.rm_dec
.predmode
900 reverse_gear
= yield self
.dec2
.rm_dec
.reverse_gear
901 sv_ptype
= yield self
.dec2
.dec
.op
.SV_Ptype
902 dstpred
= yield self
.dec2
.rm_dec
.dstpred
903 pred_dz
= yield self
.dec2
.rm_dec
.pred_dz
904 if pmode
== SVP64PredMode
.INT
.value
:
905 dstmask
= get_predint(self
.gpr
, dstpred
)
906 elif pmode
== SVP64PredMode
.CR
.value
:
907 dstmask
= get_predcr(self
.crl
, dstpred
, vl
)
908 # work out if the ssubsteps are completed
909 dsubstart
= dsubstep
== 0
911 log(" ptype", sv_ptype
)
912 log(" dstpred", bin(dstpred
))
913 log(" dstmask", bin(dstmask
))
914 log(" pred_dz", bin(pred_dz
))
915 log(" dsubstart", dsubstart
)
917 self
.dststep_skip
= False
918 self
.dstmask
= dstmask
919 self
.pred_dz
= pred_dz
920 self
.new_dsubstep
= dsubstep
921 log(" new dsubstep", dsubstep
)
923 self
.dststep_skip
= True
925 def svstate_pre_inc(self
):
926 """check if srcstep/dststep need to skip over masked-out predicate bits
927 note that this is not supposed to do anything to substep,
928 it is purely for skipping masked-out bits
931 self
.subvl
= yield self
.dec2
.rm_dec
.rm_in
.subvl
932 yield from self
.read_src_mask()
933 yield from self
.read_dst_mask()
940 srcstep
= self
.svstate
.srcstep
941 srcmask
= self
.srcmask
942 pred_src_zero
= self
.pred_sz
944 # srcstep-skipping opportunity identified
945 if self
.srcstep_skip
:
946 # cannot do this with sv.bc - XXX TODO
949 while (((1 << srcstep
) & srcmask
) == 0) and (srcstep
!= vl
):
950 log(" sskip", bin(1 << srcstep
))
953 # now work out if the relevant mask bits require zeroing
955 pred_src_zero
= ((1 << srcstep
) & srcmask
) == 0
957 # store new srcstep / dststep
958 self
.new_srcstep
= srcstep
959 self
.pred_src_zero
= pred_src_zero
960 log(" new srcstep", srcstep
)
963 # dststep-skipping opportunity identified
964 dststep
= self
.svstate
.dststep
965 dstmask
= self
.dstmask
966 pred_dst_zero
= self
.pred_dz
968 if self
.dststep_skip
:
969 # cannot do this with sv.bc - XXX TODO
972 while (((1 << dststep
) & dstmask
) == 0) and (dststep
!= vl
):
973 log(" dskip", bin(1 << dststep
))
976 # now work out if the relevant mask bits require zeroing
978 pred_dst_zero
= ((1 << dststep
) & dstmask
) == 0
980 # store new srcstep / dststep
981 self
.new_dststep
= dststep
982 self
.pred_dst_zero
= pred_dst_zero
983 log(" new dststep", dststep
)
986 class ISACaller(ISACallerHelper
, ISAFPHelpers
, StepLoop
):
987 # decoder2 - an instance of power_decoder2
988 # regfile - a list of initial values for the registers
989 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
990 # respect_pc - tracks the program counter. requires initial_insns
991 def __init__(self
, decoder2
, regfile
, initial_sprs
=None, initial_cr
=0,
992 initial_mem
=None, initial_msr
=0,
1003 self
.bigendian
= bigendian
1005 self
.is_svp64_mode
= False
1006 self
.respect_pc
= respect_pc
1007 if initial_sprs
is None:
1009 if initial_mem
is None:
1011 if fpregfile
is None:
1012 fpregfile
= [0] * 32
1013 if initial_insns
is None:
1015 assert self
.respect_pc
== False, "instructions required to honor pc"
1017 log("ISACaller insns", respect_pc
, initial_insns
, disassembly
)
1018 log("ISACaller initial_msr", initial_msr
)
1020 # "fake program counter" mode (for unit testing)
1024 if isinstance(initial_mem
, tuple):
1025 self
.fake_pc
= initial_mem
[0]
1026 disasm_start
= self
.fake_pc
1028 disasm_start
= initial_pc
1030 # disassembly: we need this for now (not given from the decoder)
1031 self
.disassembly
= {}
1033 for i
, code
in enumerate(disassembly
):
1034 self
.disassembly
[i
*4 + disasm_start
] = code
1036 # set up registers, instruction memory, data memory, PC, SPRs, MSR, CR
1037 self
.svp64rm
= SVP64RM()
1038 if initial_svstate
is None:
1040 if isinstance(initial_svstate
, int):
1041 initial_svstate
= SVP64State(initial_svstate
)
1042 # SVSTATE, MSR and PC
1043 StepLoop
.__init
__(self
, initial_svstate
)
1044 self
.msr
= SelectableInt(initial_msr
, 64) # underlying reg
1046 # GPR FPR SPR registers
1047 initial_sprs
= deepcopy(initial_sprs
) # so as not to get modified
1048 self
.gpr
= GPR(decoder2
, self
, self
.svstate
, regfile
)
1049 self
.fpr
= GPR(decoder2
, self
, self
.svstate
, fpregfile
)
1050 self
.spr
= SPR(decoder2
, initial_sprs
) # initialise SPRs before MMU
1052 # set up 4 dummy SVSHAPEs if they aren't already set up
1054 sname
= 'SVSHAPE%d' % i
1055 val
= self
.spr
.get(sname
, 0)
1056 # make sure it's an SVSHAPE
1057 self
.spr
[sname
] = SVSHAPE(val
, self
.gpr
)
1058 self
.last_op_svshape
= False
1061 self
.mem
= Mem(row_bytes
=8, initial_mem
=initial_mem
)
1062 self
.mem
.log_fancy(kind
=LogKind
.InstrInOuts
)
1063 self
.imem
= Mem(row_bytes
=4, initial_mem
=initial_insns
)
1064 # MMU mode, redirect underlying Mem through RADIX
1066 self
.mem
= RADIX(self
.mem
, self
)
1068 self
.imem
= RADIX(self
.imem
, self
)
1070 # TODO, needed here:
1071 # FPR (same as GPR except for FP nums)
1072 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
1073 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
1074 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
1075 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
1077 # 2.3.2 LR (actually SPR #8) -- Done
1078 # 2.3.3 CTR (actually SPR #9) -- Done
1079 # 2.3.4 TAR (actually SPR #815)
1080 # 3.2.2 p45 XER (actually SPR #1) -- Done
1081 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
1083 # create CR then allow portions of it to be "selectable" (below)
1084 self
.cr_fields
= CRFields(initial_cr
)
1085 self
.cr
= self
.cr_fields
.cr
1087 # "undefined", just set to variable-bit-width int (use exts "max")
1088 # self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
1091 self
.namespace
.update(self
.spr
)
1092 self
.namespace
.update({'GPR': self
.gpr
,
1096 'memassign': self
.memassign
,
1099 'SVSTATE': self
.svstate
,
1100 'SVSHAPE0': self
.spr
['SVSHAPE0'],
1101 'SVSHAPE1': self
.spr
['SVSHAPE1'],
1102 'SVSHAPE2': self
.spr
['SVSHAPE2'],
1103 'SVSHAPE3': self
.spr
['SVSHAPE3'],
1106 'undefined': undefined
,
1107 'mode_is_64bit': True,
1108 'SO': XER_bits
['SO'],
1109 'XLEN': 64 # elwidth overrides, later
1112 # update pc to requested start point
1113 self
.set_pc(initial_pc
)
1115 # field-selectable versions of Condition Register
1116 self
.crl
= self
.cr_fields
.crl
1118 self
.namespace
["CR%d" % i
] = self
.crl
[i
]
1120 self
.decoder
= decoder2
.dec
1121 self
.dec2
= decoder2
1123 super().__init
__(XLEN
=self
.namespace
["XLEN"])
1127 return self
.namespace
["XLEN"]
1129 def call_trap(self
, trap_addr
, trap_bit
):
1130 """calls TRAP and sets up NIA to the new execution location.
1131 next instruction will begin at trap_addr.
1133 self
.TRAP(trap_addr
, trap_bit
)
1134 self
.namespace
['NIA'] = self
.trap_nia
1135 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
1137 def TRAP(self
, trap_addr
=0x700, trap_bit
=PIb
.TRAP
):
1138 """TRAP> saves PC, MSR (and TODO SVSTATE), and updates MSR
1140 TRAP function is callable from inside the pseudocode itself,
1141 hence the default arguments. when calling from inside ISACaller
1142 it is best to use call_trap()
1144 # https://bugs.libre-soc.org/show_bug.cgi?id=859
1145 kaivb
= self
.spr
['KAIVB'].value
1146 msr
= self
.namespace
['MSR'].value
1147 log("TRAP:", hex(trap_addr
), hex(msr
), "kaivb", hex(kaivb
))
1148 # store CIA(+4?) in SRR0, set NIA to 0x700
1149 # store MSR in SRR1, set MSR to um errr something, have to check spec
1150 # store SVSTATE (if enabled) in SVSRR0
1151 self
.spr
['SRR0'].value
= self
.pc
.CIA
.value
1152 self
.spr
['SRR1'].value
= msr
1153 if self
.is_svp64_mode
:
1154 self
.spr
['SVSRR0'] = self
.namespace
['SVSTATE'].value
1155 self
.trap_nia
= SelectableInt(trap_addr |
(kaivb
& ~
0x1fff), 64)
1156 self
.spr
['SRR1'][trap_bit
] = 1 # change *copy* of MSR in SRR1
1158 # set exception bits. TODO: this should, based on the address
1159 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
1160 # bits appropriately. however it turns out that *for now* in all
1161 # cases (all trap_addrs) the exact same thing is needed.
1162 self
.msr
[MSRb
.IR
] = 0
1163 self
.msr
[MSRb
.DR
] = 0
1164 self
.msr
[MSRb
.FE0
] = 0
1165 self
.msr
[MSRb
.FE1
] = 0
1166 self
.msr
[MSRb
.EE
] = 0
1167 self
.msr
[MSRb
.RI
] = 0
1168 self
.msr
[MSRb
.SF
] = 1
1169 self
.msr
[MSRb
.TM
] = 0
1170 self
.msr
[MSRb
.VEC
] = 0
1171 self
.msr
[MSRb
.VSX
] = 0
1172 self
.msr
[MSRb
.PR
] = 0
1173 self
.msr
[MSRb
.FP
] = 0
1174 self
.msr
[MSRb
.PMM
] = 0
1175 self
.msr
[MSRb
.TEs
] = 0
1176 self
.msr
[MSRb
.TEe
] = 0
1177 self
.msr
[MSRb
.UND
] = 0
1178 self
.msr
[MSRb
.LE
] = 1
1180 def memassign(self
, ea
, sz
, val
):
1181 self
.mem
.memassign(ea
, sz
, val
)
1183 def prep_namespace(self
, insn_name
, formname
, op_fields
):
1184 # TODO: get field names from form in decoder*1* (not decoder2)
1185 # decoder2 is hand-created, and decoder1.sigform is auto-generated
1187 # then "yield" fields only from op_fields rather than hard-coded
1189 fields
= self
.decoder
.sigforms
[formname
]
1190 log("prep_namespace", formname
, op_fields
, insn_name
)
1191 for name
in op_fields
:
1192 # CR immediates. deal with separately. needs modifying
1194 if self
.is_svp64_mode
and name
in ['BI']: # TODO, more CRs
1195 # BI is a 5-bit, must reconstruct the value
1196 regnum
, is_vec
= yield from get_pdecode_cr_in(self
.dec2
, name
)
1197 sig
= getattr(fields
, name
)
1199 # low 2 LSBs (CR field selector) remain same, CR num extended
1200 assert regnum
<= 7, "sigh, TODO, 128 CR fields"
1201 val
= (val
& 0b11) |
(regnum
<< 2)
1203 sig
= getattr(fields
, name
)
1205 # these are all opcode fields involved in index-selection of CR,
1206 # and need to do "standard" arithmetic. CR[BA+32] for example
1207 # would, if using SelectableInt, only be 5-bit.
1208 if name
in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
1209 self
.namespace
[name
] = val
1211 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
1213 self
.namespace
['XER'] = self
.spr
['XER']
1214 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
1215 self
.namespace
['CA32'] = self
.spr
['XER'][XER_bits
['CA32']].value
1217 # add some SVSTATE convenience variables
1218 vl
= self
.svstate
.vl
1219 srcstep
= self
.svstate
.srcstep
1220 self
.namespace
['VL'] = vl
1221 self
.namespace
['srcstep'] = srcstep
1223 # sv.bc* need some extra fields
1224 if self
.is_svp64_mode
and insn_name
.startswith("sv.bc"):
1225 # blegh grab bits manually
1226 mode
= yield self
.dec2
.rm_dec
.rm_in
.mode
1227 mode
= SelectableInt(mode
, 5) # convert to SelectableInt before test
1228 bc_vlset
= mode
[SVP64MODEb
.BC_VLSET
] != 0
1229 bc_vli
= mode
[SVP64MODEb
.BC_VLI
] != 0
1230 bc_snz
= mode
[SVP64MODEb
.BC_SNZ
] != 0
1231 bc_vsb
= yield self
.dec2
.rm_dec
.bc_vsb
1232 bc_lru
= yield self
.dec2
.rm_dec
.bc_lru
1233 bc_gate
= yield self
.dec2
.rm_dec
.bc_gate
1234 sz
= yield self
.dec2
.rm_dec
.pred_sz
1235 self
.namespace
['mode'] = SelectableInt(mode
, 5)
1236 self
.namespace
['ALL'] = SelectableInt(bc_gate
, 1)
1237 self
.namespace
['VSb'] = SelectableInt(bc_vsb
, 1)
1238 self
.namespace
['LRu'] = SelectableInt(bc_lru
, 1)
1239 self
.namespace
['VLSET'] = SelectableInt(bc_vlset
, 1)
1240 self
.namespace
['VLI'] = SelectableInt(bc_vli
, 1)
1241 self
.namespace
['sz'] = SelectableInt(sz
, 1)
1242 self
.namespace
['SNZ'] = SelectableInt(bc_snz
, 1)
1244 def handle_carry_(self
, inputs
, output
, ca
, ca32
):
1245 inv_a
= yield self
.dec2
.e
.do
.invert_in
1247 inputs
[0] = ~inputs
[0]
1249 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
1251 imm
= yield self
.dec2
.e
.do
.imm_data
.data
1252 inputs
.append(SelectableInt(imm
, 64))
1255 log("gt input", x
, output
)
1256 gt
= (gtu(x
, output
))
1259 cy
= 1 if any(gts
) else 0
1261 if ca
is None: # already written
1262 self
.spr
['XER'][XER_bits
['CA']] = cy
1265 # ARGH... different for OP_ADD... *sigh*...
1266 op
= yield self
.dec2
.e
.do
.insn_type
1267 if op
== MicrOp
.OP_ADD
.value
:
1268 res32
= (output
.value
& (1 << 32)) != 0
1269 a32
= (inputs
[0].value
& (1 << 32)) != 0
1270 if len(inputs
) >= 2:
1271 b32
= (inputs
[1].value
& (1 << 32)) != 0
1274 cy32
= res32 ^ a32 ^ b32
1275 log("CA32 ADD", cy32
)
1279 log("input", x
, output
)
1280 log(" x[32:64]", x
, x
[32:64])
1281 log(" o[32:64]", output
, output
[32:64])
1282 gt
= (gtu(x
[32:64], output
[32:64])) == SelectableInt(1, 1)
1284 cy32
= 1 if any(gts
) else 0
1285 log("CA32", cy32
, gts
)
1286 if ca32
is None: # already written
1287 self
.spr
['XER'][XER_bits
['CA32']] = cy32
1289 def handle_overflow(self
, inputs
, output
, div_overflow
):
1290 if hasattr(self
.dec2
.e
.do
, "invert_in"):
1291 inv_a
= yield self
.dec2
.e
.do
.invert_in
1293 inputs
[0] = ~inputs
[0]
1295 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
1297 imm
= yield self
.dec2
.e
.do
.imm_data
.data
1298 inputs
.append(SelectableInt(imm
, 64))
1299 log("handle_overflow", inputs
, output
, div_overflow
)
1300 if len(inputs
) < 2 and div_overflow
is None:
1303 # div overflow is different: it's returned by the pseudo-code
1304 # because it's more complex than can be done by analysing the output
1305 if div_overflow
is not None:
1306 ov
, ov32
= div_overflow
, div_overflow
1307 # arithmetic overflow can be done by analysing the input and output
1308 elif len(inputs
) >= 2:
1310 input_sgn
= [exts(x
.value
, x
.bits
) < 0 for x
in inputs
]
1311 output_sgn
= exts(output
.value
, output
.bits
) < 0
1312 ov
= 1 if input_sgn
[0] == input_sgn
[1] and \
1313 output_sgn
!= input_sgn
[0] else 0
1316 input32_sgn
= [exts(x
.value
, 32) < 0 for x
in inputs
]
1317 output32_sgn
= exts(output
.value
, 32) < 0
1318 ov32
= 1 if input32_sgn
[0] == input32_sgn
[1] and \
1319 output32_sgn
!= input32_sgn
[0] else 0
1321 # now update XER OV/OV32/SO
1322 so
= self
.spr
['XER'][XER_bits
['SO']]
1323 new_so
= so | ov
# sticky overflow ORs in old with new
1324 self
.spr
['XER'][XER_bits
['OV']] = ov
1325 self
.spr
['XER'][XER_bits
['OV32']] = ov32
1326 self
.spr
['XER'][XER_bits
['SO']] = new_so
1327 log(" set overflow", ov
, ov32
, so
, new_so
)
1329 def handle_comparison(self
, out
, cr_idx
=0, overflow
=None, no_so
=False):
1330 assert isinstance(out
, SelectableInt
), \
1331 "out zero not a SelectableInt %s" % repr(outputs
)
1332 log("handle_comparison", out
.bits
, hex(out
.value
))
1333 # TODO - XXX *processor* in 32-bit mode
1334 # https://bugs.libre-soc.org/show_bug.cgi?id=424
1336 # o32 = exts(out.value, 32)
1337 # print ("handle_comparison exts 32 bit", hex(o32))
1338 out
= exts(out
.value
, out
.bits
)
1339 log("handle_comparison exts", hex(out
))
1340 # create the three main CR flags, EQ GT LT
1341 zero
= SelectableInt(out
== 0, 1)
1342 positive
= SelectableInt(out
> 0, 1)
1343 negative
= SelectableInt(out
< 0, 1)
1344 # get (or not) XER.SO. for setvl this is important *not* to read SO
1346 SO
= SelectableInt(1, 0)
1348 SO
= self
.spr
['XER'][XER_bits
['SO']]
1349 log("handle_comparison SO overflow", SO
, overflow
)
1350 # alternative overflow checking (setvl mainly at the moment)
1351 if overflow
is not None and overflow
== 1:
1352 SO
= SelectableInt(1, 1)
1353 # create the four CR field values and set the required CR field
1354 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
1355 log("handle_comparison cr_field", self
.cr
, cr_idx
, cr_field
)
1356 self
.crl
[cr_idx
].eq(cr_field
)
1358 def set_pc(self
, pc_val
):
1359 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
1360 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
1362 def get_next_insn(self
):
1363 """check instruction
1366 pc
= self
.pc
.CIA
.value
1369 ins
= self
.imem
.ld(pc
, 4, False, True, instr_fetch
=True)
1371 raise KeyError("no instruction at 0x%x" % pc
)
1374 def setup_one(self
):
1375 """set up one instruction
1377 pc
, insn
= self
.get_next_insn()
1378 yield from self
.setup_next_insn(pc
, insn
)
1380 def setup_next_insn(self
, pc
, ins
):
1381 """set up next instruction
1384 log("setup: 0x%x 0x%x %s" % (pc
, ins
& 0xffffffff, bin(ins
)))
1385 log("CIA NIA", self
.respect_pc
, self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
1387 yield self
.dec2
.sv_rm
.eq(0)
1388 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff)
1389 yield self
.dec2
.dec
.bigendian
.eq(self
.bigendian
)
1390 yield self
.dec2
.state
.msr
.eq(self
.msr
.value
)
1391 yield self
.dec2
.state
.pc
.eq(pc
)
1392 if self
.svstate
is not None:
1393 yield self
.dec2
.state
.svstate
.eq(self
.svstate
.value
)
1395 # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
1397 opcode
= yield self
.dec2
.dec
.opcode_in
1398 opcode
= SelectableInt(value
=opcode
, bits
=32)
1399 pfx
= SVP64Instruction
.Prefix(opcode
)
1400 log("prefix test: opcode:", pfx
.po
, bin(pfx
.po
), pfx
.id)
1401 self
.is_svp64_mode
= bool((pfx
.po
== 0b000001) and (pfx
.id == 0b11))
1402 self
.pc
.update_nia(self
.is_svp64_mode
)
1404 yield self
.dec2
.is_svp64_mode
.eq(self
.is_svp64_mode
)
1405 self
.namespace
['NIA'] = self
.pc
.NIA
1406 self
.namespace
['SVSTATE'] = self
.svstate
1407 if not self
.is_svp64_mode
:
1410 # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
1411 log("svp64.rm", bin(pfx
.rm
))
1412 log(" svstate.vl", self
.svstate
.vl
)
1413 log(" svstate.mvl", self
.svstate
.maxvl
)
1414 ins
= self
.imem
.ld(pc
+4, 4, False, True, instr_fetch
=True)
1415 log(" svsetup: 0x%x 0x%x %s" % (pc
+4, ins
& 0xffffffff, bin(ins
)))
1416 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff) # v3.0B suffix
1417 yield self
.dec2
.sv_rm
.eq(int(pfx
.rm
)) # svp64 prefix
1420 def execute_one(self
):
1421 """execute one instruction
1423 # get the disassembly code for this instruction
1424 if not self
.disassembly
:
1425 code
= yield from self
.get_assembly_name()
1428 if self
.is_svp64_mode
:
1429 offs
, dbg
= 4, "svp64 "
1430 code
= self
.disassembly
[self
._pc
+offs
]
1431 log(" %s sim-execute" % dbg
, hex(self
._pc
), code
)
1432 opname
= code
.split(' ')[0]
1434 yield from self
.call(opname
) # execute the instruction
1435 except MemException
as e
: # check for memory errors
1436 if e
.args
[0] == 'unaligned': # alignment error
1437 # run a Trap but set DAR first
1438 print("memory unaligned exception, DAR", e
.dar
)
1439 self
.spr
['DAR'] = SelectableInt(e
.dar
, 64)
1440 self
.call_trap(0x600, PIb
.PRIV
) # 0x600, privileged
1442 elif e
.args
[0] == 'invalid': # invalid
1443 # run a Trap but set DAR first
1444 log("RADIX MMU memory invalid error, mode %s" % e
.mode
)
1445 if e
.mode
== 'EXECUTE':
1446 # XXX TODO: must set a few bits in SRR1,
1447 # see microwatt loadstore1.vhdl
1448 # if m_in.segerr = '0' then
1449 # v.srr1(47 - 33) := m_in.invalid;
1450 # v.srr1(47 - 35) := m_in.perm_error; -- noexec fault
1451 # v.srr1(47 - 44) := m_in.badtree;
1452 # v.srr1(47 - 45) := m_in.rc_error;
1453 # v.intr_vec := 16#400#;
1455 # v.intr_vec := 16#480#;
1456 self
.call_trap(0x400, PIb
.PRIV
) # 0x400, privileged
1458 self
.call_trap(0x300, PIb
.PRIV
) # 0x300, privileged
1460 # not supported yet:
1461 raise e
# ... re-raise
1463 # don't use this except in special circumstances
1464 if not self
.respect_pc
:
1467 log("execute one, CIA NIA", hex(self
.pc
.CIA
.value
),
1468 hex(self
.pc
.NIA
.value
))
1470 def get_assembly_name(self
):
1471 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
1472 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
1473 dec_insn
= yield self
.dec2
.e
.do
.insn
1474 insn_1_11
= yield self
.dec2
.e
.do
.insn
[1:11]
1475 asmcode
= yield self
.dec2
.dec
.op
.asmcode
1476 int_op
= yield self
.dec2
.dec
.op
.internal_op
1477 log("get assembly name asmcode", asmcode
, int_op
,
1478 hex(dec_insn
), bin(insn_1_11
))
1479 asmop
= insns
.get(asmcode
, None)
1481 # sigh reconstruct the assembly instruction name
1482 if hasattr(self
.dec2
.e
.do
, "oe"):
1483 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
1484 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
1488 if hasattr(self
.dec2
.e
.do
, "rc"):
1489 rc_en
= yield self
.dec2
.e
.do
.rc
.rc
1490 rc_ok
= yield self
.dec2
.e
.do
.rc
.ok
1494 # annoying: ignore rc_ok if RC1 is set (for creating *assembly name*)
1495 RC1
= yield self
.dec2
.rm_dec
.RC1
1499 # grrrr have to special-case MUL op (see DecodeOE)
1500 log("ov %d en %d rc %d en %d op %d" %
1501 (ov_ok
, ov_en
, rc_ok
, rc_en
, int_op
))
1502 if int_op
in [MicrOp
.OP_MUL_H64
.value
, MicrOp
.OP_MUL_H32
.value
]:
1507 if not asmop
.endswith("."): # don't add "." to "andis."
1510 if hasattr(self
.dec2
.e
.do
, "lk"):
1511 lk
= yield self
.dec2
.e
.do
.lk
1514 log("int_op", int_op
)
1515 if int_op
in [MicrOp
.OP_B
.value
, MicrOp
.OP_BC
.value
]:
1516 AA
= yield self
.dec2
.dec
.fields
.FormI
.AA
[0:-1]
1520 spr_msb
= yield from self
.get_spr_msb()
1521 if int_op
== MicrOp
.OP_MFCR
.value
:
1526 # XXX TODO: for whatever weird reason this doesn't work
1527 # https://bugs.libre-soc.org/show_bug.cgi?id=390
1528 if int_op
== MicrOp
.OP_MTCRF
.value
:
1535 def reset_remaps(self
):
1536 self
.remap_loopends
= [0] * 4
1537 self
.remap_idxs
= [0, 1, 2, 3]
1539 def get_remap_indices(self
):
1540 """WARNING, this function stores remap_idxs and remap_loopends
1541 in the class for later use. this to avoid problems with yield
1543 # go through all iterators in lock-step, advance to next remap_idx
1544 srcstep
, dststep
, ssubstep
, dsubstep
= self
.get_src_dststeps()
1545 # get four SVSHAPEs. here we are hard-coding
1547 SVSHAPE0
= self
.spr
['SVSHAPE0']
1548 SVSHAPE1
= self
.spr
['SVSHAPE1']
1549 SVSHAPE2
= self
.spr
['SVSHAPE2']
1550 SVSHAPE3
= self
.spr
['SVSHAPE3']
1551 # set up the iterators
1552 remaps
= [(SVSHAPE0
, SVSHAPE0
.get_iterator()),
1553 (SVSHAPE1
, SVSHAPE1
.get_iterator()),
1554 (SVSHAPE2
, SVSHAPE2
.get_iterator()),
1555 (SVSHAPE3
, SVSHAPE3
.get_iterator()),
1559 for i
, (shape
, remap
) in enumerate(remaps
):
1560 # zero is "disabled"
1561 if shape
.value
== 0x0:
1562 self
.remap_idxs
[i
] = 0
1563 # pick src or dststep depending on reg num (0-2=in, 3-4=out)
1564 step
= dststep
if (i
in [3, 4]) else srcstep
1565 # this is terrible. O(N^2) looking for the match. but hey.
1566 for idx
, (remap_idx
, loopends
) in enumerate(remap
):
1569 self
.remap_idxs
[i
] = remap_idx
1570 self
.remap_loopends
[i
] = loopends
1571 dbg
.append((i
, step
, remap_idx
, loopends
))
1572 for (i
, step
, remap_idx
, loopends
) in dbg
:
1573 log("SVSHAPE %d idx, end" % i
, step
, remap_idx
, bin(loopends
))
1576 def get_spr_msb(self
):
1577 dec_insn
= yield self
.dec2
.e
.do
.insn
1578 return dec_insn
& (1 << 20) != 0 # sigh - XFF.spr[-1]?
1580 def call(self
, name
):
1581 """call(opcode) - the primary execution point for instructions
1583 self
.last_st_addr
= None # reset the last known store address
1584 self
.last_ld_addr
= None # etc.
1586 ins_name
= name
.strip() # remove spaces if not already done so
1588 log("halted - not executing", ins_name
)
1591 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
1592 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
1593 asmop
= yield from self
.get_assembly_name()
1594 log("call", ins_name
, asmop
)
1596 # sv.setvl is *not* a loop-function. sigh
1597 log("is_svp64_mode", self
.is_svp64_mode
, asmop
)
1600 int_op
= yield self
.dec2
.dec
.op
.internal_op
1601 spr_msb
= yield from self
.get_spr_msb()
1603 instr_is_privileged
= False
1604 if int_op
in [MicrOp
.OP_ATTN
.value
,
1605 MicrOp
.OP_MFMSR
.value
,
1606 MicrOp
.OP_MTMSR
.value
,
1607 MicrOp
.OP_MTMSRD
.value
,
1609 MicrOp
.OP_RFID
.value
]:
1610 instr_is_privileged
= True
1611 if int_op
in [MicrOp
.OP_MFSPR
.value
,
1612 MicrOp
.OP_MTSPR
.value
] and spr_msb
:
1613 instr_is_privileged
= True
1615 log("is priv", instr_is_privileged
, hex(self
.msr
.value
),
1617 # check MSR priv bit and whether op is privileged: if so, throw trap
1618 if instr_is_privileged
and self
.msr
[MSRb
.PR
] == 1:
1619 self
.call_trap(0x700, PIb
.PRIV
)
1622 # check halted condition
1623 if ins_name
== 'attn':
1627 # check illegal instruction
1629 if ins_name
not in ['mtcrf', 'mtocrf']:
1630 illegal
= ins_name
!= asmop
1632 # list of instructions not being supported by binutils (.long)
1633 dotstrp
= asmop
[:-1] if asmop
[-1] == '.' else asmop
1634 if dotstrp
in [*FPTRANS_INSNS
,
1635 'ffmadds', 'fdmadds', 'ffadds',
1636 'mins', 'maxs', 'minu', 'maxu',
1637 'setvl', 'svindex', 'svremap', 'svstep',
1638 'svshape', 'svshape2',
1639 'grev', 'ternlogi', 'bmask', 'cprop',
1640 'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
1641 'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
1647 # branch-conditional redirects to sv.bc
1648 if asmop
.startswith('bc') and self
.is_svp64_mode
:
1649 ins_name
= 'sv.%s' % ins_name
1651 log(" post-processed name", dotstrp
, ins_name
, asmop
)
1653 # illegal instructions call TRAP at 0x700
1655 print("illegal", ins_name
, asmop
)
1656 self
.call_trap(0x700, PIb
.ILLEG
)
1657 print("name %s != %s - calling ILLEGAL trap, PC: %x" %
1658 (ins_name
, asmop
, self
.pc
.CIA
.value
))
1661 # this is for setvl "Vertical" mode: if set true,
1662 # srcstep/dststep is explicitly advanced. mode says which SVSTATE to
1663 # test for Rc=1 end condition. 3 bits of all 3 loops are put into CR0
1664 self
.allow_next_step_inc
= False
1665 self
.svstate_next_mode
= 0
1667 # nop has to be supported, we could let the actual op calculate
1668 # but PowerDecoder has a pattern for nop
1669 if ins_name
== 'nop':
1670 self
.update_pc_next()
1673 # look up instruction in ISA.instrs, prepare namespace
1674 if ins_name
== 'pcdec': # grrrr yes there are others ("stbcx." etc.)
1675 info
= self
.instrs
[ins_name
+"."]
1677 info
= self
.instrs
[ins_name
]
1678 yield from self
.prep_namespace(ins_name
, info
.form
, info
.op_fields
)
1680 # preserve order of register names
1681 input_names
= create_args(list(info
.read_regs
) +
1682 list(info
.uninit_regs
))
1683 log("input names", input_names
)
1685 # get SVP64 entry for the current instruction
1686 sv_rm
= self
.svp64rm
.instrs
.get(ins_name
)
1687 if sv_rm
is not None:
1688 dest_cr
, src_cr
, src_byname
, dest_byname
= decode_extra(sv_rm
)
1690 dest_cr
, src_cr
, src_byname
, dest_byname
= False, False, {}, {}
1691 log("sv rm", sv_rm
, dest_cr
, src_cr
, src_byname
, dest_byname
)
1693 # see if srcstep/dststep need skipping over masked-out predicate bits
1695 if (self
.is_svp64_mode
or ins_name
in ['setvl', 'svremap', 'svstate']):
1696 yield from self
.svstate_pre_inc()
1697 if self
.is_svp64_mode
:
1698 pre
= yield from self
.update_new_svstate_steps()
1700 self
.svp64_reset_loop()
1702 self
.update_pc_next()
1704 srcstep
, dststep
, ssubstep
, dsubstep
= self
.get_src_dststeps()
1705 pred_dst_zero
= self
.pred_dst_zero
1706 pred_src_zero
= self
.pred_src_zero
1707 vl
= self
.svstate
.vl
1708 subvl
= yield self
.dec2
.rm_dec
.rm_in
.subvl
1710 # VL=0 in SVP64 mode means "do nothing: skip instruction"
1711 if self
.is_svp64_mode
and vl
== 0:
1712 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
1713 log("SVP64: VL=0, end of call", self
.namespace
['CIA'],
1714 self
.namespace
['NIA'], kind
=LogKind
.InstrInOuts
)
1717 # for when SVREMAP is active, using pre-arranged schedule.
1718 # note: modifying PowerDecoder2 needs to "settle"
1719 remap_en
= self
.svstate
.SVme
1720 persist
= self
.svstate
.RMpst
1721 active
= (persist
or self
.last_op_svshape
) and remap_en
!= 0
1722 if self
.is_svp64_mode
:
1723 yield self
.dec2
.remap_active
.eq(remap_en
if active
else 0)
1725 if persist
or self
.last_op_svshape
:
1726 remaps
= self
.get_remap_indices()
1727 if self
.is_svp64_mode
and (persist
or self
.last_op_svshape
):
1728 yield from self
.remap_set_steps(remaps
)
1729 # after that, settle down (combinatorial) to let Vector reg numbers
1730 # work themselves out
1732 if self
.is_svp64_mode
:
1733 remap_active
= yield self
.dec2
.remap_active
1735 remap_active
= False
1736 log("remap active", bin(remap_active
))
1738 # main input registers (RT, RA ...)
1740 for name
in input_names
:
1742 regval
= (yield from self
.get_input(name
))
1743 log("regval", regval
)
1744 inputs
.append(regval
)
1746 # arrrrgh, awful hack, to get _RT into namespace
1747 if ins_name
in ['setvl', 'svstep']:
1749 RT
= yield self
.dec2
.dec
.RT
1750 self
.namespace
[regname
] = SelectableInt(RT
, 5)
1752 self
.namespace
["RT"] = SelectableInt(0, 5)
1753 regnum
, is_vec
= yield from get_pdecode_idx_out(self
.dec2
, "RT")
1754 log('hack input reg %s %s' % (name
, str(regnum
)), is_vec
)
1756 # in SVP64 mode for LD/ST work out immediate
1757 # XXX TODO: replace_ds for DS-Form rather than D-Form.
1758 # use info.form to detect
1759 if self
.is_svp64_mode
:
1760 yield from self
.check_replace_d(info
, remap_active
)
1762 # "special" registers
1763 for special
in info
.special_regs
:
1764 if special
in special_sprs
:
1765 inputs
.append(self
.spr
[special
])
1767 inputs
.append(self
.namespace
[special
])
1769 # clear trap (trap) NIA
1770 self
.trap_nia
= None
1772 # check if this was an sv.bc* and create an indicator that
1773 # this is the last check to be made as a loop. combined with
1774 # the ALL/ANY mode we can early-exit
1775 if self
.is_svp64_mode
and ins_name
.startswith("sv.bc"):
1776 no_in_vec
= yield self
.dec2
.no_in_vec
# BI is scalar
1777 end_loop
= no_in_vec
or srcstep
== vl
-1 or dststep
== vl
-1
1778 self
.namespace
['end_loop'] = SelectableInt(end_loop
, 1)
1780 # execute actual instruction here (finally)
1781 log("inputs", inputs
)
1782 results
= info
.func(self
, *inputs
)
1783 output_names
= create_args(info
.write_regs
)
1785 for out
, n
in zip(results
or [], output_names
):
1787 log("results", outs
)
1789 # "inject" decorator takes namespace from function locals: we need to
1790 # overwrite NIA being overwritten (sigh)
1791 if self
.trap_nia
is not None:
1792 self
.namespace
['NIA'] = self
.trap_nia
1794 log("after func", self
.namespace
['CIA'], self
.namespace
['NIA'])
1796 # check if op was a LD/ST so that debugging can check the
1798 if int_op
in [MicrOp
.OP_STORE
.value
,
1800 self
.last_st_addr
= self
.mem
.last_st_addr
1801 if int_op
in [MicrOp
.OP_LOAD
.value
,
1803 self
.last_ld_addr
= self
.mem
.last_ld_addr
1804 log("op", int_op
, MicrOp
.OP_STORE
.value
, MicrOp
.OP_LOAD
.value
,
1805 self
.last_st_addr
, self
.last_ld_addr
)
1807 # detect if CA/CA32 already in outputs (sra*, basically)
1809 ca32
= outs
.get("CA32 ")
1811 log("carry already done?", ca
, ca32
, output_names
)
1812 carry_en
= yield self
.dec2
.e
.do
.output_carry
1814 yield from self
.handle_carry_(inputs
, results
[0], ca
, ca32
)
1816 # check if one of the regs was named "overflow"
1817 overflow
= outs
.get('overflow')
1818 # and one called CR0
1819 cr0
= outs
.get('CR0')
1821 if not self
.is_svp64_mode
: # yeah just no. not in parallel processing
1822 # detect if overflow was in return result
1823 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
1824 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
1825 log("internal overflow", ins_name
, overflow
, "en?", ov_en
, ov_ok
)
1827 yield from self
.handle_overflow(inputs
, results
[0], overflow
)
1829 # only do SVP64 dest predicated Rc=1 if dest-pred is not enabled
1831 if not self
.is_svp64_mode
or not pred_dst_zero
:
1832 if hasattr(self
.dec2
.e
.do
, "rc"):
1833 rc_en
= yield self
.dec2
.e
.do
.rc
.rc
1834 # don't do Rc=1 for svstep it is handled explicitly.
1835 # XXX TODO: now that CR0 is supported, sort out svstep's pseudocode
1836 # to write directly to CR0 instead of in ISACaller. hooyahh.
1837 if rc_en
and ins_name
not in ['svstep']:
1838 yield from self
.do_rc_ov(ins_name
, results
[0], overflow
, cr0
)
1842 if self
.is_svp64_mode
:
1843 ffirst_hit
= (yield from self
.check_ffirst(rc_en
, srcstep
))
1845 # any modified return results?
1846 yield from self
.do_outregs_nia(asmop
, ins_name
, info
, outs
,
1847 carry_en
, rc_en
, ffirst_hit
)
1849 def check_ffirst(self
, rc_en
, srcstep
):
1850 rm_mode
= yield self
.dec2
.rm_dec
.mode
1851 ff_inv
= yield self
.dec2
.rm_dec
.inv
1852 cr_bit
= yield self
.dec2
.rm_dec
.cr_sel
1853 RC1
= yield self
.dec2
.rm_dec
.RC1
1854 vli
= yield self
.dec2
.rm_dec
.vli
# VL inclusive if truncated
1855 log(" ff rm_mode", rc_en
, rm_mode
, SVP64RMMode
.FFIRST
.value
)
1859 log(" cr_bit", cr_bit
)
1860 if not rc_en
or rm_mode
!= SVP64RMMode
.FFIRST
.value
:
1862 regnum
, is_vec
= yield from get_pdecode_cr_out(self
.dec2
, "CR0")
1863 crtest
= self
.crl
[regnum
]
1864 ffirst_hit
= crtest
[cr_bit
] != ff_inv
1865 log("cr test", regnum
, int(crtest
), crtest
, cr_bit
, ff_inv
)
1866 log("cr test?", ffirst_hit
)
1869 vli
= SelectableInt(int(vli
), 7)
1870 self
.svstate
.vl
= srcstep
+ vli
1871 yield self
.dec2
.state
.svstate
.eq(self
.svstate
.value
)
1872 yield Settle() # let decoder update
1875 def do_rc_ov(self
, ins_name
, result
, overflow
, cr0
):
1876 if ins_name
.startswith("f"):
1877 rc_reg
= "CR1" # not calculated correctly yet (not FP compares)
1880 regnum
, is_vec
= yield from get_pdecode_cr_out(self
.dec2
, rc_reg
)
1881 # hang on... for `setvl` actually you want to test SVSTATE.VL
1882 is_setvl
= ins_name
== 'setvl'
1884 result
= SelectableInt(result
.vl
, 64)
1886 overflow
= None # do not override overflow except in setvl
1888 # if there was not an explicit CR0 in the pseudocode, do implicit Rc=1
1890 self
.handle_comparison(result
, regnum
, overflow
, no_so
=is_setvl
)
1892 # otherwise we just blat CR0 into the required regnum
1893 log("explicit rc0", cr0
)
1894 self
.crl
[regnum
].eq(cr0
)
1896 def do_outregs_nia(self
, asmop
, ins_name
, info
, outs
,
1897 carry_en
, rc_en
, ffirst_hit
):
1898 # write out any regs for this instruction
1899 for name
, output
in outs
.items():
1900 yield from self
.check_write(info
, name
, output
, carry_en
)
1903 self
.svp64_reset_loop()
1906 # check advancement of src/dst/sub-steps and if PC needs updating
1907 nia_update
= (yield from self
.check_step_increment(rc_en
,
1910 self
.update_pc_next()
1912 def check_replace_d(self
, info
, remap_active
):
1913 replace_d
= False # update / replace constant in pseudocode
1914 ldstmode
= yield self
.dec2
.rm_dec
.ldstmode
1915 vl
= self
.svstate
.vl
1916 subvl
= yield self
.dec2
.rm_dec
.rm_in
.subvl
1917 srcstep
, dststep
= self
.new_srcstep
, self
.new_dststep
1918 ssubstep
, dsubstep
= self
.new_ssubstep
, self
.new_dsubstep
1919 if info
.form
== 'DS':
1920 # DS-Form, multiply by 4 then knock 2 bits off after
1921 imm
= yield self
.dec2
.dec
.fields
.FormDS
.DS
[0:14] * 4
1923 imm
= yield self
.dec2
.dec
.fields
.FormD
.D
[0:16]
1924 imm
= exts(imm
, 16) # sign-extend to integer
1925 # get the right step. LD is from srcstep, ST is dststep
1926 op
= yield self
.dec2
.e
.do
.insn_type
1928 if op
== MicrOp
.OP_LOAD
.value
:
1930 offsmul
= yield self
.dec2
.in1_step
1931 log("D-field REMAP src", imm
, offsmul
)
1933 offsmul
= (srcstep
* (subvl
+1)) + ssubstep
1934 log("D-field src", imm
, offsmul
)
1935 elif op
== MicrOp
.OP_STORE
.value
:
1936 # XXX NOTE! no bit-reversed STORE! this should not ever be used
1937 offsmul
= (dststep
* (subvl
+1)) + dsubstep
1938 log("D-field dst", imm
, offsmul
)
1939 # Unit-Strided LD/ST adds offset*width to immediate
1940 if ldstmode
== SVP64LDSTmode
.UNITSTRIDE
.value
:
1941 ldst_len
= yield self
.dec2
.e
.do
.data_len
1942 imm
= SelectableInt(imm
+ offsmul
* ldst_len
, 32)
1944 # Element-strided multiplies the immediate by element step
1945 elif ldstmode
== SVP64LDSTmode
.ELSTRIDE
.value
:
1946 imm
= SelectableInt(imm
* offsmul
, 32)
1949 ldst_ra_vec
= yield self
.dec2
.rm_dec
.ldst_ra_vec
1950 ldst_imz_in
= yield self
.dec2
.rm_dec
.ldst_imz_in
1951 log("LDSTmode", SVP64LDSTmode(ldstmode
),
1952 offsmul
, imm
, ldst_ra_vec
, ldst_imz_in
)
1953 # new replacement D... errr.. DS
1955 if info
.form
== 'DS':
1956 # TODO: assert 2 LSBs are zero?
1957 log("DS-Form, TODO, assert 2 LSBs zero?", bin(imm
.value
))
1958 imm
.value
= imm
.value
>> 2
1959 self
.namespace
['DS'] = imm
1961 self
.namespace
['D'] = imm
1963 def get_input(self
, name
):
1964 # using PowerDecoder2, first, find the decoder index.
1965 # (mapping name RA RB RC RS to in1, in2, in3)
1966 regnum
, is_vec
= yield from get_pdecode_idx_in(self
.dec2
, name
)
1968 # doing this is not part of svp64, it's because output
1969 # registers, to be modified, need to be in the namespace.
1970 regnum
, is_vec
= yield from get_pdecode_idx_out(self
.dec2
, name
)
1972 regnum
, is_vec
= yield from get_pdecode_idx_out2(self
.dec2
, name
)
1974 # in case getting the register number is needed, _RA, _RB
1975 regname
= "_" + name
1976 self
.namespace
[regname
] = regnum
1977 if not self
.is_svp64_mode
or not self
.pred_src_zero
:
1978 log('reading reg %s %s' % (name
, str(regnum
)), is_vec
)
1980 reg_val
= SelectableInt(self
.fpr(regnum
))
1981 log("read reg %d: 0x%x" % (regnum
, reg_val
.value
))
1982 elif name
is not None:
1983 reg_val
= SelectableInt(self
.gpr(regnum
))
1984 log("read reg %d: 0x%x" % (regnum
, reg_val
.value
))
1986 log('zero input reg %s %s' % (name
, str(regnum
)), is_vec
)
1990 def remap_set_steps(self
, remaps
):
1991 """remap_set_steps sets up the in1/2/3 and out1/2 steps.
1992 they work in concert with PowerDecoder2 at the moment,
1993 there is no HDL implementation of REMAP. therefore this
1994 function, because ISACaller still uses PowerDecoder2,
1995 will *explicitly* write the dec2.XX_step values. this has
1998 # just some convenient debug info
2000 sname
= 'SVSHAPE%d' % i
2001 shape
= self
.spr
[sname
]
2002 log(sname
, bin(shape
.value
))
2003 log(" lims", shape
.lims
)
2004 log(" mode", shape
.mode
)
2005 log(" skip", shape
.skip
)
2007 # set up the list of steps to remap
2008 mi0
= self
.svstate
.mi0
2009 mi1
= self
.svstate
.mi1
2010 mi2
= self
.svstate
.mi2
2011 mo0
= self
.svstate
.mo0
2012 mo1
= self
.svstate
.mo1
2013 steps
= [(self
.dec2
.in1_step
, mi0
), # RA
2014 (self
.dec2
.in2_step
, mi1
), # RB
2015 (self
.dec2
.in3_step
, mi2
), # RC
2016 (self
.dec2
.o_step
, mo0
), # RT
2017 (self
.dec2
.o2_step
, mo1
), # EA
2019 remap_idxs
= self
.remap_idxs
2021 # now cross-index the required SHAPE for each of 3-in 2-out regs
2022 rnames
= ['RA', 'RB', 'RC', 'RT', 'EA']
2023 for i
, (dstep
, shape_idx
) in enumerate(steps
):
2024 (shape
, remap
) = remaps
[shape_idx
]
2025 remap_idx
= remap_idxs
[shape_idx
]
2026 # zero is "disabled"
2027 if shape
.value
== 0x0:
2029 # now set the actual requested step to the current index
2030 yield dstep
.eq(remap_idx
)
2032 # debug printout info
2033 rremaps
.append((shape
.mode
, i
, rnames
[i
], shape_idx
, remap_idx
))
2035 log("shape remap", x
)
2037 def check_write(self
, info
, name
, output
, carry_en
):
2038 if name
== 'overflow': # ignore, done already (above)
2040 if name
== 'CR0': # ignore, done already (above)
2042 if isinstance(output
, int):
2043 output
= SelectableInt(output
, 256)
2045 if name
in ['CA', 'CA32']:
2047 log("writing %s to XER" % name
, output
)
2048 log("write XER %s 0x%x" % (name
, output
.value
))
2049 self
.spr
['XER'][XER_bits
[name
]] = output
.value
2051 log("NOT writing %s to XER" % name
, output
)
2053 # write special SPRs
2054 if name
in info
.special_regs
:
2055 log('writing special %s' % name
, output
, special_sprs
)
2056 log("write reg %s 0x%x" % (name
, output
.value
))
2057 if name
in special_sprs
:
2058 self
.spr
[name
] = output
2060 self
.namespace
[name
].eq(output
)
2062 log('msr written', hex(self
.msr
.value
))
2064 # find out1/out2 PR/FPR
2065 regnum
, is_vec
= yield from get_pdecode_idx_out(self
.dec2
, name
)
2067 regnum
, is_vec
= yield from get_pdecode_idx_out2(self
.dec2
, name
)
2069 # temporary hack for not having 2nd output
2070 regnum
= yield getattr(self
.decoder
, name
)
2072 # convenient debug prefix
2077 # check zeroing due to predicate bit being zero
2078 if self
.is_svp64_mode
and self
.pred_dst_zero
:
2079 log('zeroing reg %d %s' % (regnum
, str(output
)), is_vec
)
2080 output
= SelectableInt(0, 256)
2081 log("write reg %s%d 0x%x" % (reg_prefix
, regnum
, output
.value
),
2082 kind
=LogKind
.InstrInOuts
)
2083 # zero-extend tov64 bit begore storing (should use EXT oh well)
2084 if output
.bits
> 64:
2085 output
= SelectableInt(output
.value
, 64)
2087 self
.fpr
[regnum
] = output
2089 self
.gpr
[regnum
] = output
2091 def check_step_increment(self
, rc_en
, asmop
, ins_name
):
2092 # check if it is the SVSTATE.src/dest step that needs incrementing
2093 # this is our Sub-Program-Counter loop from 0 to VL-1
2094 if not self
.allow_next_step_inc
:
2095 if self
.is_svp64_mode
:
2096 return (yield from self
.svstate_post_inc(ins_name
))
2098 # XXX only in non-SVP64 mode!
2099 # record state of whether the current operation was an svshape,
2101 # to be able to know if it should apply in the next instruction.
2102 # also (if going to use this instruction) should disable ability
2103 # to interrupt in between. sigh.
2104 self
.last_op_svshape
= asmop
in ['svremap', 'svindex',
2111 log("SVSTATE_NEXT: inc requested, mode",
2112 self
.svstate_next_mode
, self
.allow_next_step_inc
)
2113 yield from self
.svstate_pre_inc()
2114 pre
= yield from self
.update_new_svstate_steps()
2116 # reset at end of loop including exit Vertical Mode
2117 log("SVSTATE_NEXT: end of loop, reset")
2118 self
.svp64_reset_loop()
2119 self
.svstate
.vfirst
= 0
2123 self
.handle_comparison(SelectableInt(0, 64)) # CR0
2125 if self
.allow_next_step_inc
== 2:
2126 log("SVSTATE_NEXT: read")
2127 nia_update
= (yield from self
.svstate_post_inc(ins_name
))
2129 log("SVSTATE_NEXT: post-inc")
2130 # use actual (cached) src/dst-step here to check end
2131 remaps
= self
.get_remap_indices()
2132 remap_idxs
= self
.remap_idxs
2133 vl
= self
.svstate
.vl
2134 subvl
= yield self
.dec2
.rm_dec
.rm_in
.subvl
2135 if self
.allow_next_step_inc
!= 2:
2136 yield from self
.advance_svstate_steps()
2137 #self.namespace['SVSTATE'] = self.svstate.spr
2138 # set CR0 (if Rc=1) based on end
2139 endtest
= 1 if self
.at_loopend() else 0
2141 #results = [SelectableInt(endtest, 64)]
2142 # self.handle_comparison(results) # CR0
2144 # see if svstep was requested, if so, which SVSTATE
2146 if self
.svstate_next_mode
> 0:
2147 shape_idx
= self
.svstate_next_mode
.value
-1
2148 endings
= self
.remap_loopends
[shape_idx
]
2149 cr_field
= SelectableInt((~endings
) << 1 | endtest
, 4)
2150 log("svstep Rc=1, CR0", cr_field
, endtest
)
2151 self
.crl
[0].eq(cr_field
) # CR0
2153 # reset at end of loop including exit Vertical Mode
2154 log("SVSTATE_NEXT: after increments, reset")
2155 self
.svp64_reset_loop()
2156 self
.svstate
.vfirst
= 0
2159 def SVSTATE_NEXT(self
, mode
, submode
):
2160 """explicitly moves srcstep/dststep on to next element, for
2161 "Vertical-First" mode. this function is called from
2162 setvl pseudo-code, as a pseudo-op "svstep"
2164 WARNING: this function uses information that was created EARLIER
2165 due to it being in the middle of a yield, but this function is
2166 *NOT* called from yield (it's called from compiled pseudocode).
2168 self
.allow_next_step_inc
= submode
.value
+ 1
2169 log("SVSTATE_NEXT mode", mode
, submode
, self
.allow_next_step_inc
)
2170 self
.svstate_next_mode
= mode
2171 if self
.svstate_next_mode
> 0 and self
.svstate_next_mode
< 5:
2172 shape_idx
= self
.svstate_next_mode
.value
-1
2173 return SelectableInt(self
.remap_idxs
[shape_idx
], 7)
2174 if self
.svstate_next_mode
== 5:
2175 self
.svstate_next_mode
= 0
2176 return SelectableInt(self
.svstate
.srcstep
, 7)
2177 if self
.svstate_next_mode
== 6:
2178 self
.svstate_next_mode
= 0
2179 return SelectableInt(self
.svstate
.dststep
, 7)
2180 if self
.svstate_next_mode
== 7:
2181 self
.svstate_next_mode
= 0
2182 return SelectableInt(self
.svstate
.ssubstep
, 7)
2183 if self
.svstate_next_mode
== 8:
2184 self
.svstate_next_mode
= 0
2185 return SelectableInt(self
.svstate
.dsubstep
, 7)
2186 return SelectableInt(0, 7)
2188 def get_src_dststeps(self
):
2189 """gets srcstep, dststep, and ssubstep, dsubstep
2191 return (self
.new_srcstep
, self
.new_dststep
,
2192 self
.new_ssubstep
, self
.new_dsubstep
)
2194 def update_svstate_namespace(self
, overwrite_svstate
=True):
2195 if overwrite_svstate
:
2196 # note, do not get the bit-reversed srcstep here!
2197 srcstep
, dststep
= self
.new_srcstep
, self
.new_dststep
2198 ssubstep
, dsubstep
= self
.new_ssubstep
, self
.new_dsubstep
2200 # update SVSTATE with new srcstep
2201 self
.svstate
.srcstep
= srcstep
2202 self
.svstate
.dststep
= dststep
2203 self
.svstate
.ssubstep
= ssubstep
2204 self
.svstate
.dsubstep
= dsubstep
2205 self
.namespace
['SVSTATE'] = self
.svstate
2206 yield self
.dec2
.state
.svstate
.eq(self
.svstate
.value
)
2207 yield Settle() # let decoder update
2209 def update_new_svstate_steps(self
, overwrite_svstate
=True):
2210 yield from self
.update_svstate_namespace(overwrite_svstate
)
2211 srcstep
= self
.svstate
.srcstep
2212 dststep
= self
.svstate
.dststep
2213 ssubstep
= self
.svstate
.ssubstep
2214 dsubstep
= self
.svstate
.dsubstep
2215 pack
= self
.svstate
.pack
2216 unpack
= self
.svstate
.unpack
2217 vl
= self
.svstate
.vl
2218 subvl
= yield self
.dec2
.rm_dec
.rm_in
.subvl
2219 rm_mode
= yield self
.dec2
.rm_dec
.mode
2220 ff_inv
= yield self
.dec2
.rm_dec
.inv
2221 cr_bit
= yield self
.dec2
.rm_dec
.cr_sel
2222 log(" srcstep", srcstep
)
2223 log(" dststep", dststep
)
2225 log(" unpack", unpack
)
2226 log(" ssubstep", ssubstep
)
2227 log(" dsubstep", dsubstep
)
2229 log(" subvl", subvl
)
2230 log(" rm_mode", rm_mode
)
2232 log(" cr_bit", cr_bit
)
2234 # check if end reached (we let srcstep overrun, above)
2235 # nothing needs doing (TODO zeroing): just do next instruction
2238 return ((ssubstep
== subvl
and srcstep
== vl
) or
2239 (dsubstep
== subvl
and dststep
== vl
))
2241 def svstate_post_inc(self
, insn_name
, vf
=0):
2242 # check if SV "Vertical First" mode is enabled
2243 vfirst
= self
.svstate
.vfirst
2244 log(" SV Vertical First", vf
, vfirst
)
2245 if not vf
and vfirst
== 1:
2249 # check if it is the SVSTATE.src/dest step that needs incrementing
2250 # this is our Sub-Program-Counter loop from 0 to VL-1
2251 # XXX twin predication TODO
2252 vl
= self
.svstate
.vl
2253 subvl
= yield self
.dec2
.rm_dec
.rm_in
.subvl
2254 mvl
= self
.svstate
.maxvl
2255 srcstep
= self
.svstate
.srcstep
2256 dststep
= self
.svstate
.dststep
2257 ssubstep
= self
.svstate
.ssubstep
2258 dsubstep
= self
.svstate
.dsubstep
2259 pack
= self
.svstate
.pack
2260 unpack
= self
.svstate
.unpack
2261 rm_mode
= yield self
.dec2
.rm_dec
.mode
2262 reverse_gear
= yield self
.dec2
.rm_dec
.reverse_gear
2263 sv_ptype
= yield self
.dec2
.dec
.op
.SV_Ptype
2264 out_vec
= not (yield self
.dec2
.no_out_vec
)
2265 in_vec
= not (yield self
.dec2
.no_in_vec
)
2266 log(" svstate.vl", vl
)
2267 log(" svstate.mvl", mvl
)
2268 log(" rm.subvl", subvl
)
2269 log(" svstate.srcstep", srcstep
)
2270 log(" svstate.dststep", dststep
)
2271 log(" svstate.ssubstep", ssubstep
)
2272 log(" svstate.dsubstep", dsubstep
)
2273 log(" svstate.pack", pack
)
2274 log(" svstate.unpack", unpack
)
2275 log(" mode", rm_mode
)
2276 log(" reverse", reverse_gear
)
2277 log(" out_vec", out_vec
)
2278 log(" in_vec", in_vec
)
2279 log(" sv_ptype", sv_ptype
, sv_ptype
== SVPtype
.P2
.value
)
2280 # check if this was an sv.bc* and if so did it succeed
2281 if self
.is_svp64_mode
and insn_name
.startswith("sv.bc"):
2282 end_loop
= self
.namespace
['end_loop']
2283 log("branch %s end_loop" % insn_name
, end_loop
)
2285 self
.svp64_reset_loop()
2286 self
.update_pc_next()
2288 # check if srcstep needs incrementing by one, stop PC advancing
2289 # but for 2-pred both src/dest have to be checked.
2290 # XXX this might not be true! it may just be LD/ST
2291 if sv_ptype
== SVPtype
.P2
.value
:
2292 svp64_is_vector
= (out_vec
or in_vec
)
2294 svp64_is_vector
= out_vec
2295 # loops end at the first "hit" (source or dest)
2296 yield from self
.advance_svstate_steps()
2297 loopend
= self
.loopend
2298 log("loopend", svp64_is_vector
, loopend
)
2299 if not svp64_is_vector
or loopend
:
2300 # reset loop to zero and update NIA
2301 self
.svp64_reset_loop()
2306 # still looping, advance and update NIA
2307 self
.namespace
['SVSTATE'] = self
.svstate
2309 # not an SVP64 branch, so fix PC (NIA==CIA) for next loop
2310 # (by default, NIA is CIA+4 if v3.0B or CIA+8 if SVP64)
2311 # this way we keep repeating the same instruction (with new steps)
2312 self
.pc
.NIA
.value
= self
.pc
.CIA
.value
2313 self
.namespace
['NIA'] = self
.pc
.NIA
2314 log("end of sub-pc call", self
.namespace
['CIA'], self
.namespace
['NIA'])
2315 return False # DO NOT allow PC update whilst Sub-PC loop running
2317 def update_pc_next(self
):
2318 # UPDATE program counter
2319 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
2320 #self.svstate.spr = self.namespace['SVSTATE']
2321 log("end of call", self
.namespace
['CIA'],
2322 self
.namespace
['NIA'],
2323 self
.namespace
['SVSTATE'])
2325 def svp64_reset_loop(self
):
2326 self
.svstate
.srcstep
= 0
2327 self
.svstate
.dststep
= 0
2328 self
.svstate
.ssubstep
= 0
2329 self
.svstate
.dsubstep
= 0
2330 self
.loopend
= False
2331 log(" svstate.srcstep loop end (PC to update)")
2332 self
.namespace
['SVSTATE'] = self
.svstate
2334 def update_nia(self
):
2335 self
.pc
.update_nia(self
.is_svp64_mode
)
2336 self
.namespace
['NIA'] = self
.pc
.NIA
2340 """Decorator factory.
2342 this decorator will "inject" variables into the function's namespace,
2343 from the *dictionary* in self.namespace. it therefore becomes possible
2344 to make it look like a whole stack of variables which would otherwise
2345 need "self." inserted in front of them (*and* for those variables to be
2346 added to the instance) "appear" in the function.
2348 "self.namespace['SI']" for example becomes accessible as just "SI" but
2349 *only* inside the function, when decorated.
2351 def variable_injector(func
):
2353 def decorator(*args
, **kwargs
):
2355 func_globals
= func
.__globals
__ # Python 2.6+
2356 except AttributeError:
2357 func_globals
= func
.func_globals
# Earlier versions.
2359 context
= args
[0].namespace
# variables to be injected
2360 saved_values
= func_globals
.copy() # Shallow copy of dict.
2361 log("globals before", context
.keys())
2362 func_globals
.update(context
)
2363 result
= func(*args
, **kwargs
)
2364 log("globals after", func_globals
['CIA'], func_globals
['NIA'])
2365 log("args[0]", args
[0].namespace
['CIA'],
2366 args
[0].namespace
['NIA'],
2367 args
[0].namespace
['SVSTATE'])
2368 if 'end_loop' in func_globals
:
2369 log("args[0] end_loop", func_globals
['end_loop'])
2370 args
[0].namespace
= func_globals
2371 #exec (func.__code__, func_globals)
2374 # func_globals = saved_values # Undo changes.
2380 return variable_injector