src/openpower/decoder/isa/test_caller_fp.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from copy import deepcopy
  15
  16
  17 class DecoderTestCase(FHDLTestCase):
  18
  19     def _check_regs(self, sim, expected_int, expected_fpr):
  20         for i in range(32):
  21             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  22         for i in range(32):
  23             self.assertEqual(sim.fpr(i), SelectableInt(expected_fpr[i], 64))
  24
  25     def test_fpload(self):
  26         """>>> lst = ["lfsx 1, 0, 0",
  27                      ]
  28         """
  29         lst = ["lfsx 1, 0, 0",
  30                      ]
  31         initial_mem = {0x0000: (0x42013333, 8),
  32                        0x0008: (0x42026666, 8),
  33                        0x0020: (0x1828384822324252, 8),
  34                         }
  35
  36         with Program(lst, bigendian=False) as program:
  37             sim = self.run_tst_program(program, initial_mem=initial_mem)
  38             print("FPR 1", sim.fpr(1))
  39             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
  40
  41     def test_fpload_imm(self):
  42         """>>> lst = ["lfs 1, 8(1)",
  43                      ]
  44         """
  45         lst = ["lfs 1, 8(1)",
  46                      ]
  47         initial_mem = {0x0000: (0x42013333, 8),
  48                        0x0008: (0x42026666, 8),
  49                        0x0020: (0x1828384822324252, 8),
  50                         }
  51
  52         with Program(lst, bigendian=False) as program:
  53             sim = self.run_tst_program(program, initial_mem=initial_mem)
  54             print("FPR 1", sim.fpr(1))
  55             self.assertEqual(sim.fpr(1), SelectableInt(0x40404cccc0000000, 64))
  56
  57     def test_fpload2(self):
  58         """>>> lst = ["lfsx 1, 0, 0",
  59                      ]
  60         """
  61         lst = ["lfsx 1, 0, 0",
  62                      ]
  63         initial_mem = {0x0000: (0xac000000, 8),
  64                        0x0020: (0x1828384822324252, 8),
  65                         }
  66
  67         with Program(lst, bigendian=False) as program:
  68             sim = self.run_tst_program(program, initial_mem=initial_mem)
  69             print("FPR 1", sim.fpr(1))
  70             self.assertEqual(sim.fpr(1), SelectableInt(0xbd80000000000000, 64))
  71
  72     def test_fp_single_ldst(self):
  73         """>>> lst = ["lfsx 1, 1, 0",   # load fp 1 from mem location 0
  74                       "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA
  75                       "lfs 2, 0(1)",   # re-load from UPDATED r1
  76                      ]
  77         """
  78         lst = ["lfsx 1, 1, 0",
  79                "stfsu 1, 16(1)",
  80                "lfs 2, 0(1)",
  81                      ]
  82         initial_mem = {0x0000: (0x42013333, 8),
  83                        0x0008: (0x42026666, 8),
  84                        0x0020: (0x1828384822324252, 8),
  85                         }
  86
  87         with Program(lst, bigendian=False) as program:
  88             sim = self.run_tst_program(program, initial_mem=initial_mem)
  89             print("FPR 1", sim.fpr(1))
  90             print("FPR 2", sim.fpr(2))
  91             print("GPR 1", sim.gpr(1)) # should be 0x10 due to update
  92             self.assertEqual(sim.gpr(1), SelectableInt(0x10, 64))
  93             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
  94             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
  95
  96     def test_fp_single_ldst_update_idx(self):
  97         """>>> lst = ["lfsx 1, 0, 0",   # load fp 1 from mem location 0
  98                       "stfsux 1, 2, 1", # store fp 1 into mem 0x10, update RA
  99                       "lfs 2, 0(2)",   # re-load from UPDATED r2
 100                      ]
 101         """
 102         lst = ["lfsx 1, 0, 0",
 103                "stfsux 1, 2, 1",
 104                "lfs 2, 0(2)",
 105                      ]
 106         initial_mem = {0x0000: (0x42013333, 8),
 107                        0x0008: (0x42026666, 8),
 108                        0x0020: (0x1828384822324252, 8),
 109                         }
 110         # create an offset of 0x10 (2+3)
 111         initial_regs = [0]*32
 112         initial_regs[1] = 0x4
 113         initial_regs[2] = 0xc
 114
 115         with Program(lst, bigendian=False) as program:
 116             sim = self.run_tst_program(program, initial_regs=initial_regs,
 117                                                 initial_mem=initial_mem)
 118             print("FPR 1", sim.fpr(1))
 119             print("FPR 2", sim.fpr(2))
 120             print("GPR 1", sim.gpr(1)) # should be 0x4
 121             print("GPR 2", sim.gpr(2)) # should be 0x10 due to update
 122             print("mem dump")
 123             print(sim.mem.dump())
 124             self.assertEqual(sim.gpr(1), SelectableInt(0x4, 64))
 125             self.assertEqual(sim.gpr(2), SelectableInt(0x10, 64))
 126             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
 127             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 128
 129     def test_fp_single_ldst_idx(self):
 130         """>>> lst = ["lfsx 1, 0, 0",   # load fp 1 from mem location 0
 131                       "stfsx 1, 2, 1", # store fp 1 into mem 0x10, no update
 132                       "lfs 2, 4(2)",   # re-load from NOT updated r2
 133                      ]
 134         """
 135         lst = ["lfsx 1, 0, 0",
 136                "stfsx 1, 2, 1",
 137                "lfs 2, 4(2)",
 138                      ]
 139         initial_mem = {0x0000: (0x42013333, 8),
 140                        0x0008: (0x42026666, 8),
 141                        0x0020: (0x1828384822324252, 8),
 142                         }
 143         # create an offset of 0x10 (2+3)
 144         initial_regs = [0]*32
 145         initial_regs[1] = 0x4
 146         initial_regs[2] = 0xc
 147
 148         with Program(lst, bigendian=False) as program:
 149             sim = self.run_tst_program(program, initial_regs=initial_regs,
 150                                                 initial_mem=initial_mem)
 151             print("FPR 1", sim.fpr(1))
 152             print("FPR 2", sim.fpr(2))
 153             print("GPR 1", sim.gpr(1)) # should be 0x4
 154             print("GPR 2", sim.gpr(2)) # should be 0xc (no update)
 155             print("mem dump")
 156             print(sim.mem.dump())
 157             self.assertEqual(sim.gpr(1), SelectableInt(0x4, 64))
 158             self.assertEqual(sim.gpr(2), SelectableInt(0xc, 64))
 159             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
 160             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 161
 162     def test_fp_single_ldst_2(self):
 163         """>>> lst = ["lfsx 1, 0, 0",   # load fp 1 from mem location 0
 164                       "stfs 1, 4(2)", # store fp 1 into mem 0x10, no update
 165                       "lfs 2, 4(2)",   # re-load from NOT updated r2
 166                      ]
 167         """
 168         lst = ["lfsx 1, 0, 0",
 169                "stfs 1, 4(2)",
 170                "lfs 2, 4(2)",
 171                      ]
 172         initial_mem = {0x0000: (0x42013333, 8),
 173                        0x0008: (0x42026666, 8),
 174                        0x0020: (0x1828384822324252, 8),
 175                         }
 176         # create an offset of 0x10 (2+3)
 177         initial_regs = [0]*32
 178         initial_regs[1] = 0x4
 179         initial_regs[2] = 0xc
 180
 181         with Program(lst, bigendian=False) as program:
 182             sim = self.run_tst_program(program, initial_regs=initial_regs,
 183                                                 initial_mem=initial_mem)
 184             print("FPR 1", sim.fpr(1))
 185             print("FPR 2", sim.fpr(2))
 186             print("GPR 1", sim.gpr(1)) # should be 0x4
 187             print("GPR 2", sim.gpr(2)) # should be 0xc (no update)
 188             print("mem dump")
 189             print(sim.mem.dump())
 190             self.assertEqual(sim.gpr(1), SelectableInt(0x4, 64))
 191             self.assertEqual(sim.gpr(2), SelectableInt(0xc, 64))
 192             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
 193             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 194
 195     def test_fp_mv(self):
 196         """>>> lst = ["fmr 1, 2",
 197                      ]
 198         """
 199         lst = ["fmr 1, 2",
 200                      ]
 201
 202         fprs = [0] * 32
 203         fprs[2] = 0x4040266660000000
 204
 205         with Program(lst, bigendian=False) as program:
 206             sim = self.run_tst_program(program, initial_fprs=fprs)
 207             print("FPR 1", sim.fpr(1))
 208             print("FPR 2", sim.fpr(2))
 209             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
 210             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 211
 212     def test_fp_neg(self):
 213         """>>> lst = ["fneg 1, 2",
 214                      ]
 215         """
 216         lst = ["fneg 1, 2",
 217                      ]
 218
 219         fprs = [0] * 32
 220         fprs[2] = 0x4040266660000000
 221
 222         with Program(lst, bigendian=False) as program:
 223             sim = self.run_tst_program(program, initial_fprs=fprs)
 224             print("FPR 1", sim.fpr(1))
 225             print("FPR 2", sim.fpr(2))
 226             self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
 227             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 228
 229     def test_fp_abs(self):
 230         """>>> lst = ["fabs 3, 1",
 231                       "fabs 4, 2",
 232                       "fnabs 5, 1",
 233                       "fnabs 6, 2",
 234                      ]
 235         """
 236         lst = ["fabs 3, 1",
 237                "fabs 4, 2",
 238                "fnabs 5, 1",
 239                "fnabs 6, 2",
 240                      ]
 241
 242         fprs = [0] * 32
 243         fprs[1] = 0xC040266660000000
 244         fprs[2] = 0x4040266660000000
 245
 246         with Program(lst, bigendian=False) as program:
 247             sim = self.run_tst_program(program, initial_fprs=fprs)
 248             self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
 249             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 250             self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
 251             self.assertEqual(sim.fpr(4), SelectableInt(0x4040266660000000, 64))
 252             self.assertEqual(sim.fpr(5), SelectableInt(0xC040266660000000, 64))
 253             self.assertEqual(sim.fpr(6), SelectableInt(0xC040266660000000, 64))
 254
 255     def test_fp_sgn(self):
 256         """>>> lst = ["fcpsgn 3, 1, 2",
 257                       "fcpsgn 4, 2, 1",
 258                      ]
 259         """
 260         lst = ["fcpsgn 3, 1, 2",
 261                "fcpsgn 4, 2, 1",
 262                      ]
 263
 264         fprs = [0] * 32
 265         fprs[1] = 0xC040266660000001 # 1 in LSB, 1 in MSB
 266         fprs[2] = 0x4040266660000000 # 0 in LSB, 0 in MSB
 267
 268         with Program(lst, bigendian=False) as program:
 269             sim = self.run_tst_program(program, initial_fprs=fprs)
 270             self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000001, 64))
 271             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 272             # 1 in MSB comes from reg 1, 0 in LSB comes from reg 2
 273             self.assertEqual(sim.fpr(3), SelectableInt(0xC040266660000000, 64))
 274             # 0 in MSB comes from reg 2, 1 in LSB comes from reg 1
 275             self.assertEqual(sim.fpr(4), SelectableInt(0x4040266660000001, 64))
 276
 277     def test_fp_adds(self):
 278         """>>> lst = ["fadds 3, 1, 2",
 279                      ]
 280         """
 281         lst = ["fadds 3, 1, 2", # -32.3 + 32.3 = 0
 282                      ]
 283
 284         fprs = [0] * 32
 285         fprs[1] = 0xC040266660000000
 286         fprs[2] = 0x4040266660000000
 287
 288         with Program(lst, bigendian=False) as program:
 289             sim = self.run_tst_program(program, initial_fprs=fprs)
 290             self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
 291             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 292             self.assertEqual(sim.fpr(3), SelectableInt(0, 64))
 293
 294     def test_fp_subs(self):
 295         """>>> lst = ["fsubs 3, 1, 2",
 296                      ]
 297         """
 298         lst = ["fsubs 3, 1, 2", # 0 - -32.3 = 32.3
 299                      ]
 300
 301         fprs = [0] * 32
 302         fprs[1] = 0x0
 303         fprs[2] = 0xC040266660000000
 304
 305         with Program(lst, bigendian=False) as program:
 306             sim = self.run_tst_program(program, initial_fprs=fprs)
 307             self.assertEqual(sim.fpr(1), SelectableInt(0x0, 64))
 308             self.assertEqual(sim.fpr(2), SelectableInt(0xC040266660000000, 64))
 309             self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
 310
 311     def test_fp_add(self):
 312         """>>> lst = ["fadd 3, 1, 2",
 313                      ]
 314         """
 315         lst = ["fadd 3, 1, 2", # 7.0 + -9.8 = -2.8
 316                      ]
 317
 318         fprs = [0] * 32
 319         fprs[1] = 0x401C000000000000  # 7.0
 320         fprs[2] = 0xC02399999999999A  # -9.8
 321
 322         with Program(lst, bigendian=False) as program:
 323             sim = self.run_tst_program(program, initial_fprs=fprs)
 324             self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
 325             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
 326             self.assertEqual(sim.fpr(3), SelectableInt(0xC006666666666668, 64))
 327
 328     def test_fp_muls(self):
 329         """>>> lst = ["fmuls 3, 1, 2",
 330                      ]
 331         """
 332         lst = ["fmuls 3, 1, 2", # 7.0 * -9.8 = -68.6
 333                "fmuls 29,12,8", # test
 334                      ]
 335
 336         fprs = [0] * 32
 337         fprs[1] = 0x401C000000000000  # 7.0
 338         fprs[2] = 0xC02399999999999A  # -9.8
 339
 340         with Program(lst, bigendian=False) as program:
 341             sim = self.run_tst_program(program, initial_fprs=fprs)
 342             self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
 343             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
 344             self.assertEqual(sim.fpr(3), SelectableInt(0xc051266640000000, 64))
 345
 346     def test_fp_muls3(self):
 347         """>>> lst = ["fmuls 3, 1, 2",
 348                      ]
 349         """
 350         lst = ["fmuls 3, 1, 2", #
 351                      ]
 352
 353         fprs = [0] * 32
 354         fprs[1] = 0xbfb0ab5100000000
 355         fprs[2] = 0xbdca000000000000
 356
 357         with Program(lst, bigendian=False) as program:
 358             sim = self.run_tst_program(program, initial_fprs=fprs)
 359             self.assertEqual(sim.fpr(3), SelectableInt(0x3d8b1663a0000000, 64))
 360
 361     def test_fp_muls4(self):
 362         """>>> lst = ["fmuls 3, 1, 2",
 363                      ]
 364         """
 365         lst = ["fmuls 3, 1, 2", #
 366                      ]
 367
 368         fprs = [0] * 32
 369         fprs[1] = 0xbe724e2000000000 # negative number
 370         fprs[2] = 0x0                # times zero
 371
 372         with Program(lst, bigendian=False) as program:
 373             sim = self.run_tst_program(program, initial_fprs=fprs)
 374             # result should be -ve zero not +ve zero
 375             self.assertEqual(sim.fpr(3), SelectableInt(0x8000000000000000, 64))
 376
 377     def test_fp_muls5(self):
 378         """>>> lst = ["fmuls 3, 1, 2",
 379                      ]
 380         """
 381         lst = ["fmuls 3, 1, 2", #
 382                      ]
 383
 384         fprs = [0] * 32
 385         fprs[1] = 0xbfb0ab5100000000
 386         fprs[2] = 0xbdca000000000000
 387
 388         with Program(lst, bigendian=False) as program:
 389             sim = self.run_tst_program(program, initial_fprs=fprs)
 390             self.assertEqual(sim.fpr(3), SelectableInt(0x3d8b1663a0000000, 64))
 391
 392     def test_fp_mul(self):
 393         """>>> lst = ["fmul 3, 1, 2",
 394                      ]
 395         """
 396         lst = ["fmul 3, 1, 2", # 7.0 * -9.8 = -68.6
 397                      ]
 398
 399         fprs = [0] * 32
 400         fprs[1] = 0x401C000000000000  # 7.0
 401         fprs[2] = 0xC02399999999999A  # -9.8
 402
 403         with Program(lst, bigendian=False) as program:
 404             sim = self.run_tst_program(program, initial_fprs=fprs)
 405             self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
 406             self.assertEqual(sim.fpr(2), SelectableInt(0xC02399999999999A, 64))
 407             self.assertEqual(sim.fpr(3), SelectableInt(0xC051266666666667, 64))
 408
 409     def test_fp_madd1(self):
 410         """>>> lst = ["fmadds 3, 1, 2, 4",
 411                      ]
 412         """
 413         lst = ["fmadds 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -66.6
 414                      ]
 415
 416         fprs = [0] * 32
 417         fprs[1] = 0x401C000000000000  # 7.0
 418         fprs[2] = 0xC02399999999999A  # -9.8
 419         fprs[4] = 0x4000000000000000  # 2.0
 420
 421         with Program(lst, bigendian=False) as program:
 422             sim = self.run_tst_program(program, initial_fprs=fprs)
 423             self.assertEqual(sim.fpr(3), SelectableInt(0xC050A66660000000, 64))
 424
 425     def test_fp_msub1(self):
 426         """>>> lst = ["fmsubs 3, 1, 2, 4",
 427                      ]
 428         """
 429         lst = ["fmsubs 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -70.6
 430                      ]
 431
 432         fprs = [0] * 32
 433         fprs[1] = 0x401C000000000000  # 7.0
 434         fprs[2] = 0xC02399999999999A  # -9.8
 435         fprs[4] = 0x4000000000000000  # 2.0
 436
 437         with Program(lst, bigendian=False) as program:
 438             sim = self.run_tst_program(program, initial_fprs=fprs)
 439             self.assertEqual(sim.fpr(3), SelectableInt(0xc051a66660000000, 64))
 440
 441     def test_fp_fcfids(self):
 442         """>>> lst = ["fcfids 1, 2",
 443                lst = ["fcfids 3, 4",
 444                      ]
 445         """
 446         lst = ["fcfids 1, 2",
 447                "fcfids 3, 4",
 448                      ]
 449
 450         fprs = [0] * 32
 451         fprs[2] = 7
 452         fprs[4] = -32
 453
 454         with Program(lst, bigendian=False) as program:
 455             sim = self.run_tst_program(program, initial_fprs=fprs)
 456             self.assertEqual(sim.fpr(1), SelectableInt(0x401C000000000000, 64))
 457             self.assertEqual(sim.fpr(2), SelectableInt(7, 64))
 458             self.assertEqual(sim.fpr(3), SelectableInt(0xC040000000000000, 64))
 459             self.assertEqual(sim.fpr(4), SelectableInt(-32, 64))
 460
 461     def run_tst_program(self, prog, initial_regs=None,
 462                               initial_mem=None,
 463                               initial_fprs=None):
 464         if initial_regs is None:
 465             initial_regs = [0] * 32
 466         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 467                                   initial_fprs=initial_fprs)
 468         print ("GPRs")
 469         simulator.gpr.dump()
 470         print ("FPRs")
 471         simulator.fpr.dump()
 472         return simulator
 473
 474
 475 if __name__ == "__main__":
 476     unittest.main()