src/openpower/decoder/isa/test_caller_fp.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from copy import deepcopy
  15
  16
  17 class DecoderTestCase(FHDLTestCase):
  18
  19     def _check_regs(self, sim, expected_int, expected_fpr):
  20         for i in range(32):
  21             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  22         for i in range(32):
  23             self.assertEqual(sim.fpr(i), SelectableInt(expected_fpr[i], 64))
  24
  25     def test_fpload(self):
  26         """>>> lst = ["lfsx 1, 0, 0",
  27                      ]
  28         """
  29         lst = ["lfsx 1, 0, 0",
  30                      ]
  31         initial_mem = {0x0000: (0x42013333, 8),
  32                        0x0008: (0x42026666, 8),
  33                        0x0020: (0x1828384822324252, 8),
  34                         }
  35
  36         with Program(lst, bigendian=False) as program:
  37             sim = self.run_tst_program(program, initial_mem=initial_mem)
  38             print("FPR 1", sim.fpr(1))
  39             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
  40
  41     def test_fp_single_ldst(self):
  42         """>>> lst = ["lfsx 1, 1, 0",   # load fp 1 from mem location 0
  43                       "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA
  44                       "lfsu 2, 0(1)",   # re-load from UPDATED r1
  45                      ]
  46         """
  47         lst = ["lfsx 1, 1, 0",
  48                "stfsu 1, 16(1)",
  49                "lfs 2, 0(1)",
  50                      ]
  51         initial_mem = {0x0000: (0x42013333, 8),
  52                        0x0008: (0x42026666, 8),
  53                        0x0020: (0x1828384822324252, 8),
  54                         }
  55
  56         with Program(lst, bigendian=False) as program:
  57             sim = self.run_tst_program(program, initial_mem=initial_mem)
  58             print("FPR 1", sim.fpr(1))
  59             print("FPR 2", sim.fpr(2))
  60             print("GPR 1", sim.gpr(1)) # should be 0x10 due to update
  61             self.assertEqual(sim.gpr(1), SelectableInt(0x10, 64))
  62             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
  63             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
  64
  65     def run_tst_program(self, prog, initial_regs=None,
  66                               initial_mem=None):
  67         if initial_regs is None:
  68             initial_regs = [0] * 32
  69         simulator = run_tst(prog, initial_regs, mem=initial_mem)
  70         print ("GPRs")
  71         simulator.gpr.dump()
  72         print ("FPRs")
  73         simulator.fpr.dump()
  74         return simulator
  75
  76
  77 if __name__ == "__main__":
  78     unittest.main()