99d75192e6b49ff88d0612dba90a0ceee566846c
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from copy
import deepcopy
17 class DecoderTestCase(FHDLTestCase
):
19 def _check_regs(self
, sim
, expected_int
, expected_fpr
):
21 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
23 self
.assertEqual(sim
.fpr(i
), SelectableInt(expected_fpr
[i
], 64))
25 def test_fpload(self
):
26 """>>> lst = ["lfsx 1, 0, 0",
29 lst
= ["lfsx 1, 0, 0",
31 initial_mem
= {0x0000: (0x42013333, 8),
32 0x0008: (0x42026666, 8),
33 0x0020: (0x1828384822324252, 8),
36 with
Program(lst
, bigendian
=False) as program
:
37 sim
= self
.run_tst_program(program
, initial_mem
=initial_mem
)
38 print("FPR 1", sim
.fpr(1))
39 self
.assertEqual(sim
.fpr(1), SelectableInt(0x4040266660000000, 64))
41 def test_fp_single_ldst(self
):
42 """>>> lst = ["lfsx 1, 1, 0", # load fp 1 from mem location 0
43 "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA
44 "lfsu 2, 0(1)", # re-load from UPDATED r1
47 lst
= ["lfsx 1, 1, 0",
51 initial_mem
= {0x0000: (0x42013333, 8),
52 0x0008: (0x42026666, 8),
53 0x0020: (0x1828384822324252, 8),
56 with
Program(lst
, bigendian
=False) as program
:
57 sim
= self
.run_tst_program(program
, initial_mem
=initial_mem
)
58 print("FPR 1", sim
.fpr(1))
59 print("FPR 2", sim
.fpr(2))
60 print("GPR 1", sim
.gpr(1)) # should be 0x10 due to update
61 self
.assertEqual(sim
.gpr(1), SelectableInt(0x10, 64))
62 self
.assertEqual(sim
.fpr(1), SelectableInt(0x4040266660000000, 64))
63 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
66 """>>> lst = ["fmr 1, 2",
73 fprs
[2] = 0x4040266660000000
75 with
Program(lst
, bigendian
=False) as program
:
76 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
77 print("FPR 1", sim
.fpr(1))
78 print("FPR 2", sim
.fpr(2))
79 self
.assertEqual(sim
.fpr(1), SelectableInt(0x4040266660000000, 64))
80 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
82 def test_fp_neg(self
):
83 """>>> lst = ["fneg 1, 2",
90 fprs
[2] = 0x4040266660000000
92 with
Program(lst
, bigendian
=False) as program
:
93 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
94 print("FPR 1", sim
.fpr(1))
95 print("FPR 2", sim
.fpr(2))
96 self
.assertEqual(sim
.fpr(1), SelectableInt(0xC040266660000000, 64))
97 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
99 def test_fp_abs(self
):
100 """>>> lst = ["fabs 3, 1",
113 fprs
[1] = 0xC040266660000000
114 fprs
[2] = 0x4040266660000000
116 with
Program(lst
, bigendian
=False) as program
:
117 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
118 self
.assertEqual(sim
.fpr(1), SelectableInt(0xC040266660000000, 64))
119 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
120 self
.assertEqual(sim
.fpr(3), SelectableInt(0x4040266660000000, 64))
121 self
.assertEqual(sim
.fpr(4), SelectableInt(0x4040266660000000, 64))
122 self
.assertEqual(sim
.fpr(5), SelectableInt(0xC040266660000000, 64))
123 self
.assertEqual(sim
.fpr(6), SelectableInt(0xC040266660000000, 64))
125 def test_fp_sgn(self
):
126 """>>> lst = ["fcpsgn 3, 1, 2",
130 lst
= ["fcpsgn 3, 1, 2",
135 fprs
[1] = 0xC040266660000001 # 1 in LSB, 1 in MSB
136 fprs
[2] = 0x4040266660000000 # 0 in LSB, 0 in MSB
138 with
Program(lst
, bigendian
=False) as program
:
139 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
140 self
.assertEqual(sim
.fpr(1), SelectableInt(0xC040266660000001, 64))
141 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
142 # 1 in MSB comes from reg 1, 0 in LSB comes from reg 2
143 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC040266660000000, 64))
144 # 0 in MSB comes from reg 2, 1 in LSB comes from reg 1
145 self
.assertEqual(sim
.fpr(4), SelectableInt(0x4040266660000001, 64))
147 def test_fp_adds(self
):
148 """>>> lst = ["fadds 3, 1, 2",
151 lst
= ["fadds 3, 1, 2", # -32.3 + 32.3 = 0
155 fprs
[1] = 0xC040266660000000
156 fprs
[2] = 0x4040266660000000
158 with
Program(lst
, bigendian
=False) as program
:
159 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
160 self
.assertEqual(sim
.fpr(1), SelectableInt(0xC040266660000000, 64))
161 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
162 self
.assertEqual(sim
.fpr(3), SelectableInt(0, 64))
164 def test_fp_add(self
):
165 """>>> lst = ["fadd 3, 1, 2",
168 lst
= ["fadd 3, 1, 2", # 7.0 + -9.8 = -2.8
172 fprs
[1] = 0x401C000000000000 # 7.0
173 fprs
[2] = 0xC02399999999999A # -9.8
175 with
Program(lst
, bigendian
=False) as program
:
176 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
177 self
.assertEqual(sim
.fpr(1), SelectableInt(0x401C000000000000, 64))
178 self
.assertEqual(sim
.fpr(2), SelectableInt(0xC02399999999999A, 64))
179 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC006666666666668, 64))
181 def test_fp_muls(self
):
182 """>>> lst = ["fmuls 3, 1, 2",
185 lst
= ["fmuls 3, 1, 2", # 7.0 * -9.8 = -68.6
189 fprs
[1] = 0x401C000000000000 # 7.0
190 fprs
[2] = 0xC02399999999999A # -9.8
192 with
Program(lst
, bigendian
=False) as program
:
193 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
194 self
.assertEqual(sim
.fpr(1), SelectableInt(0x401C000000000000, 64))
195 self
.assertEqual(sim
.fpr(2), SelectableInt(0xC02399999999999A, 64))
196 self
.assertEqual(sim
.fpr(3), SelectableInt(0xc051266640000000, 64))
198 def test_fp_mul(self
):
199 """>>> lst = ["fmul 3, 1, 2",
202 lst
= ["fmul 3, 1, 2", # 7.0 * -9.8 = -68.6
206 fprs
[1] = 0x401C000000000000 # 7.0
207 fprs
[2] = 0xC02399999999999A # -9.8
209 with
Program(lst
, bigendian
=False) as program
:
210 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
211 self
.assertEqual(sim
.fpr(1), SelectableInt(0x401C000000000000, 64))
212 self
.assertEqual(sim
.fpr(2), SelectableInt(0xC02399999999999A, 64))
213 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC051266666666667, 64))
215 def test_fp_fcfids(self
):
216 """>>> lst = ["fcfids 1, 2",
217 lst = ["fcfids 3, 4",
220 lst
= ["fcfids 1, 2",
228 with
Program(lst
, bigendian
=False) as program
:
229 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
230 self
.assertEqual(sim
.fpr(1), SelectableInt(0x401C000000000000, 64))
231 self
.assertEqual(sim
.fpr(2), SelectableInt(7, 64))
232 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC040000000000000, 64))
233 self
.assertEqual(sim
.fpr(4), SelectableInt(-32, 64))
235 def run_tst_program(self
, prog
, initial_regs
=None,
238 if initial_regs
is None:
239 initial_regs
= [0] * 32
240 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
241 initial_fprs
=initial_fprs
)
249 if __name__
== "__main__":