a5e16b6baa13f54162ccb78d8038674265743a2f
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from copy
import deepcopy
17 class DecoderTestCase(FHDLTestCase
):
19 def _check_regs(self
, sim
, expected_int
, expected_fpr
):
21 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
23 self
.assertEqual(sim
.fpr(i
), SelectableInt(expected_fpr
[i
], 64))
25 def test_fpload(self
):
26 """>>> lst = ["lfsx 1, 0, 0",
29 lst
= ["lfsx 1, 0, 0",
31 initial_mem
= {0x0000: (0x42013333, 8),
32 0x0008: (0x42026666, 8),
33 0x0020: (0x1828384822324252, 8),
36 with
Program(lst
, bigendian
=False) as program
:
37 sim
= self
.run_tst_program(program
, initial_mem
=initial_mem
)
38 print("FPR 1", sim
.fpr(1))
39 self
.assertEqual(sim
.fpr(1), SelectableInt(0x4040266660000000, 64))
41 def test_fpload2(self
):
42 """>>> lst = ["lfsx 1, 0, 0",
45 lst
= ["lfsx 1, 0, 0",
47 initial_mem
= {0x0000: (0xac000000, 8),
48 0x0020: (0x1828384822324252, 8),
51 with
Program(lst
, bigendian
=False) as program
:
52 sim
= self
.run_tst_program(program
, initial_mem
=initial_mem
)
53 print("FPR 1", sim
.fpr(1))
54 self
.assertEqual(sim
.fpr(1), SelectableInt(0xbd80000000000000, 64))
56 def test_fp_single_ldst(self
):
57 """>>> lst = ["lfsx 1, 1, 0", # load fp 1 from mem location 0
58 "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA
59 "lfsu 2, 0(1)", # re-load from UPDATED r1
62 lst
= ["lfsx 1, 1, 0",
66 initial_mem
= {0x0000: (0x42013333, 8),
67 0x0008: (0x42026666, 8),
68 0x0020: (0x1828384822324252, 8),
71 with
Program(lst
, bigendian
=False) as program
:
72 sim
= self
.run_tst_program(program
, initial_mem
=initial_mem
)
73 print("FPR 1", sim
.fpr(1))
74 print("FPR 2", sim
.fpr(2))
75 print("GPR 1", sim
.gpr(1)) # should be 0x10 due to update
76 self
.assertEqual(sim
.gpr(1), SelectableInt(0x10, 64))
77 self
.assertEqual(sim
.fpr(1), SelectableInt(0x4040266660000000, 64))
78 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
81 """>>> lst = ["fmr 1, 2",
88 fprs
[2] = 0x4040266660000000
90 with
Program(lst
, bigendian
=False) as program
:
91 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
92 print("FPR 1", sim
.fpr(1))
93 print("FPR 2", sim
.fpr(2))
94 self
.assertEqual(sim
.fpr(1), SelectableInt(0x4040266660000000, 64))
95 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
97 def test_fp_neg(self
):
98 """>>> lst = ["fneg 1, 2",
105 fprs
[2] = 0x4040266660000000
107 with
Program(lst
, bigendian
=False) as program
:
108 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
109 print("FPR 1", sim
.fpr(1))
110 print("FPR 2", sim
.fpr(2))
111 self
.assertEqual(sim
.fpr(1), SelectableInt(0xC040266660000000, 64))
112 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
114 def test_fp_abs(self
):
115 """>>> lst = ["fabs 3, 1",
128 fprs
[1] = 0xC040266660000000
129 fprs
[2] = 0x4040266660000000
131 with
Program(lst
, bigendian
=False) as program
:
132 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
133 self
.assertEqual(sim
.fpr(1), SelectableInt(0xC040266660000000, 64))
134 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
135 self
.assertEqual(sim
.fpr(3), SelectableInt(0x4040266660000000, 64))
136 self
.assertEqual(sim
.fpr(4), SelectableInt(0x4040266660000000, 64))
137 self
.assertEqual(sim
.fpr(5), SelectableInt(0xC040266660000000, 64))
138 self
.assertEqual(sim
.fpr(6), SelectableInt(0xC040266660000000, 64))
140 def test_fp_sgn(self
):
141 """>>> lst = ["fcpsgn 3, 1, 2",
145 lst
= ["fcpsgn 3, 1, 2",
150 fprs
[1] = 0xC040266660000001 # 1 in LSB, 1 in MSB
151 fprs
[2] = 0x4040266660000000 # 0 in LSB, 0 in MSB
153 with
Program(lst
, bigendian
=False) as program
:
154 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
155 self
.assertEqual(sim
.fpr(1), SelectableInt(0xC040266660000001, 64))
156 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
157 # 1 in MSB comes from reg 1, 0 in LSB comes from reg 2
158 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC040266660000000, 64))
159 # 0 in MSB comes from reg 2, 1 in LSB comes from reg 1
160 self
.assertEqual(sim
.fpr(4), SelectableInt(0x4040266660000001, 64))
162 def test_fp_adds(self
):
163 """>>> lst = ["fadds 3, 1, 2",
166 lst
= ["fadds 3, 1, 2", # -32.3 + 32.3 = 0
170 fprs
[1] = 0xC040266660000000
171 fprs
[2] = 0x4040266660000000
173 with
Program(lst
, bigendian
=False) as program
:
174 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
175 self
.assertEqual(sim
.fpr(1), SelectableInt(0xC040266660000000, 64))
176 self
.assertEqual(sim
.fpr(2), SelectableInt(0x4040266660000000, 64))
177 self
.assertEqual(sim
.fpr(3), SelectableInt(0, 64))
179 def test_fp_add(self
):
180 """>>> lst = ["fadd 3, 1, 2",
183 lst
= ["fadd 3, 1, 2", # 7.0 + -9.8 = -2.8
187 fprs
[1] = 0x401C000000000000 # 7.0
188 fprs
[2] = 0xC02399999999999A # -9.8
190 with
Program(lst
, bigendian
=False) as program
:
191 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
192 self
.assertEqual(sim
.fpr(1), SelectableInt(0x401C000000000000, 64))
193 self
.assertEqual(sim
.fpr(2), SelectableInt(0xC02399999999999A, 64))
194 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC006666666666668, 64))
196 def test_fp_muls(self
):
197 """>>> lst = ["fmuls 3, 1, 2",
200 lst
= ["fmuls 3, 1, 2", # 7.0 * -9.8 = -68.6
201 "fmuls 29,12,8", # test
205 fprs
[1] = 0x401C000000000000 # 7.0
206 fprs
[2] = 0xC02399999999999A # -9.8
208 with
Program(lst
, bigendian
=False) as program
:
209 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
210 self
.assertEqual(sim
.fpr(1), SelectableInt(0x401C000000000000, 64))
211 self
.assertEqual(sim
.fpr(2), SelectableInt(0xC02399999999999A, 64))
212 self
.assertEqual(sim
.fpr(3), SelectableInt(0xc051266640000000, 64))
214 def test_fp_muls2(self
):
215 """>>> lst = ["fmuls 3, 1, 2",
218 lst
= ["fmuls 3, 1, 2", #
222 fprs
[1] = 0xbfc4e9d700000000
223 fprs
[2] = 0xbdc5000000000000
225 with
Program(lst
, bigendian
=False) as program
:
226 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
227 self
.assertEqual(sim
.fpr(3), SelectableInt(0x3d9b72ea40000000, 64))
229 def test_fp_mul(self
):
230 """>>> lst = ["fmul 3, 1, 2",
233 lst
= ["fmul 3, 1, 2", # 7.0 * -9.8 = -68.6
237 fprs
[1] = 0x401C000000000000 # 7.0
238 fprs
[2] = 0xC02399999999999A # -9.8
240 with
Program(lst
, bigendian
=False) as program
:
241 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
242 self
.assertEqual(sim
.fpr(1), SelectableInt(0x401C000000000000, 64))
243 self
.assertEqual(sim
.fpr(2), SelectableInt(0xC02399999999999A, 64))
244 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC051266666666667, 64))
246 def test_fp_fcfids(self
):
247 """>>> lst = ["fcfids 1, 2",
248 lst = ["fcfids 3, 4",
251 lst
= ["fcfids 1, 2",
259 with
Program(lst
, bigendian
=False) as program
:
260 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
261 self
.assertEqual(sim
.fpr(1), SelectableInt(0x401C000000000000, 64))
262 self
.assertEqual(sim
.fpr(2), SelectableInt(7, 64))
263 self
.assertEqual(sim
.fpr(3), SelectableInt(0xC040000000000000, 64))
264 self
.assertEqual(sim
.fpr(4), SelectableInt(-32, 64))
266 def run_tst_program(self
, prog
, initial_regs
=None,
269 if initial_regs
is None:
270 initial_regs
= [0] * 32
271 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
272 initial_fprs
=initial_fprs
)
280 if __name__
== "__main__":