6912707cc887988656ead4f2316c68d0fdfd20c1
1 """SVP64 unit test for svindex
2 svindex SVG,rmm,SVd,ew,yx,mr,sk
4 from nmigen
import Module
, Signal
5 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
6 from nmutil
.formaltest
import FHDLTestCase
8 from openpower
.decoder
.isa
.caller
import ISACaller
9 from openpower
.decoder
.power_decoder
import (create_pdecode
)
10 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
11 from openpower
.simulator
.program
import Program
12 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
, CRFields
13 from openpower
.decoder
.selectable_int
import SelectableInt
14 from openpower
.decoder
.orderedset
import OrderedSet
15 from openpower
.decoder
.isa
.all
import ISA
16 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
17 from openpower
.sv
.trans
.svp64
import SVP64Asm
18 from openpower
.consts
import SVP64CROffs
19 from copy
import deepcopy
22 class SVSTATETestCase(FHDLTestCase
):
24 def _check_regs(self
, sim
, expected
):
28 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64),
29 "GPR %d %x expected %x" % (i
, sim
.gpr(i
).value
, expected
[i
]))
31 def test_0_sv_index(self
):
32 """sets VL=10 (via SVSTATE) then does svindex, checks SPRs after
34 isa
= SVP64Asm(['svindex 1, 15, 5, 0, 0, 0, 0'
37 print ("listing", lst
)
39 # initial values in GPR regfile
40 initial_regs
= [0] * 32
41 initial_regs
[9] = 0x1234
42 initial_regs
[10] = 0x1111
43 initial_regs
[5] = 0x4321
44 initial_regs
[6] = 0x2223
47 svstate
= SVP64State()
49 svstate
.maxvl
= 10 # MAXVL
50 print ("SVSTATE", bin(svstate
.asint()))
53 expected_regs
= deepcopy(initial_regs
)
54 #expected_regs[1] = 0x3334
56 with
Program(lst
, bigendian
=False) as program
:
57 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
58 self
._check
_regs
(sim
, expected_regs
)
61 SVSHAPE0
= sim
.spr
['SVSHAPE0']
62 print ("SVSTATE after", bin(sim
.svstate
.asint()))
63 print (" vl", bin(sim
.svstate
.vl
))
64 print (" mvl", bin(sim
.svstate
.maxvl
))
65 print (" srcstep", bin(sim
.svstate
.srcstep
))
66 print (" dststep", bin(sim
.svstate
.dststep
))
67 print (" RMpst", bin(sim
.svstate
.RMpst
))
68 print (" SVme", bin(sim
.svstate
.SVme
))
69 print (" mo0", bin(sim
.svstate
.mo0
))
70 print (" mo1", bin(sim
.svstate
.mo1
))
71 print (" mi0", bin(sim
.svstate
.mi0
))
72 print (" mi1", bin(sim
.svstate
.mi1
))
73 print (" mi2", bin(sim
.svstate
.mi2
))
74 print ("STATE0svgpr", hex(SVSHAPE0
.svgpr
))
75 print ("STATE0 xdim", SVSHAPE0
.xdimsz
)
76 print ("STATE0 ydim", SVSHAPE0
.ydimsz
)
77 print ("STATE0 skip", bin(SVSHAPE0
.skip
))
78 print ("STATE0 inv", SVSHAPE0
.invxyz
)
79 print ("STATE0order", SVSHAPE0
.order
)
80 self
.assertEqual(sim
.svstate
.RMpst
, 0) # mm=0 so persist=0
81 self
.assertEqual(sim
.svstate
.SVme
, 0b01111) # same as rmm
82 # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
83 self
.assertEqual(sim
.svstate
.mi0
, 0)
84 self
.assertEqual(sim
.svstate
.mi1
, 1)
85 self
.assertEqual(sim
.svstate
.mi2
, 2)
86 self
.assertEqual(sim
.svstate
.mo0
, 3)
87 self
.assertEqual(sim
.svstate
.mo1
, 0)
89 shape
= sim
.spr
['SVSHAPE%d' % i
]
90 self
.assertEqual(shape
.svgpr
, 2) # SVG is shifted up by 1
92 def test_0_sv_index_add(self
):
93 """sets VL=6 (via SVSTATE) then does svindex, and an add.
95 only RA is re-mapped via Indexing, not RB or RT
97 isa
= SVP64Asm(['svindex 8, 1, 6, 0, 0, 0, 0',
101 print ("listing", lst
)
103 # initial values in GPR regfile
104 initial_regs
= [0] * 32
105 idxs
= [1, 0, 5, 2, 4, 3] # random enough
107 initial_regs
[16+i
] = idxs
[i
]
111 svstate
= SVP64State()
113 svstate
.maxvl
= 6 # MAXVL
114 print ("SVSTATE", bin(svstate
.asint()))
116 # copy before running
117 expected_regs
= deepcopy(initial_regs
)
119 RA
= initial_regs
[0+idxs
[i
]]
120 RB
= initial_regs
[0+i
]
121 expected_regs
[i
+8] = RA
+RB
122 print ("expected", i
, expected_regs
[i
+8])
124 with
Program(lst
, bigendian
=False) as program
:
125 sim
= self
.run_tst_program(program
, initial_regs
, svstate
=svstate
)
126 self
._check
_regs
(sim
, expected_regs
)
129 SVSHAPE0
= sim
.spr
['SVSHAPE0']
130 print ("SVSTATE after", bin(sim
.svstate
.asint()))
131 print (" vl", bin(sim
.svstate
.vl
))
132 print (" mvl", bin(sim
.svstate
.maxvl
))
133 print (" srcstep", bin(sim
.svstate
.srcstep
))
134 print (" dststep", bin(sim
.svstate
.dststep
))
135 print (" RMpst", bin(sim
.svstate
.RMpst
))
136 print (" SVme", bin(sim
.svstate
.SVme
))
137 print (" mo0", bin(sim
.svstate
.mo0
))
138 print (" mo1", bin(sim
.svstate
.mo1
))
139 print (" mi0", bin(sim
.svstate
.mi0
))
140 print (" mi1", bin(sim
.svstate
.mi1
))
141 print (" mi2", bin(sim
.svstate
.mi2
))
142 print ("STATE0svgpr", hex(SVSHAPE0
.svgpr
))
143 print (sim
.gpr
.dump())
144 self
.assertEqual(sim
.svstate
.RMpst
, 0) # mm=0 so persist=0
145 self
.assertEqual(sim
.svstate
.SVme
, 0b00001) # same as rmm
146 # rmm is 0b00001 which means mi0=0 and all others inactive (0)
147 self
.assertEqual(sim
.svstate
.mi0
, 0)
148 self
.assertEqual(sim
.svstate
.mi1
, 0)
149 self
.assertEqual(sim
.svstate
.mi2
, 0)
150 self
.assertEqual(sim
.svstate
.mo0
, 0)
151 self
.assertEqual(sim
.svstate
.mo1
, 0)
152 self
.assertEqual(SVSHAPE0
.svgpr
, 16) # SVG is shifted up by 1
154 shape
= sim
.spr
['SVSHAPE%d' % i
]
155 self
.assertEqual(shape
.svgpr
, 0)
157 def run_tst_program(self
, prog
, initial_regs
=None,
159 if initial_regs
is None:
160 initial_regs
= [0] * 32
161 simulator
= run_tst(prog
, initial_regs
, svstate
=svstate
)
166 if __name__
== "__main__":