src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py

   1 import unittest
   2 from copy import deepcopy
   3
   4 from nmutil.formaltest import FHDLTestCase
   5 from openpower.decoder.isa.caller import SVP64State
   6 from openpower.decoder.isa.test_caller import run_tst
   7 from openpower.decoder.selectable_int import SelectableInt
   8 from openpower.simulator.program import Program
   9 from openpower.sv.trans.svp64 import SVP64Asm
  10
  11
  12 class DecoderTestCase(FHDLTestCase):
  13
  14     def _check_regs(self, sim, expected):
  15         for i in range(32):
  16             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  17
  18     def test_sv_addi_ffirst_le(self):
  19         lst = SVP64Asm(["sv.subf./ff=le *0,8,*0"
  20                         ])
  21         lst = list(lst)
  22
  23         # SVSTATE
  24         svstate = SVP64State()
  25         svstate.vl = 4  # VL
  26         svstate.maxvl = 4  # MAXVL
  27         print("SVSTATE", bin(svstate.asint()))
  28
  29         gprs = [0] * 64
  30         gprs[8] = 3
  31         vec = [9, 8, 3, 4]
  32
  33         res = []
  34         # store GPRs
  35         for i, x in enumerate(vec):
  36             gprs[i] = x
  37
  38         with Program(lst, bigendian=False) as program:
  39             sim = self.run_tst_program(program, initial_regs=gprs,
  40                                        svstate=svstate)
  41             for i in range(4):
  42                 val = sim.gpr(i).value
  43                 res.append(val)
  44                 print("i", i, val)
  45             # confirm that the results are as expected
  46             expected = deepcopy(vec)
  47             expected_vl = 0
  48             for i in range(4):
  49                 result = expected[i] - gprs[8]
  50                 expected[i] = result
  51                 if result <= 0:
  52                     break
  53                 # only write out if successful
  54                 expected_vl += 1
  55             for i, v in enumerate(res):
  56                 self.assertEqual(v, expected[i])
  57
  58             self.assertEqual(sim.svstate.vl, expected_vl)
  59             self.assertEqual(sim.svstate.maxvl, 4)
  60             self.assertEqual(sim.svstate.srcstep, 0)
  61             self.assertEqual(sim.svstate.dststep, 0)
  62
  63     def test_sv_addi_ffirst(self):
  64         lst = SVP64Asm(["sv.subf./ff=eq *0,8,*0"
  65                         ])
  66         lst = list(lst)
  67
  68         # SVSTATE
  69         svstate = SVP64State()
  70         svstate.vl = 4  # VL
  71         svstate.maxvl = 4  # MAXVL
  72         print("SVSTATE", bin(svstate.asint()))
  73
  74         gprs = [0] * 64
  75         gprs[8] = 3
  76         vec = [9, 8, 3, 4]
  77
  78         res = []
  79         # store GPRs
  80         for i, x in enumerate(vec):
  81             gprs[i] = x
  82
  83         with Program(lst, bigendian=False) as program:
  84             sim = self.run_tst_program(program, initial_regs=gprs,
  85                                        svstate=svstate)
  86             for i in range(4):
  87                 val = sim.gpr(i).value
  88                 res.append(val)
  89                 print("i", i, val)
  90             # confirm that the results are as expected
  91             expected = deepcopy(vec)
  92             for i in range(4):
  93                 result = expected[i] - gprs[8]
  94                 expected[i] = result
  95                 if result == 0:
  96                     break
  97             for i, v in enumerate(res):
  98                 self.assertEqual(v, expected[i])
  99
 100             self.assertEqual(sim.svstate.vl, 2)
 101             self.assertEqual(sim.svstate.maxvl, 4)
 102             self.assertEqual(sim.svstate.srcstep, 0)
 103             self.assertEqual(sim.svstate.dststep, 0)
 104
 105     def test_sv_addi_ffirst_rc1(self):
 106         lst = SVP64Asm(["sv.subf/ff=RC1 *0,8,*0"  # RC1 auto-sets EQ (and Rc=1)
 107                         ])
 108         lst = list(lst)
 109
 110         # SVSTATE
 111         svstate = SVP64State()
 112         svstate.vl = 4  # VL
 113         svstate.maxvl = 4  # MAXVL
 114         print("SVSTATE", bin(svstate.asint()))
 115
 116         gprs = [0] * 64
 117         gprs[8] = 3
 118         vec = [9, 8, 3, 4]
 119
 120         res = []
 121         # store GPRs
 122         for i, x in enumerate(vec):
 123             gprs[i] = x
 124
 125         with Program(lst, bigendian=False) as program:
 126             sim = self.run_tst_program(program, initial_regs=gprs,
 127                                        svstate=svstate)
 128             for i in range(4):
 129                 val = sim.gpr(i).value
 130                 res.append(val)
 131                 print("i", i, val)
 132             # confirm that the results are as expected
 133             expected = deepcopy(vec)
 134             for i in range(4):
 135                 result = expected[i] - gprs[8]
 136                 expected[i] = result
 137                 if result == 0:
 138                     break
 139             for i, v in enumerate(res):
 140                 self.assertEqual(v, expected[i])
 141
 142             self.assertEqual(sim.svstate.vl, 2)
 143             self.assertEqual(sim.svstate.maxvl, 4)
 144             self.assertEqual(sim.svstate.srcstep, 0)
 145             self.assertEqual(sim.svstate.dststep, 0)
 146
 147     def test_sv_addi_ffirst_vli(self):
 148         lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
 149                         ])
 150         lst = list(lst)
 151
 152         # SVSTATE
 153         svstate = SVP64State()
 154         svstate.vl = 4  # VL
 155         svstate.maxvl = 4  # MAXVL
 156         print("SVSTATE", bin(svstate.asint()))
 157
 158         gprs = [0] * 64
 159         gprs[8] = 3
 160         vec = [9, 8, 3, 4]
 161
 162         res = []
 163         # store GPRs
 164         for i, x in enumerate(vec):
 165             gprs[i] = x
 166
 167         with Program(lst, bigendian=False) as program:
 168             sim = self.run_tst_program(program, initial_regs=gprs,
 169                                        svstate=svstate)
 170             for i in range(4):
 171                 val = sim.gpr(i).value
 172                 res.append(val)
 173                 print("i", i, val)
 174             # confirm that the results are as expected
 175             expected = deepcopy(vec)
 176             for i in range(4):
 177                 expected[i] -= gprs[8]
 178                 if expected[i] == 0:
 179                     break
 180             for i, v in enumerate(res):
 181                 self.assertEqual(v, expected[i])
 182
 183             self.assertEqual(sim.svstate.vl, 3)
 184             self.assertEqual(sim.svstate.maxvl, 4)
 185             self.assertEqual(sim.svstate.srcstep, 0)
 186             self.assertEqual(sim.svstate.dststep, 0)
 187
 188     def run_tst_program(self, prog, initial_regs=None,
 189                         svstate=None,
 190                         initial_mem=None,
 191                         initial_fprs=None):
 192         if initial_regs is None:
 193             initial_regs = [0] * 32
 194         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 195                             initial_fprs=initial_fprs,
 196                             svstate=svstate)
 197
 198         print("GPRs")
 199         simulator.gpr.dump()
 200         print("FPRs")
 201         simulator.fpr.dump()
 202
 203         return simulator
 204
 205
 206 if __name__ == "__main__":
 207     unittest.main()