src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17 from openpower.decoder.helpers import fp64toselectable
  18 from functools import reduce
  19 import operator
  20
  21
  22 class DecoderTestCase(FHDLTestCase):
  23
  24     def _check_regs(self, sim, expected):
  25         for i in range(32):
  26             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  27
  28     def test_sv_addi_ffirst_le(self):
  29         lst = SVP64Asm([ "sv.subf./ff=le *0,8,*0"
  30                         ])
  31         lst = list(lst)
  32
  33         # SVSTATE
  34         svstate = SVP64State()
  35         svstate.vl = 4 # VL
  36         svstate.maxvl = 4 # MAXVL
  37         print ("SVSTATE", bin(svstate.asint()))
  38
  39         gprs = [0] * 64
  40         gprs[8] = 3
  41         vec = [9, 8, 3, 4]
  42
  43         res = []
  44         # store GPRs
  45         for i, x in enumerate(vec):
  46             gprs[i] = x
  47
  48         with Program(lst, bigendian=False) as program:
  49             sim = self.run_tst_program(program, initial_regs=gprs,
  50                                                 svstate=svstate)
  51             for i in range(4):
  52                 val = sim.gpr(i).value
  53                 res.append(val)
  54                 print ("i", i, val)
  55             # confirm that the results are as expected
  56             expected = deepcopy(vec)
  57             expected_vl = 0
  58             for i in range(4):
  59                 result = expected[i] - gprs[8]
  60                 expected[i] = result
  61                 if result <= 0:
  62                     break
  63                 # only write out if successful
  64                 expected_vl += 1
  65             for i, v in enumerate(res):
  66                 self.assertEqual(v, expected[i])
  67
  68             self.assertEqual(sim.svstate.vl, expected_vl)
  69             self.assertEqual(sim.svstate.maxvl, 4)
  70             self.assertEqual(sim.svstate.srcstep, 0)
  71             self.assertEqual(sim.svstate.dststep, 0)
  72
  73     def test_sv_addi_ffirst(self):
  74         lst = SVP64Asm([ "sv.subf./ff=eq *0,8,*0"
  75                         ])
  76         lst = list(lst)
  77
  78         # SVSTATE
  79         svstate = SVP64State()
  80         svstate.vl = 4 # VL
  81         svstate.maxvl = 4 # MAXVL
  82         print ("SVSTATE", bin(svstate.asint()))
  83
  84         gprs = [0] * 64
  85         gprs[8] = 3
  86         vec = [9, 8, 3, 4]
  87
  88         res = []
  89         # store GPRs
  90         for i, x in enumerate(vec):
  91             gprs[i] = x
  92
  93         with Program(lst, bigendian=False) as program:
  94             sim = self.run_tst_program(program, initial_regs=gprs,
  95                                                 svstate=svstate)
  96             for i in range(4):
  97                 val = sim.gpr(i).value
  98                 res.append(val)
  99                 print ("i", i, val)
 100             # confirm that the results are as expected
 101             expected = deepcopy(vec)
 102             for i in range(4):
 103                 result = expected[i] - gprs[8]
 104                 expected[i] = result
 105                 if result == 0:
 106                     break
 107             for i, v in enumerate(res):
 108                 self.assertEqual(v, expected[i])
 109
 110             self.assertEqual(sim.svstate.vl, 2)
 111             self.assertEqual(sim.svstate.maxvl, 4)
 112             self.assertEqual(sim.svstate.srcstep, 0)
 113             self.assertEqual(sim.svstate.dststep, 0)
 114
 115     def test_sv_addi_ffirst_rc1(self):
 116         lst = SVP64Asm([ "sv.subf/ff=RC1 *0,8,*0" # RC1 auto-sets EQ (and Rc=1)
 117                         ])
 118         lst = list(lst)
 119
 120         # SVSTATE
 121         svstate = SVP64State()
 122         svstate.vl = 4 # VL
 123         svstate.maxvl = 4 # MAXVL
 124         print ("SVSTATE", bin(svstate.asint()))
 125
 126         gprs = [0] * 64
 127         gprs[8] = 3
 128         vec = [9, 8, 3, 4]
 129
 130         res = []
 131         # store GPRs
 132         for i, x in enumerate(vec):
 133             gprs[i] = x
 134
 135         with Program(lst, bigendian=False) as program:
 136             sim = self.run_tst_program(program, initial_regs=gprs,
 137                                                 svstate=svstate)
 138             for i in range(4):
 139                 val = sim.gpr(i).value
 140                 res.append(val)
 141                 print ("i", i, val)
 142             # confirm that the results are as expected
 143             expected = deepcopy(vec)
 144             for i in range(4):
 145                 result = expected[i] - gprs[8]
 146                 expected[i] = result
 147                 if result == 0:
 148                     break
 149             for i, v in enumerate(res):
 150                 self.assertEqual(v, expected[i])
 151
 152             self.assertEqual(sim.svstate.vl, 2)
 153             self.assertEqual(sim.svstate.maxvl, 4)
 154             self.assertEqual(sim.svstate.srcstep, 0)
 155             self.assertEqual(sim.svstate.dststep, 0)
 156
 157     def test_sv_addi_ffirst_vli(self):
 158         lst = SVP64Asm([ "sv.subf/ff=RC1/vli *0,8,*0"
 159                         ])
 160         lst = list(lst)
 161
 162         # SVSTATE
 163         svstate = SVP64State()
 164         svstate.vl = 4 # VL
 165         svstate.maxvl = 4 # MAXVL
 166         print ("SVSTATE", bin(svstate.asint()))
 167
 168         gprs = [0] * 64
 169         gprs[8] = 3
 170         vec = [9, 8, 3, 4]
 171
 172         res = []
 173         # store GPRs
 174         for i, x in enumerate(vec):
 175             gprs[i] = x
 176
 177         with Program(lst, bigendian=False) as program:
 178             sim = self.run_tst_program(program, initial_regs=gprs,
 179                                                 svstate=svstate)
 180             for i in range(4):
 181                 val = sim.gpr(i).value
 182                 res.append(val)
 183                 print ("i", i, val)
 184             # confirm that the results are as expected
 185             expected = deepcopy(vec)
 186             for i in range(4):
 187                 expected[i] -= gprs[8]
 188                 if expected[i] == 0:
 189                     break
 190             for i, v in enumerate(res):
 191                 self.assertEqual(v, expected[i])
 192
 193             self.assertEqual(sim.svstate.vl, 3)
 194             self.assertEqual(sim.svstate.maxvl, 4)
 195             self.assertEqual(sim.svstate.srcstep, 0)
 196             self.assertEqual(sim.svstate.dststep, 0)
 197
 198     def run_tst_program(self, prog, initial_regs=None,
 199                               svstate=None,
 200                               initial_mem=None,
 201                               initial_fprs=None):
 202         if initial_regs is None:
 203             initial_regs = [0] * 32
 204         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 205                                                 initial_fprs=initial_fprs,
 206                                                 svstate=svstate)
 207
 208         print ("GPRs")
 209         simulator.gpr.dump()
 210         print ("FPRs")
 211         simulator.fpr.dump()
 212
 213         return simulator
 214
 215
 216 if __name__ == "__main__":
 217     unittest.main()