fa784c45ccacd60ecf4916e386dfe68ccb437a44
2 from copy
import deepcopy
4 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import SVP64State
6 from openpower
.decoder
.isa
.test_caller
import run_tst
7 from openpower
.decoder
.selectable_int
import SelectableInt
8 from openpower
.simulator
.program
import Program
9 from openpower
.insndb
.asm
import SVP64Asm
10 from openpower
.util
import log
15 return "<lt %d gt %d eq %d>" % (self
.lt
, self
.gt
, self
.eq
)
23 # example sv.cmpi/ff=lt 0, 1, *10, 5
24 # see https://bugs.libre-soc.org/show_bug.cgi?id=1183#c3
25 def sv_cmpi(gpr
, CR
, vl
, ra
, si
):
28 CR
[i
] = cmpd(gpr
[ra
+ i
], si
)
35 class DDFFirstTestCase(FHDLTestCase
):
37 def _check_regs(self
, sim
, expected
):
39 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
42 lst
= SVP64Asm(["sv.cmpi/ff=lt 0, 1, *10, 5"
47 svstate
= SVP64State()
50 svstate
.maxvl
= vl
# MAXVL
51 print("SVSTATE", bin(svstate
.asint()))
61 newvl
= sv_cmpi(gprs
, cr_res
, vl
, 10, 5)
62 log("sv_cmpi", newvl
, cr_res
)
64 with
Program(lst
, bigendian
=False) as program
:
65 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
68 val
= sim
.gpr(i
).value
72 # confirm that the results are as expected
73 expected
= deepcopy(vec
)
76 # calculate expected result and expected CR field
77 result
= vec
[i
] - gprs
[8]
78 crf
= ((result
==0)<<1) |
((result
> 0)<<2) |
((result
< 0) << 3)
82 # VLi=0 - test comes FIRST!
84 # only write out if successful
87 for i
, v
in enumerate(cr_res
):
88 crf
= sim
.crl
[i
].get_range().value
89 print ("crf", i
, res
[i
], bin(crf
), bin(v
))
90 self
.assertEqual(crf
, v
)
92 for i
, v
in enumerate(res
):
93 self
.assertEqual(v
, expected
[i
])
95 self
.assertEqual(sim
.svstate
.vl
, expected_vl
)
96 self
.assertEqual(sim
.svstate
.maxvl
, 4)
97 self
.assertEqual(sim
.svstate
.srcstep
, 0)
98 self
.assertEqual(sim
.svstate
.dststep
, 0)
100 def test_sv_addi_ffirst_le(self
):
101 lst
= SVP64Asm(["sv.subf./ff=le *0,8,*0"
106 svstate
= SVP64State()
108 svstate
.maxvl
= 4 # MAXVL
109 print("SVSTATE", bin(svstate
.asint()))
118 for i
, x
in enumerate(vec
):
121 with
Program(lst
, bigendian
=False) as program
:
122 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
125 val
= sim
.gpr(i
).value
129 # confirm that the results are as expected
130 expected
= deepcopy(vec
)
133 # calculate expected result and expected CR field
134 result
= vec
[i
] - gprs
[8]
135 crf
= ((result
==0)<<1) |
((result
> 0)<<2) |
((result
< 0) << 3)
139 # VLi=0 - test comes FIRST!
141 # only write out if successful
144 for i
, v
in enumerate(cr_res
):
145 crf
= sim
.crl
[i
].get_range().value
146 print ("crf", i
, res
[i
], bin(crf
), bin(v
))
147 self
.assertEqual(crf
, v
)
149 for i
, v
in enumerate(res
):
150 self
.assertEqual(v
, expected
[i
])
152 self
.assertEqual(sim
.svstate
.vl
, expected_vl
)
153 self
.assertEqual(sim
.svstate
.maxvl
, 4)
154 self
.assertEqual(sim
.svstate
.srcstep
, 0)
155 self
.assertEqual(sim
.svstate
.dststep
, 0)
157 def test_sv_addi_ffirst(self
):
158 lst
= SVP64Asm(["sv.subf./ff=eq *0,8,*0"
163 svstate
= SVP64State()
165 svstate
.maxvl
= 4 # MAXVL
166 print("SVSTATE", bin(svstate
.asint()))
175 for i
, x
in enumerate(vec
):
178 with
Program(lst
, bigendian
=False) as program
:
179 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
182 val
= sim
.gpr(i
).value
186 # confirm that the results are as expected
187 expected
= deepcopy(vec
)
189 result
= vec
[i
] - gprs
[8]
190 crf
= ((result
==0)<<1) |
((result
> 0)<<2) |
((result
< 0) << 3)
194 # VLi=0 - test comes FIRST!
196 for i
, v
in enumerate(cr_res
):
197 crf
= sim
.crl
[i
].get_range().value
198 print ("crf", i
, res
[i
], bin(crf
), bin(v
))
199 self
.assertEqual(crf
, v
)
201 for i
, v
in enumerate(res
):
202 self
.assertEqual(v
, expected
[i
])
204 self
.assertEqual(sim
.svstate
.vl
, 2)
205 self
.assertEqual(sim
.svstate
.maxvl
, 4)
206 self
.assertEqual(sim
.svstate
.srcstep
, 0)
207 self
.assertEqual(sim
.svstate
.dststep
, 0)
209 def test_sv_addi_ffirst_rc1(self
):
210 lst
= SVP64Asm(["sv.subf/ff=RC1 *0,8,*0" # RC1 auto-sets EQ (and Rc=1)
215 svstate
= SVP64State()
217 svstate
.maxvl
= 4 # MAXVL
218 print("SVSTATE", bin(svstate
.asint()))
226 for i
, x
in enumerate(vec
):
229 with
Program(lst
, bigendian
=False) as program
:
230 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
233 val
= sim
.gpr(i
).value
236 # confirm that the results are as expected
237 expected
= deepcopy(vec
)
239 result
= expected
[i
] - gprs
[8]
242 # VLi=0 - test comes FIRST!
244 for i
, v
in enumerate(res
):
245 self
.assertEqual(v
, expected
[i
])
247 self
.assertEqual(sim
.svstate
.vl
, 2)
248 self
.assertEqual(sim
.svstate
.maxvl
, 4)
249 self
.assertEqual(sim
.svstate
.srcstep
, 0)
250 self
.assertEqual(sim
.svstate
.dststep
, 0)
252 def test_sv_addi_ffirst_vli(self
):
253 """data-dependent fail-first with VLi=1, the test comes *after* write
255 lst
= SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
260 svstate
= SVP64State()
262 svstate
.maxvl
= 4 # MAXVL
263 print("SVSTATE", bin(svstate
.asint()))
271 for i
, x
in enumerate(vec
):
274 with
Program(lst
, bigendian
=False) as program
:
275 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
278 val
= sim
.gpr(i
).value
281 # confirm that the results are as expected
282 expected
= deepcopy(vec
)
284 # VLi=1 - test comes AFTER write!
285 expected
[i
] -= gprs
[8]
288 for i
, v
in enumerate(res
):
289 self
.assertEqual(v
, expected
[i
])
291 self
.assertEqual(sim
.svstate
.vl
, 3)
292 self
.assertEqual(sim
.svstate
.maxvl
, 4)
293 self
.assertEqual(sim
.svstate
.srcstep
, 0)
294 self
.assertEqual(sim
.svstate
.dststep
, 0)
296 def run_tst_program(self
, prog
, initial_regs
=None,
300 if initial_regs
is None:
301 initial_regs
= [0] * 32
302 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
303 initial_fprs
=initial_fprs
,
314 if __name__
== "__main__":