fa784c45ccacd60ecf4916e386dfe68ccb437a44
[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_dd_ffirst.py
1 import unittest
2 from copy import deepcopy
3
4 from nmutil.formaltest import FHDLTestCase
5 from openpower.decoder.isa.caller import SVP64State
6 from openpower.decoder.isa.test_caller import run_tst
7 from openpower.decoder.selectable_int import SelectableInt
8 from openpower.simulator.program import Program
9 from openpower.insndb.asm import SVP64Asm
10 from openpower.util import log
11
12 def cmpd(x, y):
13 class CRfield:
14 def __repr__(self):
15 return "<lt %d gt %d eq %d>" % (self.lt, self.gt, self.eq)
16 CRf = CRfield()
17 CRf.lt = x < y
18 CRf.gt = x > y
19 CRf.eq = x == y
20 return CRf
21
22
23 # example sv.cmpi/ff=lt 0, 1, *10, 5
24 # see https://bugs.libre-soc.org/show_bug.cgi?id=1183#c3
25 def sv_cmpi(gpr, CR, vl, ra, si):
26 i = 0
27 while i < vl:
28 CR[i] = cmpd(gpr[ra + i], si)
29 if CR[i].lt:
30 break
31 i += 1
32 return i # new VL
33
34
35 class DDFFirstTestCase(FHDLTestCase):
36
37 def _check_regs(self, sim, expected):
38 for i in range(32):
39 self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
40
41 def test_1(self):
42 lst = SVP64Asm(["sv.cmpi/ff=lt 0, 1, *10, 5"
43 ])
44 lst = list(lst)
45
46 # SVSTATE
47 svstate = SVP64State()
48 vl = 3 # VL
49 svstate.vl = vl # VL
50 svstate.maxvl = vl # MAXVL
51 print("SVSTATE", bin(svstate.asint()))
52
53 gprs = [0] * 32
54 gprs[10] = 4
55 gprs[11] = 5
56 gprs[12] = 12
57
58 res = []
59 cr_res = [0]*8
60
61 newvl = sv_cmpi(gprs, cr_res, vl, 10, 5)
62 log("sv_cmpi", newvl, cr_res)
63
64 with Program(lst, bigendian=False) as program:
65 sim = self.run_tst_program(program, initial_regs=gprs,
66 svstate=svstate)
67 for i in range(4):
68 val = sim.gpr(i).value
69 res.append(val)
70 cr_res.append(0)
71 print("i", i, val)
72 # confirm that the results are as expected
73 expected = deepcopy(vec)
74 expected_vl = 0
75 for i in range(4):
76 # calculate expected result and expected CR field
77 result = vec[i] - gprs[8]
78 crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
79 cr_res[i] = crf
80 if result <= 0:
81 break
82 # VLi=0 - test comes FIRST!
83 expected[i] = result
84 # only write out if successful
85 expected_vl += 1
86
87 for i, v in enumerate(cr_res):
88 crf = sim.crl[i].get_range().value
89 print ("crf", i, res[i], bin(crf), bin(v))
90 self.assertEqual(crf, v)
91
92 for i, v in enumerate(res):
93 self.assertEqual(v, expected[i])
94
95 self.assertEqual(sim.svstate.vl, expected_vl)
96 self.assertEqual(sim.svstate.maxvl, 4)
97 self.assertEqual(sim.svstate.srcstep, 0)
98 self.assertEqual(sim.svstate.dststep, 0)
99
100 def test_sv_addi_ffirst_le(self):
101 lst = SVP64Asm(["sv.subf./ff=le *0,8,*0"
102 ])
103 lst = list(lst)
104
105 # SVSTATE
106 svstate = SVP64State()
107 svstate.vl = 4 # VL
108 svstate.maxvl = 4 # MAXVL
109 print("SVSTATE", bin(svstate.asint()))
110
111 gprs = [0] * 64
112 gprs[8] = 3
113 vec = [9, 8, 3, 4]
114
115 res = []
116 cr_res = []
117 # store GPRs
118 for i, x in enumerate(vec):
119 gprs[i] = x
120
121 with Program(lst, bigendian=False) as program:
122 sim = self.run_tst_program(program, initial_regs=gprs,
123 svstate=svstate)
124 for i in range(4):
125 val = sim.gpr(i).value
126 res.append(val)
127 cr_res.append(0)
128 print("i", i, val)
129 # confirm that the results are as expected
130 expected = deepcopy(vec)
131 expected_vl = 0
132 for i in range(4):
133 # calculate expected result and expected CR field
134 result = vec[i] - gprs[8]
135 crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
136 cr_res[i] = crf
137 if result <= 0:
138 break
139 # VLi=0 - test comes FIRST!
140 expected[i] = result
141 # only write out if successful
142 expected_vl += 1
143
144 for i, v in enumerate(cr_res):
145 crf = sim.crl[i].get_range().value
146 print ("crf", i, res[i], bin(crf), bin(v))
147 self.assertEqual(crf, v)
148
149 for i, v in enumerate(res):
150 self.assertEqual(v, expected[i])
151
152 self.assertEqual(sim.svstate.vl, expected_vl)
153 self.assertEqual(sim.svstate.maxvl, 4)
154 self.assertEqual(sim.svstate.srcstep, 0)
155 self.assertEqual(sim.svstate.dststep, 0)
156
157 def test_sv_addi_ffirst(self):
158 lst = SVP64Asm(["sv.subf./ff=eq *0,8,*0"
159 ])
160 lst = list(lst)
161
162 # SVSTATE
163 svstate = SVP64State()
164 svstate.vl = 4 # VL
165 svstate.maxvl = 4 # MAXVL
166 print("SVSTATE", bin(svstate.asint()))
167
168 gprs = [0] * 64
169 gprs[8] = 3
170 vec = [9, 8, 3, 4]
171
172 res = []
173 cr_res = []
174 # store GPRs
175 for i, x in enumerate(vec):
176 gprs[i] = x
177
178 with Program(lst, bigendian=False) as program:
179 sim = self.run_tst_program(program, initial_regs=gprs,
180 svstate=svstate)
181 for i in range(4):
182 val = sim.gpr(i).value
183 res.append(val)
184 cr_res.append(0)
185 print("i", i, val)
186 # confirm that the results are as expected
187 expected = deepcopy(vec)
188 for i in range(4):
189 result = vec[i] - gprs[8]
190 crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
191 cr_res[i] = crf
192 if result == 0:
193 break
194 # VLi=0 - test comes FIRST!
195 expected[i] = result
196 for i, v in enumerate(cr_res):
197 crf = sim.crl[i].get_range().value
198 print ("crf", i, res[i], bin(crf), bin(v))
199 self.assertEqual(crf, v)
200
201 for i, v in enumerate(res):
202 self.assertEqual(v, expected[i])
203
204 self.assertEqual(sim.svstate.vl, 2)
205 self.assertEqual(sim.svstate.maxvl, 4)
206 self.assertEqual(sim.svstate.srcstep, 0)
207 self.assertEqual(sim.svstate.dststep, 0)
208
209 def test_sv_addi_ffirst_rc1(self):
210 lst = SVP64Asm(["sv.subf/ff=RC1 *0,8,*0" # RC1 auto-sets EQ (and Rc=1)
211 ])
212 lst = list(lst)
213
214 # SVSTATE
215 svstate = SVP64State()
216 svstate.vl = 4 # VL
217 svstate.maxvl = 4 # MAXVL
218 print("SVSTATE", bin(svstate.asint()))
219
220 gprs = [0] * 64
221 gprs[8] = 3
222 vec = [9, 8, 3, 4]
223
224 res = []
225 # store GPRs
226 for i, x in enumerate(vec):
227 gprs[i] = x
228
229 with Program(lst, bigendian=False) as program:
230 sim = self.run_tst_program(program, initial_regs=gprs,
231 svstate=svstate)
232 for i in range(4):
233 val = sim.gpr(i).value
234 res.append(val)
235 print("i", i, val)
236 # confirm that the results are as expected
237 expected = deepcopy(vec)
238 for i in range(4):
239 result = expected[i] - gprs[8]
240 if result == 0:
241 break
242 # VLi=0 - test comes FIRST!
243 expected[i] = result
244 for i, v in enumerate(res):
245 self.assertEqual(v, expected[i])
246
247 self.assertEqual(sim.svstate.vl, 2)
248 self.assertEqual(sim.svstate.maxvl, 4)
249 self.assertEqual(sim.svstate.srcstep, 0)
250 self.assertEqual(sim.svstate.dststep, 0)
251
252 def test_sv_addi_ffirst_vli(self):
253 """data-dependent fail-first with VLi=1, the test comes *after* write
254 """
255 lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
256 ])
257 lst = list(lst)
258
259 # SVSTATE
260 svstate = SVP64State()
261 svstate.vl = 4 # VL
262 svstate.maxvl = 4 # MAXVL
263 print("SVSTATE", bin(svstate.asint()))
264
265 gprs = [0] * 64
266 gprs[8] = 3
267 vec = [9, 8, 3, 4]
268
269 res = []
270 # store GPRs
271 for i, x in enumerate(vec):
272 gprs[i] = x
273
274 with Program(lst, bigendian=False) as program:
275 sim = self.run_tst_program(program, initial_regs=gprs,
276 svstate=svstate)
277 for i in range(4):
278 val = sim.gpr(i).value
279 res.append(val)
280 print("i", i, val)
281 # confirm that the results are as expected
282 expected = deepcopy(vec)
283 for i in range(4):
284 # VLi=1 - test comes AFTER write!
285 expected[i] -= gprs[8]
286 if expected[i] == 0:
287 break
288 for i, v in enumerate(res):
289 self.assertEqual(v, expected[i])
290
291 self.assertEqual(sim.svstate.vl, 3)
292 self.assertEqual(sim.svstate.maxvl, 4)
293 self.assertEqual(sim.svstate.srcstep, 0)
294 self.assertEqual(sim.svstate.dststep, 0)
295
296 def run_tst_program(self, prog, initial_regs=None,
297 svstate=None,
298 initial_mem=None,
299 initial_fprs=None):
300 if initial_regs is None:
301 initial_regs = [0] * 32
302 simulator = run_tst(prog, initial_regs, mem=initial_mem,
303 initial_fprs=initial_fprs,
304 svstate=svstate)
305
306 print("GPRs")
307 simulator.gpr.dump()
308 print("FPRs")
309 simulator.fpr.dump()
310
311 return simulator
312
313
314 if __name__ == "__main__":
315 unittest.main()