d54a59c94a295cd3c71da92d3678d7b242ddedb0
1 from nmigen
import Module
, Signal
2 from nmigen
.sim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.isa
.caller
import ISACaller
6 from openpower
.decoder
.power_decoder
import (create_pdecode
)
7 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
8 from openpower
.simulator
.program
import Program
9 from openpower
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from openpower
.decoder
.selectable_int
import SelectableInt
11 from openpower
.decoder
.orderedset
import OrderedSet
12 from openpower
.decoder
.isa
.all
import ISA
13 from openpower
.decoder
.isa
.test_caller
import Register
, run_tst
14 from openpower
.sv
.trans
.svp64
import SVP64Asm
15 from openpower
.consts
import SVP64CROffs
16 from copy
import deepcopy
17 from openpower
.decoder
.helpers
import fp64toselectable
18 from openpower
.decoder
.isa
.remap_preduce_yield
import preduce_y
19 from functools
import reduce
30 class DecoderTestCase(FHDLTestCase
):
32 def _check_regs(self
, sim
, expected
):
34 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
36 def test_sv_cmp_ff_vli(self
):
37 lst
= SVP64Asm(["sv.cmp/ff=eq/vli *0, 1, *16, 0",
42 svstate
= SVP64State()
44 svstate
.maxvl
= 3 # MAXVL
45 print ("SVSTATE", bin(svstate
.asint()))
49 crs_expected
= [8, 2, 0] # LT EQ GT
53 for i
, x
in enumerate(vec
):
56 gprs
[0] = 2 # middle value of vec
58 with
Program(lst
, bigendian
=False) as program
:
59 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
61 print ("spr svstate ", sim
.svstate
)
62 print (" vl", sim
.svstate
.vl
)
63 for i
in range(len(vec
)):
64 val
= sim
.gpr(16+i
).value
66 crf
= sim
.crl
[i
].get_range().value
67 print ("i", i
, val
, crf
)
68 for i
in range(len(vec
)):
69 crf
= sim
.crl
[i
].get_range().value
70 assert crf
== crs_expected
[i
], "cr %d %s expect %s" % \
71 (i
, crf
, crs_expected
[i
])
72 assert sim
.svstate
.vl
== 2
74 def test_sv_cmp_ff(self
):
75 lst
= SVP64Asm(["sv.cmp/ff=eq *0, 1, *16, 0",
80 svstate
= SVP64State()
82 svstate
.maxvl
= 3 # MAXVL
83 print ("SVSTATE", bin(svstate
.asint()))
87 crs_expected
= [8, 2, 0] # LT EQ GT
91 for i
, x
in enumerate(vec
):
94 gprs
[0] = 2 # middle value of vec
96 with
Program(lst
, bigendian
=False) as program
:
97 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
99 print ("spr svstate ", sim
.svstate
)
100 print (" vl", sim
.svstate
.vl
)
101 for i
in range(len(vec
)):
102 val
= sim
.gpr(16+i
).value
104 crf
= sim
.crl
[i
].get_range().value
105 print ("i", i
, val
, crf
)
106 for i
in range(len(vec
)):
107 crf
= sim
.crl
[i
].get_range().value
108 assert crf
== crs_expected
[i
], "cr %d %s expect %s" % \
109 (i
, crf
, crs_expected
[i
])
110 assert sim
.svstate
.vl
== 1
112 def test_sv_cmp_ff_lt(self
):
113 lst
= SVP64Asm(["sv.cmp/ff=gt *0, 1, *16, 0",
118 svstate
= SVP64State()
120 svstate
.maxvl
= 3 # MAXVL
121 print ("SVSTATE", bin(svstate
.asint()))
125 crs_expected
= [8, 2, 4] # LT EQ GT
129 for i
, x
in enumerate(vec
):
132 gprs
[0] = 2 # middle value of vec
134 with
Program(lst
, bigendian
=False) as program
:
135 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
137 print ("spr svstate ", sim
.svstate
)
138 print (" vl", sim
.svstate
.vl
)
139 for i
in range(len(vec
)):
140 val
= sim
.gpr(16+i
).value
142 crf
= sim
.crl
[i
].get_range().value
143 print ("i", i
, val
, crf
)
144 for i
in range(len(vec
)):
145 crf
= sim
.crl
[i
].get_range().value
146 assert crf
== crs_expected
[i
], "cr %d %s expect %s" % \
147 (i
, crf
, crs_expected
[i
])
148 assert sim
.svstate
.vl
== 2
150 def test_sv_cmp(self
):
151 lst
= SVP64Asm(["sv.cmp *0, 1, *16, 0",
156 svstate
= SVP64State()
158 svstate
.maxvl
= 3 # MAXVL
159 print ("SVSTATE", bin(svstate
.asint()))
163 crs_expected
= [8, 2, 4] # LT EQ GT
167 for i
, x
in enumerate(vec
):
170 gprs
[0] = 2 # middle value of vec
172 with
Program(lst
, bigendian
=False) as program
:
173 sim
= self
.run_tst_program(program
, initial_regs
=gprs
,
175 print ("spr svstate ", sim
.spr
['SVSTATE'])
176 for i
in range(len(vec
)):
177 val
= sim
.gpr(16+i
).value
179 crf
= sim
.crl
[i
].get_range().value
180 print ("i", i
, val
, crf
)
181 assert crf
== crs_expected
[i
]
183 def test_sv_insert_sort(self
):
186 li r10, 1 # prepare mask
188 addi r10, r10, -1 # all 1s. must be better way
191 sv.mv/m=1<<r3 key, *array # get key item
192 sld r10, 1 # shift in another zero MSB
193 sv.cmp/ff=GT/m=~r10 *0, *array, key # stop cmp at 1st GT fail
194 sv.mv/m=GT *array-1, *array # after cmp and ffirst
196 sub r3, 1 # reduce by one
197 sv.mv/m=1<<r3 *array, key # put key into array
198 bc 16, loop # dec CTR, back around
200 def insertion_sort(array):
202 for i in range(lim,-1,-1):
205 while j <= lim and array[j] > key_item:
206 array[j - 1] = array[j]
208 array[j - 1] = key_item
211 lst
= SVP64Asm(["addi 10, 0, 1",
216 "setvl 3, 0, 10, 0, 1, 1",
218 "sv.addi/m=1<<r3 12, *16, 0", # key item to 12
219 "sv.cmp/ff=lt/m=~r10 *0, 1, *16, 12",
220 "sv.addi/m=ge *16, *17, 0", # move down
221 "setvl 3, 0, 0, 0, 0, 0", # get VL into r3
223 "setvl 13, 0, 10, 0, 1, 1", # put VL back from CTR
224 "sv.addi/m=1<<r3 *16, 12, 0", # restore key
225 "slw 10, 10, 9", # shift up start-mask ("inc" j)
226 "bc 16, 0, -52", # decrement CTR, repeat
231 #vec = [1, 2, 3, 4, 9, 5, 6]
236 for i
, x
in enumerate(vec
):
241 with
Program(lst
, bigendian
=False) as program
:
242 sim
= self
.run_tst_program(program
, initial_regs
=gprs
)
243 print ("spr svstate ", sim
.spr
['SVSTATE'])
244 print ("spr svshape0", sim
.spr
['SVSHAPE0'])
245 print (" xdimsz", sim
.spr
['SVSHAPE0'].xdimsz
)
246 print (" ydimsz", sim
.spr
['SVSHAPE0'].ydimsz
)
247 print (" zdimsz", sim
.spr
['SVSHAPE0'].zdimsz
)
248 print ("spr svshape1", sim
.spr
['SVSHAPE1'])
249 print ("spr svshape2", sim
.spr
['SVSHAPE2'])
250 print ("spr svshape3", sim
.spr
['SVSHAPE3'])
251 for i
in range(len(vec
)):
252 val
= sim
.gpr(16+i
).value
254 crf
= sim
.crl
[i
].get_range().value
255 print ("i", i
, val
, crf
)
257 # confirm that the results are as expected
258 expected
= list(reversed(sorted(vec
)))
259 for i
, v
in enumerate(res
):
260 self
.assertEqual(v
, expected
[i
])
262 def run_tst_program(self
, prog
, initial_regs
=None,
266 if initial_regs
is None:
267 initial_regs
= [0] * 32
268 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
269 initial_fprs
=initial_fprs
,
280 if __name__
== "__main__":