d54a59c94a295cd3c71da92d3678d7b242ddedb0
[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svp64_inssort.py
1 from nmigen import Module, Signal
2 from nmigen.sim import Simulator, Delay, Settle
3 from nmutil.formaltest import FHDLTestCase
4 import unittest
5 from openpower.decoder.isa.caller import ISACaller
6 from openpower.decoder.power_decoder import (create_pdecode)
7 from openpower.decoder.power_decoder2 import (PowerDecode2)
8 from openpower.simulator.program import Program
9 from openpower.decoder.isa.caller import ISACaller, SVP64State
10 from openpower.decoder.selectable_int import SelectableInt
11 from openpower.decoder.orderedset import OrderedSet
12 from openpower.decoder.isa.all import ISA
13 from openpower.decoder.isa.test_caller import Register, run_tst
14 from openpower.sv.trans.svp64 import SVP64Asm
15 from openpower.consts import SVP64CROffs
16 from copy import deepcopy
17 from openpower.decoder.helpers import fp64toselectable
18 from openpower.decoder.isa.remap_preduce_yield import preduce_y
19 from functools import reduce
20 import operator
21
22
23 def signcopy(x, y):
24 y = abs(y)
25 if x < 0:
26 return -y
27 return y
28
29
30 class DecoderTestCase(FHDLTestCase):
31
32 def _check_regs(self, sim, expected):
33 for i in range(32):
34 self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
35
36 def test_sv_cmp_ff_vli(self):
37 lst = SVP64Asm(["sv.cmp/ff=eq/vli *0, 1, *16, 0",
38 ])
39 lst = list(lst)
40
41 # SVSTATE vl=10
42 svstate = SVP64State()
43 svstate.vl = 3 # VL
44 svstate.maxvl = 3 # MAXVL
45 print ("SVSTATE", bin(svstate.asint()))
46
47 gprs = [0] * 64
48 vec = [1, 2, 3]
49 crs_expected = [8, 2, 0] # LT EQ GT
50
51 res = []
52 # store GPRs
53 for i, x in enumerate(vec):
54 gprs[i+16] = x
55
56 gprs[0] = 2 # middle value of vec
57
58 with Program(lst, bigendian=False) as program:
59 sim = self.run_tst_program(program, initial_regs=gprs,
60 svstate=svstate)
61 print ("spr svstate ", sim.svstate)
62 print (" vl", sim.svstate.vl)
63 for i in range(len(vec)):
64 val = sim.gpr(16+i).value
65 res.append(val)
66 crf = sim.crl[i].get_range().value
67 print ("i", i, val, crf)
68 for i in range(len(vec)):
69 crf = sim.crl[i].get_range().value
70 assert crf == crs_expected[i], "cr %d %s expect %s" % \
71 (i, crf, crs_expected[i])
72 assert sim.svstate.vl == 2
73
74 def test_sv_cmp_ff(self):
75 lst = SVP64Asm(["sv.cmp/ff=eq *0, 1, *16, 0",
76 ])
77 lst = list(lst)
78
79 # SVSTATE vl=10
80 svstate = SVP64State()
81 svstate.vl = 3 # VL
82 svstate.maxvl = 3 # MAXVL
83 print ("SVSTATE", bin(svstate.asint()))
84
85 gprs = [0] * 64
86 vec = [1, 2, 3]
87 crs_expected = [8, 2, 0] # LT EQ GT
88
89 res = []
90 # store GPRs
91 for i, x in enumerate(vec):
92 gprs[i+16] = x
93
94 gprs[0] = 2 # middle value of vec
95
96 with Program(lst, bigendian=False) as program:
97 sim = self.run_tst_program(program, initial_regs=gprs,
98 svstate=svstate)
99 print ("spr svstate ", sim.svstate)
100 print (" vl", sim.svstate.vl)
101 for i in range(len(vec)):
102 val = sim.gpr(16+i).value
103 res.append(val)
104 crf = sim.crl[i].get_range().value
105 print ("i", i, val, crf)
106 for i in range(len(vec)):
107 crf = sim.crl[i].get_range().value
108 assert crf == crs_expected[i], "cr %d %s expect %s" % \
109 (i, crf, crs_expected[i])
110 assert sim.svstate.vl == 1
111
112 def test_sv_cmp_ff_lt(self):
113 lst = SVP64Asm(["sv.cmp/ff=gt *0, 1, *16, 0",
114 ])
115 lst = list(lst)
116
117 # SVSTATE vl=10
118 svstate = SVP64State()
119 svstate.vl = 3 # VL
120 svstate.maxvl = 3 # MAXVL
121 print ("SVSTATE", bin(svstate.asint()))
122
123 gprs = [0] * 64
124 vec = [1, 2, 3]
125 crs_expected = [8, 2, 4] # LT EQ GT
126
127 res = []
128 # store GPRs
129 for i, x in enumerate(vec):
130 gprs[i+16] = x
131
132 gprs[0] = 2 # middle value of vec
133
134 with Program(lst, bigendian=False) as program:
135 sim = self.run_tst_program(program, initial_regs=gprs,
136 svstate=svstate)
137 print ("spr svstate ", sim.svstate)
138 print (" vl", sim.svstate.vl)
139 for i in range(len(vec)):
140 val = sim.gpr(16+i).value
141 res.append(val)
142 crf = sim.crl[i].get_range().value
143 print ("i", i, val, crf)
144 for i in range(len(vec)):
145 crf = sim.crl[i].get_range().value
146 assert crf == crs_expected[i], "cr %d %s expect %s" % \
147 (i, crf, crs_expected[i])
148 assert sim.svstate.vl == 2
149
150 def test_sv_cmp(self):
151 lst = SVP64Asm(["sv.cmp *0, 1, *16, 0",
152 ])
153 lst = list(lst)
154
155 # SVSTATE vl=10
156 svstate = SVP64State()
157 svstate.vl = 3 # VL
158 svstate.maxvl = 3 # MAXVL
159 print ("SVSTATE", bin(svstate.asint()))
160
161 gprs = [0] * 64
162 vec = [1, 2, 3]
163 crs_expected = [8, 2, 4] # LT EQ GT
164
165 res = []
166 # store GPRs
167 for i, x in enumerate(vec):
168 gprs[i+16] = x
169
170 gprs[0] = 2 # middle value of vec
171
172 with Program(lst, bigendian=False) as program:
173 sim = self.run_tst_program(program, initial_regs=gprs,
174 svstate=svstate)
175 print ("spr svstate ", sim.spr['SVSTATE'])
176 for i in range(len(vec)):
177 val = sim.gpr(16+i).value
178 res.append(val)
179 crf = sim.crl[i].get_range().value
180 print ("i", i, val, crf)
181 assert crf == crs_expected[i]
182
183 def test_sv_insert_sort(self):
184 """
185 ctr = alen-1
186 li r10, 1 # prepare mask
187 sld r10, alen, r10
188 addi r10, r10, -1 # all 1s. must be better way
189 loop:
190 setvl r3, ctr
191 sv.mv/m=1<<r3 key, *array # get key item
192 sld r10, 1 # shift in another zero MSB
193 sv.cmp/ff=GT/m=~r10 *0, *array, key # stop cmp at 1st GT fail
194 sv.mv/m=GT *array-1, *array # after cmp and ffirst
195 getvl r3
196 sub r3, 1 # reduce by one
197 sv.mv/m=1<<r3 *array, key # put key into array
198 bc 16, loop # dec CTR, back around
199
200 def insertion_sort(array):
201 lim = len(array)-1
202 for i in range(lim,-1,-1):
203 key_item = array[i]
204 j = i + 1
205 while j <= lim and array[j] > key_item:
206 array[j - 1] = array[j]
207 j += 1
208 array[j - 1] = key_item
209 return array
210 """
211 lst = SVP64Asm(["addi 10, 0, 1",
212 "addi 9, 11, 0",
213 "slw 10, 10, 9",
214 "addi 10, 10, -1",
215 "mtspr 9, 11",
216 "setvl 3, 0, 10, 0, 1, 1",
217 "addi 3, 3, -1",
218 "sv.addi/m=1<<r3 12, *16, 0", # key item to 12
219 "sv.cmp/ff=lt/m=~r10 *0, 1, *16, 12",
220 "sv.addi/m=ge *16, *17, 0", # move down
221 "setvl 3, 0, 0, 0, 0, 0", # get VL into r3
222 "addi 3, 3, -1",
223 "setvl 13, 0, 10, 0, 1, 1", # put VL back from CTR
224 "sv.addi/m=1<<r3 *16, 12, 0", # restore key
225 "slw 10, 10, 9", # shift up start-mask ("inc" j)
226 "bc 16, 0, -52", # decrement CTR, repeat
227 ])
228 lst = list(lst)
229
230 gprs = [0] * 64
231 #vec = [1, 2, 3, 4, 9, 5, 6]
232 vec = [9, 5, 6]
233
234 res = []
235 # store GPRs
236 for i, x in enumerate(vec):
237 gprs[i+16] = x
238
239 gprs[11] = len(vec)
240
241 with Program(lst, bigendian=False) as program:
242 sim = self.run_tst_program(program, initial_regs=gprs)
243 print ("spr svstate ", sim.spr['SVSTATE'])
244 print ("spr svshape0", sim.spr['SVSHAPE0'])
245 print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz)
246 print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz)
247 print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz)
248 print ("spr svshape1", sim.spr['SVSHAPE1'])
249 print ("spr svshape2", sim.spr['SVSHAPE2'])
250 print ("spr svshape3", sim.spr['SVSHAPE3'])
251 for i in range(len(vec)):
252 val = sim.gpr(16+i).value
253 res.append(val)
254 crf = sim.crl[i].get_range().value
255 print ("i", i, val, crf)
256 return
257 # confirm that the results are as expected
258 expected = list(reversed(sorted(vec)))
259 for i, v in enumerate(res):
260 self.assertEqual(v, expected[i])
261
262 def run_tst_program(self, prog, initial_regs=None,
263 svstate=None,
264 initial_mem=None,
265 initial_fprs=None):
266 if initial_regs is None:
267 initial_regs = [0] * 32
268 simulator = run_tst(prog, initial_regs, mem=initial_mem,
269 initial_fprs=initial_fprs,
270 svstate=svstate)
271
272 print ("GPRs")
273 simulator.gpr.dump()
274 print ("FPRs")
275 simulator.fpr.dump()
276
277 return simulator
278
279
280 if __name__ == "__main__":
281 unittest.main()