src/openpower/decoder/isa/test_caller_svp64_subvl.py

   1 from nmigen import Module, Signal
   2 from nmigen.sim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_sv_add_intpred(self):
  25         # adds, integer predicated mask r3=0b10
  26         #       1 = 5 + 9   => not to be touched (skipped)
  27         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  28         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
  29         #   src r3=0b10      | |     N N Y Y N N Y Y
  30         #                    | |         | |     | |
  31         #                    | | +-------+-|-add-+ |
  32         #                    | | | +-------+-add---+
  33         #                    | | | |
  34         #   dest r3=0b10     N N Y Y
  35         isa = SVP64Asm(['sv.add/vec2/m=r30 *1, *5, *9'
  36                        ])
  37         lst = list(isa)
  38         print ("listing", lst)
  39
  40         # initial values in GPR regfile
  41         initial_regs = [0] * 32
  42         initial_regs[1] = 0xbeef   # not to be altered
  43         initial_regs[2] = 0xefbe  # not to be altered
  44         initial_regs[3] = 0xebbe
  45         initial_regs[4] = 0xbeeb
  46         initial_regs[30] = 0b10   # predicate mask
  47         initial_regs[9] = 0x1234
  48         initial_regs[10] = 0x1111
  49         initial_regs[11] = 0x7eee
  50         initial_regs[12] = 0x2aaa
  51         initial_regs[5] = 0x4321
  52         initial_regs[6] = 0x2223
  53         initial_regs[7] = 0x4321
  54         initial_regs[8] = 0x2223
  55         # SVSTATE (in this case, VL=2)
  56         svstate = SVP64State()
  57         svstate.vl = 2 # VL
  58         svstate.maxvl = 2 # MAXVL
  59         print ("SVSTATE", bin(svstate.asint()))
  60         # copy before running
  61         expected_regs = deepcopy(initial_regs)
  62         expected_regs[3] = initial_regs[7]+initial_regs[11]
  63         expected_regs[4] = initial_regs[8]+initial_regs[12]
  64
  65         with Program(lst, bigendian=False) as program:
  66             sim = self.run_tst_program(program, initial_regs, svstate)
  67             self._check_regs(sim, expected_regs)
  68
  69
  70     def run_tst_program(self, prog, initial_regs=None,
  71                               svstate=None,
  72                               initial_cr=0):
  73         if initial_regs is None:
  74             initial_regs = [0] * 32
  75         simulator = run_tst(prog, initial_regs, svstate=svstate,
  76                             initial_cr=initial_cr)
  77         simulator.gpr.dump()
  78         return simulator
  79
  80
  81 if __name__ == "__main__":
  82     unittest.main()