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e45015b5bcae2ec95b5c55748fce53afdb56ac4d
[openpower-isa.git] / src / openpower / decoder / isa / test_caller_svshape2.py
1 """SVP64 unit test for svshape2
2 svshape2 offs,yx,rmm,SVd,sk,mm
3 """
4 from nmigen import Module, Signal
5 from nmigen.sim import Simulator, Delay, Settle
6 from nmutil.formaltest import FHDLTestCase
7 import unittest
8 from openpower.decoder.isa.caller import ISACaller
9 from openpower.decoder.power_decoder import (create_pdecode)
10 from openpower.decoder.power_decoder2 import (PowerDecode2)
11 from openpower.simulator.program import Program
12 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
13 from openpower.decoder.selectable_int import SelectableInt
14 from openpower.decoder.orderedset import OrderedSet
15 from openpower.decoder.isa.all import ISA
16 from openpower.decoder.isa.test_caller import Register, run_tst
17 from openpower.sv.trans.svp64 import SVP64Asm
18 from openpower.consts import SVP64CROffs
19 from copy import deepcopy
20
21
22 class SVSTATETestCase(FHDLTestCase):
23
24 def _check_regs(self, sim, expected):
25 print("GPR")
26 sim.gpr.dump()
27 for i in range(32):
28 self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64),
29 "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i]))
30
31 def test_0_sv_shape2(self):
32 """sets VL=10 (via SVSTATE) then does svshape mm=0, checks SPRs after
33 """
34 isa = SVP64Asm(['svshape2 6, 1, 1, 15, 5, 0, 0'
35 ])
36 lst = list(isa)
37 print("listing", lst)
38
39 # initial values in GPR regfile
40 initial_regs = [0] * 32
41 initial_regs[9] = 0x1234
42 initial_regs[10] = 0x1111
43 initial_regs[5] = 0x4321
44 initial_regs[6] = 0x2223
45
46 # SVSTATE vl=10
47 svstate = SVP64State()
48 svstate.vl = 10 # VL
49 svstate.maxvl = 10 # MAXVL
50 print("SVSTATE", bin(svstate.asint()))
51
52 # copy before running
53 expected_regs = deepcopy(initial_regs)
54 #expected_regs[1] = 0x3334
55
56 with Program(lst, bigendian=False) as program:
57 sim = self.run_tst_program(program, initial_regs, svstate=svstate)
58 self._check_regs(sim, expected_regs)
59
60 print(sim.spr)
61 SVSHAPE0 = sim.spr['SVSHAPE0']
62 print("SVSTATE after", bin(sim.svstate.asint()))
63 print(" vl", bin(sim.svstate.vl))
64 print(" mvl", bin(sim.svstate.maxvl))
65 print(" srcstep", bin(sim.svstate.srcstep))
66 print(" dststep", bin(sim.svstate.dststep))
67 print(" RMpst", bin(sim.svstate.RMpst))
68 print(" SVme", bin(sim.svstate.SVme))
69 print(" mo0", bin(sim.svstate.mo0))
70 print(" mo1", bin(sim.svstate.mo1))
71 print(" mi0", bin(sim.svstate.mi0))
72 print(" mi1", bin(sim.svstate.mi1))
73 print(" mi2", bin(sim.svstate.mi2))
74 print("STATE0 ", SVSHAPE0)
75 print("STATE0 offs", SVSHAPE0.offset)
76 print("STATE0 xdim", SVSHAPE0.xdimsz)
77 print("STATE0 ydim", SVSHAPE0.ydimsz)
78 print("STATE0 skip", bin(SVSHAPE0.skip))
79 print("STATE0 inv", SVSHAPE0.invxyz)
80 print("STATE0order", SVSHAPE0.order)
81 self.assertEqual(SVSHAPE0.xdimsz, 5) # set
82 self.assertEqual(SVSHAPE0.ydimsz, 2) # calculated from MVL/xdimsz
83 self.assertEqual(SVSHAPE0.skip, 0) # no skip
84 # invert y rather than x because yx=1
85 self.assertEqual(SVSHAPE0.invxyz, [0, 1, 0])
86 self.assertEqual(SVSHAPE0.offset, 6)
87 self.assertEqual(SVSHAPE0.order, (1, 0, 2)) # y,x(,z)
88 self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
89 self.assertEqual(sim.svstate.SVme, 0b01111) # same as rmm
90 # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
91 self.assertEqual(sim.svstate.mi0, 0)
92 self.assertEqual(sim.svstate.mi1, 1)
93 self.assertEqual(sim.svstate.mi2, 2)
94 self.assertEqual(sim.svstate.mo0, 3)
95 self.assertEqual(sim.svstate.mo1, 0)
96
97 def tst_1_sv_index(self):
98 """sets VL=10 (via SVSTATE) then does svindex mm=1, checks SPRs after
99 """
100 # rmm: bits 0-2 (MSB0) are 0b011 and bits 3-4 are 0b10.
101 # therefore rmm is 0b011 || 0b10 --> 0b01110 -> 14
102 isa = SVP64Asm(['svindex 1, 14, 5, 0, 0, 1, 0'
103 ])
104 lst = list(isa)
105 print("listing", lst)
106
107 # initial values in GPR regfile
108 initial_regs = [0] * 32
109 initial_regs[9] = 0x1234
110 initial_regs[10] = 0x1111
111 initial_regs[5] = 0x4321
112 initial_regs[6] = 0x2223
113
114 # SVSTATE vl=10
115 svstate = SVP64State()
116 svstate.vl = 10 # VL
117 svstate.maxvl = 10 # MAXVL
118 print("SVSTATE", bin(svstate.asint()))
119
120 # copy before running
121 expected_regs = deepcopy(initial_regs)
122 #expected_regs[1] = 0x3334
123
124 with Program(lst, bigendian=False) as program:
125 sim = self.run_tst_program(program, initial_regs, svstate=svstate)
126 self._check_regs(sim, expected_regs)
127
128 print(sim.spr)
129 SVSHAPE2 = sim.spr['SVSHAPE2']
130 print("SVSTATE after", bin(sim.svstate.asint()))
131 print(" vl", bin(sim.svstate.vl))
132 print(" mvl", bin(sim.svstate.maxvl))
133 print(" srcstep", bin(sim.svstate.srcstep))
134 print(" dststep", bin(sim.svstate.dststep))
135 print(" RMpst", bin(sim.svstate.RMpst))
136 print(" SVme", bin(sim.svstate.SVme))
137 print(" mo0", bin(sim.svstate.mo0))
138 print(" mo1", bin(sim.svstate.mo1))
139 print(" mi0", bin(sim.svstate.mi0))
140 print(" mi1", bin(sim.svstate.mi1))
141 print(" mi2", bin(sim.svstate.mi2))
142 print("STATE2svgpr", hex(SVSHAPE2.svgpr))
143 print("STATE2 xdim", SVSHAPE2.xdimsz)
144 print("STATE2 ydim", SVSHAPE2.ydimsz)
145 print("STATE2 skip", bin(SVSHAPE2.skip))
146 print("STATE2 inv", SVSHAPE2.invxyz)
147 print("STATE2order", SVSHAPE2.order)
148 self.assertEqual(sim.svstate.RMpst, 1) # mm=1 so persist=1
149 # rmm is 0b01110 which means mo0 = 2
150 self.assertEqual(sim.svstate.mi0, 0)
151 self.assertEqual(sim.svstate.mi1, 0)
152 self.assertEqual(sim.svstate.mi2, 0)
153 self.assertEqual(sim.svstate.mo0, 2)
154 self.assertEqual(sim.svstate.mo1, 0)
155 # and mo0 should be activated
156 self.assertEqual(sim.svstate.SVme, 0b01000)
157 # now check the SVSHAPEs. 2 was the one targetted
158 self.assertEqual(SVSHAPE2.svgpr, 2) # SVG is shifted up by 1
159 self.assertEqual(SVSHAPE2.xdimsz, 5) # SHAPE2 xdim set to 5
160 self.assertEqual(SVSHAPE2.ydimsz, 1) # SHAPE2 ydim 1
161 # all others must be zero
162 for i in [0, 1, 3]:
163 shape = sim.spr['SVSHAPE%d' % i]
164 self.assertEqual(shape.asint(), 0) # all others zero
165
166 def tst_0_sv_index_add(self):
167 """sets VL=6 (via SVSTATE) then does svindex, and an add.
168
169 only RA is re-mapped via Indexing, not RB or RT
170 """
171 isa = SVP64Asm(['svindex 8, 1, 1, 0, 0, 0, 0',
172 'sv.add *8, *0, *0',
173 ])
174 lst = list(isa)
175 print("listing", lst)
176
177 # initial values in GPR regfile
178 initial_regs = [0] * 32
179 idxs = [1, 0, 5, 2, 4, 3] # random enough
180 for i in range(6):
181 initial_regs[16+i] = idxs[i]
182 initial_regs[i] = i
183
184 # SVSTATE vl=10
185 svstate = SVP64State()
186 svstate.vl = 6 # VL
187 svstate.maxvl = 6 # MAXVL
188 print("SVSTATE", bin(svstate.asint()))
189
190 # copy before running
191 expected_regs = deepcopy(initial_regs)
192 for i in range(6):
193 RA = initial_regs[0+idxs[i]]
194 RB = initial_regs[0+i]
195 expected_regs[i+8] = RA+RB
196 print("expected", i, expected_regs[i+8])
197
198 with Program(lst, bigendian=False) as program:
199 sim = self.run_tst_program(program, initial_regs, svstate=svstate)
200
201 print(sim.spr)
202 SVSHAPE0 = sim.spr['SVSHAPE0']
203 print("SVSTATE after", bin(sim.svstate.asint()))
204 print(" vl", bin(sim.svstate.vl))
205 print(" mvl", bin(sim.svstate.maxvl))
206 print(" srcstep", bin(sim.svstate.srcstep))
207 print(" dststep", bin(sim.svstate.dststep))
208 print(" RMpst", bin(sim.svstate.RMpst))
209 print(" SVme", bin(sim.svstate.SVme))
210 print(" mo0", bin(sim.svstate.mo0))
211 print(" mo1", bin(sim.svstate.mo1))
212 print(" mi0", bin(sim.svstate.mi0))
213 print(" mi1", bin(sim.svstate.mi1))
214 print(" mi2", bin(sim.svstate.mi2))
215 print("STATE0svgpr", hex(SVSHAPE0.svgpr))
216 print(sim.gpr.dump())
217 self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
218 self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm
219 # rmm is 0b00001 which means mi0=0 and all others inactive (0)
220 self.assertEqual(sim.svstate.mi0, 0)
221 self.assertEqual(sim.svstate.mi1, 0)
222 self.assertEqual(sim.svstate.mi2, 0)
223 self.assertEqual(sim.svstate.mo0, 0)
224 self.assertEqual(sim.svstate.mo1, 0)
225 self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1
226 for i in range(1, 4):
227 shape = sim.spr['SVSHAPE%d' % i]
228 self.assertEqual(shape.svgpr, 0)
229 self._check_regs(sim, expected_regs)
230
231 def tst_1_sv_index_add(self):
232 """sets VL=6 (via SVSTATE) then does modulo 3 svindex, and an add.
233
234 only RA is re-mapped via Indexing, not RB or RT
235 """
236 isa = SVP64Asm(['svindex 8, 1, 3, 0, 0, 0, 0',
237 'sv.add *8, *0, *0',
238 ])
239 lst = list(isa)
240 print("listing", lst)
241
242 # initial values in GPR regfile
243 initial_regs = [0] * 32
244 idxs = [1, 0, 5, 2, 4, 3] # random enough
245 for i in range(6):
246 initial_regs[16+i] = idxs[i]
247 initial_regs[i] = i
248
249 # SVSTATE vl=10
250 svstate = SVP64State()
251 svstate.vl = 6 # VL
252 svstate.maxvl = 6 # MAXVL
253 print("SVSTATE", bin(svstate.asint()))
254
255 # copy before running
256 expected_regs = deepcopy(initial_regs)
257 for i in range(6):
258 RA = initial_regs[0+idxs[i % 3]] # modulo 3 but still indexed
259 RB = initial_regs[0+i]
260 expected_regs[i+8] = RA+RB
261 print("expected", i, expected_regs[i+8])
262
263 with Program(lst, bigendian=False) as program:
264 sim = self.run_tst_program(program, initial_regs, svstate=svstate)
265
266 print(sim.spr)
267 SVSHAPE0 = sim.spr['SVSHAPE0']
268 print("SVSTATE after", bin(sim.svstate.asint()))
269 print(" vl", bin(sim.svstate.vl))
270 print(" mvl", bin(sim.svstate.maxvl))
271 print(" srcstep", bin(sim.svstate.srcstep))
272 print(" dststep", bin(sim.svstate.dststep))
273 print(" RMpst", bin(sim.svstate.RMpst))
274 print(" SVme", bin(sim.svstate.SVme))
275 print(" mo0", bin(sim.svstate.mo0))
276 print(" mo1", bin(sim.svstate.mo1))
277 print(" mi0", bin(sim.svstate.mi0))
278 print(" mi1", bin(sim.svstate.mi1))
279 print(" mi2", bin(sim.svstate.mi2))
280 print("STATE0svgpr", hex(SVSHAPE0.svgpr))
281 print("STATE0 xdim", SVSHAPE0.xdimsz)
282 print("STATE0 ydim", SVSHAPE0.ydimsz)
283 print("STATE0 skip", bin(SVSHAPE0.skip))
284 print("STATE0 inv", SVSHAPE0.invxyz)
285 print("STATE0order", SVSHAPE0.order)
286 print(sim.gpr.dump())
287 self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
288 self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm
289 # rmm is 0b00001 which means mi0=0 and all others inactive (0)
290 self.assertEqual(sim.svstate.mi0, 0)
291 self.assertEqual(sim.svstate.mi1, 0)
292 self.assertEqual(sim.svstate.mi2, 0)
293 self.assertEqual(sim.svstate.mo0, 0)
294 self.assertEqual(sim.svstate.mo1, 0)
295 self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1
296 for i in range(1, 4):
297 shape = sim.spr['SVSHAPE%d' % i]
298 self.assertEqual(shape.svgpr, 0)
299 self._check_regs(sim, expected_regs)
300
301 def tst_2_sv_index_add(self):
302 """sets VL=6 (via SVSTATE) then does 2D remapped svindex, and an add.
303
304 dim=3,yx=1
305 only RA is re-mapped via Indexing, not RB or RT
306 """
307 isa = SVP64Asm(['svindex 8, 1, 3, 0, 1, 0, 0',
308 'sv.add *8, *0, *0',
309 ])
310 lst = list(isa)
311 print("listing", lst)
312
313 # initial values in GPR regfile
314 initial_regs = [0] * 32
315 idxs = [1, 0, 5, 2, 4, 3] # random enough
316 for i in range(6):
317 initial_regs[16+i] = idxs[i]
318 initial_regs[i] = i
319
320 # SVSTATE vl=10
321 svstate = SVP64State()
322 svstate.vl = 6 # VL
323 svstate.maxvl = 6 # MAXVL
324 print("SVSTATE", bin(svstate.asint()))
325
326 # copy before running
327 expected_regs = deepcopy(initial_regs)
328 for i in range(6):
329 xi = i % 3
330 yi = i // 3
331 remap = yi+xi*2
332 RA = initial_regs[0+idxs[remap]] # modulo 3 but still indexed
333 RB = initial_regs[0+i]
334 expected_regs[i+8] = RA+RB
335 print("expected", i, expected_regs[i+8])
336
337 with Program(lst, bigendian=False) as program:
338 sim = self.run_tst_program(program, initial_regs, svstate=svstate)
339
340 print(sim.spr)
341 SVSHAPE0 = sim.spr['SVSHAPE0']
342 print("SVSTATE after", bin(sim.svstate.asint()))
343 print(" vl", bin(sim.svstate.vl))
344 print(" mvl", bin(sim.svstate.maxvl))
345 print(" srcstep", bin(sim.svstate.srcstep))
346 print(" dststep", bin(sim.svstate.dststep))
347 print(" RMpst", bin(sim.svstate.RMpst))
348 print(" SVme", bin(sim.svstate.SVme))
349 print(" mo0", bin(sim.svstate.mo0))
350 print(" mo1", bin(sim.svstate.mo1))
351 print(" mi0", bin(sim.svstate.mi0))
352 print(" mi1", bin(sim.svstate.mi1))
353 print(" mi2", bin(sim.svstate.mi2))
354 print("STATE0svgpr", hex(SVSHAPE0.svgpr))
355 print("STATE0 xdim", SVSHAPE0.xdimsz)
356 print("STATE0 ydim", SVSHAPE0.ydimsz)
357 print("STATE0 skip", bin(SVSHAPE0.skip))
358 print("STATE0 inv", SVSHAPE0.invxyz)
359 print("STATE0order", SVSHAPE0.order)
360 print(sim.gpr.dump())
361 self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
362 self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm
363 # rmm is 0b00001 which means mi0=0 and all others inactive (0)
364 self.assertEqual(sim.svstate.mi0, 0)
365 self.assertEqual(sim.svstate.mi1, 0)
366 self.assertEqual(sim.svstate.mi2, 0)
367 self.assertEqual(sim.svstate.mo0, 0)
368 self.assertEqual(sim.svstate.mo1, 0)
369 self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1
370 for i in range(1, 4):
371 shape = sim.spr['SVSHAPE%d' % i]
372 self.assertEqual(shape.svgpr, 0)
373 self._check_regs(sim, expected_regs)
374
375 def run_tst_program(self, prog, initial_regs=None,
376 svstate=None):
377 if initial_regs is None:
378 initial_regs = [0] * 32
379 simulator = run_tst(prog, initial_regs, svstate=svstate)
380 simulator.gpr.dump()
381 return simulator
382
383
384 if __name__ == "__main__":
385 unittest.main()