src/openpower/decoder/isa/test_caller_svshape2.py

   1 """SVP64 unit test for svshape2
   2 svshape2 SVo,yx,rmm,SVd,sk,mm
   3 """
   4 from nmigen import Module, Signal
   5 from nmigen.sim import Simulator, Delay, Settle
   6 from nmutil.formaltest import FHDLTestCase
   7 import unittest
   8 from openpower.decoder.isa.caller import ISACaller
   9 from openpower.decoder.power_decoder import (create_pdecode)
  10 from openpower.decoder.power_decoder2 import (PowerDecode2)
  11 from openpower.simulator.program import Program
  12 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  13 from openpower.decoder.selectable_int import SelectableInt
  14 from openpower.decoder.orderedset import OrderedSet
  15 from openpower.decoder.isa.all import ISA
  16 from openpower.decoder.isa.test_caller import Register, run_tst
  17 from openpower.sv.trans.svp64 import SVP64Asm
  18 from openpower.consts import SVP64CROffs
  19 from copy import deepcopy
  20
  21
  22 class SVSTATETestCase(FHDLTestCase):
  23
  24     def _check_regs(self, sim, expected):
  25         print("GPR")
  26         sim.gpr.dump()
  27         for i in range(32):
  28             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64),
  29                              "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i]))
  30
  31     def test_0_sv_shape2(self):
  32         """sets VL=10 (via SVSTATE) then does svshape mm=0, checks SPRs after
  33         """
  34         isa = SVP64Asm(['svshape2 12, 1, 15, 5, 0, 0'
  35                         ])
  36         lst = list(isa)
  37         print("listing", lst)
  38
  39         # initial values in GPR regfile
  40         initial_regs = [0] * 32
  41         initial_regs[9] = 0x1234
  42         initial_regs[10] = 0x1111
  43         initial_regs[5] = 0x4321
  44         initial_regs[6] = 0x2223
  45
  46         # SVSTATE vl=10
  47         svstate = SVP64State()
  48         svstate.vl = 10  # VL
  49         svstate.maxvl = 10  # MAXVL
  50         print("SVSTATE", bin(svstate.asint()))
  51
  52         # copy before running
  53         expected_regs = deepcopy(initial_regs)
  54         #expected_regs[1] = 0x3334
  55
  56         with Program(lst, bigendian=False) as program:
  57             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
  58             self._check_regs(sim, expected_regs)
  59
  60             print(sim.spr)
  61             SVSHAPE0 = sim.spr['SVSHAPE0']
  62             print("SVSTATE after", bin(sim.svstate.asint()))
  63             print("        vl", bin(sim.svstate.vl))
  64             print("        mvl", bin(sim.svstate.maxvl))
  65             print("    srcstep", bin(sim.svstate.srcstep))
  66             print("    dststep", bin(sim.svstate.dststep))
  67             print("      RMpst", bin(sim.svstate.RMpst))
  68             print("       SVme", bin(sim.svstate.SVme))
  69             print("        mo0", bin(sim.svstate.mo0))
  70             print("        mo1", bin(sim.svstate.mo1))
  71             print("        mi0", bin(sim.svstate.mi0))
  72             print("        mi1", bin(sim.svstate.mi1))
  73             print("        mi2", bin(sim.svstate.mi2))
  74             print("STATE0     ", SVSHAPE0)
  75             print("STATE0 offs", SVSHAPE0.offset)
  76             print("STATE0 xdim", SVSHAPE0.xdimsz)
  77             print("STATE0 ydim", SVSHAPE0.ydimsz)
  78             print("STATE0 skip", bin(SVSHAPE0.skip))
  79             print("STATE0  inv", SVSHAPE0.invxyz)
  80             print("STATE0order", SVSHAPE0.order)
  81             self.assertEqual(SVSHAPE0.xdimsz, 5)  # set
  82             self.assertEqual(SVSHAPE0.ydimsz, 2)  # calculated from MVL/xdimsz
  83             self.assertEqual(SVSHAPE0.skip, 0)   # no skip
  84             # (no inversion possible)
  85             self.assertEqual(SVSHAPE0.invxyz, [0, 0, 0])
  86             self.assertEqual(SVSHAPE0.offset, 12)
  87             self.assertEqual(SVSHAPE0.order, (1, 0, 2))  # y,x(,z)
  88             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
  89             self.assertEqual(sim.svstate.SVme, 0b01111)  # same as rmm
  90             # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
  91             self.assertEqual(sim.svstate.mi0, 0)
  92             self.assertEqual(sim.svstate.mi1, 1)
  93             self.assertEqual(sim.svstate.mi2, 2)
  94             self.assertEqual(sim.svstate.mo0, 3)
  95             self.assertEqual(sim.svstate.mo1, 0)
  96
  97     def test_1_sv_offset2_add(self):
  98         """sets VL=6 (via SVSTATE) then does modulo 3 svindex, and an add.
  99
 100         only RA is re-mapped via svshape2, not RB or RT, but an offset of
 101         1 is included on RA.
 102
 103         whilst this does not look useful for sv.add because it is EXTRA3
 104         encoded, it *is* a useful demo for anything EXTRA2-encoded which
 105         only has even-numbered GPR/FPR vector register accessibility.
 106         set the offset to compensate for EXTRA2 being so restricted.
 107         """
 108         # set some parameters here with comments
 109         offs = 1 # an offset of 1
 110         mod = 3  # modulo 3 on the range
 111         VL = 6   # RB will go 0..5 but RA will go 1 2 3 1 2 3
 112         isa = SVP64Asm(['svshape2 %d, 0, 1, %d, 0, 0' % (offs, mod),
 113                         'sv.add *8, *0, *0',
 114                         ])
 115         lst = list(isa)
 116         print("listing", lst)
 117
 118         # initial values in GPR regfile
 119         initial_regs = [0] * 32
 120         for i in range(VL):
 121             initial_regs[i] = i
 122
 123         # SVSTATE vl=10
 124         svstate = SVP64State()
 125         svstate.vl = VL  # VL
 126         svstate.maxvl = VL  # MAXVL
 127         print("SVSTATE", bin(svstate.asint()))
 128
 129         # copy before running and compute the expected results
 130         expected_regs = deepcopy(initial_regs)
 131         for i in range(VL):
 132             RA = initial_regs[offs+(i % mod)]  # modulo but also offset
 133             RB = initial_regs[0+i]             # RB is not re-mapped
 134             expected_regs[i+8] = RA+RB
 135             print("expected", i, expected_regs[i+8])
 136
 137         with Program(lst, bigendian=False) as program:
 138             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 139
 140             print(sim.spr)
 141             SVSHAPE0 = sim.spr['SVSHAPE0']
 142             SVSHAPE1 = sim.spr['SVSHAPE1']
 143             SVSHAPE2 = sim.spr['SVSHAPE2']
 144             SVSHAPE3 = sim.spr['SVSHAPE3']
 145             print("SVSTATE after", bin(sim.svstate.asint()))
 146             print("        vl", bin(sim.svstate.vl))
 147             print("        mvl", bin(sim.svstate.maxvl))
 148             print("    srcstep", bin(sim.svstate.srcstep))
 149             print("    dststep", bin(sim.svstate.dststep))
 150             print("      RMpst", bin(sim.svstate.RMpst))
 151             print("       SVme", bin(sim.svstate.SVme))
 152             print("        mo0", bin(sim.svstate.mo0))
 153             print("        mo1", bin(sim.svstate.mo1))
 154             print("        mi0", bin(sim.svstate.mi0))
 155             print("        mi1", bin(sim.svstate.mi1))
 156             print("        mi2", bin(sim.svstate.mi2))
 157             print("STATE0     ", SVSHAPE0)
 158             print("STATE0 offs", SVSHAPE0.offset)
 159             print("STATE0 xdim", SVSHAPE0.xdimsz)
 160             print("STATE0 ydim", SVSHAPE0.ydimsz)
 161             print("STATE0 skip", bin(SVSHAPE0.skip))
 162             print("STATE0  inv", SVSHAPE0.invxyz)
 163             print("STATE0order", SVSHAPE0.order)
 164             print(sim.gpr.dump())
 165             self.assertEqual(SVSHAPE0.xdimsz, 3)  # set
 166             self.assertEqual(SVSHAPE0.ydimsz, 1)  # calculated from MVL/xdimsz
 167             self.assertEqual(SVSHAPE0.skip, 0)   # no skip
 168             # (no inversion possible)
 169             self.assertEqual(SVSHAPE0.invxyz, [0, 0, 0])
 170             self.assertEqual(SVSHAPE0.offset, 1)
 171             self.assertEqual(SVSHAPE0.order, (0, 1, 2))  # x,y(,z)
 172             self.assertEqual(sim.svstate.RMpst, 0)  # mm=0 so persist=0
 173             self.assertEqual(sim.svstate.SVme, 0b00001)  # same as rmm
 174             # SVSHAPE1-3 zero
 175             self.assertEqual(SVSHAPE1, 0)
 176             self.assertEqual(SVSHAPE2, 0)
 177             self.assertEqual(SVSHAPE3, 0)
 178             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 179             self.assertEqual(sim.svstate.mi0, 0)
 180             self.assertEqual(sim.svstate.mi1, 0)
 181             self.assertEqual(sim.svstate.mi2, 0)
 182             self.assertEqual(sim.svstate.mo0, 0)
 183             self.assertEqual(sim.svstate.mo1, 0)
 184             self._check_regs(sim, expected_regs)
 185
 186     def run_tst_program(self, prog, initial_regs=None,
 187                         svstate=None):
 188         if initial_regs is None:
 189             initial_regs = [0] * 32
 190         simulator = run_tst(prog, initial_regs, svstate=svstate)
 191         simulator.gpr.dump()
 192         return simulator
 193
 194
 195 if __name__ == "__main__":
 196     unittest.main()