1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RC
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEtype
, SVPtype
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, spr_to_state
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(4, name
="fast_o")
82 self
.state_o
= Data(3, name
="state_o")
84 def elaborate(self
, platform
):
90 with m
.Switch(self
.spr_i
):
91 for i
, x
in enumerate(SPR
):
93 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
94 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
95 for x
, v
in spr_to_fast
.items():
97 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
98 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 for x
, v
in spr_to_state
.items():
100 with m
.Case(x
.value
):
101 m
.d
.comb
+= self
.state_o
.data
.eq(v
)
102 m
.d
.comb
+= self
.state_o
.ok
.eq(1)
106 class DecodeA(Elaboratable
):
107 """DecodeA from instruction
109 decodes register RA, implicit and explicit CSRs
112 def __init__(self
, dec
, op
, regreduce_en
):
113 self
.regreduce_en
= regreduce_en
114 if self
.regreduce_en
:
120 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
121 self
.insn_in
= Signal(32, reset_less
=True)
122 self
.reg_out
= Data(5, name
="reg_a")
123 self
.spr_out
= Data(SPR
, "spr_a")
124 self
.fast_out
= Data(4, "fast_a")
125 self
.state_out
= Data(3, "state_a")
126 self
.sv_nz
= Signal(1)
128 def elaborate(self
, platform
):
133 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
135 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
136 ra
= Signal(5, reset_less
=True)
137 comb
+= ra
.eq(self
.dec
.RA
)
138 with m
.If((self
.sel_in
== In1Sel
.RA
) |
139 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
140 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
141 comb
+= reg
.data
.eq(ra
)
144 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
145 # moved it to 1st position (in1_sel)... because
146 rs
= Signal(5, reset_less
=True)
147 comb
+= rs
.eq(self
.dec
.RS
)
148 with m
.If(self
.sel_in
== In1Sel
.RS
):
149 comb
+= reg
.data
.eq(rs
)
152 # select Register FRA field,
153 fra
= Signal(5, reset_less
=True)
154 comb
+= fra
.eq(self
.dec
.FRA
)
155 with m
.If(self
.sel_in
== In1Sel
.FRA
):
156 comb
+= reg
.data
.eq(fra
)
159 # select Register FRS field,
160 frs
= Signal(5, reset_less
=True)
161 comb
+= frs
.eq(self
.dec
.FRS
)
162 with m
.If(self
.sel_in
== In1Sel
.FRS
):
163 comb
+= reg
.data
.eq(frs
)
166 # decode Fast-SPR based on instruction type
167 with m
.Switch(op
.internal_op
):
169 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
170 with m
.Case(MicrOp
.OP_BC
):
171 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
173 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
174 comb
+= self
.fast_out
.ok
.eq(1)
175 with m
.Case(MicrOp
.OP_BCREG
):
176 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
177 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
178 with m
.If(xo9
& ~xo5
):
180 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
181 comb
+= self
.fast_out
.ok
.eq(1)
183 # MFSPR move from SPRs
184 with m
.Case(MicrOp
.OP_MFSPR
):
185 spr
= Signal(10, reset_less
=True)
186 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
187 comb
+= sprmap
.spr_i
.eq(spr
)
188 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
189 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
190 comb
+= self
.state_out
.eq(sprmap
.state_o
)
195 class DecodeAImm(Elaboratable
):
196 """DecodeA immediate from instruction
198 decodes register RA, whether immediate-zero, implicit and
199 explicit CSRs. SVP64 mode requires 2 extra bits
202 def __init__(self
, dec
):
204 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
205 self
.immz_out
= Signal(reset_less
=True)
206 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
208 def elaborate(self
, platform
):
212 # zero immediate requested
213 ra
= Signal(5, reset_less
=True)
214 comb
+= ra
.eq(self
.dec
.RA
)
215 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
216 (ra
== Const(0, 5)) &
217 (self
.sv_nz
== Const(0, 1))):
218 comb
+= self
.immz_out
.eq(1)
223 class DecodeB(Elaboratable
):
224 """DecodeB from instruction
226 decodes register RB, different forms of immediate (signed, unsigned),
227 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
228 by industry-standard convention, "lane 2" is where fully-decoded
229 immediates are muxed in.
232 def __init__(self
, dec
, op
):
235 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
236 self
.insn_in
= Signal(32, reset_less
=True)
237 self
.reg_out
= Data(7, "reg_b")
238 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
239 self
.fast_out
= Data(4, "fast_b")
241 def elaborate(self
, platform
):
247 # select Register B field
248 with m
.Switch(self
.sel_in
):
249 with m
.Case(In2Sel
.FRB
):
250 comb
+= reg
.data
.eq(self
.dec
.FRB
)
252 with m
.Case(In2Sel
.RB
):
253 comb
+= reg
.data
.eq(self
.dec
.RB
)
255 with m
.Case(In2Sel
.RS
):
256 # for M-Form shiftrot
257 comb
+= reg
.data
.eq(self
.dec
.RS
)
260 # decode SPR2 based on instruction type
261 # BCREG implicitly uses LR or TAR for 2nd reg
262 # CTR however is already in fast_spr1 *not* 2.
263 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
264 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
265 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
267 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
268 comb
+= self
.fast_out
.ok
.eq(1)
270 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
271 comb
+= self
.fast_out
.ok
.eq(1)
276 class DecodeBImm(Elaboratable
):
277 """DecodeB immediate from instruction
280 def __init__(self
, dec
):
282 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
283 self
.imm_out
= Data(64, "imm_b")
285 def elaborate(self
, platform
):
289 # select Register B Immediate
290 with m
.Switch(self
.sel_in
):
291 with m
.Case(In2Sel
.CONST_UI
): # unsigned
292 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
293 comb
+= self
.imm_out
.ok
.eq(1)
294 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
295 si
= Signal(16, reset_less
=True)
296 comb
+= si
.eq(self
.dec
.SI
)
297 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
298 comb
+= self
.imm_out
.ok
.eq(1)
299 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
300 si_hi
= Signal(32, reset_less
=True)
301 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
302 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
303 comb
+= self
.imm_out
.ok
.eq(1)
304 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
305 ui
= Signal(16, reset_less
=True)
306 comb
+= ui
.eq(self
.dec
.UI
)
307 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
308 comb
+= self
.imm_out
.ok
.eq(1)
309 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
310 li
= Signal(26, reset_less
=True)
311 comb
+= li
.eq(self
.dec
.LI
<< 2)
312 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
313 comb
+= self
.imm_out
.ok
.eq(1)
314 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
315 bd
= Signal(16, reset_less
=True)
316 comb
+= bd
.eq(self
.dec
.BD
<< 2)
317 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
318 comb
+= self
.imm_out
.ok
.eq(1)
319 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
320 ds
= Signal(16, reset_less
=True)
321 comb
+= ds
.eq(self
.dec
.DS
<< 2)
322 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
323 comb
+= self
.imm_out
.ok
.eq(1)
324 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
325 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
326 comb
+= self
.imm_out
.ok
.eq(1)
327 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
328 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
329 comb
+= self
.imm_out
.ok
.eq(1)
330 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
331 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
332 comb
+= self
.imm_out
.ok
.eq(1)
333 with m
.Case(In2Sel
.CONST_XBI
): # unsigned - for grevi
334 comb
+= self
.imm_out
.data
.eq(self
.dec
.FormXB
.XBI
)
335 comb
+= self
.imm_out
.ok
.eq(1)
340 class DecodeC(Elaboratable
):
341 """DecodeC from instruction
343 decodes register RC. this is "lane 3" into some CompUnits (not many)
346 def __init__(self
, dec
, op
):
349 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
350 self
.insn_in
= Signal(32, reset_less
=True)
351 self
.reg_out
= Data(5, "reg_c")
353 def elaborate(self
, platform
):
359 # select Register C field
360 with m
.Switch(self
.sel_in
):
361 with m
.Case(In3Sel
.RB
):
362 # for M-Form shiftrot
363 comb
+= reg
.data
.eq(self
.dec
.RB
)
365 with m
.Case(In3Sel
.FRS
):
366 comb
+= reg
.data
.eq(self
.dec
.FRS
)
368 with m
.Case(In3Sel
.FRC
):
369 comb
+= reg
.data
.eq(self
.dec
.FRC
)
371 with m
.Case(In3Sel
.RS
):
372 comb
+= reg
.data
.eq(self
.dec
.RS
)
374 with m
.Case(In3Sel
.RC
):
375 comb
+= reg
.data
.eq(self
.dec
.RC
)
377 with m
.Case(In3Sel
.RT
):
378 # for TLI-form ternlogi
379 comb
+= reg
.data
.eq(self
.dec
.RT
)
385 class DecodeOut(Elaboratable
):
386 """DecodeOut from instruction
388 decodes output register RA, RT or SPR
391 def __init__(self
, dec
, op
, regreduce_en
):
392 self
.regreduce_en
= regreduce_en
393 if self
.regreduce_en
:
399 self
.sel_in
= Signal(OutSel
, reset_less
=True)
400 self
.insn_in
= Signal(32, reset_less
=True)
401 self
.reg_out
= Data(5, "reg_o")
402 self
.spr_out
= Data(SPR
, "spr_o")
403 self
.fast_out
= Data(4, "fast_o")
404 self
.state_out
= Data(3, "state_o")
406 def elaborate(self
, platform
):
409 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
413 # select Register out field
414 with m
.Switch(self
.sel_in
):
415 with m
.Case(OutSel
.FRT
):
416 comb
+= reg
.data
.eq(self
.dec
.FRT
)
418 with m
.Case(OutSel
.RT
):
419 comb
+= reg
.data
.eq(self
.dec
.RT
)
421 with m
.Case(OutSel
.RA
):
422 comb
+= reg
.data
.eq(self
.dec
.RA
)
424 with m
.Case(OutSel
.SPR
):
425 spr
= Signal(10, reset_less
=True)
426 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
427 # MFSPR move to SPRs - needs mapping
428 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
429 comb
+= sprmap
.spr_i
.eq(spr
)
430 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
431 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
432 comb
+= self
.state_out
.eq(sprmap
.state_o
)
435 with m
.Switch(op
.internal_op
):
437 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
438 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
439 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
441 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
442 comb
+= self
.fast_out
.ok
.eq(1)
444 # RFID 1st spr (fast)
445 with m
.Case(MicrOp
.OP_RFID
):
446 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
447 comb
+= self
.fast_out
.ok
.eq(1)
452 class DecodeOut2(Elaboratable
):
453 """DecodeOut2 from instruction
455 decodes output registers (2nd one). note that RA is *implicit* below,
456 which now causes problems with SVP64
458 TODO: SVP64 is a little more complex, here. svp64 allows extending
459 by one more destination by having one more EXTRA field. RA-as-src
460 is not the same as RA-as-dest. limited in that it's the same first
461 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
462 for operations that have src-as-dest: mostly this is LD/ST-with-update
463 but there are others.
466 def __init__(self
, dec
, op
):
469 self
.sel_in
= Signal(OutSel
, reset_less
=True)
470 self
.svp64_fft_mode
= Signal(reset_less
=True) # SVP64 FFT mode
471 self
.lk
= Signal(reset_less
=True)
472 self
.insn_in
= Signal(32, reset_less
=True)
473 self
.reg_out
= Data(5, "reg_o2")
474 self
.fp_madd_en
= Signal(reset_less
=True) # FFT instruction detected
475 self
.fast_out
= Data(4, "fast_o2")
476 self
.fast_out3
= Data(4, "fast_o3")
478 def elaborate(self
, platform
):
482 #m.submodules.svdec = svdec = SVP64RegExtra()
484 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
485 #reg = Signal(5, reset_less=True)
487 if hasattr(op
, "upd"):
488 # update mode LD/ST uses read-reg A also as an output
489 with m
.If(op
.upd
== LDSTMode
.update
):
490 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
491 comb
+= self
.reg_out
.ok
.eq(1)
493 # B, BC or BCREG: potential implicit register (LR) output
494 # these give bl, bcl, bclrl, etc.
495 with m
.Switch(op
.internal_op
):
497 # BC* implicit register (LR)
498 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
499 with m
.If(self
.lk
): # "link" mode
500 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
501 comb
+= self
.fast_out
.ok
.eq(1)
503 # RFID 2nd and 3rd spr (fast)
504 with m
.Case(MicrOp
.OP_RFID
):
505 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
506 comb
+= self
.fast_out
.ok
.eq(1)
507 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
508 comb
+= self
.fast_out3
.ok
.eq(1)
510 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
511 # will be offset by VL in hardware
512 # with m.Case(MicrOp.OP_FP_MADD):
513 with m
.If(self
.svp64_fft_mode
):
514 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
)
515 comb
+= self
.reg_out
.ok
.eq(1)
516 comb
+= self
.fp_madd_en
.eq(1)
521 class DecodeRC(Elaboratable
):
522 """DecodeRc from instruction
524 decodes Record bit Rc
527 def __init__(self
, dec
):
529 self
.sel_in
= Signal(RC
, reset_less
=True)
530 self
.insn_in
= Signal(32, reset_less
=True)
531 self
.rc_out
= Data(1, "rc")
533 def elaborate(self
, platform
):
537 # select Record bit out field
538 with m
.Switch(self
.sel_in
):
540 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
541 comb
+= self
.rc_out
.ok
.eq(1)
543 comb
+= self
.rc_out
.data
.eq(1)
544 comb
+= self
.rc_out
.ok
.eq(1)
545 with m
.Case(RC
.NONE
):
546 comb
+= self
.rc_out
.data
.eq(0)
547 comb
+= self
.rc_out
.ok
.eq(1)
552 class DecodeOE(Elaboratable
):
553 """DecodeOE from instruction
555 decodes OE field: uses RC decode detection which might not be good
557 -- For now, use "rc" in the decode table to decide whether oe exists.
558 -- This is not entirely correct architecturally: For mulhd and
559 -- mulhdu, the OE field is reserved. It remains to be seen what an
560 -- actual POWER9 does if we set it on those instructions, for now we
561 -- test that further down when assigning to the multiplier oe input.
564 def __init__(self
, dec
, op
):
567 self
.sel_in
= Signal(RC
, reset_less
=True)
568 self
.insn_in
= Signal(32, reset_less
=True)
569 self
.oe_out
= Data(1, "oe")
571 def elaborate(self
, platform
):
576 with m
.Switch(op
.internal_op
):
578 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
580 # XXX ARGH! ignoring OE causes incompatibility with microwatt
581 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
582 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
583 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
584 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
585 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
586 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
587 MicrOp
.OP_EXTSWSLI
, MicrOp
.OP_GREV
, MicrOp
.OP_TERNLOG
):
590 # all other ops decode OE field
592 # select OE bit out field
593 with m
.Switch(self
.sel_in
):
595 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
596 comb
+= self
.oe_out
.ok
.eq(1)
601 class DecodeCRIn(Elaboratable
):
602 """Decodes input CR from instruction
604 CR indices - insn fields - (not the data *in* the CR) require only 3
605 bits because they refer to CR0-CR7
608 def __init__(self
, dec
, op
):
611 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
612 self
.insn_in
= Signal(32, reset_less
=True)
613 self
.cr_bitfield
= Data(3, "cr_bitfield")
614 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
615 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
616 self
.whole_reg
= Data(8, "cr_fxm")
617 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
619 def elaborate(self
, platform
):
623 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
626 # zero-initialisation
627 comb
+= self
.cr_bitfield
.ok
.eq(0)
628 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
629 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
630 comb
+= self
.whole_reg
.ok
.eq(0)
631 comb
+= self
.sv_override
.eq(0)
633 # select the relevant CR bitfields
634 with m
.Switch(self
.sel_in
):
635 with m
.Case(CRInSel
.NONE
):
636 pass # No bitfield activated
637 with m
.Case(CRInSel
.CR0
):
638 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
639 comb
+= self
.cr_bitfield
.ok
.eq(1)
640 comb
+= self
.sv_override
.eq(1)
641 with m
.Case(CRInSel
.CR1
):
642 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
643 comb
+= self
.cr_bitfield
.ok
.eq(1)
644 comb
+= self
.sv_override
.eq(2)
645 with m
.Case(CRInSel
.BI
):
646 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
647 comb
+= self
.cr_bitfield
.ok
.eq(1)
648 with m
.Case(CRInSel
.BFA
):
649 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
650 comb
+= self
.cr_bitfield
.ok
.eq(1)
651 with m
.Case(CRInSel
.BA_BB
):
652 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
653 comb
+= self
.cr_bitfield
.ok
.eq(1)
654 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
655 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
656 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
657 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
658 with m
.Case(CRInSel
.BC
):
659 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
660 comb
+= self
.cr_bitfield
.ok
.eq(1)
661 with m
.Case(CRInSel
.WHOLE_REG
):
662 comb
+= self
.whole_reg
.ok
.eq(1)
663 move_one
= Signal(reset_less
=True)
664 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
665 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
666 # must one-hot the FXM field
667 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
668 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
670 # otherwise use all of it
671 comb
+= self
.whole_reg
.data
.eq(0xff)
676 class DecodeCROut(Elaboratable
):
677 """Decodes input CR from instruction
679 CR indices - insn fields - (not the data *in* the CR) require only 3
680 bits because they refer to CR0-CR7
683 def __init__(self
, dec
, op
):
686 self
.rc_in
= Signal(reset_less
=True)
687 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
688 self
.insn_in
= Signal(32, reset_less
=True)
689 self
.cr_bitfield
= Data(3, "cr_bitfield")
690 self
.whole_reg
= Data(8, "cr_fxm")
691 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
693 def elaborate(self
, platform
):
697 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
700 comb
+= self
.cr_bitfield
.ok
.eq(0)
701 comb
+= self
.whole_reg
.ok
.eq(0)
702 comb
+= self
.sv_override
.eq(0)
704 # please note these MUST match (setting of cr_bitfield.ok) exactly
705 # with write_cr0 below in PowerDecoder2. the reason it's separated
706 # is to avoid having duplicate copies of DecodeCROut in multiple
707 # PowerDecoderSubsets. register decoding should be a one-off in
708 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
710 with m
.Switch(self
.sel_in
):
711 with m
.Case(CROutSel
.NONE
):
712 pass # No bitfield activated
713 with m
.Case(CROutSel
.CR0
):
714 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
715 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
716 comb
+= self
.sv_override
.eq(1)
717 with m
.Case(CROutSel
.CR1
):
718 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
719 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
720 comb
+= self
.sv_override
.eq(2)
721 with m
.Case(CROutSel
.BF
):
722 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
723 comb
+= self
.cr_bitfield
.ok
.eq(1)
724 with m
.Case(CROutSel
.BT
):
725 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
726 comb
+= self
.cr_bitfield
.ok
.eq(1)
727 with m
.Case(CROutSel
.WHOLE_REG
):
728 comb
+= self
.whole_reg
.ok
.eq(1)
729 move_one
= Signal(reset_less
=True)
730 comb
+= move_one
.eq(self
.insn_in
[20])
731 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
733 # must one-hot the FXM field
734 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
735 with m
.If(ppick
.en_o
):
736 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
738 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
740 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
742 # otherwise use all of it
743 comb
+= self
.whole_reg
.data
.eq(0xff)
748 # dictionary of Input Record field names that, if they exist,
749 # will need a corresponding CSV Decoder file column (actually, PowerOp)
750 # to be decoded (this includes the single bit names)
751 record_names
= {'insn_type': 'internal_op',
752 'fn_unit': 'function_unit',
753 'SV_Ptype': 'SV_Ptype',
757 'imm_data': 'in2_sel',
758 'invert_in': 'inv_a',
759 'invert_out': 'inv_out',
762 'output_carry': 'cry_out',
763 'input_carry': 'cry_in',
764 'is_32bit': 'is_32b',
767 'data_len': 'ldst_len',
769 'byte_reverse': 'br',
770 'sign_extend': 'sgn_ext',
775 class PowerDecodeSubset(Elaboratable
):
776 """PowerDecodeSubset: dynamic subset decoder
778 only fields actually requested are copied over. hence, "subset" (duh).
781 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
782 svp64_en
=True, regreduce_en
=False):
784 self
.svp64_en
= svp64_en
785 self
.regreduce_en
= regreduce_en
787 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
788 self
.use_svp64_ldst_dec
= Signal() # must use LDST decoder
789 self
.use_svp64_fft
= Signal() # FFT Mode
790 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
791 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
792 # set these to the predicate mask bits needed for the ALU
793 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
794 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
795 self
.sv_a_nz
= Signal(1)
798 self
.fn_name
= fn_name
800 opkls
= Decode2ToOperand
801 self
.do
= opkls(fn_name
)
803 col_subset
= self
.get_col_subset(self
.do
)
804 row_subset
= self
.rowsubsetfn
809 # "conditions" for Decoders, to enable some weird and wonderful
810 # alternatives. useful for PCR (Program Compatibility Register)
811 # amongst other things
813 conditions
= {'SVP64BREV': self
.use_svp64_ldst_dec
,
814 'SVP64FFT': self
.use_svp64_fft
,
819 # only needed for "main" PowerDecode2
821 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
822 regreduce_en
=regreduce_en
)
824 # create decoder if one not already given
826 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
827 row_subset
=row_subset
,
828 conditions
=conditions
)
831 # set up a copy of the PowerOp
832 self
.op
= PowerOp
.like(self
.dec
.op
)
834 # state information needed by the Decoder
836 state
= CoreState("dec2")
839 def get_col_subset(self
, do
):
840 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
841 for k
, v
in record_names
.items():
844 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
847 def rowsubsetfn(self
, opcode
, row
):
848 """select per-Function-Unit subset of opcodes to be processed
850 normally this just looks at the "unit" column. MMU is different
851 in that it processes specific SPR set/get operations that the SPR
854 return (row
['unit'] == self
.fn_name
or
855 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
856 # by the MMU pipeline so we direct those opcodes to MMU **AND**
857 # SPR pipelines, then selectively weed out the SPRs that should
858 # or should not not go to each pipeline, further down.
859 # really this should be done by modifying the CSV syntax
860 # to support multiple tasks (unit column multiple entries)
861 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
862 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
863 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
867 ports
= self
.dec
.ports() + self
.e
.ports()
869 ports
+= self
.sv_rm
.ports()
870 ports
.append(self
.is_svp64_mode
)
871 ports
.append(self
.use_svp64_ldst_dec
)
872 ports
.append(self
.use_svp64_fft
)
875 def needs_field(self
, field
, op_field
):
880 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
882 def do_get(self
, field
, final
=False):
883 if final
or self
.final
:
887 return getattr(do
, field
, None)
889 def do_copy(self
, field
, val
, final
=False):
890 df
= self
.do_get(field
, final
)
891 if df
is not None and val
is not None:
895 def op_get(self
, op_field
):
896 return getattr(self
.op
, op_field
, None)
898 def elaborate(self
, platform
):
899 if self
.regreduce_en
:
906 op
, do
= self
.dec
.op
, self
.do
907 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
908 # fill in for a normal instruction (not an exception)
909 # copy over if non-exception, non-privileged etc. is detected
911 if self
.fn_name
is None:
914 name
= self
.fn_name
+ "tmp"
915 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
916 regreduce_en
=self
.regreduce_en
)
918 # set up submodule decoders
919 m
.submodules
.dec
= dec
= self
.dec
920 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
921 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
924 # and SVP64 RM mode decoder
925 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
927 # copy op from decoder
928 comb
+= self
.op
.eq(self
.dec
.op
)
930 # copy instruction through...
931 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
932 comb
+= i
.eq(self
.dec
.opcode_in
)
934 # ...and subdecoders' input fields
935 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
936 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
939 comb
+= self
.do_copy("msr", msr
)
940 comb
+= self
.do_copy("cia", cia
)
941 comb
+= self
.do_copy("svstate", svstate
)
943 # set up instruction type
944 # no op: defaults to OP_ILLEGAL
945 internal_op
= self
.op_get("internal_op")
946 comb
+= self
.do_copy("insn_type", internal_op
)
948 # function unit for decoded instruction: requires minor redirect
950 fn
= self
.op_get("function_unit")
951 spr
= Signal(10, reset_less
=True)
952 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
954 # Microwatt doesn't implement the partition table
955 # instead has PRTBL register (SPR) to point to process table
957 is_mmu_spr
= Signal()
958 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
959 (internal_op
== MicrOp
.OP_MFSPR
))
960 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
961 (spr
== SPR
.DAR
.value
) |
962 (spr
== SPR
.PRTBL
.value
) |
963 (spr
== SPR
.PIDR
.value
))
964 # MMU must receive MMU SPRs
965 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
966 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
967 comb
+= self
.do_copy("insn_type", internal_op
)
968 # SPR pipe must *not* receive MMU SPRs
969 with m
.Elif(is_spr_mv
& (fn
== Function
.MMU
) & ~is_mmu_spr
):
970 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
971 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
974 comb
+= self
.do_copy("fn_unit", fn
)
977 if self
.needs_field("zero_a", "in1_sel"):
978 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
979 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
980 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
981 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
982 if self
.needs_field("imm_data", "in2_sel"):
983 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
984 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
985 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
988 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
990 # OE only enabled when SVP64 not active
991 with m
.If(~self
.is_svp64_mode
):
992 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
994 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
996 # CR in/out - note: these MUST match with what happens in
998 rc_out
= self
.dec_rc
.rc_out
.data
999 with m
.Switch(self
.op_get("cr_out")):
1000 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
1001 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
1002 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
1003 comb
+= self
.do_copy("write_cr0", 1)
1005 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1006 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1009 # connect up SVP64 RM Mode decoding. however... we need a shorter
1010 # path, for the LDST bit-reverse detection. so perform partial
1011 # decode when SVP64 is detected. then, bit-reverse mode can be
1012 # quickly determined, and the Decoder result MUXed over to
1013 # the alternative decoder, svdecldst. what a mess... *sigh*
1014 sv_ptype
= self
.op_get("SV_Ptype")
1015 fn
= self
.op_get("function_unit")
1016 # detect major opcode for LDs: include 58 here. from CSV files.
1017 # BLECH! TODO: these should be done using "mini decoders",
1018 # using row and column subsets
1019 is_major_ld
= Signal()
1020 # bits... errr... MSB0 0..5 which is 26:32 python
1022 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1023 comb
+= is_major_ld
.eq((major
== 34) |
(major
== 35) |
1024 (major
== 50) |
(major
== 51) |
1025 (major
== 48) |
(major
== 49) |
1026 (major
== 42) |
(major
== 43) |
1027 (major
== 40) |
(major
== 41) |
1028 (major
== 32) |
(major
== 33) |
1030 with m
.If(self
.is_svp64_mode
& is_major_ld
):
1031 # straight-up: "it's a LD". this gives enough info
1032 # for SVP64 RM Mode decoding to detect LD/ST, and
1033 # consequently detect the SHIFT mode. sigh
1034 comb
+= rm_dec
.fn_in
.eq(Function
.LDST
)
1036 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1037 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1038 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1039 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1040 if self
.needs_field("imm_data", "in2_sel"):
1041 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1042 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1044 # main PowerDecoder2 determines if different SVP64 modes enabled
1046 # if shift mode requested
1047 shiftmode
= rm_dec
.ldstmode
== SVP64LDSTmode
.SHIFT
1048 comb
+= self
.use_svp64_ldst_dec
.eq(shiftmode
)
1049 # detect if SVP64 FFT mode enabled (really bad hack),
1050 # exclude fcfids and others
1051 # XXX this is a REALLY bad hack, REALLY has to be done better.
1052 # likely with a sub-decoder.
1053 xo5
= Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX
1054 comb
+= xo5
.eq(self
.dec
.opcode_in
[5])
1055 xo
= Signal(5) # 5 bits from Minor 59 fcfids == 0b01110
1056 comb
+= xo
.eq(self
.dec
.opcode_in
[1:6])
1057 comb
+= self
.use_svp64_fft
.eq((major
== 59) & (xo5
== 0b0) &
1060 # decoded/selected instruction flags
1061 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1062 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1063 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1064 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1065 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1066 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1067 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1068 lk
= self
.op_get("lk")
1071 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1073 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1074 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1075 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1076 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1078 # copy over SVP64 input record fields (if they exist)
1080 # TODO, really do we have to do these explicitly?? sigh
1081 # for (field, _) in sv_input_record_layout:
1082 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1083 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1084 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1085 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1086 # these get set up based on incoming mask bits. TODO:
1087 # pass in multiple bits (later, when SIMD backends are enabled)
1088 with m
.If(self
.rm_dec
.pred_sz
):
1089 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1090 with m
.If(self
.rm_dec
.pred_dz
):
1091 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1096 class PowerDecode2(PowerDecodeSubset
):
1097 """PowerDecode2: the main instruction decoder.
1099 whilst PowerDecode is responsible for decoding the actual opcode, this
1100 module encapsulates further specialist, sparse information and
1101 expansion of fields that is inconvenient to have in the CSV files.
1102 for example: the encoding of the immediates, which are detected
1103 and expanded out to their full value from an annotated (enum)
1106 implicit register usage is also set up, here. for example: OP_BC
1107 requires implicitly reading CTR, OP_RFID requires implicitly writing
1110 in addition, PowerDecoder2 is responsible for detecting whether
1111 instructions are illegal (or privileged) or not, and instead of
1112 just leaving at that, *replacing* the instruction to execute with
1113 a suitable alternative (trap).
1115 LDSTExceptions are done the cycle _after_ they're detected (after
1116 they come out of LDSTCompUnit). basically despite the instruction
1117 being decoded, the results of the decode are completely ignored
1118 and "exception.happened" used to set the "actual" instruction to
1119 "OP_TRAP". the LDSTException data structure gets filled in,
1120 in the CompTrapOpSubset and that's what it fills in SRR.
1122 to make this work, TestIssuer must notice "exception.happened"
1123 after the (failed) LD/ST and copies the LDSTException info from
1124 the output, into here (PowerDecoder2). without incrementing PC.
1126 also instr_fault works the same way: the instruction is "rewritten"
1127 so that the "fake" op that gets created is OP_FETCH_FAILED
1130 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1131 state
=None, svp64_en
=True, regreduce_en
=False):
1132 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1134 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1135 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1138 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1139 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1140 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1141 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1142 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1143 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1144 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1145 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1146 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1147 self
.in1_step
= Signal(7, name
="reg_a_step")
1148 self
.in2_step
= Signal(7, name
="reg_b_step")
1149 self
.in3_step
= Signal(7, name
="reg_c_step")
1150 self
.o_step
= Signal(7, name
="reg_o_step")
1151 self
.o2_step
= Signal(7, name
="reg_o2_step")
1152 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1153 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1154 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1155 self
.loop_continue
= Signal(1, name
="loop_continue")
1157 self
.no_in_vec
= Const(1, 1)
1158 self
.no_out_vec
= Const(1, 1)
1159 self
.loop_continue
= Const(0, 1)
1161 def get_col_subset(self
, opkls
):
1162 subset
= super().get_col_subset(opkls
)
1163 subset
.add("asmcode")
1164 subset
.add("in1_sel")
1165 subset
.add("in2_sel")
1166 subset
.add("in3_sel")
1167 subset
.add("out_sel")
1169 subset
.add("sv_in1")
1170 subset
.add("sv_in2")
1171 subset
.add("sv_in3")
1172 subset
.add("sv_out")
1173 subset
.add("sv_out2")
1174 subset
.add("sv_cr_in")
1175 subset
.add("sv_cr_out")
1176 subset
.add("SV_Etype")
1177 subset
.add("SV_Ptype")
1178 # from SVP64RMModeDecode
1179 for (field
, _
) in sv_input_record_layout
:
1182 subset
.add("internal_op")
1186 def elaborate(self
, platform
):
1187 m
= super().elaborate(platform
)
1190 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1191 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1192 rc_out
= self
.dec_rc
.rc_out
.data
1196 # fill in for a normal instruction (not an exception)
1197 # copy over if non-exception, non-privileged etc. is detected
1199 # set up submodule decoders
1200 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1201 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1202 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1203 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1204 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1205 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1206 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1207 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1210 # and SVP64 Extra decoders
1211 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1212 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1213 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1214 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1215 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1216 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1217 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1218 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1219 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1221 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1222 self
.crout_svdec
= crout_svdec
1223 self
.crin_svdec
= crin_svdec
1225 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1226 reg
= Signal(5, reset_less
=True)
1228 # copy instruction through...
1229 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1230 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1231 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1232 comb
+= i
.eq(self
.dec
.opcode_in
)
1235 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1236 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1237 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1240 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1241 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1243 # ...and subdecoders' input fields
1244 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1245 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1246 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1247 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1248 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1250 comb
+= dec_o2
.svp64_fft_mode
.eq(self
.use_svp64_fft
)
1251 if hasattr(do
, "lk"):
1252 comb
+= dec_o2
.lk
.eq(do
.lk
)
1255 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1256 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1257 # which in turn were auto-generated by sv_analysis.py
1258 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1263 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1264 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1267 # CR in - selection slightly different due to shared CR field sigh
1268 cr_a_idx
= Signal(SVEXTRA
)
1269 cr_b_idx
= Signal(SVEXTRA
)
1271 # these change slightly, when decoding BA/BB. really should have
1272 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1273 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1274 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1275 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1276 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1277 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1279 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1280 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1281 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1283 # indices are slightly different, BA/BB mess sorted above
1284 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1285 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1287 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1289 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1290 vl
= Signal
.like(self
.state
.svstate
.vl
)
1291 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1292 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1293 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1294 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1295 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1297 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1298 in3_step
= self
.in3_step
1299 o_step
, o2_step
= self
.o_step
, self
.o2_step
1301 # registers a, b, c and out and out2 (LD/ST EA)
1302 sv_etype
= self
.op_get("SV_Etype")
1303 for i
, stuff
in enumerate((
1304 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1305 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1306 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1307 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1308 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1309 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1310 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1311 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1312 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1313 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1314 # *screaam* FFT mode needs an extra offset for RB
1315 # similar to FRS/FRT (below). all of this needs cleanup
1316 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1319 # when FFT sv.ffmadd detected, and REMAP not in use,
1320 # automagically add on an extra offset to RB.
1321 # however when REMAP is active, the FFT REMAP
1322 # schedule takes care of this offset.
1323 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1324 with m
.If(~self
.remap_active
[i
]):
1325 with m
.If(svdec
.isvec
):
1326 comb
+= offs
.eq(vl
) # VL for Vectors
1327 # detect if Vectorised: add srcstep/dststep if yes.
1328 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1329 with m
.If(svdec
.isvec
):
1330 selectstep
= dststep
if out
else srcstep
1331 step
= Signal(7, name
="step_%s" % rname
.lower())
1332 with m
.If(self
.remap_active
[i
]):
1333 comb
+= step
.eq(remapstep
)
1335 comb
+= step
.eq(selectstep
)
1336 # reverse gear goes the opposite way
1337 with m
.If(self
.rm_dec
.reverse_gear
):
1338 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
+(vl
-1-step
))
1340 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1342 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1344 # SVP64 in/out fields
1345 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1346 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1347 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1348 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1350 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1351 # XXX TODO - work out where this should come from. the problem is
1352 # that LD-with-update is implied (computed from "is instruction in
1353 # "update mode" rather than specified cleanly as its own CSV column
1355 # output reg-is-vectorised (and when no in/out is vectorised)
1356 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1357 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1358 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1359 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1360 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1362 # urrr... don't ask... the implicit register FRS in FFT mode
1363 # "tracks" FRT exactly except it's offset by VL. rather than
1364 # mess up the above with if-statements, override it here.
1365 # same trick is applied to FRA, above, but it's a lot cleaner, there
1366 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1368 with m
.If(~self
.remap_active
[4]):
1369 with m
.If(o2_svdec
.isvec
):
1370 comb
+= offs
.eq(vl
) # VL for Vectors
1372 comb
+= offs
.eq(1) # add 1 if scalar
1373 svdec
= o_svdec
# yes take source as o_svdec...
1374 with m
.If(svdec
.isvec
):
1375 step
= Signal(7, name
="step_%s" % rname
.lower())
1376 with m
.If(self
.remap_active
[4]):
1377 comb
+= step
.eq(o2_step
)
1379 comb
+= step
.eq(dststep
)
1380 # reverse gear goes the opposite way
1381 with m
.If(self
.rm_dec
.reverse_gear
):
1382 roffs
= offs
+(vl
-1-step
)
1383 comb
+= to_reg
.data
.eq(roffs
+svdec
.reg_out
)
1385 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1387 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1388 # ... but write to *second* output
1389 comb
+= self
.o2_isvec
.eq(svdec
.isvec
)
1390 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1392 # TODO add SPRs here. must be True when *all* are scalar
1393 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1394 crin_svdec
, crin_svdec_b
,
1396 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1397 l
= map(lambda svdec
: svdec
.isvec
, [
1398 o2_svdec
, o_svdec
, crout_svdec
])
1399 # in mapreduce mode, scalar out is *allowed*
1400 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1401 comb
+= self
.no_out_vec
.eq(0)
1404 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1405 # now create a general-purpose "test" as to whether looping
1406 # should continue. this doesn't include predication bit-tests
1407 loop
= self
.loop_continue
1408 with m
.Switch(self
.op_get("SV_Ptype")):
1409 with m
.Case(SVPtype
.P2
.value
):
1411 # TODO: *and cache-inhibited LD/ST!*
1412 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1413 with m
.Case(SVPtype
.P1
.value
):
1414 # single-predication, test relies on dest only
1415 comb
+= loop
.eq(~self
.no_out_vec
)
1417 # not an SV operation, no looping
1420 # condition registers (CR)
1421 for to_reg
, cr
, name
, svdec
, out
in (
1422 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1423 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1424 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1425 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1426 fromreg
= getattr(cr
, name
)
1427 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1428 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1429 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1430 with m
.If(svdec
.isvec
):
1431 # check if this is CR0 or CR1: treated differently
1432 # (does not "listen" to EXTRA2/3 spec for a start)
1433 # also: the CRs start from completely different locations
1434 step
= dststep
if out
else srcstep
1435 with m
.If(cr
.sv_override
== 1): # CR0
1436 offs
= SVP64CROffs
.CR0
1437 comb
+= to_reg
.data
.eq(step
+offs
)
1438 with m
.Elif(cr
.sv_override
== 2): # CR1
1439 offs
= SVP64CROffs
.CR1
1440 comb
+= to_reg
.data
.eq(step
+1)
1442 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1444 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1445 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1447 # sigh must determine if RA is nonzero (7 bit)
1448 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1450 # connect up to/from read/write GPRs
1451 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1452 (e
.read_reg2
, dec_b
.reg_out
),
1453 (e
.read_reg3
, dec_c
.reg_out
),
1454 (e
.write_reg
, dec_o
.reg_out
),
1455 (e
.write_ea
, dec_o2
.reg_out
)):
1456 comb
+= to_reg
.data
.eq(fromreg
.data
)
1457 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1459 # connect up to/from read/write CRs
1460 for to_reg
, cr
, name
in (
1461 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1462 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1463 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1464 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1465 fromreg
= getattr(cr
, name
)
1466 comb
+= to_reg
.data
.eq(fromreg
.data
)
1467 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1470 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1473 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1474 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1476 # Fast regs out including SRR0/1/SVSRR0
1477 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1478 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1479 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1480 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1481 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1482 # and State regs (DEC, TB)
1483 comb
+= e
.read_state1
.eq(dec_a
.state_out
) # DEC/TB
1484 comb
+= e
.write_state1
.eq(dec_o
.state_out
) # DEC/TB
1486 # sigh this is exactly the sort of thing for which the
1487 # decoder is designed to not need. MTSPR, MFSPR and others need
1488 # access to the XER bits. however setting e.oe is not appropriate
1489 internal_op
= self
.op_get("internal_op")
1490 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1491 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1492 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1493 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1494 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1495 comb
+= e
.xer_out
.eq(1)
1497 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1498 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1499 # *DO NOT* call self.trap here. that would reset absolutely
1500 # everything including destroying read of RA and RB.
1501 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1503 ####################
1504 # ok so the instruction's been decoded, blah blah, however
1505 # now we need to determine if it's actually going to go ahead...
1506 # *or* if in fact it's a privileged operation, whether there's
1507 # an external interrupt, etc. etc. this is a simple priority
1508 # if-elif-elif sequence. decrement takes highest priority,
1509 # EINT next highest, privileged operation third.
1511 # check if instruction is privileged
1512 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1514 # different IRQ conditions
1515 ext_irq_ok
= Signal()
1516 dec_irq_ok
= Signal()
1519 ldst_exc
= self
.ldst_exc
1521 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1522 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1523 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1524 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1526 # absolute top priority: check for an instruction failed
1527 with m
.If(self
.instr_fault
):
1528 comb
+= self
.e
.eq(0) # reset eeeeeverything
1529 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1530 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1531 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1532 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1533 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1534 # special override on internal_op, due to being a "fake" op
1535 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1537 # LD/ST exceptions. TestIssuer copies the exception info at us
1538 # after a failed LD/ST.
1539 with m
.Elif(ldst_exc
.happened
):
1540 with m
.If(ldst_exc
.alignment
):
1541 self
.trap(m
, TT
.MEMEXC
, 0x600)
1542 with m
.Elif(ldst_exc
.instr_fault
):
1543 with m
.If(ldst_exc
.segment_fault
):
1544 self
.trap(m
, TT
.MEMEXC
, 0x480)
1546 # pass exception info to trap to create SRR1
1547 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1549 with m
.If(ldst_exc
.segment_fault
):
1550 self
.trap(m
, TT
.MEMEXC
, 0x380)
1552 self
.trap(m
, TT
.MEMEXC
, 0x300)
1554 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1555 with m
.Elif(dec_irq_ok
):
1556 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1558 # external interrupt? only if MSR.EE set
1559 with m
.Elif(ext_irq_ok
):
1560 self
.trap(m
, TT
.EINT
, 0x500)
1562 # privileged instruction trap
1563 with m
.Elif(priv_ok
):
1564 self
.trap(m
, TT
.PRIV
, 0x700)
1566 # illegal instruction must redirect to trap. this is done by
1567 # *overwriting* the decoded instruction and starting again.
1568 # (note: the same goes for interrupts and for privileged operations,
1569 # just with different trapaddr and traptype)
1570 with m
.Elif(illeg_ok
):
1571 # illegal instruction trap
1572 self
.trap(m
, TT
.ILLEG
, 0x700)
1574 # no exception, just copy things to the output
1578 ####################
1579 # follow-up after trap/irq to set up SRR0/1
1581 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1582 # Note: OP_SC could actually be modified to just be a trap
1583 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1584 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1585 # TRAP write fast1 = SRR0
1586 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1587 comb
+= e_out
.write_fast1
.ok
.eq(1)
1588 # TRAP write fast2 = SRR1
1589 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1590 comb
+= e_out
.write_fast2
.ok
.eq(1)
1591 # TRAP write fast2 = SRR1
1592 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1593 comb
+= e_out
.write_fast3
.ok
.eq(1)
1595 # RFID: needs to read SRR0/1
1596 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1597 # TRAP read fast1 = SRR0
1598 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1599 comb
+= e_out
.read_fast1
.ok
.eq(1)
1600 # TRAP read fast2 = SRR1
1601 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1602 comb
+= e_out
.read_fast2
.ok
.eq(1)
1603 # TRAP read fast2 = SVSRR0
1604 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1605 comb
+= e_out
.read_fast3
.ok
.eq(1)
1607 # annoying simulator bug.
1608 # asmcode may end up getting used for perfcounters?
1609 asmcode
= self
.op_get("asmcode")
1610 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1611 comb
+= e_out
.asmcode
.eq(asmcode
)
1615 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1616 """trap: this basically "rewrites" the decoded instruction as a trap
1620 comb
+= e
.eq(0) # reset eeeeeverything
1623 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1624 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1625 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1626 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1627 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1628 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1629 comb
+= self
.do_copy("msr", self
.state
.msr
,
1630 True) # copy of MSR "state"
1631 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1632 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1635 def get_rdflags(m
, e
, cu
):
1636 """returns a sequential list of the read "ok" flags for a given FU.
1637 this list is in order of the CompUnit input specs
1640 for idx
in range(cu
.n_src
):
1641 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1642 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1643 rdl
.append(decinfo
.okflag
)
1648 if __name__
== '__main__':
1649 pdecode
= create_pdecode()
1650 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1651 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1652 with
open("dec2.il", "w") as f
: