81279ca5ec6918400f2b03848b520ebedd36dd24
1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64
,)
29 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
31 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
32 OutSel
, SPRfull
, SPRreduced
,
34 SVEXTRA
, SVEtype
, SVPtype
)
35 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
38 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
39 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
40 FastRegsEnum
, XERRegsEnum
, TT
)
42 from openpower
.state
import CoreState
43 from openpower
.util
import (spr_to_fast
, log
)
46 def decode_spr_num(spr
):
47 return Cat(spr
[5:10], spr
[0:5])
50 def instr_is_priv(m
, op
, insn
):
51 """determines if the instruction is privileged or not
54 is_priv_insn
= Signal(reset_less
=True)
56 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
57 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
58 comb
+= is_priv_insn
.eq(1)
59 with m
.Case(MicrOp
.OP_TLBIE
) : comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
61 with m
.If(insn
[20]): # field XFX.spr[-1] i think
62 comb
+= is_priv_insn
.eq(1)
66 class SPRMap(Elaboratable
):
67 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
70 def __init__(self
, regreduce_en
):
71 self
.regreduce_en
= regreduce_en
77 self
.spr_i
= Signal(10, reset_less
=True)
78 self
.spr_o
= Data(SPR
, name
="spr_o")
79 self
.fast_o
= Data(3, name
="fast_o")
81 def elaborate(self
, platform
):
87 with m
.Switch(self
.spr_i
):
88 for i
, x
in enumerate(SPR
):
90 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
91 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
92 for x
, v
in spr_to_fast
.items():
94 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
95 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
99 class DecodeA(Elaboratable
):
100 """DecodeA from instruction
102 decodes register RA, implicit and explicit CSRs
105 def __init__(self
, dec
, op
, regreduce_en
):
106 self
.regreduce_en
= regreduce_en
107 if self
.regreduce_en
:
113 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
114 self
.insn_in
= Signal(32, reset_less
=True)
115 self
.reg_out
= Data(5, name
="reg_a")
116 self
.spr_out
= Data(SPR
, "spr_a")
117 self
.fast_out
= Data(3, "fast_a")
118 self
.sv_nz
= Signal(1)
120 def elaborate(self
, platform
):
125 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
127 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
128 ra
= Signal(5, reset_less
=True)
129 comb
+= ra
.eq(self
.dec
.RA
)
130 with m
.If((self
.sel_in
== In1Sel
.RA
) |
131 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
132 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
133 comb
+= reg
.data
.eq(ra
)
136 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
137 # moved it to 1st position (in1_sel)... because
138 rs
= Signal(5, reset_less
=True)
139 comb
+= rs
.eq(self
.dec
.RS
)
140 with m
.If(self
.sel_in
== In1Sel
.RS
):
141 comb
+= reg
.data
.eq(rs
)
144 # select Register FRA field,
145 fra
= Signal(5, reset_less
=True)
146 comb
+= fra
.eq(self
.dec
.FRA
)
147 with m
.If(self
.sel_in
== In1Sel
.FRA
):
148 comb
+= reg
.data
.eq(fra
)
151 # select Register FRS field,
152 frs
= Signal(5, reset_less
=True)
153 comb
+= frs
.eq(self
.dec
.FRS
)
154 with m
.If(self
.sel_in
== In1Sel
.FRS
):
155 comb
+= reg
.data
.eq(frs
)
158 # decode Fast-SPR based on instruction type
159 with m
.Switch(op
.internal_op
):
161 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
162 with m
.Case(MicrOp
.OP_BC
):
163 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
165 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
166 comb
+= self
.fast_out
.ok
.eq(1)
167 with m
.Case(MicrOp
.OP_BCREG
):
168 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
169 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
170 with m
.If(xo9
& ~xo5
):
172 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
173 comb
+= self
.fast_out
.ok
.eq(1)
175 # MFSPR move from SPRs
176 with m
.Case(MicrOp
.OP_MFSPR
):
177 spr
= Signal(10, reset_less
=True)
178 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
179 comb
+= sprmap
.spr_i
.eq(spr
)
180 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
181 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
186 class DecodeAImm(Elaboratable
):
187 """DecodeA immediate from instruction
189 decodes register RA, whether immediate-zero, implicit and
190 explicit CSRs. SVP64 mode requires 2 extra bits
193 def __init__(self
, dec
):
195 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
196 self
.immz_out
= Signal(reset_less
=True)
197 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
199 def elaborate(self
, platform
):
203 # zero immediate requested
204 ra
= Signal(5, reset_less
=True)
205 comb
+= ra
.eq(self
.dec
.RA
)
206 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
207 (ra
== Const(0, 5)) &
208 (self
.sv_nz
== Const(0, 1))):
209 comb
+= self
.immz_out
.eq(1)
214 class DecodeB(Elaboratable
):
215 """DecodeB from instruction
217 decodes register RB, different forms of immediate (signed, unsigned),
218 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
219 by industry-standard convention, "lane 2" is where fully-decoded
220 immediates are muxed in.
223 def __init__(self
, dec
, op
):
226 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
227 self
.insn_in
= Signal(32, reset_less
=True)
228 self
.reg_out
= Data(7, "reg_b")
229 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
230 self
.fast_out
= Data(3, "fast_b")
232 def elaborate(self
, platform
):
238 # select Register B field
239 with m
.Switch(self
.sel_in
):
240 with m
.Case(In2Sel
.FRB
):
241 comb
+= reg
.data
.eq(self
.dec
.FRB
)
243 with m
.Case(In2Sel
.RB
):
244 comb
+= reg
.data
.eq(self
.dec
.RB
)
246 with m
.Case(In2Sel
.RS
):
247 # for M-Form shiftrot
248 comb
+= reg
.data
.eq(self
.dec
.RS
)
251 # decode SPR2 based on instruction type
252 # BCREG implicitly uses LR or TAR for 2nd reg
253 # CTR however is already in fast_spr1 *not* 2.
254 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
255 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
256 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
258 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
259 comb
+= self
.fast_out
.ok
.eq(1)
261 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
262 comb
+= self
.fast_out
.ok
.eq(1)
267 class DecodeBImm(Elaboratable
):
268 """DecodeB immediate from instruction
270 def __init__(self
, dec
):
272 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
273 self
.imm_out
= Data(64, "imm_b")
275 def elaborate(self
, platform
):
279 # select Register B Immediate
280 with m
.Switch(self
.sel_in
):
281 with m
.Case(In2Sel
.CONST_UI
): # unsigned
282 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
283 comb
+= self
.imm_out
.ok
.eq(1)
284 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
285 si
= Signal(16, reset_less
=True)
286 comb
+= si
.eq(self
.dec
.SI
)
287 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
288 comb
+= self
.imm_out
.ok
.eq(1)
289 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
290 si_hi
= Signal(32, reset_less
=True)
291 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
292 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
293 comb
+= self
.imm_out
.ok
.eq(1)
294 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
295 ui
= Signal(16, reset_less
=True)
296 comb
+= ui
.eq(self
.dec
.UI
)
297 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
298 comb
+= self
.imm_out
.ok
.eq(1)
299 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
300 li
= Signal(26, reset_less
=True)
301 comb
+= li
.eq(self
.dec
.LI
<< 2)
302 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
303 comb
+= self
.imm_out
.ok
.eq(1)
304 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
305 bd
= Signal(16, reset_less
=True)
306 comb
+= bd
.eq(self
.dec
.BD
<< 2)
307 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
308 comb
+= self
.imm_out
.ok
.eq(1)
309 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
310 ds
= Signal(16, reset_less
=True)
311 comb
+= ds
.eq(self
.dec
.DS
<< 2)
312 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
313 comb
+= self
.imm_out
.ok
.eq(1)
314 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
315 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
316 comb
+= self
.imm_out
.ok
.eq(1)
317 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
318 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
319 comb
+= self
.imm_out
.ok
.eq(1)
320 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
321 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
322 comb
+= self
.imm_out
.ok
.eq(1)
327 class DecodeC(Elaboratable
):
328 """DecodeC from instruction
330 decodes register RC. this is "lane 3" into some CompUnits (not many)
333 def __init__(self
, dec
, op
):
336 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
337 self
.insn_in
= Signal(32, reset_less
=True)
338 self
.reg_out
= Data(5, "reg_c")
340 def elaborate(self
, platform
):
346 # select Register C field
347 with m
.Switch(self
.sel_in
):
348 with m
.Case(In3Sel
.RB
):
349 # for M-Form shiftrot
350 comb
+= reg
.data
.eq(self
.dec
.RB
)
352 with m
.Case(In3Sel
.FRS
):
353 comb
+= reg
.data
.eq(self
.dec
.FRS
)
355 with m
.Case(In3Sel
.FRC
):
356 comb
+= reg
.data
.eq(self
.dec
.FRC
)
358 with m
.Case(In3Sel
.RS
):
359 comb
+= reg
.data
.eq(self
.dec
.RS
)
361 with m
.Case(In3Sel
.RC
):
362 comb
+= reg
.data
.eq(self
.dec
.RC
)
368 class DecodeOut(Elaboratable
):
369 """DecodeOut from instruction
371 decodes output register RA, RT or SPR
374 def __init__(self
, dec
, op
, regreduce_en
):
375 self
.regreduce_en
= regreduce_en
376 if self
.regreduce_en
:
382 self
.sel_in
= Signal(OutSel
, reset_less
=True)
383 self
.insn_in
= Signal(32, reset_less
=True)
384 self
.reg_out
= Data(5, "reg_o")
385 self
.spr_out
= Data(SPR
, "spr_o")
386 self
.fast_out
= Data(3, "fast_o")
388 def elaborate(self
, platform
):
391 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
395 # select Register out field
396 with m
.Switch(self
.sel_in
):
397 with m
.Case(OutSel
.FRT
):
398 comb
+= reg
.data
.eq(self
.dec
.FRT
)
400 with m
.Case(OutSel
.RT
):
401 comb
+= reg
.data
.eq(self
.dec
.RT
)
403 with m
.Case(OutSel
.RA
):
404 comb
+= reg
.data
.eq(self
.dec
.RA
)
406 with m
.Case(OutSel
.SPR
):
407 spr
= Signal(10, reset_less
=True)
408 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
409 # MFSPR move to SPRs - needs mapping
410 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
411 comb
+= sprmap
.spr_i
.eq(spr
)
412 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
413 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
416 with m
.Switch(op
.internal_op
):
418 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
419 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
420 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
422 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
423 comb
+= self
.fast_out
.ok
.eq(1)
425 # RFID 1st spr (fast)
426 with m
.Case(MicrOp
.OP_RFID
):
427 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
428 comb
+= self
.fast_out
.ok
.eq(1)
433 class DecodeOut2(Elaboratable
):
434 """DecodeOut2 from instruction
436 decodes output registers (2nd one). note that RA is *implicit* below,
437 which now causes problems with SVP64
439 TODO: SVP64 is a little more complex, here. svp64 allows extending
440 by one more destination by having one more EXTRA field. RA-as-src
441 is not the same as RA-as-dest. limited in that it's the same first
442 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
443 for operations that have src-as-dest: mostly this is LD/ST-with-update
444 but there are others.
447 def __init__(self
, dec
, op
):
450 self
.sel_in
= Signal(OutSel
, reset_less
=True)
451 self
.lk
= Signal(reset_less
=True)
452 self
.insn_in
= Signal(32, reset_less
=True)
453 self
.reg_out
= Data(5, "reg_o2")
454 self
.fast_out
= Data(3, "fast_o2")
455 self
.fast_out3
= Data(3, "fast_o3")
457 def elaborate(self
, platform
):
461 #m.submodules.svdec = svdec = SVP64RegExtra()
463 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
464 #reg = Signal(5, reset_less=True)
466 if hasattr(op
, "upd"):
467 # update mode LD/ST uses read-reg A also as an output
468 with m
.If(op
.upd
== LDSTMode
.update
):
469 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
470 comb
+= self
.reg_out
.ok
.eq(1)
472 # B, BC or BCREG: potential implicit register (LR) output
473 # these give bl, bcl, bclrl, etc.
474 with m
.Switch(op
.internal_op
):
476 # BC* implicit register (LR)
477 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
478 with m
.If(self
.lk
): # "link" mode
479 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
480 comb
+= self
.fast_out
.ok
.eq(1)
482 # RFID 2nd and 3rd spr (fast)
483 with m
.Case(MicrOp
.OP_RFID
):
484 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
485 comb
+= self
.fast_out
.ok
.eq(1)
486 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
487 comb
+= self
.fast_out3
.ok
.eq(1)
492 class DecodeRC(Elaboratable
):
493 """DecodeRc from instruction
495 decodes Record bit Rc
498 def __init__(self
, dec
):
500 self
.sel_in
= Signal(RC
, reset_less
=True)
501 self
.insn_in
= Signal(32, reset_less
=True)
502 self
.rc_out
= Data(1, "rc")
504 def elaborate(self
, platform
):
508 # select Record bit out field
509 with m
.Switch(self
.sel_in
):
511 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
512 comb
+= self
.rc_out
.ok
.eq(1)
514 comb
+= self
.rc_out
.data
.eq(1)
515 comb
+= self
.rc_out
.ok
.eq(1)
516 with m
.Case(RC
.NONE
):
517 comb
+= self
.rc_out
.data
.eq(0)
518 comb
+= self
.rc_out
.ok
.eq(1)
523 class DecodeOE(Elaboratable
):
524 """DecodeOE from instruction
526 decodes OE field: uses RC decode detection which might not be good
528 -- For now, use "rc" in the decode table to decide whether oe exists.
529 -- This is not entirely correct architecturally: For mulhd and
530 -- mulhdu, the OE field is reserved. It remains to be seen what an
531 -- actual POWER9 does if we set it on those instructions, for now we
532 -- test that further down when assigning to the multiplier oe input.
535 def __init__(self
, dec
, op
):
538 self
.sel_in
= Signal(RC
, reset_less
=True)
539 self
.insn_in
= Signal(32, reset_less
=True)
540 self
.oe_out
= Data(1, "oe")
542 def elaborate(self
, platform
):
547 with m
.Switch(op
.internal_op
):
549 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
551 # XXX ARGH! ignoring OE causes incompatibility with microwatt
552 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
553 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
554 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
555 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
556 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
557 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
561 # all other ops decode OE field
563 # select OE bit out field
564 with m
.Switch(self
.sel_in
):
566 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
567 comb
+= self
.oe_out
.ok
.eq(1)
572 class DecodeCRIn(Elaboratable
):
573 """Decodes input CR from instruction
575 CR indices - insn fields - (not the data *in* the CR) require only 3
576 bits because they refer to CR0-CR7
579 def __init__(self
, dec
, op
):
582 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
583 self
.insn_in
= Signal(32, reset_less
=True)
584 self
.cr_bitfield
= Data(3, "cr_bitfield")
585 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
586 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
587 self
.whole_reg
= Data(8, "cr_fxm")
588 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
590 def elaborate(self
, platform
):
594 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
597 # zero-initialisation
598 comb
+= self
.cr_bitfield
.ok
.eq(0)
599 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
600 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
601 comb
+= self
.whole_reg
.ok
.eq(0)
602 comb
+= self
.sv_override
.eq(0)
604 # select the relevant CR bitfields
605 with m
.Switch(self
.sel_in
):
606 with m
.Case(CRInSel
.NONE
):
607 pass # No bitfield activated
608 with m
.Case(CRInSel
.CR0
):
609 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
610 comb
+= self
.cr_bitfield
.ok
.eq(1)
611 comb
+= self
.sv_override
.eq(1)
612 with m
.Case(CRInSel
.CR1
):
613 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
614 comb
+= self
.cr_bitfield
.ok
.eq(1)
615 comb
+= self
.sv_override
.eq(2)
616 with m
.Case(CRInSel
.BI
):
617 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
618 comb
+= self
.cr_bitfield
.ok
.eq(1)
619 with m
.Case(CRInSel
.BFA
):
620 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
621 comb
+= self
.cr_bitfield
.ok
.eq(1)
622 with m
.Case(CRInSel
.BA_BB
):
623 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
624 comb
+= self
.cr_bitfield
.ok
.eq(1)
625 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
626 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
627 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
628 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
629 with m
.Case(CRInSel
.BC
):
630 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
631 comb
+= self
.cr_bitfield
.ok
.eq(1)
632 with m
.Case(CRInSel
.WHOLE_REG
):
633 comb
+= self
.whole_reg
.ok
.eq(1)
634 move_one
= Signal(reset_less
=True)
635 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
636 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
637 # must one-hot the FXM field
638 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
639 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
641 # otherwise use all of it
642 comb
+= self
.whole_reg
.data
.eq(0xff)
647 class DecodeCROut(Elaboratable
):
648 """Decodes input CR from instruction
650 CR indices - insn fields - (not the data *in* the CR) require only 3
651 bits because they refer to CR0-CR7
654 def __init__(self
, dec
, op
):
657 self
.rc_in
= Signal(reset_less
=True)
658 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
659 self
.insn_in
= Signal(32, reset_less
=True)
660 self
.cr_bitfield
= Data(3, "cr_bitfield")
661 self
.whole_reg
= Data(8, "cr_fxm")
662 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
664 def elaborate(self
, platform
):
668 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
671 comb
+= self
.cr_bitfield
.ok
.eq(0)
672 comb
+= self
.whole_reg
.ok
.eq(0)
673 comb
+= self
.sv_override
.eq(0)
675 # please note these MUST match (setting of cr_bitfield.ok) exactly
676 # with write_cr0 below in PowerDecoder2. the reason it's separated
677 # is to avoid having duplicate copies of DecodeCROut in multiple
678 # PowerDecoderSubsets. register decoding should be a one-off in
679 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
681 with m
.Switch(self
.sel_in
):
682 with m
.Case(CROutSel
.NONE
):
683 pass # No bitfield activated
684 with m
.Case(CROutSel
.CR0
):
685 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
686 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
687 comb
+= self
.sv_override
.eq(1)
688 with m
.Case(CROutSel
.CR1
):
689 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
690 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
691 comb
+= self
.sv_override
.eq(2)
692 with m
.Case(CROutSel
.BF
):
693 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
694 comb
+= self
.cr_bitfield
.ok
.eq(1)
695 with m
.Case(CROutSel
.BT
):
696 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
697 comb
+= self
.cr_bitfield
.ok
.eq(1)
698 with m
.Case(CROutSel
.WHOLE_REG
):
699 comb
+= self
.whole_reg
.ok
.eq(1)
700 move_one
= Signal(reset_less
=True)
701 comb
+= move_one
.eq(self
.insn_in
[20])
702 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
704 # must one-hot the FXM field
705 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
706 with m
.If(ppick
.en_o
):
707 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
709 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
711 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
713 # otherwise use all of it
714 comb
+= self
.whole_reg
.data
.eq(0xff)
718 # dictionary of Input Record field names that, if they exist,
719 # will need a corresponding CSV Decoder file column (actually, PowerOp)
720 # to be decoded (this includes the single bit names)
721 record_names
= {'insn_type': 'internal_op',
722 'fn_unit': 'function_unit',
723 'SV_Ptype': 'SV_Ptype',
727 'imm_data': 'in2_sel',
728 'invert_in': 'inv_a',
729 'invert_out': 'inv_out',
732 'output_carry': 'cry_out',
733 'input_carry': 'cry_in',
734 'is_32bit': 'is_32b',
737 'data_len': 'ldst_len',
738 'byte_reverse': 'br',
739 'sign_extend': 'sgn_ext',
744 class PowerDecodeSubset(Elaboratable
):
745 """PowerDecodeSubset: dynamic subset decoder
747 only fields actually requested are copied over. hence, "subset" (duh).
749 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
750 svp64_en
=True, regreduce_en
=False):
752 self
.svp64_en
= svp64_en
753 self
.regreduce_en
= regreduce_en
755 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
756 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
757 # set these to the predicate mask bits needed for the ALU
758 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
759 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
760 self
.sv_a_nz
= Signal(1)
763 self
.fn_name
= fn_name
765 opkls
= Decode2ToOperand
766 self
.do
= opkls(fn_name
)
767 col_subset
= self
.get_col_subset(self
.do
)
769 # only needed for "main" PowerDecode2
771 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
772 regreduce_en
=regreduce_en
)
774 # create decoder if one not already given
776 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
777 row_subset
=self
.rowsubsetfn
)
779 # create SVP64 decoder
785 svdec
= create_pdecode(name
=name
,
786 col_subset
=col_subset
,
787 row_subset
=self
.rowsubsetfn
)
790 # state information needed by the Decoder
792 state
= CoreState("dec2")
795 def get_col_subset(self
, do
):
796 subset
= { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
797 for k
, v
in record_names
.items():
800 log ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
803 def rowsubsetfn(self
, opcode
, row
):
804 """select per-Function-Unit subset of opcodes to be processed
806 normally this just looks at the "unit" column. MMU is different
807 in that it processes specific SPR set/get operations that the SPR
810 return (row
['unit'] == self
.fn_name
or
811 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
812 # by the MMU pipeline so we direct those opcodes to MMU **AND**
813 # SPR pipelines, then selectively weed out the SPRs that should
814 # or should not not go to each pipeline, further down.
815 # really this should be done by modifying the CSV syntax
816 # to support multiple tasks (unit column multiple entries)
817 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
818 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
819 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
823 ports
= self
.dec
.ports() + self
.e
.ports()
825 ports
+= self
.sv_rm
.ports()
826 ports
+= self
.svdec
.ports()
829 def needs_field(self
, field
, op_field
):
834 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
836 def do_get(self
, field
, final
=False):
837 if final
or self
.final
:
841 return getattr(do
, field
, None)
843 def do_copy(self
, field
, val
, final
=False):
844 df
= self
.do_get(field
, final
)
845 if df
is not None and val
is not None:
849 def op_get(self
, op_field
):
850 return getattr(self
.dec
.op
, op_field
, None)
852 def elaborate(self
, platform
):
853 if self
.regreduce_en
:
860 op
, do
= self
.dec
.op
, self
.do
861 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
862 # fill in for a normal instruction (not an exception)
863 # copy over if non-exception, non-privileged etc. is detected
865 if self
.fn_name
is None:
868 name
= self
.fn_name
+ "tmp"
869 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
870 regreduce_en
=self
.regreduce_en
)
872 # set up submodule decoders
873 m
.submodules
.dec
= self
.dec
874 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
875 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
878 # and SVP64 RM mode decoder
879 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
881 m
.submodules
.svdec
= svdec
= self
.svdec
883 # copy instruction through...
884 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
885 comb
+= i
.eq(self
.dec
.opcode_in
)
887 # ...and subdecoders' input fields
888 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
889 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
892 comb
+= self
.do_copy("msr", msr
)
893 comb
+= self
.do_copy("cia", cia
)
894 comb
+= self
.do_copy("svstate", svstate
)
896 # set up instruction type
897 # no op: defaults to OP_ILLEGAL
898 internal_op
= self
.op_get("internal_op")
899 comb
+= self
.do_copy("insn_type", internal_op
)
901 # function unit for decoded instruction: requires minor redirect
903 fn
= self
.op_get("function_unit")
904 spr
= Signal(10, reset_less
=True)
905 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
907 # Microwatt doesn't implement the partition table
908 # instead has PRTBL register (SPR) to point to process table
910 is_mmu_spr
= Signal()
911 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
912 (internal_op
== MicrOp
.OP_MFSPR
))
913 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
914 (spr
== SPR
.DAR
.value
) |
915 (spr
== SPR
.PRTBL
.value
) |
916 (spr
== SPR
.PIDR
.value
))
917 # MMU must receive MMU SPRs
918 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
919 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
920 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
921 # SPR pipe must *not* receive MMU SPRs
922 with m
.Elif(is_spr_mv
& (fn
== Function
.MMU
) & ~is_mmu_spr
):
923 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
924 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
927 comb
+= self
.do_copy("fn_unit", fn
)
930 if self
.needs_field("zero_a", "in1_sel"):
931 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
932 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
933 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
934 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
935 if self
.needs_field("imm_data", "in2_sel"):
936 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
937 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
938 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
941 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
942 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
944 # CR in/out - note: these MUST match with what happens in
946 rc_out
= self
.dec_rc
.rc_out
.data
947 with m
.Switch(self
.op_get("cr_out")):
948 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
949 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
950 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
951 comb
+= self
.do_copy("write_cr0", 1)
953 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
954 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
957 # connect up SVP64 RM Mode decoding
958 sv_ptype
= self
.op_get("SV_Ptype")
959 fn
= self
.op_get("function_unit")
960 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know if LD/ST type
961 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
962 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
963 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
964 if self
.needs_field("imm_data", "in2_sel"):
965 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
966 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
968 # decoded/selected instruction flags
969 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
970 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
971 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
972 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
973 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
974 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
975 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
976 lk
= self
.op_get("lk")
979 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
981 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
982 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
983 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
985 # copy over SVP64 input record fields (if they exist)
987 # TODO, really do we have to do these explicitly?? sigh
988 #for (field, _) in sv_input_record_layout:
989 # comb += self.do_copy(field, self.rm_dec.op_get(field))
990 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
991 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
992 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
993 # these get set up based on incoming mask bits. TODO:
994 # pass in multiple bits (later, when SIMD backends are enabled)
995 with m
.If(self
.rm_dec
.pred_sz
):
996 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
997 with m
.If(self
.rm_dec
.pred_dz
):
998 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1003 class PowerDecode2(PowerDecodeSubset
):
1004 """PowerDecode2: the main instruction decoder.
1006 whilst PowerDecode is responsible for decoding the actual opcode, this
1007 module encapsulates further specialist, sparse information and
1008 expansion of fields that is inconvenient to have in the CSV files.
1009 for example: the encoding of the immediates, which are detected
1010 and expanded out to their full value from an annotated (enum)
1013 implicit register usage is also set up, here. for example: OP_BC
1014 requires implicitly reading CTR, OP_RFID requires implicitly writing
1017 in addition, PowerDecoder2 is responsible for detecting whether
1018 instructions are illegal (or privileged) or not, and instead of
1019 just leaving at that, *replacing* the instruction to execute with
1020 a suitable alternative (trap).
1022 LDSTExceptions are done the cycle _after_ they're detected (after
1023 they come out of LDSTCompUnit). basically despite the instruction
1024 being decoded, the results of the decode are completely ignored
1025 and "exception.happened" used to set the "actual" instruction to
1026 "OP_TRAP". the LDSTException data structure gets filled in,
1027 in the CompTrapOpSubset and that's what it fills in SRR.
1029 to make this work, TestIssuer must notice "exception.happened"
1030 after the (failed) LD/ST and copies the LDSTException info from
1031 the output, into here (PowerDecoder2). without incrementing PC.
1034 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1035 state
=None, svp64_en
=True, regreduce_en
=False):
1036 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1038 self
.ldst_exc
= LDSTException("dec2_exc")
1041 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1042 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1043 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1044 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1045 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1046 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1047 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1048 self
.o_isvec
= Signal(1, name
="reg_o_isvec")
1049 self
.o2_isvec
= Signal(1, name
="reg_o2_isvec")
1050 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1051 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1052 self
.loop_continue
= Signal(1, name
="loop_continue")
1054 self
.no_in_vec
= Const(1, 1)
1055 self
.no_out_vec
= Const(1, 1)
1056 self
.loop_continue
= Const(0, 1)
1058 def get_col_subset(self
, opkls
):
1059 subset
= super().get_col_subset(opkls
)
1060 subset
.add("asmcode")
1061 subset
.add("in1_sel")
1062 subset
.add("in2_sel")
1063 subset
.add("in3_sel")
1064 subset
.add("out_sel")
1066 subset
.add("sv_in1")
1067 subset
.add("sv_in2")
1068 subset
.add("sv_in3")
1069 subset
.add("sv_out")
1070 subset
.add("sv_out2")
1071 subset
.add("sv_cr_in")
1072 subset
.add("sv_cr_out")
1073 subset
.add("SV_Etype")
1074 subset
.add("SV_Ptype")
1075 # from SVP64RMModeDecode
1076 for (field
, _
) in sv_input_record_layout
:
1079 subset
.add("internal_op")
1083 def elaborate(self
, platform
):
1084 m
= super().elaborate(platform
)
1087 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1088 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1089 rc_out
= self
.dec_rc
.rc_out
.data
1093 # fill in for a normal instruction (not an exception)
1094 # copy over if non-exception, non-privileged etc. is detected
1096 # set up submodule decoders
1097 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1098 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1099 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1100 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1101 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1102 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1103 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1104 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1107 # and SVP64 Extra decoders
1108 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1109 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1110 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1111 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1112 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1113 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1114 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1115 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1116 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1118 # debug access to crout_svdec (used in get_pdecode_cr_out)
1119 self
.crout_svdec
= crout_svdec
1121 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1122 reg
= Signal(5, reset_less
=True)
1124 # copy instruction through...
1125 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1126 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1127 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1128 comb
+= i
.eq(self
.dec
.opcode_in
)
1131 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1132 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1133 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1136 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1137 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1139 # ...and subdecoders' input fields
1140 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1141 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1142 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1143 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1144 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1145 if hasattr(do
, "lk"):
1146 comb
+= dec_o2
.lk
.eq(do
.lk
)
1149 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1150 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1151 # which in turn were auto-generated by sv_analysis.py
1152 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1156 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out")) # SVP64 CR out
1157 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1160 # CR in - selection slightly different due to shared CR field sigh
1161 cr_a_idx
= Signal(SVEXTRA
)
1162 cr_b_idx
= Signal(SVEXTRA
)
1164 # these change slightly, when decoding BA/BB. really should have
1165 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1166 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1167 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1168 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1169 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1170 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1172 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1173 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1174 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1176 # indices are slightly different, BA/BB mess sorted above
1177 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1178 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1179 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out")) # SVP64 CR out
1181 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1182 vl
= Signal
.like(self
.state
.svstate
.vl
)
1183 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1184 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1185 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1186 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1187 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1189 # registers a, b, c and out and out2 (LD/ST EA)
1190 sv_etype
= self
.op_get("SV_Etype")
1191 for to_reg
, fromreg
, svdec
, out
in (
1192 (e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, False),
1193 (e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, False),
1194 (e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, False),
1195 (e
.write_reg
, dec_o
.reg_out
, o_svdec
, True),
1196 (e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, True)):
1197 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1198 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1199 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1200 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1201 # detect if Vectorised: add srcstep/dststep if yes.
1202 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1203 with m
.If(svdec
.isvec
):
1204 step
= dststep
if out
else srcstep
1205 # reverse gear goes the opposite way
1206 with m
.If(self
.rm_dec
.reverse_gear
):
1207 comb
+= to_reg
.data
.eq(svdec
.reg_out
+(vl
-1-step
))
1209 comb
+= to_reg
.data
.eq(step
+svdec
.reg_out
)
1211 comb
+= to_reg
.data
.eq(svdec
.reg_out
)
1213 # SVP64 in/out fields
1214 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1215 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1216 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1217 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1218 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2")) # output (implicit)
1219 # XXX TODO - work out where this should come from. the problem is
1220 # that LD-with-update is implied (computed from "is instruction in
1221 # "update mode" rather than specified cleanly as its own CSV column
1223 # output reg-is-vectorised (and when no in/out is vectorised)
1224 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1225 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1226 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1227 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1228 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1229 # TODO add SPRs here. must be True when *all* are scalar
1230 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1231 crin_svdec
, crin_svdec_b
, crin_svdec_o
])
1232 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1233 l
= map(lambda svdec
: svdec
.isvec
, [o2_svdec
, o_svdec
, crout_svdec
])
1234 # in mapreduce mode, scalar out is *allowed*
1235 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1236 comb
+= self
.no_out_vec
.eq(0)
1238 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool()) # all output scalar
1239 # now create a general-purpose "test" as to whether looping
1240 # should continue. this doesn't include predication bit-tests
1241 loop
= self
.loop_continue
1242 with m
.Switch(self
.op_get("SV_Ptype")):
1243 with m
.Case(SVPtype
.P2
.value
):
1245 # TODO: *and cache-inhibited LD/ST!*
1246 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1247 with m
.Case(SVPtype
.P1
.value
):
1248 # single-predication, test relies on dest only
1249 comb
+= loop
.eq(~self
.no_out_vec
)
1251 # not an SV operation, no looping
1254 # condition registers (CR)
1255 for to_reg
, cr
, name
, svdec
, out
in (
1256 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1257 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1258 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1259 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1260 fromreg
= getattr(cr
, name
)
1261 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1262 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1263 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1264 with m
.If(svdec
.isvec
):
1265 # check if this is CR0 or CR1: treated differently
1266 # (does not "listen" to EXTRA2/3 spec for a start)
1267 # also: the CRs start from completely different locations
1268 step
= dststep
if out
else srcstep
1269 with m
.If(cr
.sv_override
== 1): # CR0
1270 offs
= SVP64CROffs
.CR0
1271 comb
+= to_reg
.data
.eq(step
+offs
)
1272 with m
.Elif(cr
.sv_override
== 2): # CR1
1273 offs
= SVP64CROffs
.CR1
1274 comb
+= to_reg
.data
.eq(step
+1)
1276 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1278 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1279 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1281 # sigh must determine if RA is nonzero (7 bit)
1282 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1284 # connect up to/from read/write GPRs
1285 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1286 (e
.read_reg2
, dec_b
.reg_out
),
1287 (e
.read_reg3
, dec_c
.reg_out
),
1288 (e
.write_reg
, dec_o
.reg_out
),
1289 (e
.write_ea
, dec_o2
.reg_out
)):
1290 comb
+= to_reg
.data
.eq(fromreg
.data
)
1291 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1293 # connect up to/from read/write CRs
1294 for to_reg
, cr
, name
in (
1295 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1296 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1297 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1298 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1299 fromreg
= getattr(cr
, name
)
1300 comb
+= to_reg
.data
.eq(fromreg
.data
)
1301 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1304 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1307 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1308 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1310 # Fast regs out including SRR0/1/SVSRR0
1311 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1312 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1313 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1314 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1315 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1317 # sigh this is exactly the sort of thing for which the
1318 # decoder is designed to not need. MTSPR, MFSPR and others need
1319 # access to the XER bits. however setting e.oe is not appropriate
1320 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1321 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1322 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1323 comb
+= e
.xer_in
.eq(1<<XERRegsEnum
.SO
) # SO
1324 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1325 comb
+= e
.xer_out
.eq(1)
1327 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1328 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1329 # *DO NOT* call self.trap here. that would reset absolutely
1330 # everything including destroying read of RA and RB.
1331 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1333 ####################
1334 # ok so the instruction's been decoded, blah blah, however
1335 # now we need to determine if it's actually going to go ahead...
1336 # *or* if in fact it's a privileged operation, whether there's
1337 # an external interrupt, etc. etc. this is a simple priority
1338 # if-elif-elif sequence. decrement takes highest priority,
1339 # EINT next highest, privileged operation third.
1341 # check if instruction is privileged
1342 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1344 # different IRQ conditions
1345 ext_irq_ok
= Signal()
1346 dec_irq_ok
= Signal()
1349 ldst_exc
= self
.ldst_exc
1351 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1352 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1353 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1354 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1356 # LD/ST exceptions. TestIssuer copies the exception info at us
1357 # after a failed LD/ST.
1358 with m
.If(ldst_exc
.happened
):
1359 with m
.If(ldst_exc
.alignment
):
1360 self
.trap(m
, TT
.PRIV
, 0x600)
1361 with m
.Elif(ldst_exc
.instr_fault
):
1362 with m
.If(ldst_exc
.segment_fault
):
1363 self
.trap(m
, TT
.PRIV
, 0x480)
1365 # pass exception info to trap to create SRR1
1366 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1368 with m
.If(ldst_exc
.segment_fault
):
1369 self
.trap(m
, TT
.PRIV
, 0x380)
1371 self
.trap(m
, TT
.PRIV
, 0x300)
1373 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1374 with m
.Elif(dec_irq_ok
):
1375 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1377 # external interrupt? only if MSR.EE set
1378 with m
.Elif(ext_irq_ok
):
1379 self
.trap(m
, TT
.EINT
, 0x500)
1381 # privileged instruction trap
1382 with m
.Elif(priv_ok
):
1383 self
.trap(m
, TT
.PRIV
, 0x700)
1385 # illegal instruction must redirect to trap. this is done by
1386 # *overwriting* the decoded instruction and starting again.
1387 # (note: the same goes for interrupts and for privileged operations,
1388 # just with different trapaddr and traptype)
1389 with m
.Elif(illeg_ok
):
1390 # illegal instruction trap
1391 self
.trap(m
, TT
.ILLEG
, 0x700)
1393 # no exception, just copy things to the output
1397 ####################
1398 # follow-up after trap/irq to set up SRR0/1
1400 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1401 # Note: OP_SC could actually be modified to just be a trap
1402 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1403 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1404 # TRAP write fast1 = SRR0
1405 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1406 comb
+= e_out
.write_fast1
.ok
.eq(1)
1407 # TRAP write fast2 = SRR1
1408 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1409 comb
+= e_out
.write_fast2
.ok
.eq(1)
1410 # TRAP write fast2 = SRR1
1411 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1412 comb
+= e_out
.write_fast3
.ok
.eq(1)
1414 # RFID: needs to read SRR0/1
1415 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1416 # TRAP read fast1 = SRR0
1417 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1418 comb
+= e_out
.read_fast1
.ok
.eq(1)
1419 # TRAP read fast2 = SRR1
1420 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1421 comb
+= e_out
.read_fast2
.ok
.eq(1)
1422 # TRAP read fast2 = SVSRR0
1423 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1424 comb
+= e_out
.read_fast3
.ok
.eq(1)
1426 # annoying simulator bug.
1427 # asmcode may end up getting used for perfcounters?
1428 asmcode
= self
.op_get("asmcode")
1429 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1430 comb
+= e_out
.asmcode
.eq(asmcode
)
1434 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1435 """trap: this basically "rewrites" the decoded instruction as a trap
1439 comb
+= e
.eq(0) # reset eeeeeverything
1442 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1443 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1444 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1445 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1446 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1447 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1448 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1449 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1450 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1454 def get_rdflags(e
, cu
):
1456 for idx
in range(cu
.n_src
):
1457 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1458 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1464 if __name__
== '__main__':
1465 pdecode
= create_pdecode()
1466 dec2
= PowerDecode2(pdecode
)
1467 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1468 with
open("dec2.il", "w") as f
: