478b1451913aeed5fa3fbf21338c19326128b42f
1 # SPDX-License: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020, Michael Nolan
5 """Enums used in OpenPOWER ISA decoding
7 Note: for SV, from v3.1B p12:
9 The designated SPR sandbox consists of non-privileged SPRs 704-719 and
10 privileged SPRs 720-735.
12 Note: the option exists to select a much shorter list of SPRs, to reduce
13 regfile size in HDL. this is SPRreduced and the supported list is in
17 from enum
import Enum
, unique
20 from os
.path
import dirname
, join
21 from collections
import namedtuple
25 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
26 basedir
= dirname(dirname(dirname(filedir
)))
27 tabledir
= join(basedir
, 'openpower')
28 isatables
= join(tabledir
, 'isatables')
29 #print ("find_wiki_dir", isatables)
33 def find_wiki_file(name
):
34 return join(find_wiki_dir(), name
)
38 file_path
= find_wiki_file(name
)
39 with
open(file_path
, 'r') as csvfile
:
40 reader
= csv
.DictReader(csvfile
)
44 # names of the fields in the tables that don't correspond to an enum
45 single_bit_flags
= ['inv A', 'inv out',
46 'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
47 'sgn', 'lk', 'sgl pipe']
49 # default values for fields in the table
50 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
51 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
55 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
58 def get_signal_name(name
):
61 return name
.lower().replace(' ', '_')
63 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
64 # is to process and guard the operation. they are roughly divided by having
65 # the same register input/output signature (X-Form, etc.)
82 SV
= 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
118 SVL
= 29 # Simple-V for setvl instruction
119 SVD
= 30 # Simple-V for LD/ST bit-reverse, variant of D-Form
120 SVDS
= 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form
121 SVM
= 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
122 SVRM
= 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY
124 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
148 Idx_1_2
= 5 # due to weird BA/BB for crops
152 class SVP64PredMode(Enum
):
159 class SVP64PredInt(Enum
):
171 class SVP64PredCR(Enum
):
183 class SVP64RMMode(Enum
):
192 class SVP64width(Enum
):
200 class SVP64subvl(Enum
):
208 class SVP64sat(Enum
):
214 class SVP64LDSTmode(Enum
):
222 # supported instructions: make sure to keep up-to-date with CSV files
223 # just like everything else
225 "NONE", "add", "addc", "addco", "adde", "addeo",
226 "addi", "addic", "addic.", "addis",
227 "addme", "addmeo", "addo", "addze", "addzeo",
228 "and", "andc", "andi.", "andis.",
230 "b", "bc", "bcctr", "bclr", "bctar",
232 "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
233 "cntlzd", "cntlzw", "cnttzd", "cnttzw",
234 "crand", "crandc", "creqv",
235 "crnand", "crnor", "cror", "crorc", "crxor",
237 "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
238 "divd", "divde", "divdeo", "divdeu",
239 "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
240 "divweu", "divweuo", "divwo", "divwu", "divwuo",
242 "extsb", "extsh", "extsw", "extswsli",
243 "fadd", "fadds", "fsub", "fsubs", # FP add / sub
244 "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes", # FP stuff
245 "fmsubs", "fmadds", "fnmsubs", "fnmadds", # FP 3-arg
246 "ffadds", "ffsubs", "ffmuls", "ffdivs", # FFT FP 2-arg
247 "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds", # FFT FP 3-arg
248 "fmul", "fmuls", "fdiv", "fdivs", # FP mul / div
249 "fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
250 "fsins", "fcoss", # FP SIN/COS
251 "hrfid", "icbi", "icbt", "isel", "isync",
252 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
253 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
254 #"lbzbr", "lbzubr", # load byte SVP64 bit-reversed
255 #"ldbr", "ldubr", # load double SVP64 bit-reversed
256 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
257 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
258 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
259 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
260 #"lhabr", "lhaubr", # load half SVP64 bit-reversed
261 #"lhzbr", "lhzubr", # more load half SVP64 bit-reversed
262 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
263 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
264 #"lwabr", # load word SVP64 bit-reversed
265 #"lwzbr", "lwzubr", # more load word SVP64 bit-reversed
266 "maddhd", "maddhdu", "maddld", # INT multiply-and-add
267 "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
269 "modsd", "modsw", "modud", "moduw",
270 "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
271 "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
272 "mulli", "mullw", "mullwo",
273 "nand", "neg", "nego",
275 "nor", "or", "orc", "ori", "oris",
276 "popcntb", "popcntd", "popcntw",
279 "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
280 "rlwimi", "rlwinm", "rlwnm",
282 "setvl", # https://libre-soc.org/openpower/sv/setvl
283 "svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
284 "svshape", # https://libre-soc.org/openpower/sv/remap
286 "slbia", "sld", "slw", "srad", "sradi",
287 "sraw", "srawi", "srd", "srw",
288 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
289 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
290 "stfs", "stfsx", "stfsu", "stfux", # FP store single
291 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
292 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
293 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
294 "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
295 "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
300 "xor", "xori", "xoris",
303 # two-way lookup of instruction-to-index and vice-versa
306 for i
, insn
in enumerate(_insns
):
310 # must be long enough to cover all instructions
311 asmlen
= len(_insns
).bit_length()
313 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
318 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
392 OP_FPOP
= 77 # temporary: replace with actual ops
393 OP_FPOP_I
= 78 # temporary: replace with actual ops
405 RS
= 4 # for some ALU/Logical operations
425 RS
= 13 # for shiftrot (M-Form)
427 CONST_SVD
= 15 # for SVD-Form
428 CONST_SVDS
= 16 # for SVDS-Form
435 RB
= 2 # for shiftrot (M-Form)
438 RC
= 5 # for SVP64 bit-reverse LD/ST
462 class LDSTMode(Enum
):
497 class CROutSel(Enum
):
506 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
507 # http://libre-riscv.org/openpower/isatables/sprs.csv
508 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
510 def get_spr_enum(full_file
):
511 """get_spr_enum - creates an Enum of SPRs, dynamically
512 has the option to reduce the enum to a much shorter list.
513 this saves drastically on the size of the regfile
515 short_list
= {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
516 'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
517 'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
521 for row
in get_csv("sprs.csv"):
522 if full_file
or row
['SPR'] in short_list
:
525 spr_info
= namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
529 info
= spr_info(SPR
=row
['SPR'], priv_mtspr
=row
['priv_mtspr'],
530 priv_mfspr
=row
['priv_mfspr'], length
=int(row
['len']),
532 spr_dict
[int(row
['Idx'])] = info
533 spr_byname
[row
['SPR']] = info
534 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
535 SPR
= Enum('SPR', fields
)
536 return SPR
, spr_dict
, spr_byname
538 SPRfull
, spr_dict
, spr_byname
= get_spr_enum(full_file
=True)
539 SPRreduced
, _
, _
= get_spr_enum(full_file
=False)
549 if __name__
== '__main__':
550 # find out what the heck is in SPR enum :)
551 print("sprs full", len(SPRfull
))
553 print("sprs reduced", len(SPRreduced
))
554 print(dir(SPRreduced
))
556 print(SPRfull
.__members
__['TAR'])
558 print("full", x
, x
.value
, str(x
), x
.name
)
560 print("reduced", x
, x
.value
, str(x
), x
.name
)
562 print("function", Function
.ALU
.name
)