src/openpower/decoder/power_enums.py

   1 # SPDX-License-Identifier: LGPL-3-or-later
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020, Michael Nolan
   4
   5 """Enums used in OpenPOWER ISA decoding
   6
   7 Note: for SV, from v3.1B p12:
   8
   9     The designated SPR sandbox consists of non-privileged SPRs 704-719 and
  10     privileged SPRs 720-735.
  11
  12 Note: the option exists to select a much shorter list of SPRs, to reduce
  13 regfile size in HDL.  this is SPRreduced and the supported list is in
  14 get_spr_enum
  15 """
  16
  17 from enum import (
  18     auto,
  19     Enum as _Enum,
  20     unique,
  21 )
  22 import csv
  23 import os
  24 from os.path import dirname, join
  25 from collections import namedtuple
  26 import functools
  27
  28
  29 def find_wiki_dir():
  30     filedir = os.path.dirname(os.path.abspath(__file__))
  31     basedir = dirname(dirname(dirname(filedir)))
  32     tabledir = join(basedir, 'openpower')
  33     isatables = join(tabledir, 'isatables')
  34     #print ("find_wiki_dir", isatables)
  35     return isatables
  36
  37
  38 def find_wiki_file(name):
  39     return join(find_wiki_dir(), name)
  40
  41
  42 def get_csv(name):
  43     """gets a not-entirely-csv-file-formatted database, which allows comments
  44     """
  45     file_path = find_wiki_file(name)
  46     with open(file_path, 'r') as csvfile:
  47         csvfile = filter(lambda row: row[0] !='#', csvfile) # strip "#..."
  48         reader = csv.DictReader(csvfile)
  49         return list(reader)
  50
  51
  52 # names of the fields in the tables that don't correspond to an enum
  53 single_bit_flags = ['inv A', 'inv out',
  54                     'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
  55                     'sgn', 'lk', 'sgl pipe']
  56
  57 # default values for fields in the table
  58 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  59                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  60                   'CR in': 'NONE',
  61                   'ldst len': 'NONE',
  62                   'upd': '0',
  63                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  64
  65
  66 def get_signal_name(name):
  67     if name[0].isdigit():
  68         name = "is_" + name
  69     return name.lower().replace(' ', '_')
  70
  71
  72 class Enum(_Enum):
  73     @classmethod
  74     def _missing_(cls, value):
  75         if isinstance(value, str):
  76             try:
  77                 if value == "":
  78                     value = 0
  79                 else:
  80                     value = int(value, 0)
  81             except ValueError:
  82                 pass
  83         keys = {item.name:item for item in cls}
  84         values = {item.value:item for item in cls}
  85         item = keys.get(value, values.get(value))
  86         if item is None:
  87             raise ValueError(value)
  88         return item
  89
  90
  91 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
  92 # is to process and guard the operation.  they are roughly divided by having
  93 # the same register input/output signature (X-Form, etc.)
  94
  95
  96 @unique
  97 class Function(Enum):
  98     NONE = 0
  99     ALU = 1 << 1
 100     LDST = 1 << 2
 101     SHIFT_ROT = 1 << 3
 102     LOGICAL = 1 << 4
 103     BRANCH = 1 << 5
 104     CR = 1 << 6
 105     TRAP = 1 << 7
 106     MUL = 1 << 8
 107     DIV = 1 << 9
 108     SPR = 1 << 10
 109     MMU = 1 << 11
 110     SV = 1 << 12  # Simple-V https://libre-soc.org/openpower/sv
 111     VL = 1 << 13  # setvl
 112     FPU = 1 << 14  # FPU
 113
 114     @functools.lru_cache(maxsize=None)
 115     def __repr__(self):
 116         counter = 0
 117         value = int(self.value)
 118         if value != 0:
 119             while value != 0:
 120                 counter += 1
 121                 value >>= 1
 122             counter -= 1
 123             desc = f"(1 << {counter})"
 124         else:
 125             desc = "0"
 126         return f"<{self.__class__.__name__}.{self.name}: {desc}>"
 127
 128
 129 @unique
 130 class Form(Enum):
 131     NONE = 0
 132     I = 1
 133     B = 2
 134     SC = 3
 135     D = 4
 136     DS = 5
 137     DQ = 6
 138     DX = 7
 139     X = 8
 140     XL = 9
 141     XFX = 10
 142     XFL = 11
 143     XX1 = 12
 144     XX2 = 13
 145     XX3 = 14
 146     XX4 = 15
 147     XS = 16
 148     XO = 17
 149     A = 18
 150     M = 19
 151     MD = 20
 152     MDS = 21
 153     VA = 22
 154     VC = 23
 155     VX = 24
 156     EVX = 25
 157     EVS = 26
 158     Z22 = 27
 159     Z23 = 28
 160     SVL = 29  # Simple-V for setvl instruction
 161     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
 162     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
 163     SVM = 32  # Simple-V SHAPE mode
 164     SVM2 = 33  # Simple-V SHAPE2 mode - fits into SVM
 165     SVRM = 34  # Simple-V REMAP mode
 166     TLI = 35  # ternlogi
 167     XB = 36
 168     BM2 = 37 # bmask
 169     SVI = 38  # Simple-V Index Mode
 170     VA2 = 39
 171     SVC = 40
 172     SVR = 41
 173
 174 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 175
 176
 177 class SVMode(Enum):
 178     NORMAL = auto()
 179     LDST_IDX = auto()
 180     LDST_IMM = auto()
 181     BRANCH = auto()
 182     CROP = auto()
 183
 184
 185 @unique
 186 class SVPtype(Enum):
 187     NONE = 0
 188     P1 = 1
 189     P2 = 2
 190
 191     @classmethod
 192     def _missing_(cls, value):
 193         return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
 194
 195     def __repr__(self):
 196         return {
 197             SVPtype.NONE: "NONE",
 198             SVPtype.P1: "1P",
 199             SVPtype.P2: "2P",
 200         }[self]
 201
 202
 203 @unique
 204 class SVEtype(Enum):
 205     NONE = 0
 206     EXTRA2 = 1
 207     EXTRA3 = 2
 208
 209     def __repr__(self):
 210         return self.name
 211
 212
 213 @unique
 214 class SVExtra(Enum):
 215     NONE = 0
 216     Idx0 = 1
 217     Idx1 = 2
 218     Idx2 = 3
 219     Idx3 = 4
 220     Idx_1_2 = 5  # due to weird BA/BB for crops
 221
 222     def __repr__(self):
 223         return {
 224             SVExtra.NONE: "NONE",
 225             SVExtra.Idx0: "[0]",
 226             SVExtra.Idx1: "[1]",
 227             SVExtra.Idx2: "[2]",
 228             SVExtra.Idx3: "[3]",
 229             SVExtra.Idx_1_2: "[1:2]",
 230         }[self]
 231
 232 # Backward compatibility
 233 SVEXTRA = SVExtra
 234
 235
 236 class SVExtraRegType(Enum):
 237     NONE = None
 238     SRC = 's'
 239     DST = 'd'
 240
 241
 242 class SVExtraReg(Enum):
 243     NONE = auto()
 244     RA = auto()
 245     RA_OR_ZERO = RA
 246     RB = auto()
 247     RC = auto()
 248     RS = auto()
 249     RT = auto()
 250     RT_OR_ZERO = RT
 251     FRA = auto()
 252     FRB = auto()
 253     FRC = auto()
 254     FRS = auto()
 255     FRT = auto()
 256     CR = auto()
 257     CR0 = auto()
 258     CR1 = auto()
 259     BF = auto()
 260     BFA = auto()
 261     BA = auto()
 262     BB = auto()
 263     BC = auto()
 264     BI = auto()
 265     BT = auto()
 266     BFT = auto()
 267     WHOLE_REG = auto()
 268     SPR = auto()
 269
 270     @classmethod
 271     def _missing_(cls, value):
 272         selectors = (
 273             In1Sel, In2Sel, In3Sel, CRInSel, CRIn2Sel,
 274             OutSel, CROutSel,
 275         )
 276         if isinstance(value, selectors):
 277             return cls.__members__[value.name]
 278         return super()._missing_(value)
 279
 280
 281 @unique
 282 class SVP64PredMode(Enum):
 283     ALWAYS = 0
 284     INT = 1
 285     CR = 2
 286
 287
 288 @unique
 289 class SVP64PredInt(Enum):
 290     ALWAYS = 0
 291     R3_UNARY = 1
 292     R3 = 2
 293     R3_N = 3
 294     R10 = 4
 295     R10_N = 5
 296     R30 = 6
 297     R30_N = 7
 298
 299
 300 @unique
 301 class SVP64PredCR(Enum):
 302     LT = 0
 303     GE = 1
 304     GT = 2
 305     LE = 3
 306     EQ = 4
 307     NE = 5
 308     SO = 6
 309     NS = 7
 310
 311
 312 @unique
 313 class SVP64RMMode(Enum):
 314     NORMAL = 0
 315     MAPREDUCE = 1
 316     FFIRST = 2
 317     SATURATE = 3
 318     PREDRES = 4
 319     BRANCH = 5
 320
 321
 322 @unique
 323 class SVP64BCPredMode(Enum):
 324     NONE = 0
 325     MASKZERO = 1
 326     MASKONE = 2
 327
 328
 329 @unique
 330 class SVP64BCVLSETMode(Enum):
 331     NONE = 0
 332     VL_INCL = 1
 333     VL_EXCL = 2
 334
 335
 336 # note that these are chosen to be exactly the same as
 337 # SVP64 RM bit 4.  ALL=1 => bit4=1
 338 @unique
 339 class SVP64BCGate(Enum):
 340     ANY = 0
 341     ALL = 1
 342
 343
 344 class SVP64BCCTRMode(Enum):
 345     NONE = 0
 346     TEST = 1
 347     TEST_INV = 2
 348
 349
 350 @unique
 351 class SVP64width(Enum):
 352     DEFAULT = 0
 353     EW_32 = 1
 354     EW_16 = 2
 355     EW_8 = 3
 356
 357
 358 @unique
 359 class SVP64subvl(Enum):
 360     VEC1 = 0
 361     VEC2 = 1
 362     VEC3 = 2
 363     VEC4 = 3
 364
 365
 366 @unique
 367 class SVP64sat(Enum):
 368     NONE = 0
 369     SIGNED = 1
 370     UNSIGNED = 2
 371
 372
 373 @unique
 374 class SVP64LDSTmode(Enum):
 375     NONE = 0
 376     INDEXED = 1
 377     ELSTRIDE = 2
 378     UNITSTRIDE = 3
 379
 380
 381 class RegType(Enum):
 382     GPR = 0
 383     RA = GPR
 384     RB = GPR
 385     RC = GPR
 386     RS = GPR
 387     RT = GPR
 388
 389     FPR = 1
 390     FRA = FPR
 391     FRB = FPR
 392     FRC = FPR
 393     FRS = FPR
 394     FRT = FPR
 395
 396     CR_REG = 2  # actually CR Field. the CR register is 32-bit.
 397     BF = CR_REG
 398     BFA = CR_REG
 399
 400     CR_BIT = 3 # refers to one bit of the 32-bit CR register
 401     BA = CR_BIT
 402     BB = CR_BIT
 403     BC = CR_BIT
 404     BI = CR_BIT
 405     BT = CR_BIT
 406
 407
 408 # supported instructions: make sure to keep up-to-date with CSV files
 409 # just like everything else
 410 _insns = [
 411     "NONE", "add", "addc", "addco", "adde", "addeo",
 412     "addi", "addic", "addic.", "addis",
 413     "addme", "addmeo", "addo", "addze", "addzeo",
 414     "addg6s",
 415     "and", "andc", "andi.", "andis.",
 416     "attn",
 417     "absdu", "absds",                         # AV bitmanip
 418     "absdacs", "absdacu",                     # AV bitmanip
 419     "avgadd",                                 # AV bitmanip
 420     "b", "bc", "bcctr", "bclr", "bctar",
 421     "bmask",                                  # AV bitmanip
 422     "bpermd",
 423     "cbcdtd",
 424     "cdtbcd",
 425     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
 426     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
 427     "cprop", # AV bitmanip
 428     "crand", "crandc", "creqv",
 429     "crnand", "crnor", "cror", "crorc", "crxor",
 430     "darn",
 431     "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
 432     "divd", "divde", "divdeo", "divdeu",
 433     "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
 434     "divweu", "divweuo", "divwo", "divwu", "divwuo",
 435     "eieio", "eqv",
 436     "extsb", "extsh", "extsw", "extswsli",
 437     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
 438     "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
 439     "fdmadds",                                          # DCT FP 3-arg
 440     "fmsubs", "fmadds", "fnmsubs", "fnmadds",           # FP 3-arg
 441     "ffadds", "ffsubs", "ffmuls", "ffdivs",             # FFT FP 2-arg
 442     "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
 443     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
 444     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
 445     "fsins", "fcoss",                                   # FP SIN/COS
 446     "fmvis",                                            # FP load immediate
 447     "fishmv",                                           # Float Replace Lower-Half Single, Immediate
 448     'grev', 'grev.', 'grevi', 'grevi.',
 449     'grevw', 'grevw.', 'grevwi', 'grevwi.',
 450     "hrfid", "icbi", "icbt", "isel", "isync",
 451     "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx",  # load byte
 452     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
 453     # "lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
 454     # "ldbr", "ldubr",    # load double SVP64 bit-reversed
 455     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
 456     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax",  # FP load double
 457     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
 458     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
 459     # "lhabr", "lhaubr",  # load half SVP64 bit-reversed
 460     # "lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
 461     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
 462     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
 463     # "lwabr",           # load word SVP64 bit-reversed
 464     # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
 465     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
 466     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
 467     "mfmsr", "mfspr",
 468     "mins", "maxs", "minu", "maxu",                     # AV bitmanip
 469     "modsd", "modsw", "modud", "moduw",
 470     "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
 471     "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
 472     "mulli", "mullw", "mullwo",
 473     "nand", "neg", "nego",
 474     "nop",
 475     "nor", "or", "orc", "ori", "oris",
 476     "popcntb", "popcntd", "popcntw",
 477     "prtyd", "prtyw",
 478     "rfid",
 479     "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
 480     "rlwimi", "rlwinm",    "rlwnm",
 481     "setb",
 482     "setvl",  # https://libre-soc.org/openpower/sv/setvl
 483     "svindex",  # https://libre-soc.org/openpower/sv/remap
 484     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
 485     "svshape",  # https://libre-soc.org/openpower/sv/remap/#svshape
 486     "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
 487     "svstep",  # https://libre-soc.org/openpower/sv/setvl
 488     "sim_cfg",
 489     "slbia", "sld", "slw", "srad", "sradi",
 490     "sraw", "srawi", "srd", "srw",
 491     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
 492     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
 493     "stfs", "stfsx", "stfsu", "stfux", "stfsux",        # FP store single
 494     "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store double
 495     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
 496     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
 497     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
 498     "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
 499     "sync",
 500     "ternlogi",
 501     "td", "tdi",
 502     "tlbie", "tlbiel", "tlbsync",
 503     "tw", "twi",
 504     "wait",
 505     "xor", "xori", "xoris",
 506 ]
 507
 508 # two-way lookup of instruction-to-index and vice-versa
 509 insns = {}
 510 asmidx = {}
 511 for i, insn in enumerate(_insns):
 512     insns[i] = insn
 513     asmidx[insn] = i
 514
 515 # must be long enough to cover all instructions
 516 asmlen = len(_insns).bit_length()
 517
 518 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 519
 520
 521 @unique
 522 class MicrOp(Enum):
 523     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
 524     OP_NOP = 1
 525     OP_ADD = 2
 526     OP_ADDPCIS = 3
 527     OP_AND = 4
 528     OP_ATTN = 5
 529     OP_B = 6
 530     OP_BC = 7
 531     OP_BCREG = 8
 532     OP_BPERM = 9
 533     OP_CMP = 10
 534     OP_CMPB = 11
 535     OP_CMPEQB = 12
 536     OP_CMPRB = 13
 537     OP_CNTZ = 14
 538     OP_CRAND = 15
 539     OP_CRANDC = 16
 540     OP_CREQV = 17
 541     OP_CRNAND = 18
 542     OP_CRNOR = 19
 543     OP_CROR = 20
 544     OP_CRORC = 21
 545     OP_CRXOR = 22
 546     OP_DARN = 23
 547     OP_DCBF = 24
 548     OP_DCBST = 25
 549     OP_DCBT = 26
 550     OP_DCBTST = 27
 551     OP_DCBZ = 28
 552     OP_DIV = 29
 553     OP_DIVE = 30
 554     OP_EXTS = 31
 555     OP_EXTSWSLI = 32
 556     OP_ICBI = 33
 557     OP_ICBT = 34
 558     OP_ISEL = 35
 559     OP_ISYNC = 36
 560     OP_LOAD = 37
 561     OP_STORE = 38
 562     OP_MADDHD = 39
 563     OP_MADDHDU = 40
 564     OP_MADDLD = 41
 565     OP_MCRF = 42
 566     OP_MCRXR = 43
 567     OP_MCRXRX = 44
 568     OP_MFCR = 45
 569     OP_MFSPR = 46
 570     OP_MOD = 47
 571     OP_MTCRF = 48
 572     OP_MTSPR = 49
 573     OP_MUL_L64 = 50
 574     OP_MUL_H64 = 51
 575     OP_MUL_H32 = 52
 576     OP_OR = 53
 577     OP_POPCNT = 54
 578     OP_PRTY = 55
 579     OP_RLC = 56
 580     OP_RLCL = 57
 581     OP_RLCR = 58
 582     OP_SETB = 59
 583     OP_SHL = 60
 584     OP_SHR = 61
 585     OP_SYNC = 62
 586     OP_TRAP = 63
 587     OP_XOR = 67
 588     OP_SIM_CONFIG = 68
 589     OP_CROP = 69
 590     OP_RFID = 70
 591     OP_MFMSR = 71
 592     OP_MTMSRD = 72
 593     OP_SC = 73
 594     OP_MTMSR = 74
 595     OP_TLBIE = 75
 596     OP_SETVL = 76
 597     OP_FPOP = 77  # temporary: replace with actual ops
 598     OP_FPOP_I = 78  # temporary: replace with actual ops
 599     OP_FP_MADD = 79
 600     OP_SVREMAP = 80
 601     OP_SVSHAPE = 81
 602     OP_SVSTEP = 82
 603     OP_ADDG6S = 83
 604     OP_CDTBCD = 84
 605     OP_CBCDTD = 85
 606     OP_TERNLOG = 86
 607     OP_FETCH_FAILED = 87
 608     OP_GREV = 88
 609     OP_MINMAX = 89
 610     OP_AVGADD = 90
 611     OP_ABSDIFF = 91
 612     OP_ABSADD = 92
 613     OP_CPROP = 93
 614     OP_BMASK = 94
 615     OP_SVINDEX = 95
 616     OP_FMVIS = 96
 617     OP_FISHMV = 97
 618
 619
 620 @unique
 621 class In1Sel(Enum):
 622     NONE = 0
 623     RA = 1
 624     RA_OR_ZERO = 2
 625     SPR = 3
 626     RS = 4  # for some ALU/Logical operations
 627     FRA = 5
 628     FRS = 6
 629     CIA = 7 # for addpcis
 630
 631
 632 @unique
 633 class In2Sel(Enum):
 634     NONE = 0
 635     RB = 1
 636     CONST_UI = 2
 637     CONST_SI = 3
 638     CONST_UI_HI = 4
 639     CONST_SI_HI = 5
 640     CONST_LI = 6
 641     CONST_BD = 7
 642     CONST_DS = 8
 643     CONST_M1 = 9
 644     CONST_SH = 10
 645     CONST_SH32 = 11
 646     SPR = 12
 647     RS = 13  # for shiftrot (M-Form)
 648     FRB = 14
 649     CONST_SVD = 15  # for SVD-Form
 650     CONST_SVDS = 16  # for SVDS-Form
 651     CONST_XBI = 17
 652     CONST_DXHI4 = 18 # for addpcis
 653
 654
 655 @unique
 656 class In3Sel(Enum):
 657     NONE = 0
 658     RS = 1
 659     RB = 2  # for shiftrot (M-Form)
 660     FRS = 3
 661     FRC = 4
 662     RC = 5  # for SVP64 bit-reverse LD/ST
 663     RT = 6  # for ternlog[i]
 664
 665
 666 @unique
 667 class OutSel(Enum):
 668     NONE = 0
 669     RT = 1
 670     RA = 2
 671     SPR = 3
 672     RT_OR_ZERO = 4
 673     FRT = 5
 674     FRS = 6
 675
 676
 677 @unique
 678 class LDSTLen(Enum):
 679     NONE = 0
 680     is1B = 1
 681     is2B = 2
 682     is4B = 4
 683     is8B = 8
 684
 685 # Backward compatibility
 686 LdstLen = LDSTLen
 687
 688
 689 @unique
 690 class LDSTMode(Enum):
 691     NONE = 0
 692     update = 1
 693     cix = 2
 694     cx = 3
 695
 696
 697 @unique
 698 class RCOE(Enum):
 699     NONE = 0
 700     ONE = 1
 701     RC = 2    # includes OE
 702     RC_ONLY = 3  # does not include OE
 703
 704
 705 @unique
 706 class CryIn(Enum):
 707     ZERO = 0
 708     ONE = 1
 709     CA = 2
 710     # TODO OV = 3
 711
 712
 713 @unique
 714 class CRInSel(Enum):
 715     NONE = 0
 716     CR0 = 1
 717     BI = 2
 718     BFA = 3
 719     BA_BB = 4
 720     BC = 5
 721     WHOLE_REG = 6
 722     CR1 = 7
 723     BA = 8
 724
 725
 726 @unique
 727 class CRIn2Sel(Enum):
 728     NONE = 0
 729     BB = 1
 730
 731
 732 @unique
 733 class CROutSel(Enum):
 734     NONE = 0
 735     CR0 = 1
 736     BF = 2
 737     BT = 3
 738     WHOLE_REG = 4
 739     CR1 = 5
 740
 741
 742 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 743 # http://libre-riscv.org/openpower/isatables/sprs.csv
 744 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 745 # http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
 746
 747 def get_spr_enum(full_file):
 748     """get_spr_enum - creates an Enum of SPRs, dynamically
 749     has the option to reduce the enum to a much shorter list.
 750     this saves drastically on the size of the regfile
 751     """
 752     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
 753                   'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
 754                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
 755                   'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
 756                   # hmmm should not be including these, they are FAST regs
 757                   'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
 758                   'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
 759                   }
 760     spr_csv = []
 761     for row in get_csv("sprs.csv"):
 762         if full_file or row['SPR'] in short_list:
 763             spr_csv.append(row)
 764
 765     spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
 766     spr_dict = {}
 767     spr_byname = {}
 768     for row in spr_csv:
 769         info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
 770                         priv_mfspr=row['priv_mfspr'], length=int(row['len']),
 771                         idx=int(row['Idx']))
 772         spr_dict[int(row['Idx'])] = info
 773         spr_byname[row['SPR']] = info
 774     fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 775     SPR = Enum('SPR', fields)
 776     return SPR, spr_dict, spr_byname
 777
 778
 779 SPRfull, spr_dict, spr_byname = get_spr_enum(full_file=True)
 780 SPRreduced, _, _ = get_spr_enum(full_file=False)
 781
 782 XER_bits = {
 783     'SO': 32,
 784     'OV': 33,
 785     'CA': 34,
 786     'OV32': 44,
 787     'CA32': 45
 788 }
 789
 790 MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
 791
 792 if __name__ == '__main__':
 793     # find out what the heck is in SPR enum :)
 794     print("sprs full", len(SPRfull))
 795     print(dir(SPRfull))
 796     print("sprs reduced", len(SPRreduced))
 797     print(dir(SPRreduced))
 798     print(dir(Enum))
 799     print(SPRfull.__members__['TAR'])
 800     for x in SPRfull:
 801         print("full", x, x.value, str(x), x.name)
 802     for x in SPRreduced:
 803         print("reduced", x, x.value, str(x), x.name)
 804
 805     print("function", Function.ALU.name)