src/openpower/decoder/power_enums.py

   1 # SPDX-License-Identifier: LGPL-3-or-later
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020, Michael Nolan
   4
   5 """Enums used in OpenPOWER ISA decoding
   6
   7 Note: for SV, from v3.1B p12:
   8
   9     The designated SPR sandbox consists of non-privileged SPRs 704-719 and
  10     privileged SPRs 720-735.
  11
  12 Note: the option exists to select a much shorter list of SPRs, to reduce
  13 regfile size in HDL.  this is SPRreduced and the supported list is in
  14 get_spr_enum
  15 """
  16
  17 from enum import (
  18     auto,
  19     Enum as _Enum,
  20     unique,
  21 )
  22 import csv
  23 import os
  24 from os.path import dirname, join
  25 from collections import namedtuple
  26 import functools
  27
  28
  29 def find_wiki_dir():
  30     filedir = os.path.dirname(os.path.abspath(__file__))
  31     basedir = dirname(dirname(dirname(filedir)))
  32     tabledir = join(basedir, 'openpower')
  33     isatables = join(tabledir, 'isatables')
  34     #print ("find_wiki_dir", isatables)
  35     return isatables
  36
  37
  38 def find_wiki_file(name):
  39     return join(find_wiki_dir(), name)
  40
  41
  42 def get_csv(name):
  43     """gets a not-entirely-csv-file-formatted database, which allows comments
  44     """
  45     file_path = find_wiki_file(name)
  46     with open(file_path, 'r') as csvfile:
  47         csvfile = filter(lambda row: row[0] !='#', csvfile) # strip "#..."
  48         reader = csv.DictReader(csvfile)
  49         return list(reader)
  50
  51
  52 # names of the fields in the tables that don't correspond to an enum
  53 single_bit_flags = ['inv A', 'inv out',
  54                     'cry out', 'BR', 'sgn ext', 'rsrv', '32b',
  55                     'sgn', 'lk', 'sgl pipe']
  56
  57 # default values for fields in the table
  58 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  59                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  60                   'CR in': 'NONE',
  61                   'ldst len': 'NONE',
  62                   'upd': '0',
  63                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  64
  65
  66 def get_signal_name(name):
  67     if name[0].isdigit():
  68         name = "is_" + name
  69     return name.lower().replace(' ', '_')
  70
  71
  72 class Enum(_Enum):
  73     @classmethod
  74     def _missing_(cls, value):
  75         if isinstance(value, str):
  76             try:
  77                 if value == "":
  78                     value = 0
  79                 else:
  80                     value = int(value, 0)
  81             except ValueError:
  82                 pass
  83         keys = {item.name:item for item in cls}
  84         values = {item.value:item for item in cls}
  85         item = keys.get(value, values.get(value))
  86         if item is None:
  87             raise ValueError(value)
  88         return item
  89
  90
  91 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
  92 # is to process and guard the operation.  they are roughly divided by having
  93 # the same register input/output signature (X-Form, etc.)
  94
  95
  96 @unique
  97 class Function(Enum):
  98     NONE = 0
  99     ALU = 1 << 1
 100     LDST = 1 << 2
 101     SHIFT_ROT = 1 << 3
 102     LOGICAL = 1 << 4
 103     BRANCH = 1 << 5
 104     CR = 1 << 6
 105     TRAP = 1 << 7
 106     MUL = 1 << 8
 107     DIV = 1 << 9
 108     SPR = 1 << 10
 109     MMU = 1 << 11
 110     SV = 1 << 12  # Simple-V https://libre-soc.org/openpower/sv
 111     VL = 1 << 13  # setvl
 112     FPU = 1 << 14  # FPU
 113
 114     @functools.lru_cache(maxsize=None)
 115     def __repr__(self):
 116         counter = 0
 117         value = int(self.value)
 118         if value != 0:
 119             while value != 0:
 120                 counter += 1
 121                 value >>= 1
 122             counter -= 1
 123             desc = f"(1 << {counter})"
 124         else:
 125             desc = "0"
 126         return f"<{self.__class__.__name__}.{self.name}: {desc}>"
 127
 128
 129 @unique
 130 class Form(Enum):
 131     NONE = 0
 132     I = 1
 133     B = 2
 134     SC = 3
 135     D = 4
 136     DS = 5
 137     DQ = 6
 138     DX = 7
 139     X = 8
 140     XL = 9
 141     XFX = 10
 142     XFL = 11
 143     XX1 = 12
 144     XX2 = 13
 145     XX3 = 14
 146     XX4 = 15
 147     XS = 16
 148     XO = 17
 149     A = 18
 150     M = 19
 151     MD = 20
 152     MDS = 21
 153     VA = 22
 154     VC = 23
 155     VX = 24
 156     EVX = 25
 157     EVS = 26
 158     Z22 = 27
 159     Z23 = 28
 160     SVL = 29  # Simple-V for setvl instruction
 161     SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
 162     SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
 163     SVM = 32  # Simple-V SHAPE mode
 164     SVM2 = 33  # Simple-V SHAPE2 mode - fits into SVM
 165     SVRM = 34  # Simple-V REMAP mode
 166     TLI = 35  # ternlogi
 167     XB = 36
 168     BM2 = 37 # bmask
 169     SVI = 38  # Simple-V Index Mode
 170     VA2 = 39
 171     SVC = 40
 172     SVR = 41
 173
 174 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 175
 176
 177 class SVMode(Enum):
 178     NORMAL = auto()
 179     LDST_IDX = auto()
 180     LDST_IMM = auto()
 181     BRANCH = auto()
 182     CROP = auto()
 183
 184
 185 @unique
 186 class SVPtype(Enum):
 187     NONE = 0
 188     P1 = 1
 189     P2 = 2
 190
 191     @classmethod
 192     def _missing_(cls, value):
 193         return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
 194
 195
 196 @unique
 197 class SVEtype(Enum):
 198     NONE = 0
 199     EXTRA2 = 1
 200     EXTRA3 = 2
 201
 202
 203 @unique
 204 class SVExtra(Enum):
 205     NONE = 0
 206     Idx0 = 1
 207     Idx1 = 2
 208     Idx2 = 3
 209     Idx3 = 4
 210     Idx_1_2 = 5  # due to weird BA/BB for crops
 211
 212 # Backward compatibility
 213 SVEXTRA = SVExtra
 214
 215
 216 class SVExtraRegType(Enum):
 217     NONE = None
 218     SRC = 's'
 219     DST = 'd'
 220
 221
 222 class SVExtraReg(Enum):
 223     NONE = auto()
 224     RA = auto()
 225     RA_OR_ZERO = RA
 226     RB = auto()
 227     RC = auto()
 228     RS = auto()
 229     RT = auto()
 230     RT_OR_ZERO = RT
 231     FRA = auto()
 232     FRB = auto()
 233     FRC = auto()
 234     FRS = auto()
 235     FRT = auto()
 236     CR = auto()
 237     CR0 = auto()
 238     CR1 = auto()
 239     BF = auto()
 240     BFA = auto()
 241     BA = auto()
 242     BB = auto()
 243     BC = auto()
 244     BI = auto()
 245     BT = auto()
 246     BFT = auto()
 247     WHOLE_REG = auto()
 248     SPR = auto()
 249
 250     @classmethod
 251     def _missing_(cls, value):
 252         selectors = (
 253             In1Sel, In2Sel, In3Sel, CRInSel,
 254             OutSel, CROutSel,
 255         )
 256         if isinstance(value, selectors):
 257             return cls.__members__.get(value.name, cls.NONE)
 258         return super()._missing_(value)
 259
 260
 261 @unique
 262 class SVP64PredMode(Enum):
 263     ALWAYS = 0
 264     INT = 1
 265     CR = 2
 266
 267
 268 @unique
 269 class SVP64PredInt(Enum):
 270     ALWAYS = 0
 271     R3_UNARY = 1
 272     R3 = 2
 273     R3_N = 3
 274     R10 = 4
 275     R10_N = 5
 276     R30 = 6
 277     R30_N = 7
 278
 279
 280 @unique
 281 class SVP64PredCR(Enum):
 282     LT = 0
 283     GE = 1
 284     GT = 2
 285     LE = 3
 286     EQ = 4
 287     NE = 5
 288     SO = 6
 289     NS = 7
 290
 291
 292 @unique
 293 class SVP64RMMode(Enum):
 294     NORMAL = 0
 295     MAPREDUCE = 1
 296     FFIRST = 2
 297     SATURATE = 3
 298     PREDRES = 4
 299     BRANCH = 5
 300     PARALLEL = 6 # Parallel Reduction
 301
 302
 303 @unique
 304 class SVP64BCPredMode(Enum):
 305     NONE = 0
 306     MASKZERO = 1
 307     MASKONE = 2
 308
 309
 310 @unique
 311 class SVP64BCVLSETMode(Enum):
 312     NONE = 0
 313     VL_INCL = 1
 314     VL_EXCL = 2
 315
 316
 317 # note that these are chosen to be exactly the same as
 318 # SVP64 RM bit 4.  ALL=1 => bit4=1
 319 @unique
 320 class SVP64BCGate(Enum):
 321     ANY = 0
 322     ALL = 1
 323
 324
 325 class SVP64BCCTRMode(Enum):
 326     NONE = 0
 327     TEST = 1
 328     TEST_INV = 2
 329
 330
 331 @unique
 332 class SVP64width(Enum):
 333     DEFAULT = 0
 334     EW_32 = 1
 335     EW_16 = 2
 336     EW_8 = 3
 337
 338
 339 @unique
 340 class SVP64subvl(Enum):
 341     VEC1 = 0
 342     VEC2 = 1
 343     VEC3 = 2
 344     VEC4 = 3
 345
 346
 347 @unique
 348 class SVP64sat(Enum):
 349     NONE = 0
 350     SIGNED = 1
 351     UNSIGNED = 2
 352
 353
 354 @unique
 355 class SVP64LDSTmode(Enum):
 356     NONE = 0
 357     INDEXED = 1
 358     ELSTRIDE = 2
 359     UNITSTRIDE = 3
 360
 361
 362 class RegType(Enum):
 363     GPR = 0
 364     RA = GPR
 365     RB = GPR
 366     RC = GPR
 367     RS = GPR
 368     RT = GPR
 369
 370     FPR = 1
 371     FRA = FPR
 372     FRB = FPR
 373     FRC = FPR
 374     FRS = FPR
 375     FRT = FPR
 376
 377     CR_REG = 2
 378     BF = CR_REG
 379     BFA = CR_REG
 380
 381     CR_BIT = 3
 382     BA = CR_BIT
 383     BB = CR_BIT
 384     BC = CR_BIT
 385     BI = CR_BIT
 386     BT = CR_BIT
 387     BFT = CR_BIT
 388
 389
 390 # supported instructions: make sure to keep up-to-date with CSV files
 391 # just like everything else
 392 _insns = [
 393     "NONE", "add", "addc", "addco", "adde", "addeo",
 394     "addi", "addic", "addic.", "addis",
 395     "addme", "addmeo", "addo", "addze", "addzeo",
 396     "addg6s",
 397     "and", "andc", "andi.", "andis.",
 398     "attn",
 399     "absdu", "absds",                         # AV bitmanip
 400     "absdacs", "absdacu",                     # AV bitmanip
 401     "avgadd",                                 # AV bitmanip
 402     "b", "bc", "bcctr", "bclr", "bctar",
 403     "bmask",                                  # AV bitmanip
 404     "bpermd",
 405     "cbcdtd",
 406     "cdtbcd",
 407     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
 408     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
 409     "cprop", # AV bitmanip
 410     "crand", "crandc", "creqv",
 411     "crnand", "crnor", "cror", "crorc", "crxor",
 412     "darn",
 413     "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
 414     "divd", "divde", "divdeo", "divdeu",
 415     "divdeuo", "divdo", "divdu", "divduo", "divw", "divwe", "divweo",
 416     "divweu", "divweuo", "divwo", "divwu", "divwuo",
 417     "eieio", "eqv",
 418     "extsb", "extsh", "extsw", "extswsli",
 419     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
 420     "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
 421     "fdmadds",                                          # DCT FP 3-arg
 422     "fmsubs", "fmadds", "fnmsubs", "fnmadds",           # FP 3-arg
 423     "ffadds", "ffsubs", "ffmuls", "ffdivs",             # FFT FP 2-arg
 424     "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
 425     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
 426     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
 427     "fsins", "fcoss",                                   # FP SIN/COS
 428     "fmvis",                                            # FP load immediate
 429     "fishmv",                                           # Float Replace Lower-Half Single, Immediate
 430     'grev', 'grev.', 'grevi', 'grevi.',
 431     'grevw', 'grevw.', 'grevwi', 'grevwi.',
 432     "hrfid", "icbi", "icbt", "isel", "isync",
 433     "lbarx", "lbz", "lbzcix", "lbzu", "lbzux", "lbzx",  # load byte
 434     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
 435     # "lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
 436     # "ldbr", "ldubr",    # load double SVP64 bit-reversed
 437     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
 438     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax",  # FP load double
 439     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
 440     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
 441     # "lhabr", "lhaubr",  # load half SVP64 bit-reversed
 442     # "lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
 443     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
 444     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
 445     # "lwabr",           # load word SVP64 bit-reversed
 446     # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
 447     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
 448     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
 449     "mfmsr", "mfspr",
 450     "mins", "maxs", "minu", "maxu",                     # AV bitmanip
 451     "modsd", "modsw", "modud", "moduw",
 452     "mtcrf/mtocrf", "mtmsr", "mtmsrd", "mtspr",
 453     "mulhd", "mulhdu", "mulhw", "mulhwu", "mulld", "mulldo",
 454     "mulli", "mullw", "mullwo",
 455     "nand", "neg", "nego",
 456     "nop",
 457     "nor", "or", "orc", "ori", "oris",
 458     "popcntb", "popcntd", "popcntw",
 459     "prtyd", "prtyw",
 460     "rfid",
 461     "rldcl", "rldcr", "rldic", "rldicl", "rldicr", "rldimi",
 462     "rlwimi", "rlwinm",    "rlwnm",
 463     "setb",
 464     "setvl",  # https://libre-soc.org/openpower/sv/setvl
 465     "svindex",  # https://libre-soc.org/openpower/sv/remap
 466     "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
 467     "svshape",  # https://libre-soc.org/openpower/sv/remap/#svshape
 468     "svshape2",  # https://libre-soc.org/openpower/sv/remap/discussion TODO
 469     "svstep",  # https://libre-soc.org/openpower/sv/setvl
 470     "sim_cfg",
 471     "slbia", "sld", "slw", "srad", "sradi",
 472     "sraw", "srawi", "srd", "srw",
 473     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
 474     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
 475     "stfs", "stfsx", "stfsu", "stfux", "stfsux",        # FP store single
 476     "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store double
 477     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
 478     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
 479     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
 480     "subfme", "subfmeo", "subfo", "subfze", "subfzeo",
 481     "sync",
 482     "ternlogi",
 483     "td", "tdi",
 484     "tlbie", "tlbiel", "tlbsync",
 485     "tw", "twi",
 486     "wait",
 487     "xor", "xori", "xoris",
 488 ]
 489
 490 # two-way lookup of instruction-to-index and vice-versa
 491 insns = {}
 492 asmidx = {}
 493 for i, insn in enumerate(_insns):
 494     insns[i] = insn
 495     asmidx[insn] = i
 496
 497 # must be long enough to cover all instructions
 498 asmlen = len(_insns).bit_length()
 499
 500 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 501
 502
 503 @unique
 504 class MicrOp(Enum):
 505     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
 506     OP_NOP = 1
 507     OP_ADD = 2
 508     OP_ADDPCIS = 3
 509     OP_AND = 4
 510     OP_ATTN = 5
 511     OP_B = 6
 512     OP_BC = 7
 513     OP_BCREG = 8
 514     OP_BPERM = 9
 515     OP_CMP = 10
 516     OP_CMPB = 11
 517     OP_CMPEQB = 12
 518     OP_CMPRB = 13
 519     OP_CNTZ = 14
 520     OP_CRAND = 15
 521     OP_CRANDC = 16
 522     OP_CREQV = 17
 523     OP_CRNAND = 18
 524     OP_CRNOR = 19
 525     OP_CROR = 20
 526     OP_CRORC = 21
 527     OP_CRXOR = 22
 528     OP_DARN = 23
 529     OP_DCBF = 24
 530     OP_DCBST = 25
 531     OP_DCBT = 26
 532     OP_DCBTST = 27
 533     OP_DCBZ = 28
 534     OP_DIV = 29
 535     OP_DIVE = 30
 536     OP_EXTS = 31
 537     OP_EXTSWSLI = 32
 538     OP_ICBI = 33
 539     OP_ICBT = 34
 540     OP_ISEL = 35
 541     OP_ISYNC = 36
 542     OP_LOAD = 37
 543     OP_STORE = 38
 544     OP_MADDHD = 39
 545     OP_MADDHDU = 40
 546     OP_MADDLD = 41
 547     OP_MCRF = 42
 548     OP_MCRXR = 43
 549     OP_MCRXRX = 44
 550     OP_MFCR = 45
 551     OP_MFSPR = 46
 552     OP_MOD = 47
 553     OP_MTCRF = 48
 554     OP_MTSPR = 49
 555     OP_MUL_L64 = 50
 556     OP_MUL_H64 = 51
 557     OP_MUL_H32 = 52
 558     OP_OR = 53
 559     OP_POPCNT = 54
 560     OP_PRTY = 55
 561     OP_RLC = 56
 562     OP_RLCL = 57
 563     OP_RLCR = 58
 564     OP_SETB = 59
 565     OP_SHL = 60
 566     OP_SHR = 61
 567     OP_SYNC = 62
 568     OP_TRAP = 63
 569     OP_XOR = 67
 570     OP_SIM_CONFIG = 68
 571     OP_CROP = 69
 572     OP_RFID = 70
 573     OP_MFMSR = 71
 574     OP_MTMSRD = 72
 575     OP_SC = 73
 576     OP_MTMSR = 74
 577     OP_TLBIE = 75
 578     OP_SETVL = 76
 579     OP_FPOP = 77  # temporary: replace with actual ops
 580     OP_FPOP_I = 78  # temporary: replace with actual ops
 581     OP_FP_MADD = 79
 582     OP_SVREMAP = 80
 583     OP_SVSHAPE = 81
 584     OP_SVSTEP = 82
 585     OP_ADDG6S = 83
 586     OP_CDTBCD = 84
 587     OP_CBCDTD = 85
 588     OP_TERNLOG = 86
 589     OP_FETCH_FAILED = 87
 590     OP_GREV = 88
 591     OP_MINMAX = 89
 592     OP_AVGADD = 90
 593     OP_ABSDIFF = 91
 594     OP_ABSADD = 92
 595     OP_CPROP = 93
 596     OP_BMASK = 94
 597     OP_SVINDEX = 95
 598     OP_FMVIS = 96
 599     OP_FISHMV = 97
 600
 601
 602 @unique
 603 class In1Sel(Enum):
 604     NONE = 0
 605     RA = 1
 606     RA_OR_ZERO = 2
 607     SPR = 3
 608     RS = 4  # for some ALU/Logical operations
 609     FRA = 5
 610     FRS = 6
 611
 612
 613 @unique
 614 class In2Sel(Enum):
 615     NONE = 0
 616     RB = 1
 617     CONST_UI = 2
 618     CONST_SI = 3
 619     CONST_UI_HI = 4
 620     CONST_SI_HI = 5
 621     CONST_LI = 6
 622     CONST_BD = 7
 623     CONST_DS = 8
 624     CONST_M1 = 9
 625     CONST_SH = 10
 626     CONST_SH32 = 11
 627     SPR = 12
 628     RS = 13  # for shiftrot (M-Form)
 629     FRB = 14
 630     CONST_SVD = 15  # for SVD-Form
 631     CONST_SVDS = 16  # for SVDS-Form
 632     CONST_XBI = 17
 633
 634
 635 @unique
 636 class In3Sel(Enum):
 637     NONE = 0
 638     RS = 1
 639     RB = 2  # for shiftrot (M-Form)
 640     FRS = 3
 641     FRC = 4
 642     RC = 5  # for SVP64 bit-reverse LD/ST
 643     RT = 6  # for ternlog[i]
 644
 645
 646 @unique
 647 class OutSel(Enum):
 648     NONE = 0
 649     RT = 1
 650     RA = 2
 651     SPR = 3
 652     RT_OR_ZERO = 4
 653     FRT = 5
 654     FRS = 6
 655
 656
 657 @unique
 658 class LDSTLen(Enum):
 659     NONE = 0
 660     is1B = 1
 661     is2B = 2
 662     is4B = 4
 663     is8B = 8
 664
 665 # Backward compatibility
 666 LdstLen = LDSTLen
 667
 668
 669 @unique
 670 class LDSTMode(Enum):
 671     NONE = 0
 672     update = 1
 673     cix = 2
 674     cx = 3
 675
 676
 677 @unique
 678 class RCOE(Enum):
 679     NONE = 0
 680     ONE = 1
 681     RC = 2    # includes OE
 682     RC_ONLY = 3  # does not include OE
 683
 684
 685 @unique
 686 class CryIn(Enum):
 687     ZERO = 0
 688     ONE = 1
 689     CA = 2
 690     # TODO OV = 3
 691
 692
 693 @unique
 694 class CRInSel(Enum):
 695     NONE = 0
 696     CR0 = 1
 697     BI = 2
 698     BFA = 3
 699     BA_BB = 4
 700     BC = 5
 701     WHOLE_REG = 6
 702     CR1 = 7
 703
 704
 705 @unique
 706 class CROutSel(Enum):
 707     NONE = 0
 708     CR0 = 1
 709     BF = 2
 710     BT = 3
 711     WHOLE_REG = 4
 712     CR1 = 5
 713
 714
 715 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 716 # http://libre-riscv.org/openpower/isatables/sprs.csv
 717 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 718 # http://bugs.libre-riscv.org/show_bug.cgi?id=859 - KAIVB
 719
 720 def get_spr_enum(full_file):
 721     """get_spr_enum - creates an Enum of SPRs, dynamically
 722     has the option to reduce the enum to a much shorter list.
 723     this saves drastically on the size of the regfile
 724     """
 725     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
 726                   'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',
 727                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
 728                   'SPRG0', 'SPRG1', 'SPRG2', 'SPRG3', 'KAIVB',
 729                   # hmmm should not be including these, they are FAST regs
 730                   'CTR', 'LR', 'TAR', 'SRR0', 'SRR1', 'XER', 'DEC', 'TB', 'TBU',
 731                   'HSRR0', 'HSRR1', 'HSPRG0', 'HSPRG1',
 732                   }
 733     spr_csv = []
 734     for row in get_csv("sprs.csv"):
 735         if full_file or row['SPR'] in short_list:
 736             spr_csv.append(row)
 737
 738     spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length idx')
 739     spr_dict = {}
 740     spr_byname = {}
 741     for row in spr_csv:
 742         info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
 743                         priv_mfspr=row['priv_mfspr'], length=int(row['len']),
 744                         idx=int(row['Idx']))
 745         spr_dict[int(row['Idx'])] = info
 746         spr_byname[row['SPR']] = info
 747     fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 748     SPR = Enum('SPR', fields)
 749     return SPR, spr_dict, spr_byname
 750
 751
 752 SPRfull, spr_dict, spr_byname = get_spr_enum(full_file=True)
 753 SPRreduced, _, _ = get_spr_enum(full_file=False)
 754
 755 XER_bits = {
 756     'SO': 32,
 757     'OV': 33,
 758     'CA': 34,
 759     'OV32': 44,
 760     'CA32': 45
 761 }
 762
 763 MSRSpec = namedtuple("MSRSpec", ["dr", "pr", "sf"])
 764
 765 if __name__ == '__main__':
 766     # find out what the heck is in SPR enum :)
 767     print("sprs full", len(SPRfull))
 768     print(dir(SPRfull))
 769     print("sprs reduced", len(SPRreduced))
 770     print(dir(SPRreduced))
 771     print(dir(Enum))
 772     print(SPRfull.__members__['TAR'])
 773     for x in SPRfull:
 774         print("full", x, x.value, str(x), x.name)
 775     for x in SPRreduced:
 776         print("reduced", x, x.value, str(x), x.name)
 777
 778     print("function", Function.ALU.name)