1 import collections
as _collections
3 import dataclasses
as _dataclasses
5 import functools
as _functools
7 import operator
as _operator
8 import pathlib
as _pathlib
12 from functools
import cached_property
14 from cached_property
import cached_property
16 from openpower
.decoder
.power_enums
import (
17 Function
as _Function
,
24 CRIn2Sel
as _CRIn2Sel
,
25 CROutSel
as _CROutSel
,
27 LDSTMode
as _LDSTMode
,
32 SVMaskSrc
as _SVMaskSrc
,
37 SVP64RMMode
as _SVP64RMMode
,
38 SVExtraRegType
as _SVExtraRegType
,
39 SVExtraReg
as _SVExtraReg
,
40 SVP64SubVL
as _SVP64SubVL
,
41 SVP64Pred
as _SVP64Pred
,
42 SVP64PredMode
as _SVP64PredMode
,
43 SVP64Width
as _SVP64Width
,
45 from openpower
.decoder
.selectable_int
import (
46 SelectableInt
as _SelectableInt
,
47 selectconcat
as _selectconcat
,
49 from openpower
.decoder
.power_fields
import (
52 DecodeFields
as _DecodeFields
,
54 from openpower
.decoder
.pseudo
.pagereader
import ISA
as _ISA
57 @_functools.total_ordering
58 class Style(_enum
.Enum
):
62 VERBOSE
= _enum
.auto()
64 def __lt__(self
, other
):
65 if not isinstance(other
, self
.__class
__):
67 return (self
.value
< other
.value
)
70 @_functools.total_ordering
71 class Priority(_enum
.Enum
):
77 def _missing_(cls
, value
):
78 if isinstance(value
, str):
83 return super()._missing
_(value
)
85 def __lt__(self
, other
):
86 if not isinstance(other
, self
.__class
__):
89 # NOTE: the order is inversed, LOW < NORMAL < HIGH
90 return (self
.value
> other
.value
)
93 def dataclass(cls
, record
, keymap
=None, typemap
=None):
97 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
99 def transform(key_value
):
100 (key
, value
) = key_value
101 key
= keymap
.get(key
, key
)
102 hook
= typemap
.get(key
, lambda value
: value
)
103 if hook
is bool and value
in ("", "0"):
109 record
= dict(map(transform
, record
.items()))
110 for key
in frozenset(record
.keys()):
111 if record
[key
] == "":
117 @_functools.total_ordering
118 @_dataclasses.dataclass(eq
=True, frozen
=True)
121 def __new__(cls
, value
):
122 if isinstance(value
, str):
123 value
= int(value
, 0)
124 if not isinstance(value
, int):
125 raise ValueError(value
)
127 if value
.bit_length() > 64:
128 raise ValueError(value
)
130 return super().__new
__(cls
, value
)
133 return self
.__repr
__()
136 return f
"{self:0{self.bit_length()}b}"
138 def bit_length(self
):
139 if super().bit_length() > 32:
143 class Value(Integer
):
152 def __lt__(self
, other
):
153 if not isinstance(other
, Opcode
):
154 return NotImplemented
155 return ((self
.value
, self
.mask
) < (other
.value
, other
.mask
))
158 def pattern(value
, mask
, bit_length
):
159 for bit
in range(bit_length
):
160 if ((mask
& (1 << (bit_length
- bit
- 1))) == 0):
162 elif (value
& (1 << (bit_length
- bit
- 1))):
167 return "".join(pattern(self
.value
, self
.mask
, self
.value
.bit_length()))
169 def match(self
, key
):
170 return ((self
.value
& self
.mask
) == (key
& self
.mask
))
173 @_functools.total_ordering
174 @_dataclasses.dataclass(eq
=True, frozen
=True)
175 class IntegerOpcode(Opcode
):
176 def __init__(self
, value
):
177 if value
.startswith("0b"):
178 mask
= int(("1" * len(value
[2:])), 2)
182 value
= Opcode
.Value(value
)
183 mask
= Opcode
.Mask(mask
)
185 return super().__init
__(value
=value
, mask
=mask
)
188 @_functools.total_ordering
189 @_dataclasses.dataclass(eq
=True, frozen
=True)
190 class PatternOpcode(Opcode
):
191 def __init__(self
, pattern
):
192 if not isinstance(pattern
, str):
193 raise ValueError(pattern
)
195 (value
, mask
) = (0, 0)
196 for symbol
in pattern
:
197 if symbol
not in {"0", "1", "-"}:
198 raise ValueError(pattern
)
199 value |
= (symbol
== "1")
200 mask |
= (symbol
!= "-")
206 value
= Opcode
.Value(value
)
207 mask
= Opcode
.Mask(mask
)
209 return super().__init
__(value
=value
, mask
=mask
)
212 @_dataclasses.dataclass(eq
=True, frozen
=True)
214 class FlagsMeta(type):
229 class Flags(tuple, metaclass
=FlagsMeta
):
230 def __new__(cls
, flags
=frozenset()):
231 flags
= frozenset(flags
)
232 diff
= (flags
- frozenset(cls
))
234 raise ValueError(flags
)
235 return super().__new
__(cls
, sorted(flags
))
239 flags
: Flags
= Flags()
241 function
: _Function
= _Function
.NONE
242 intop
: _MicrOp
= _MicrOp
.OP_ILLEGAL
243 in1
: _In1Sel
= _In1Sel
.RA
244 in2
: _In2Sel
= _In2Sel
.NONE
245 in3
: _In3Sel
= _In3Sel
.NONE
246 out
: _OutSel
= _OutSel
.NONE
247 cr_in
: _CRInSel
= _CRInSel
.NONE
248 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
249 cr_out
: _CROutSel
= _CROutSel
.NONE
250 cry_in
: _CryIn
= _CryIn
.ZERO
251 ldst_len
: _LDSTLen
= _LDSTLen
.NONE
252 upd
: _LDSTMode
= _LDSTMode
.NONE
253 Rc
: _RCOE
= _RCOE
.NONE
254 form
: _Form
= _Form
.NONE
256 unofficial
: bool = False
260 "internal op": "intop",
264 "ldst len": "ldst_len",
266 "CONDITIONS": "conditions",
269 def __lt__(self
, other
):
270 if not isinstance(other
, self
.__class
__):
271 return NotImplemented
272 lhs
= (self
.opcode
, self
.comment
)
273 rhs
= (other
.opcode
, other
.comment
)
277 def CSV(cls
, record
, opcode_cls
):
278 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
279 typemap
["opcode"] = opcode_cls
281 if record
["CR in"] == "BA_BB":
282 record
["cr_in"] = "BA"
283 record
["cr_in2"] = "BB"
287 for flag
in frozenset(PPCRecord
.Flags
):
288 if bool(record
.pop(flag
, "")):
290 record
["flags"] = PPCRecord
.Flags(flags
)
292 return dataclass(cls
, record
,
293 keymap
=PPCRecord
.__KEYMAP
,
298 return frozenset(self
.comment
.split("=")[-1].split("/"))
301 class PPCMultiRecord(tuple):
302 def __getattr__(self
, attr
):
305 raise AttributeError(attr
)
306 return getattr(self
[0], attr
)
309 @_dataclasses.dataclass(eq
=True, frozen
=True)
311 class ExtraMap(tuple):
313 @_dataclasses.dataclass(eq
=True, frozen
=True)
315 regtype
: _SVExtraRegType
= _SVExtraRegType
.NONE
316 reg
: _SVExtraReg
= _SVExtraReg
.NONE
319 return f
"{self.regtype.value}:{self.reg.name}"
321 def __new__(cls
, value
="0"):
322 if isinstance(value
, str):
323 def transform(value
):
324 (regtype
, reg
) = value
.split(":")
325 regtype
= _SVExtraRegType(regtype
)
326 reg
= _SVExtraReg(reg
)
327 return cls
.Entry(regtype
=regtype
, reg
=reg
)
332 value
= map(transform
, value
.split(";"))
334 return super().__new
__(cls
, value
)
337 return repr(list(self
))
339 def __new__(cls
, value
=tuple()):
343 return super().__new
__(cls
, map(cls
.Extra
, value
))
346 return repr({index
:self
[index
] for index
in range(0, 4)})
349 ptype
: _SVPType
= _SVPType
.NONE
350 etype
: _SVEType
= _SVEType
.NONE
351 msrc
: _SVMaskSrc
= _SVMaskSrc
.NO
# MASK_SRC is active
352 in1
: _In1Sel
= _In1Sel
.NONE
353 in2
: _In2Sel
= _In2Sel
.NONE
354 in3
: _In3Sel
= _In3Sel
.NONE
355 out
: _OutSel
= _OutSel
.NONE
356 out2
: _OutSel
= _OutSel
.NONE
357 cr_in
: _CRInSel
= _CRInSel
.NONE
358 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
359 cr_out
: _CROutSel
= _CROutSel
.NONE
360 extra
: ExtraMap
= ExtraMap()
362 mode
: _SVMode
= _SVMode
.NORMAL
366 "CONDITIONS": "conditions",
375 def CSV(cls
, record
):
376 for key
in frozenset({
377 "in1", "in2", "in3", "CR in",
378 "out", "out2", "CR out",
384 if record
["CR in"] == "BA_BB":
385 record
["cr_in"] = "BA"
386 record
["cr_in2"] = "BB"
390 for idx
in range(0, 4):
391 extra
.append(record
.pop(f
"{idx}"))
393 record
["extra"] = cls
.ExtraMap(extra
)
395 return dataclass(cls
, record
, keymap
=cls
.__KEYMAP
)
397 @_functools.lru_cache(maxsize
=None)
398 def extra_idx(self
, key
):
406 if key
not in frozenset({
407 "in1", "in2", "in3", "cr_in", "cr_in2",
408 "out", "out2", "cr_out",
412 sel
= getattr(self
, key
)
413 if sel
is _CRInSel
.BA_BB
:
414 return _SVExtra
.Idx_1_2
415 reg
= _SVExtraReg(sel
)
416 if reg
is _SVExtraReg
.NONE
:
420 _SVExtraRegType
.SRC
: {},
421 _SVExtraRegType
.DST
: {},
423 for index
in range(0, 4):
424 for entry
in self
.extra
[index
]:
425 extra_map
[entry
.regtype
][entry
.reg
] = extra_idx
[index
]
427 for regtype
in (_SVExtraRegType
.SRC
, _SVExtraRegType
.DST
):
428 extra
= extra_map
[regtype
].get(reg
, _SVExtra
.NONE
)
429 if extra
is not _SVExtra
.NONE
:
434 extra_idx_in1
= property(_functools
.partial(extra_idx
, key
="in1"))
435 extra_idx_in2
= property(_functools
.partial(extra_idx
, key
="in2"))
436 extra_idx_in3
= property(_functools
.partial(extra_idx
, key
="in3"))
437 extra_idx_out
= property(_functools
.partial(extra_idx
, key
="out"))
438 extra_idx_out2
= property(_functools
.partial(extra_idx
, key
="out2"))
439 extra_idx_cr_in
= property(_functools
.partial(extra_idx
, key
="cr_in"))
440 extra_idx_cr_in2
= property(_functools
.partial(extra_idx
, key
="cr_in2"))
441 extra_idx_cr_out
= property(_functools
.partial(extra_idx
, key
="cr_out"))
443 @_functools.lru_cache(maxsize
=None)
444 def extra_reg(self
, key
):
445 return _SVExtraReg(getattr(self
, key
))
447 extra_reg_in1
= property(_functools
.partial(extra_reg
, key
="in1"))
448 extra_reg_in2
= property(_functools
.partial(extra_reg
, key
="in2"))
449 extra_reg_in3
= property(_functools
.partial(extra_reg
, key
="in3"))
450 extra_reg_out
= property(_functools
.partial(extra_reg
, key
="out"))
451 extra_reg_out2
= property(_functools
.partial(extra_reg
, key
="out2"))
452 extra_reg_cr_in
= property(_functools
.partial(extra_reg
, key
="cr_in"))
453 extra_reg_cr_in2
= property(_functools
.partial(extra_reg
, key
="cr_in2"))
454 extra_reg_cr_out
= property(_functools
.partial(extra_reg
, key
="cr_out"))
459 for idx
in range(0, 4):
460 for entry
in self
.extra
[idx
]:
461 if entry
.regtype
is _SVExtraRegType
.DST
:
462 if extra
is not None:
463 raise ValueError(self
.svp64
)
467 if _RegType(extra
.reg
) not in (_RegType
.CR_3BIT
, _RegType
.CR_5BIT
):
468 raise ValueError(self
.svp64
)
473 def extra_CR_3bit(self
):
474 return (_RegType(self
.extra_CR
.reg
) is _RegType
.CR_3BIT
)
478 def __init__(self
, value
=(0, 32)):
479 if isinstance(value
, str):
480 (start
, end
) = map(int, value
.split(":"))
483 if start
< 0 or end
< 0 or start
>= end
:
484 raise ValueError(value
)
489 return super().__init
__()
492 return (self
.__end
- self
.__start
+ 1)
495 return f
"[{self.__start}:{self.__end}]"
498 yield from range(self
.start
, (self
.end
+ 1))
500 def __reversed__(self
):
501 return tuple(reversed(tuple(self
)))
512 @_dataclasses.dataclass(eq
=True, frozen
=True)
514 class Mode(_enum
.Enum
):
515 INTEGER
= _enum
.auto()
516 PATTERN
= _enum
.auto()
519 def _missing_(cls
, value
):
520 if isinstance(value
, str):
521 return cls
[value
.upper()]
522 return super()._missing
_(value
)
525 def __new__(cls
, value
=None):
526 if isinstance(value
, str):
527 if value
.upper() == "NONE":
530 value
= int(value
, 0)
534 return super().__new
__(cls
, value
)
540 return (bin(self
) if self
else "None")
546 opcode
: IntegerOpcode
= None
547 priority
: Priority
= Priority
.NORMAL
549 def __lt__(self
, other
):
550 if not isinstance(other
, self
.__class
__):
551 return NotImplemented
552 return (self
.priority
< other
.priority
)
555 def CSV(cls
, record
):
556 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
557 if record
["opcode"] == "NONE":
558 typemap
["opcode"] = lambda _
: None
560 return dataclass(cls
, record
, typemap
=typemap
)
564 def __init__(self
, items
):
565 if isinstance(items
, dict):
566 items
= items
.items()
569 (name
, bitrange
) = item
570 return (name
, tuple(bitrange
.values()))
572 self
.__mapping
= dict(map(transform
, items
))
574 return super().__init
__()
577 return repr(self
.__mapping
)
580 yield from self
.__mapping
.items()
582 def __contains__(self
, key
):
583 return self
.__mapping
.__contains
__(key
)
585 def __getitem__(self
, key
):
586 return self
.__mapping
.get(key
, None)
601 def __init__(self
, insn
, iterable
):
603 "b": {"target_addr": TargetAddrOperandLI
},
604 "ba": {"target_addr": TargetAddrOperandLI
},
605 "bl": {"target_addr": TargetAddrOperandLI
},
606 "bla": {"target_addr": TargetAddrOperandLI
},
607 "bc": {"target_addr": TargetAddrOperandBD
},
608 "bca": {"target_addr": TargetAddrOperandBD
},
609 "bcl": {"target_addr": TargetAddrOperandBD
},
610 "bcla": {"target_addr": TargetAddrOperandBD
},
611 "addpcis": {"D": DOperandDX
},
612 "fishmv": {"D": DOperandDX
},
613 "fmvis": {"D": DOperandDX
},
616 "SVi": NonZeroOperand
,
617 "SVd": NonZeroOperand
,
618 "SVxd": NonZeroOperand
,
619 "SVyd": NonZeroOperand
,
620 "SVzd": NonZeroOperand
,
622 "D": SignedImmediateOperand
,
626 "SIM": SignedOperand
,
627 "SVD": SignedOperand
,
628 "SVDS": SignedOperand
,
629 "RSp": GPRPairOperand
,
630 "RTp": GPRPairOperand
,
631 "FRAp": FPRPairOperand
,
632 "FRBp": FPRPairOperand
,
633 "FRSp": FPRPairOperand
,
634 "FRTp": FPRPairOperand
,
636 custom_immediates
= {
642 for operand
in iterable
:
646 (name
, value
) = operand
.split("=")
647 mapping
[name
] = (StaticOperand
, {
653 if name
.endswith(")"):
654 name
= name
.replace("(", " ").replace(")", "")
655 (imm_name
, _
, name
) = name
.partition(" ")
659 if imm_name
is not None:
660 imm_cls
= custom_immediates
.get(imm_name
, ImmediateOperand
)
662 if insn
in custom_insns
and name
in custom_insns
[insn
]:
663 cls
= custom_insns
[insn
][name
]
664 elif name
in custom_fields
:
665 cls
= custom_fields
[name
]
667 if name
in _SVExtraReg
.__members
__:
668 reg
= _SVExtraReg
[name
]
669 if reg
in self
.__class
__.__GPR
_PAIRS
:
671 elif reg
in self
.__class
__.__FPR
_PAIRS
:
674 regtype
= _RegType
[name
]
675 if regtype
is _RegType
.GPR
:
677 elif regtype
is _RegType
.FPR
:
679 elif regtype
is _RegType
.CR_3BIT
:
681 elif regtype
is _RegType
.CR_5BIT
:
684 if imm_name
is not None:
685 mapping
[imm_name
] = (imm_cls
, {"name": imm_name
})
686 mapping
[name
] = (cls
, {"name": name
})
690 for (name
, (cls
, kwargs
)) in mapping
.items():
691 kwargs
= dict(kwargs
)
692 kwargs
["name"] = name
693 if issubclass(cls
, StaticOperand
):
694 static
.append((cls
, kwargs
))
695 elif issubclass(cls
, DynamicOperand
):
696 dynamic
.append((cls
, kwargs
))
698 raise ValueError(name
)
700 self
.__mapping
= mapping
701 self
.__static
= tuple(static
)
702 self
.__dynamic
= tuple(dynamic
)
704 return super().__init
__()
707 for (_
, items
) in self
.__mapping
.items():
708 (cls
, kwargs
) = items
712 return self
.__mapping
.__repr
__()
714 def __contains__(self
, key
):
715 return self
.__mapping
.__contains
__(key
)
717 def __getitem__(self
, key
):
718 return self
.__mapping
.__getitem
__(key
)
726 return self
.__dynamic
729 class Arguments(tuple):
730 def __new__(cls
, arguments
, operands
):
731 arguments
= iter(tuple(arguments
))
732 operands
= iter(tuple(operands
))
737 operand
= next(operands
)
738 except StopIteration:
742 argument
= next(arguments
)
743 except StopIteration:
744 raise ValueError("operands count mismatch")
746 if isinstance(operand
, ImmediateOperand
):
747 argument
= argument
.replace("(", " ").replace(")", "")
748 (imm_argument
, _
, argument
) = argument
.partition(" ")
750 (imm_operand
, operand
) = (operand
, next(operands
))
751 except StopIteration:
752 raise ValueError("operands count mismatch")
753 items
.append((imm_argument
, imm_operand
))
754 items
.append((argument
, operand
))
758 except StopIteration:
761 raise ValueError("operands count mismatch")
763 return super().__new
__(cls
, items
)
767 def __init__(self
, iterable
):
768 self
.__pcode
= tuple(iterable
)
769 return super().__init
__()
772 yield from self
.__pcode
775 return self
.__pcode
.__repr
__()
778 @_dataclasses.dataclass(eq
=True, frozen
=True)
779 class MarkdownRecord
:
784 @_functools.total_ordering
785 @_dataclasses.dataclass(eq
=True, frozen
=True)
792 svp64
: SVP64Record
= None
794 def __lt__(self
, other
):
795 if not isinstance(other
, Record
):
796 return NotImplemented
797 lhs
= (min(self
.opcodes
), self
.name
)
798 rhs
= (min(other
.opcodes
), other
.name
)
803 return (self
.static_operands
+ self
.dynamic_operands
)
806 def static_operands(self
):
808 operands
.append(POStaticOperand(record
=self
, value
=self
.PO
))
810 operands
.append(XOStaticOperand(
812 value
=ppc
.opcode
.value
,
813 span
=self
.section
.bitsel
,
815 for (cls
, kwargs
) in self
.mdwn
.operands
.static
:
816 operands
.append(cls(record
=self
, **kwargs
))
817 return tuple(operands
)
820 def dynamic_operands(self
):
822 for (cls
, kwargs
) in self
.mdwn
.operands
.dynamic
:
823 operands
.append(cls(record
=self
, **kwargs
))
824 return tuple(operands
)
829 return int("".join(str(int(mapping
[bit
])) for bit
in sorted(mapping
)), 2)
831 def PO_XO(value
, mask
, opcode
, bits
):
834 for (src
, dst
) in enumerate(reversed(bits
)):
835 value
[dst
] = ((opcode
.value
& (1 << src
)) != 0)
836 mask
[dst
] = ((opcode
.mask
& (1 << src
)) != 0)
839 def PO(value
, mask
, opcode
, bits
):
840 return PO_XO(value
=value
, mask
=mask
, opcode
=opcode
, bits
=bits
)
842 def XO(value
, mask
, opcode
, bits
):
843 (value
, mask
) = PO_XO(value
=value
, mask
=mask
, opcode
=opcode
, bits
=bits
)
844 for (op_cls
, op_kwargs
) in self
.mdwn
.operands
.static
:
845 operand
= op_cls(record
=self
, **op_kwargs
)
846 for (src
, dst
) in enumerate(reversed(operand
.span
)):
847 value
[dst
] = ((operand
.value
& (1 << src
)) != 0)
852 value
= {bit
:False for bit
in range(32)}
853 mask
= {bit
:False for bit
in range(32)}
854 if self
.section
.opcode
is not None:
855 (value
, mask
) = PO(value
=value
, mask
=mask
,
856 opcode
=self
.section
.opcode
, bits
=range(0, 6))
858 pairs
.append(XO(value
=value
, mask
=mask
,
859 opcode
=ppc
.opcode
, bits
=self
.section
.bitsel
))
862 for (value
, mask
) in pairs
:
863 value
= Opcode
.Value(binary(value
))
864 mask
= Opcode
.Mask(binary(mask
))
865 result
.append(Opcode(value
=value
, mask
=mask
))
871 opcode
= self
.section
.opcode
873 opcode
= self
.ppc
[0].opcode
874 if isinstance(opcode
, PatternOpcode
):
875 value
= int(opcode
.value
)
876 bits
= opcode
.value
.bit_length()
877 return int(_SelectableInt(value
=value
, bits
=bits
)[0:6])
879 return int(opcode
.value
)
883 return tuple(ppc
.opcode
for ppc
in self
.ppc
)
885 def match(self
, key
):
886 for opcode
in self
.opcodes
:
887 if opcode
.match(key
):
894 return self
.svp64
.mode
914 if self
.svp64
is None:
920 return self
.ppc
.cr_in
924 return self
.ppc
.cr_in2
928 return self
.ppc
.cr_out
930 ptype
= property(lambda self
: self
.svp64
.ptype
)
931 etype
= property(lambda self
: self
.svp64
.etype
)
933 def extra_idx(self
, key
):
934 return self
.svp64
.extra_idx(key
)
936 extra_idx_in1
= property(lambda self
: self
.svp64
.extra_idx_in1
)
937 extra_idx_in2
= property(lambda self
: self
.svp64
.extra_idx_in2
)
938 extra_idx_in3
= property(lambda self
: self
.svp64
.extra_idx_in3
)
939 extra_idx_out
= property(lambda self
: self
.svp64
.extra_idx_out
)
940 extra_idx_out2
= property(lambda self
: self
.svp64
.extra_idx_out2
)
941 extra_idx_cr_in
= property(lambda self
: self
.svp64
.extra_idx_cr_in
)
942 extra_idx_cr_in2
= property(lambda self
: self
.svp64
.extra_idx_cr_in2
)
943 extra_idx_cr_out
= property(lambda self
: self
.svp64
.extra_idx_cr_out
)
945 def __contains__(self
, key
):
946 return self
.mdwn
.operands
.__contains
__(key
)
948 def __getitem__(self
, key
):
949 (cls
, kwargs
) = self
.mdwn
.operands
.__getitem
__(key
)
950 return cls(record
=self
, **kwargs
)
956 return self
["Rc"].value
960 def __init__(self
, record
, name
):
961 self
.__record
= record
965 yield ("record", self
.record
)
966 yield ("name", self
.__name
)
969 return f
"{self.__class__.__name__}({self.name})"
981 return self
.record
.fields
[self
.name
]
983 def assemble(self
, insn
):
984 raise NotImplementedError()
986 def disassemble(self
, insn
,
987 style
=Style
.NORMAL
, indent
=""):
988 raise NotImplementedError()
991 class DynamicOperand(Operand
):
992 def assemble(self
, insn
, value
):
994 if isinstance(value
, str):
995 value
= int(value
, 0)
997 raise ValueError("signed operands not allowed")
1000 def disassemble(self
, insn
,
1001 style
=Style
.NORMAL
, indent
=""):
1005 if style
>= Style
.VERBOSE
:
1006 span
= map(str, span
)
1007 yield f
"{indent}{self.name}"
1008 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1009 yield f
"{indent}{indent}{', '.join(span)}"
1011 yield str(int(value
))
1014 class SignedOperand(DynamicOperand
):
1015 def assemble(self
, insn
, value
):
1016 if isinstance(value
, str):
1017 value
= int(value
, 0)
1018 return super().assemble(value
=value
, insn
=insn
)
1020 def assemble(self
, insn
, value
):
1022 if isinstance(value
, str):
1023 value
= int(value
, 0)
1026 def disassemble(self
, insn
,
1027 style
=Style
.NORMAL
, indent
=""):
1029 value
= insn
[span
].to_signed_int()
1030 sign
= "-" if (value
< 0) else ""
1033 if style
>= Style
.VERBOSE
:
1034 span
= map(str, span
)
1035 yield f
"{indent}{self.name}"
1036 yield f
"{indent}{indent}{sign}{value}"
1037 yield f
"{indent}{indent}{', '.join(span)}"
1039 yield f
"{sign}{value}"
1042 class StaticOperand(Operand
):
1043 def __init__(self
, record
, name
, value
):
1044 self
.__value
= value
1045 return super().__init
__(record
=record
, name
=name
)
1048 yield ("value", self
.__value
)
1049 yield from super().__iter
__()
1052 return f
"{self.__class__.__name__}({self.name}, value={self.value})"
1058 def assemble(self
, insn
):
1059 insn
[self
.span
] = self
.value
1061 def disassemble(self
, insn
,
1062 style
=Style
.NORMAL
, indent
=""):
1066 if style
>= Style
.VERBOSE
:
1067 span
= map(str, span
)
1068 yield f
"{indent}{self.name}"
1069 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1070 yield f
"{indent}{indent}{', '.join(span)}"
1072 yield str(int(value
))
1075 class SpanStaticOperand(StaticOperand
):
1076 def __init__(self
, record
, name
, value
, span
):
1077 self
.__span
= tuple(span
)
1078 return super().__init
__(record
=record
, name
=name
, value
=value
)
1081 yield ("span", self
.__span
)
1082 yield from super().__iter
__()
1089 class POStaticOperand(SpanStaticOperand
):
1090 def __init__(self
, record
, value
):
1091 return super().__init
__(record
=record
, name
="PO", value
=value
, span
=range(0, 6))
1094 for (key
, value
) in super().__iter
__():
1095 if key
not in {"name", "span"}:
1099 class XOStaticOperand(SpanStaticOperand
):
1100 def __init__(self
, record
, value
, span
):
1101 bits
= record
.section
.bitsel
1102 value
= _SelectableInt(value
=value
, bits
=len(bits
))
1103 span
= dict(zip(bits
, range(len(bits
))))
1104 span_rev
= {value
:key
for (key
, value
) in span
.items()}
1106 # This part is tricky: we cannot use record.operands,
1107 # as this code is called by record.static_operands method.
1108 for (cls
, kwargs
) in record
.mdwn
.operands
:
1109 operand
= cls(record
=record
, **kwargs
)
1110 for idx
in operand
.span
:
1111 rev
= span
.pop(idx
, None)
1113 span_rev
.pop(rev
, None)
1115 value
= int(_selectconcat(*(value
[bit
] for bit
in span
.values())))
1116 span
= tuple(span
.keys())
1118 return super().__init
__(record
=record
, name
="XO", value
=value
, span
=span
)
1121 for (key
, value
) in super().__iter
__():
1122 if key
not in {"name"}:
1126 class ImmediateOperand(DynamicOperand
):
1130 class SignedImmediateOperand(SignedOperand
, ImmediateOperand
):
1134 class NonZeroOperand(DynamicOperand
):
1135 def assemble(self
, insn
, value
):
1136 if isinstance(value
, str):
1137 value
= int(value
, 0)
1138 if not isinstance(value
, int):
1139 raise ValueError("non-integer operand")
1141 return super().assemble(value
=value
, insn
=insn
)
1143 def disassemble(self
, insn
,
1144 style
=Style
.NORMAL
, indent
=""):
1148 if style
>= Style
.VERBOSE
:
1149 span
= map(str, span
)
1150 yield f
"{indent}{self.name}"
1151 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1152 yield f
"{indent}{indent}{', '.join(span)}"
1154 yield str(int(value
) + 1)
1157 class ExtendableOperand(DynamicOperand
):
1158 def sv_spec_enter(self
, value
, span
):
1159 return (value
, span
)
1161 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1162 return (value
, span
)
1164 def spec(self
, insn
):
1168 span
= tuple(map(str, span
))
1170 if isinstance(insn
, SVP64Instruction
):
1171 (origin_value
, origin_span
) = (value
, span
)
1172 (value
, span
) = self
.sv_spec_enter(value
=value
, span
=span
)
1174 extra_idx
= self
.extra_idx
1175 if extra_idx
is _SVExtra
.NONE
:
1176 return (vector
, value
, span
)
1178 if self
.record
.etype
is _SVEType
.EXTRA3
:
1179 spec
= insn
.prefix
.rm
.extra3
[extra_idx
]
1180 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1181 spec
= insn
.prefix
.rm
.extra2
[extra_idx
]
1183 raise ValueError(self
.record
.etype
)
1186 vector
= bool(spec
[0])
1187 spec_span
= spec
.__class
__
1188 if self
.record
.etype
is _SVEType
.EXTRA3
:
1189 spec_span
= tuple(map(str, spec_span
[1, 2]))
1191 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1192 spec_span
= tuple(map(str, spec_span
[1,]))
1193 spec
= _SelectableInt(value
=spec
[1].value
, bits
=2)
1196 spec_span
= (spec_span
+ ("{0}",))
1198 spec_span
= (("{0}",) + spec_span
)
1200 raise ValueError(self
.record
.etype
)
1202 vector_shift
= (2 + (5 - value
.bits
))
1203 scalar_shift
= value
.bits
1204 spec_shift
= (5 - value
.bits
)
1206 bits
= (len(span
) + len(spec_span
))
1207 value
= _SelectableInt(value
=value
.value
, bits
=bits
)
1208 spec
= _SelectableInt(value
=spec
.value
, bits
=bits
)
1210 value
= ((value
<< vector_shift
) |
(spec
<< spec_shift
))
1211 span
= (span
+ spec_span
+ ((spec_shift
* ("{0}",))))
1213 value
= ((spec
<< scalar_shift
) | value
)
1214 span
= ((spec_shift
* ("{0}",)) + spec_span
+ span
)
1216 (value
, span
) = self
.sv_spec_leave(value
=value
, span
=span
,
1217 origin_value
=origin_value
, origin_span
=origin_span
)
1219 return (vector
, value
, span
)
1222 def extra_reg(self
):
1223 return _SVExtraReg(self
.name
)
1226 def extra_idx(self
):
1228 _SVExtraReg
.RSp
: _SVExtraReg
.RS
,
1229 _SVExtraReg
.RTp
: _SVExtraReg
.RT
,
1230 _SVExtraReg
.FRAp
: _SVExtraReg
.FRA
,
1231 _SVExtraReg
.FRBp
: _SVExtraReg
.FRB
,
1232 _SVExtraReg
.FRSp
: _SVExtraReg
.FRS
,
1233 _SVExtraReg
.FRTp
: _SVExtraReg
.FRT
,
1236 for key
in frozenset({
1237 "in1", "in2", "in3", "cr_in", "cr_in2",
1238 "out", "out2", "cr_out",
1240 extra_reg
= self
.record
.svp64
.extra_reg(key
=key
)
1241 if pairs
.get(extra_reg
, extra_reg
) is pairs
.get(self
.extra_reg
, self
.extra_reg
):
1242 return self
.record
.extra_idx(key
=key
)
1244 return _SVExtra
.NONE
1246 def remap(self
, value
, vector
):
1247 raise NotImplementedError()
1249 def assemble(self
, value
, insn
, prefix
):
1252 if isinstance(value
, str):
1253 value
= value
.lower()
1254 if value
.startswith("%"):
1256 if value
.startswith("*"):
1257 if not isinstance(insn
, SVP64Instruction
):
1258 raise ValueError(value
)
1261 if value
.startswith(prefix
):
1262 value
= value
[len(prefix
):]
1263 value
= int(value
, 0)
1265 if isinstance(insn
, SVP64Instruction
):
1266 (value
, extra
) = self
.remap(value
=value
, vector
=vector
)
1268 extra_idx
= self
.extra_idx
1269 if extra_idx
is _SVExtra
.NONE
:
1270 raise ValueError(self
.record
)
1272 if self
.record
.etype
is _SVEType
.EXTRA3
:
1273 insn
.prefix
.rm
.extra3
[extra_idx
] = extra
1274 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1275 insn
.prefix
.rm
.extra2
[extra_idx
] = extra
1277 raise ValueError(self
.record
.etype
)
1279 return super().assemble(value
=value
, insn
=insn
)
1281 def disassemble(self
, insn
,
1282 style
=Style
.NORMAL
, prefix
="", indent
=""):
1283 (vector
, value
, span
) = self
.spec(insn
=insn
)
1285 if style
>= Style
.VERBOSE
:
1286 mode
= "vector" if vector
else "scalar"
1287 yield f
"{indent}{self.name} ({mode})"
1288 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1289 yield f
"{indent}{indent}{', '.join(span)}"
1290 if isinstance(insn
, SVP64Instruction
):
1291 extra_idx
= self
.extra_idx
1292 if self
.record
.etype
is _SVEType
.NONE
:
1293 yield f
"{indent}{indent}extra[none]"
1295 etype
= repr(self
.record
.etype
).lower()
1296 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1298 vector
= "*" if vector
else ""
1299 yield f
"{vector}{prefix}{int(value)}"
1302 class SimpleRegisterOperand(ExtendableOperand
):
1303 def remap(self
, value
, vector
):
1305 extra
= (value
& 0b11)
1306 value
= (value
>> 2)
1308 extra
= (value
>> 5)
1309 value
= (value
& 0b11111)
1311 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
1312 # (and shrink to a single bit if ok)
1313 if self
.record
.etype
is _SVEType
.EXTRA2
:
1315 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
1316 assert (extra
& 0b01) == 0, \
1317 ("vector field %s cannot fit into EXTRA2" % value
)
1318 extra
= (0b10 |
(extra
>> 1))
1320 # range is r0-r63 in increments of 1
1321 assert (extra
>> 1) == 0, \
1322 ("scalar GPR %d cannot fit into EXTRA2" % value
)
1324 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1326 # EXTRA3 vector bit needs marking
1329 raise ValueError(self
.record
.etype
)
1331 return (value
, extra
)
1334 class GPROperand(SimpleRegisterOperand
):
1335 def assemble(self
, insn
, value
):
1336 return super().assemble(value
=value
, insn
=insn
, prefix
="r")
1338 def disassemble(self
, insn
,
1339 style
=Style
.NORMAL
, indent
=""):
1340 prefix
= "" if (style
<= Style
.SHORT
) else "r"
1341 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1342 style
=style
, indent
=indent
)
1345 class GPRPairOperand(GPROperand
):
1349 class FPROperand(SimpleRegisterOperand
):
1350 def assemble(self
, insn
, value
):
1351 return super().assemble(value
=value
, insn
=insn
, prefix
="f")
1353 def disassemble(self
, insn
,
1354 style
=Style
.NORMAL
, indent
=""):
1355 prefix
= "" if (style
<= Style
.SHORT
) else "f"
1356 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1357 style
=style
, indent
=indent
)
1360 class FPRPairOperand(FPROperand
):
1364 class ConditionRegisterFieldOperand(ExtendableOperand
):
1365 def pattern(name_pattern
):
1366 (name
, pattern
) = name_pattern
1367 return (name
, _re
.compile(f
"^{pattern}$", _re
.S
))
1376 CR
= r
"(?:CR|cr)([0-9]+)"
1378 BIT
= rf
"({'|'.join(CONDS.keys())})"
1379 LBIT
= fr
"{BIT}\s*\+\s*" # BIT+
1380 RBIT
= fr
"\s*\+\s*{BIT}" # +BIT
1381 CRN
= fr
"{CR}\s*\*\s*{N}" # CR*N
1382 NCR
= fr
"{N}\s*\*\s*{CR}" # N*CR
1383 XCR
= fr
"{CR}\.{BIT}"
1384 PATTERNS
= tuple(map(pattern
, (
1389 ("BIT+CR", (LBIT
+ CR
)),
1390 ("CR+BIT", (CR
+ RBIT
)),
1391 ("BIT+CR*N", (LBIT
+ CRN
)),
1392 ("CR*N+BIT", (CRN
+ RBIT
)),
1393 ("BIT+N*CR", (LBIT
+ NCR
)),
1394 ("N*CR+BIT", (NCR
+ RBIT
)),
1397 def remap(self
, value
, vector
, regtype
):
1398 if regtype
is _RegType
.CR_5BIT
:
1399 subvalue
= (value
& 0b11)
1403 extra
= (value
& 0b1111)
1406 extra
= (value
>> 3)
1409 if self
.record
.etype
is _SVEType
.EXTRA2
:
1411 assert (extra
& 0b111) == 0, \
1412 "vector CR cannot fit into EXTRA2"
1413 extra
= (0b10 |
(extra
>> 3))
1415 assert (extra
>> 1) == 0, \
1416 "scalar CR cannot fit into EXTRA2"
1418 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1420 assert (extra
& 0b11) == 0, \
1421 "vector CR cannot fit into EXTRA3"
1422 extra
= (0b100 |
(extra
>> 2))
1424 assert (extra
>> 2) == 0, \
1425 "scalar CR cannot fit into EXTRA3"
1428 if regtype
is _RegType
.CR_5BIT
:
1429 value
= ((value
<< 2) | subvalue
)
1431 return (value
, extra
)
1433 def assemble(self
, insn
, value
):
1434 if isinstance(value
, str):
1437 if value
.startswith("*"):
1438 if not isinstance(insn
, SVP64Instruction
):
1439 raise ValueError(value
)
1443 for (name
, pattern
) in reversed(self
.__class
__.PATTERNS
):
1444 match
= pattern
.match(value
)
1445 if match
is not None:
1446 keys
= name
.replace("+", "_").replace("*", "_").split("_")
1447 values
= match
.groups()
1448 match
= dict(zip(keys
, values
))
1449 CR
= int(match
["CR"])
1453 N
= int(match
.get("N", "1"))
1454 BIT
= self
.__class
__.CONDS
[match
.get("BIT", "lt")]
1455 value
= ((CR
* N
) + BIT
)
1462 return super().assemble(value
=value
, insn
=insn
, prefix
="cr")
1464 def disassemble(self
, insn
,
1465 style
=Style
.NORMAL
, prefix
="", indent
=""):
1466 (vector
, value
, span
) = self
.spec(insn
=insn
)
1468 if style
>= Style
.VERBOSE
:
1469 mode
= "vector" if vector
else "scalar"
1470 yield f
"{indent}{self.name} ({mode})"
1471 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1472 yield f
"{indent}{indent}{', '.join(span)}"
1473 if isinstance(insn
, SVP64Instruction
):
1474 extra_idx
= self
.extra_idx
1475 if self
.record
.etype
is _SVEType
.NONE
:
1476 yield f
"{indent}{indent}extra[none]"
1478 etype
= repr(self
.record
.etype
).lower()
1479 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1481 vector
= "*" if vector
else ""
1482 CR
= int(value
>> 2)
1484 cond
= ("lt", "gt", "eq", "so")[CC
]
1485 if style
>= Style
.NORMAL
:
1487 if isinstance(insn
, SVP64Instruction
):
1488 yield f
"{vector}cr{CR}.{cond}"
1490 yield f
"4*cr{CR}+{cond}"
1494 yield f
"{vector}{prefix}{int(value)}"
1497 class CR3Operand(ConditionRegisterFieldOperand
):
1498 def remap(self
, value
, vector
):
1499 return super().remap(value
=value
, vector
=vector
,
1500 regtype
=_RegType
.CR_3BIT
)
1503 class CR5Operand(ConditionRegisterFieldOperand
):
1504 def remap(self
, value
, vector
):
1505 return super().remap(value
=value
, vector
=vector
,
1506 regtype
=_RegType
.CR_5BIT
)
1508 def sv_spec_enter(self
, value
, span
):
1509 value
= _SelectableInt(value
=(value
.value
>> 2), bits
=3)
1510 return (value
, span
)
1512 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1513 value
= _selectconcat(value
, origin_value
[3:5])
1515 return (value
, span
)
1518 class EXTSOperand(SignedOperand
):
1519 field
: str # real name to report
1520 nz
: int = 0 # number of zeros
1521 fmt
: str = "d" # integer formatter
1523 def __init__(self
, record
, name
, field
, nz
=0, fmt
="d"):
1524 self
.__field
= field
1527 return super().__init
__(record
=record
, name
=name
)
1543 return self
.record
.fields
[self
.field
]
1545 def assemble(self
, insn
, value
):
1547 if isinstance(value
, str):
1548 value
= int(value
, 0)
1549 insn
[span
] = (value
>> self
.nz
)
1551 def disassemble(self
, insn
,
1552 style
=Style
.NORMAL
, indent
=""):
1554 value
= insn
[span
].to_signed_int()
1555 sign
= "-" if (value
< 0) else ""
1556 value
= (abs(value
) << self
.nz
)
1558 if style
>= Style
.VERBOSE
:
1559 span
= (tuple(map(str, span
)) + (("{0}",) * self
.nz
))
1560 zeros
= ("0" * self
.nz
)
1561 hint
= f
"{self.name} = EXTS({self.field} || {zeros})"
1562 yield f
"{indent * 1}{hint}"
1563 yield f
"{indent * 2}{self.field}"
1564 yield f
"{indent * 3}{sign}{value:{self.fmt}}"
1565 yield f
"{indent * 3}{', '.join(span)}"
1567 yield f
"{sign}{value:{self.fmt}}"
1570 class TargetAddrOperand(EXTSOperand
):
1571 def __init__(self
, record
, name
, field
):
1572 return super().__init
__(record
=record
, name
=name
, field
=field
, nz
=2, fmt
="#x")
1575 class TargetAddrOperandLI(TargetAddrOperand
):
1576 def __init__(self
, record
, name
):
1577 return super().__init
__(record
=record
, name
=name
, field
="LI")
1580 class TargetAddrOperandBD(TargetAddrOperand
):
1581 def __init__(self
, record
, name
):
1582 return super().__init
__(record
=record
, name
=name
, field
="BD")
1585 class EXTSOperandDS(EXTSOperand
, ImmediateOperand
):
1586 def __init__(self
, record
, name
):
1587 return super().__init
__(record
=record
, name
=name
, field
="DS", nz
=2)
1590 class EXTSOperandDQ(EXTSOperand
, ImmediateOperand
):
1591 def __init__(self
, record
, name
):
1592 return super().__init
__(record
=record
, name
=name
, field
="DQ", nz
=4)
1595 class DOperandDX(SignedOperand
):
1598 cls
= lambda name
: DynamicOperand(record
=self
.record
, name
=name
)
1599 operands
= map(cls
, ("d0", "d1", "d2"))
1600 spans
= map(lambda operand
: operand
.span
, operands
)
1601 return sum(spans
, tuple())
1603 def disassemble(self
, insn
,
1604 style
=Style
.NORMAL
, indent
=""):
1606 value
= insn
[span
].to_signed_int()
1607 sign
= "-" if (value
< 0) else ""
1610 if style
>= Style
.VERBOSE
:
1617 for (subname
, subspan
) in mapping
.items():
1618 operand
= DynamicOperand(name
=subname
)
1620 span
= map(str, span
)
1621 yield f
"{indent}{indent}{operand.name} = D{subspan}"
1622 yield f
"{indent}{indent}{indent}{sign}{value}"
1623 yield f
"{indent}{indent}{indent}{', '.join(span)}"
1625 yield f
"{sign}{value}"
1628 class Instruction(_Mapping
):
1630 def integer(cls
, value
=0, bits
=None, byteorder
="little"):
1631 if isinstance(value
, (int, bytes
)) and not isinstance(bits
, int):
1632 raise ValueError(bits
)
1634 if isinstance(value
, bytes
):
1635 if ((len(value
) * 8) != bits
):
1636 raise ValueError(f
"bit length mismatch")
1637 value
= int.from_bytes(value
, byteorder
=byteorder
)
1639 if isinstance(value
, int):
1640 value
= _SelectableInt(value
=value
, bits
=bits
)
1641 elif isinstance(value
, Instruction
):
1642 value
= value
.storage
1644 if not isinstance(value
, _SelectableInt
):
1645 raise ValueError(value
)
1648 if len(value
) != bits
:
1649 raise ValueError(value
)
1651 value
= _SelectableInt(value
=value
, bits
=bits
)
1653 return cls(storage
=value
)
1656 return hash(int(self
))
1658 def __getitem__(self
, key
):
1659 return self
.storage
.__getitem
__(key
)
1661 def __setitem__(self
, key
, value
):
1662 return self
.storage
.__setitem
__(key
, value
)
1664 def bytes(self
, byteorder
="little"):
1665 nr_bytes
= (len(self
.__class
__) // 8)
1666 return int(self
).to_bytes(nr_bytes
, byteorder
=byteorder
)
1669 def record(cls
, db
, entry
):
1672 raise KeyError(entry
)
1676 def operands(cls
, record
):
1677 yield from record
.operands
1680 def static_operands(cls
, record
):
1681 return filter(lambda operand
: isinstance(operand
, StaticOperand
),
1682 cls
.operands(record
=record
))
1685 def dynamic_operands(cls
, record
):
1686 return filter(lambda operand
: isinstance(operand
, DynamicOperand
),
1687 cls
.operands(record
=record
))
1689 def spec(self
, record
, prefix
):
1690 dynamic_operands
= tuple(map(_operator
.itemgetter(0),
1691 self
.spec_dynamic_operands(record
=record
)))
1693 static_operands
= []
1694 for (name
, value
) in self
.spec_static_operands(record
=record
):
1695 static_operands
.append(f
"{name}={value}")
1698 if dynamic_operands
:
1700 operands
+= ",".join(dynamic_operands
)
1703 operands
+= " ".join(static_operands
)
1705 return f
"{prefix}{record.name}{operands}"
1707 def spec_static_operands(self
, record
):
1708 for operand
in self
.static_operands(record
=record
):
1709 if not isinstance(operand
, (POStaticOperand
, XOStaticOperand
)):
1710 yield (operand
.name
, operand
.value
)
1712 def spec_dynamic_operands(self
, record
, style
=Style
.NORMAL
):
1716 for operand
in self
.dynamic_operands(record
=record
):
1718 value
= " ".join(operand
.disassemble(insn
=self
,
1719 style
=min(style
, Style
.NORMAL
)))
1721 name
= f
"{imm_name}({name})"
1722 value
= f
"{imm_value}({value})"
1724 if isinstance(operand
, ImmediateOperand
):
1732 def assemble(cls
, record
, arguments
=None):
1733 if arguments
is None:
1736 insn
= cls
.integer(value
=0)
1738 for operand
in cls
.static_operands(record
=record
):
1739 operand
.assemble(insn
=insn
)
1741 dynamic_operands
= tuple(cls
.dynamic_operands(record
=record
))
1742 for (value
, operand
) in Arguments(arguments
, dynamic_operands
):
1743 operand
.assemble(insn
=insn
, value
=value
)
1747 def disassemble(self
, record
,
1749 style
=Style
.NORMAL
):
1750 raise NotImplementedError()
1753 class WordInstruction(Instruction
):
1754 _
: _Field
= range(0, 32)
1755 PO
: _Field
= range(0, 6)
1758 def integer(cls
, value
, byteorder
="little"):
1759 return super().integer(bits
=32, value
=value
, byteorder
=byteorder
)
1764 for idx
in range(32):
1765 bit
= int(self
[idx
])
1767 return "".join(map(str, bits
))
1769 def disassemble(self
, record
,
1771 style
=Style
.NORMAL
):
1772 if style
<= Style
.SHORT
:
1775 blob
= self
.bytes(byteorder
=byteorder
)
1776 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
1780 yield f
"{blob}.long 0x{int(self):08x}"
1784 if style
is Style
.LEGACY
:
1786 for operand
in self
.dynamic_operands(record
=record
):
1787 if isinstance(operand
, (GPRPairOperand
, FPRPairOperand
)):
1790 if style
is Style
.LEGACY
and (paired
or record
.ppc
.unofficial
):
1791 yield f
"{blob}.long 0x{int(self):08x}"
1793 operands
= tuple(map(_operator
.itemgetter(1),
1794 self
.spec_dynamic_operands(record
=record
, style
=style
)))
1796 operands
= ",".join(operands
)
1797 yield f
"{blob}{record.name} {operands}"
1799 yield f
"{blob}{record.name}"
1801 if style
>= Style
.VERBOSE
:
1803 binary
= self
.binary
1804 spec
= self
.spec(record
=record
, prefix
="")
1805 yield f
"{indent}spec"
1806 yield f
"{indent}{indent}{spec}"
1807 yield f
"{indent}pcode"
1808 for stmt
in record
.mdwn
.pcode
:
1809 yield f
"{indent}{indent}{stmt}"
1810 yield f
"{indent}binary"
1811 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
1812 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
1813 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
1814 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
1815 yield f
"{indent}opcodes"
1816 for opcode
in record
.opcodes
:
1817 yield f
"{indent}{indent}{opcode!r}"
1818 for operand
in self
.operands(record
=record
):
1819 yield from operand
.disassemble(insn
=self
,
1820 style
=style
, indent
=indent
)
1824 class PrefixedInstruction(Instruction
):
1825 class Prefix(WordInstruction
.remap(range(0, 32))):
1828 class Suffix(WordInstruction
.remap(range(32, 64))):
1831 _
: _Field
= range(64)
1837 def integer(cls
, value
, byteorder
="little"):
1838 return super().integer(bits
=64, value
=value
, byteorder
=byteorder
)
1841 def pair(cls
, prefix
=0, suffix
=0, byteorder
="little"):
1842 def transform(value
):
1843 return WordInstruction
.integer(value
=value
,
1844 byteorder
=byteorder
)[0:32]
1846 (prefix
, suffix
) = map(transform
, (prefix
, suffix
))
1847 value
= _selectconcat(prefix
, suffix
)
1849 return super().integer(bits
=64, value
=value
)
1852 class Mode(_Mapping
):
1853 _
: _Field
= range(0, 5)
1854 sel
: _Field
= (0, 1)
1857 class Extra(_Mapping
):
1858 _
: _Field
= range(0, 9)
1861 class Extra2(Extra
):
1862 idx0
: _Field
= range(0, 2)
1863 idx1
: _Field
= range(2, 4)
1864 idx2
: _Field
= range(4, 6)
1865 idx3
: _Field
= range(6, 8)
1867 def __getitem__(self
, key
):
1873 _SVExtra
.Idx0
: self
.idx0
,
1874 _SVExtra
.Idx1
: self
.idx1
,
1875 _SVExtra
.Idx2
: self
.idx2
,
1876 _SVExtra
.Idx3
: self
.idx3
,
1879 def __setitem__(self
, key
, value
):
1880 self
[key
].assign(value
)
1883 class Extra3(Extra
):
1884 idx0
: _Field
= range(0, 3)
1885 idx1
: _Field
= range(3, 6)
1886 idx2
: _Field
= range(6, 9)
1888 def __getitem__(self
, key
):
1893 _SVExtra
.Idx0
: self
.idx0
,
1894 _SVExtra
.Idx1
: self
.idx1
,
1895 _SVExtra
.Idx2
: self
.idx2
,
1898 def __setitem__(self
, key
, value
):
1899 self
[key
].assign(value
)
1902 class BaseRM(_Mapping
):
1903 _
: _Field
= range(24)
1904 mmode
: _Field
= (0,)
1905 mask
: _Field
= range(1, 4)
1906 elwidth
: _Field
= range(4, 6)
1907 ewsrc
: _Field
= range(6, 8)
1908 subvl
: _Field
= range(8, 10)
1909 mode
: Mode
.remap(range(19, 24))
1910 smask
: _Field
= range(16, 19)
1911 extra
: Extra
.remap(range(10, 19))
1912 extra2
: Extra2
.remap(range(10, 19))
1913 extra3
: Extra3
.remap(range(10, 19))
1915 def specifiers(self
, record
):
1916 subvl
= int(self
.subvl
)
1924 def disassemble(self
, style
=Style
.NORMAL
):
1925 if style
>= Style
.VERBOSE
:
1927 for (name
, span
) in self
.traverse(path
="RM"):
1928 value
= self
.storage
[span
]
1930 yield f
"{indent}{int(value):0{value.bits}b}"
1931 yield f
"{indent}{', '.join(map(str, span))}"
1934 class FFPRRc1BaseRM(BaseRM
):
1935 def specifiers(self
, record
, mode
):
1936 inv
= _SelectableInt(value
=int(self
.inv
), bits
=1)
1937 CR
= _SelectableInt(value
=int(self
.CR
), bits
=2)
1938 mask
= int(_selectconcat(CR
, inv
))
1939 predicate
= PredicateBaseRM
.predicate(True, mask
)
1940 yield f
"{mode}={predicate}"
1942 yield from super().specifiers(record
=record
)
1945 class FFPRRc0BaseRM(BaseRM
):
1946 def specifiers(self
, record
, mode
):
1948 inv
= "~" if self
.inv
else ""
1949 yield f
"{mode}={inv}RC1"
1951 yield from super().specifiers(record
=record
)
1954 class SatBaseRM(BaseRM
):
1955 def specifiers(self
, record
):
1961 yield from super().specifiers(record
=record
)
1964 class ZZBaseRM(BaseRM
):
1965 def specifiers(self
, record
):
1969 yield from super().specifiers(record
=record
)
1972 class ZZCombinedBaseRM(BaseRM
):
1973 def specifiers(self
, record
):
1974 if self
.sz
and self
.dz
:
1981 yield from super().specifiers(record
=record
)
1984 class DZBaseRM(BaseRM
):
1985 def specifiers(self
, record
):
1989 yield from super().specifiers(record
=record
)
1992 class SZBaseRM(BaseRM
):
1993 def specifiers(self
, record
):
1997 yield from super().specifiers(record
=record
)
2000 class MRBaseRM(BaseRM
):
2001 def specifiers(self
, record
):
2007 yield from super().specifiers(record
=record
)
2010 class ElsBaseRM(BaseRM
):
2011 def specifiers(self
, record
):
2015 yield from super().specifiers(record
=record
)
2018 class WidthBaseRM(BaseRM
):
2020 def width(FP
, width
):
2029 width
= ("fp" + width
)
2032 def specifiers(self
, record
):
2033 # elwidths: use "w=" if same otherwise dw/sw
2034 # FIXME this should consider FP instructions
2036 dw
= WidthBaseRM
.width(FP
, int(self
.elwidth
))
2037 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
2046 yield from super().specifiers(record
=record
)
2049 class PredicateBaseRM(BaseRM
):
2051 def predicate(CR
, mask
):
2054 (False, 0b001): "1<<r3",
2055 (False, 0b010): "r3",
2056 (False, 0b011): "~r3",
2057 (False, 0b100): "r10",
2058 (False, 0b101): "~r10",
2059 (False, 0b110): "r30",
2060 (False, 0b111): "~r30",
2062 (True, 0b000): "lt",
2063 (True, 0b001): "ge",
2064 (True, 0b010): "gt",
2065 (True, 0b011): "le",
2066 (True, 0b100): "eq",
2067 (True, 0b101): "ne",
2068 (True, 0b110): "so",
2069 (True, 0b111): "ns",
2072 def specifiers(self
, record
):
2073 # predication - single and twin
2074 # use "m=" if same otherwise sm/dm
2075 CR
= (int(self
.mmode
) == 1)
2076 mask
= int(self
.mask
)
2077 sm
= dm
= PredicateBaseRM
.predicate(CR
, mask
)
2078 if record
.svp64
.ptype
is _SVPType
.P2
:
2079 smask
= int(self
.smask
)
2080 sm
= PredicateBaseRM
.predicate(CR
, smask
)
2089 yield from super().specifiers(record
=record
)
2092 class PredicateWidthBaseRM(WidthBaseRM
, PredicateBaseRM
):
2096 class SEABaseRM(BaseRM
):
2097 def specifiers(self
, record
):
2101 yield from super().specifiers(record
=record
)
2104 class VLiBaseRM(BaseRM
):
2105 def specifiers(self
, record
):
2109 yield from super().specifiers(record
=record
)
2112 class NormalBaseRM(PredicateWidthBaseRM
):
2115 https://libre-soc.org/openpower/sv/normal/
2120 class NormalSimpleRM(ZZCombinedBaseRM
, NormalBaseRM
):
2121 """normal: simple mode"""
2125 def specifiers(self
, record
):
2126 yield from super().specifiers(record
=record
)
2129 class NormalMRRM(MRBaseRM
, NormalBaseRM
):
2130 """normal: scalar reduce mode (mapreduce), SUBVL=1"""
2134 class NormalFFRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2135 """normal: Rc=1: ffirst CR sel"""
2137 CR
: BaseRM
.mode
[3, 4]
2139 def specifiers(self
, record
):
2140 yield from super().specifiers(record
=record
, mode
="ff")
2143 class NormalFFRc0RM(FFPRRc0BaseRM
, VLiBaseRM
, NormalBaseRM
):
2144 """normal: Rc=0: ffirst z/nonz"""
2149 def specifiers(self
, record
):
2150 yield from super().specifiers(record
=record
, mode
="ff")
2153 class NormalSatRM(SatBaseRM
, ZZCombinedBaseRM
, NormalBaseRM
):
2154 """normal: sat mode: N=0/1 u/s, SUBVL=1"""
2160 class NormalPRRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2161 """normal: Rc=1: pred-result CR sel"""
2163 CR
: BaseRM
.mode
[3, 4]
2165 def specifiers(self
, record
):
2166 yield from super().specifiers(record
=record
, mode
="pr")
2169 class NormalPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, NormalBaseRM
):
2170 """normal: Rc=0: pred-result z/nonz"""
2177 def specifiers(self
, record
):
2178 yield from super().specifiers(record
=record
, mode
="pr")
2181 class NormalRM(NormalBaseRM
):
2182 simple
: NormalSimpleRM
2184 ffrc1
: NormalFFRc1RM
2185 ffrc0
: NormalFFRc0RM
2187 prrc1
: NormalPRRc1RM
2188 prrc0
: NormalPRRc0RM
2191 class LDSTImmBaseRM(PredicateWidthBaseRM
):
2193 LD/ST Immediate mode
2194 https://libre-soc.org/openpower/sv/ldst/
2199 class LDSTImmSimpleRM(ElsBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2200 """ld/st immediate: simple mode"""
2207 class LDSTImmPostRM(LDSTImmBaseRM
):
2208 """ld/st immediate: postinc mode (and load-fault)"""
2209 pi
: BaseRM
.mode
[3] # Post-Increment Mode
2210 lf
: BaseRM
.mode
[4] # Fault-First Mode (not *Data-Dependent* Fail-First)
2212 def specifiers(self
, record
):
2219 class LDSTImmFFRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2220 """ld/st immediate: Rc=1: ffirst CR sel"""
2222 CR
: BaseRM
.mode
[3, 4]
2224 def specifiers(self
, record
):
2225 yield from super().specifiers(record
=record
, mode
="ff")
2228 class LDSTImmFFRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2229 """ld/st immediate: Rc=0: ffirst z/nonz"""
2234 def specifiers(self
, record
):
2235 yield from super().specifiers(record
=record
, mode
="ff")
2238 class LDSTImmSatRM(ElsBaseRM
, SatBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2239 """ld/st immediate: sat mode: N=0/1 u/s"""
2247 class LDSTImmPRRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2248 """ld/st immediate: Rc=1: pred-result CR sel"""
2250 CR
: BaseRM
.mode
[3, 4]
2252 def specifiers(self
, record
):
2253 yield from super().specifiers(record
=record
, mode
="pr")
2256 class LDSTImmPRRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2257 """ld/st immediate: Rc=0: pred-result z/nonz"""
2262 def specifiers(self
, record
):
2263 yield from super().specifiers(record
=record
, mode
="pr")
2266 class LDSTImmRM(LDSTImmBaseRM
):
2267 simple
: LDSTImmSimpleRM
2269 ffrc1
: LDSTImmFFRc1RM
2270 ffrc0
: LDSTImmFFRc0RM
2272 prrc1
: LDSTImmPRRc1RM
2273 prrc0
: LDSTImmPRRc0RM
2276 class LDSTIdxBaseRM(PredicateWidthBaseRM
):
2279 https://libre-soc.org/openpower/sv/ldst/
2284 class LDSTIdxSimpleRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2285 """ld/st index: simple mode"""
2291 class LDSTIdxStrideRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2292 """ld/st index: strided (scalar only source)"""
2297 def specifiers(self
, record
):
2300 yield from super().specifiers(record
=record
)
2303 class LDSTIdxSatRM(SatBaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2304 """ld/st index: sat mode: N=0/1 u/s"""
2310 class LDSTIdxPRRc1RM(LDSTIdxBaseRM
):
2311 """ld/st index: Rc=1: pred-result CR sel"""
2313 CR
: BaseRM
.mode
[3, 4]
2315 def specifiers(self
, record
):
2316 yield from super().specifiers(record
=record
, mode
="pr")
2319 class LDSTIdxPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, LDSTIdxBaseRM
):
2320 """ld/st index: Rc=0: pred-result z/nonz"""
2327 def specifiers(self
, record
):
2328 yield from super().specifiers(record
=record
, mode
="pr")
2331 class LDSTIdxRM(LDSTIdxBaseRM
):
2332 simple
: LDSTIdxSimpleRM
2333 stride
: LDSTIdxStrideRM
2335 prrc1
: LDSTIdxPRRc1RM
2336 prrc0
: LDSTIdxPRRc0RM
2340 class CROpBaseRM(BaseRM
):
2343 https://libre-soc.org/openpower/sv/cr_ops/
2348 class CROpSimpleRM(PredicateBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2349 """crop: simple mode"""
2354 def specifiers(self
, record
):
2356 yield "rg" # simple CR Mode reports /rg
2358 yield from super().specifiers(record
=record
)
2361 class CROpMRRM(MRBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2362 """crop: scalar reduce mode (mapreduce), SUBVL=1"""
2368 class CROpFF3RM(FFPRRc0BaseRM
, PredicateBaseRM
, VLiBaseRM
, DZBaseRM
, SZBaseRM
, CROpBaseRM
):
2369 """crop: ffirst 3-bit mode"""
2376 def specifiers(self
, record
):
2377 yield from super().specifiers(record
=record
, mode
="ff")
2380 # FIXME: almost everything in this class contradicts the specs.
2381 # However, this is the direct translation of the pysvp64asm code.
2382 # Please revisit this code; there is an inactive sketch below.
2383 class CROpFF5RM(FFPRRc1BaseRM
, PredicateBaseRM
, VLiBaseRM
, CROpBaseRM
):
2384 """cr_op: ffirst 5-bit mode"""
2391 def specifiers(self
, record
):
2392 yield from super().specifiers(record
=record
, mode
="ff")
2395 class CROpRM(CROpBaseRM
):
2396 simple
: CROpSimpleRM
2402 # ********************
2404 # https://libre-soc.org/openpower/sv/branches/
2405 class BranchBaseRM(BaseRM
):
2415 def specifiers(self
, record
):
2427 raise ValueError(self
.sz
)
2439 # Branch modes lack source mask.
2440 # Therefore a custom code is needed.
2441 CR
= (int(self
.mmode
) == 1)
2442 mask
= int(self
.mask
)
2443 m
= PredicateBaseRM
.predicate(CR
, mask
)
2447 yield from super().specifiers(record
=record
)
2450 class BranchSimpleRM(BranchBaseRM
):
2451 """branch: simple mode"""
2455 class BranchVLSRM(BranchBaseRM
):
2456 """branch: VLSET mode"""
2460 def specifiers(self
, record
):
2466 }[int(self
.VSb
), int(self
.VLi
)]
2468 yield from super().specifiers(record
=record
)
2471 class BranchCTRRM(BranchBaseRM
):
2472 """branch: CTR-test mode"""
2475 def specifiers(self
, record
):
2481 yield from super().specifiers(record
=record
)
2484 class BranchCTRVLSRM(BranchVLSRM
, BranchCTRRM
):
2485 """branch: CTR-test+VLSET mode"""
2489 class BranchRM(BranchBaseRM
):
2490 simple
: BranchSimpleRM
2493 ctrvls
: BranchCTRVLSRM
2504 @_dataclasses.dataclass(eq
=True, frozen
=True)
2509 def match(cls
, desc
, record
):
2510 raise NotImplementedError()
2512 def validate(self
, others
):
2515 def assemble(self
, insn
):
2516 raise NotImplementedError()
2519 @_dataclasses.dataclass(eq
=True, frozen
=True)
2520 class SpecifierWidth(Specifier
):
2524 def match(cls
, desc
, record
, etalon
):
2525 (mode
, _
, value
) = desc
.partition("=")
2527 value
= value
.strip()
2530 width
= _SVP64Width(value
)
2532 return cls(record
=record
, width
=width
)
2535 @_dataclasses.dataclass(eq
=True, frozen
=True)
2536 class SpecifierW(SpecifierWidth
):
2538 def match(cls
, desc
, record
):
2539 return super().match(desc
=desc
, record
=record
, etalon
="w")
2541 def assemble(self
, insn
):
2542 selector
= insn
.select(record
=self
.record
)
2543 selector
.ewsrc
= self
.width
.value
2544 selector
.elwidth
= self
.width
.value
2547 @_dataclasses.dataclass(eq
=True, frozen
=True)
2548 class SpecifierSW(SpecifierWidth
):
2550 def match(cls
, desc
, record
):
2551 return super().match(desc
=desc
, record
=record
, etalon
="sw")
2553 def assemble(self
, insn
):
2554 selector
= insn
.select(record
=self
.record
)
2555 selector
.ewsrc
= self
.width
.value
2558 @_dataclasses.dataclass(eq
=True, frozen
=True)
2559 class SpecifierDW(SpecifierWidth
):
2561 def match(cls
, desc
, record
):
2562 return super().match(desc
=desc
, record
=record
, etalon
="dw")
2564 def assemble(self
, insn
):
2565 selector
= insn
.select(record
=self
.record
)
2566 selector
.elwidth
= self
.width
.value
2569 @_dataclasses.dataclass(eq
=True, frozen
=True)
2570 class SpecifierSubVL(Specifier
):
2574 def match(cls
, desc
, record
):
2576 value
= _SVP64SubVL(desc
)
2580 return cls(record
=record
, value
=value
)
2582 def assemble(self
, insn
):
2583 selector
= insn
.select(record
=self
.record
)
2584 selector
.subvl
= int(self
.value
.value
)
2587 @_dataclasses.dataclass(eq
=True, frozen
=True)
2588 class SpecifierPredicate(Specifier
):
2593 def match(cls
, desc
, record
, mode_match
, pred_match
):
2594 (mode
, _
, pred
) = desc
.partition("=")
2597 if not mode_match(mode
):
2600 pred
= _SVP64Pred(pred
.strip())
2601 if not pred_match(pred
):
2602 raise ValueError(pred
)
2604 return cls(record
=record
, mode
=mode
, pred
=pred
)
2607 @_dataclasses.dataclass(eq
=True, frozen
=True)
2608 class SpecifierFFPR(SpecifierPredicate
):
2610 def match(cls
, desc
, record
, mode
):
2611 return super().match(desc
=desc
, record
=record
,
2612 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2613 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2618 def validate(self
, others
):
2619 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2620 if self
.mode
== "pr":
2621 raise ValueError("crop: 'pr' mode not supported")
2622 if (self
.record
.svp64
.extra_CR_3bit
and
2623 (self
.pred
.mode
is not _SVP64PredMode
.RC1
)):
2624 raise ValueError("3-bit CRs only support RC1/~RC1 BO")
2626 def assemble(self
, insn
):
2627 selector
= insn
.select(record
=self
.record
)
2628 if selector
.mode
.sel
!= 0:
2629 raise ValueError("cannot override mode")
2630 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2631 selector
.mode
.sel
= 0b10
2632 selector
.inv
= self
.pred
.inv
2633 if not self
.record
.svp64
.extra_CR_3bit
:
2634 selector
.CR
= self
.pred
.state
2636 selector
.mode
.sel
= 0b01 if self
.mode
== "ff" else 0b11
2637 selector
.inv
= self
.pred
.inv
2639 selector
.CR
= self
.pred
.state
2641 selector
.RC1
= self
.pred
.state
2644 @_dataclasses.dataclass(eq
=True, frozen
=True)
2645 class SpecifierFF(SpecifierFFPR
):
2647 def match(cls
, desc
, record
):
2648 return super().match(desc
=desc
, record
=record
, mode
="ff")
2651 @_dataclasses.dataclass(eq
=True, frozen
=True)
2652 class SpecifierPR(SpecifierFFPR
):
2654 def match(cls
, desc
, record
):
2655 return super().match(desc
=desc
, record
=record
, mode
="pr")
2658 @_dataclasses.dataclass(eq
=True, frozen
=True)
2659 class SpecifierMask(SpecifierPredicate
):
2661 def match(cls
, desc
, record
, mode
):
2662 return super().match(desc
=desc
, record
=record
,
2663 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2664 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2669 def assemble(self
, insn
):
2670 raise NotImplementedError()
2673 @_dataclasses.dataclass(eq
=True, frozen
=True)
2674 class SpecifierM(SpecifierMask
):
2676 def match(cls
, desc
, record
):
2677 return super().match(desc
=desc
, record
=record
, mode
="m")
2679 def validate(self
, others
):
2681 if isinstance(spec
, SpecifierSM
):
2682 raise ValueError("source-mask and predicate mask conflict")
2683 elif isinstance(spec
, SpecifierDM
):
2684 raise ValueError("dest-mask and predicate mask conflict")
2686 def assemble(self
, insn
):
2687 selector
= insn
.select(record
=self
.record
)
2688 selector
.mask
= int(self
.pred
)
2689 if ((self
.record
.ptype
is _SVPType
.P2
) and
2690 (self
.record
.svp64
.mode
is not _SVMode
.BRANCH
)):
2691 selector
.smask
= int(self
.pred
)
2692 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2695 @_dataclasses.dataclass(eq
=True, frozen
=True)
2696 class SpecifierSM(SpecifierMask
):
2698 def match(cls
, desc
, record
):
2699 return super().match(desc
=desc
, record
=record
, mode
="sm")
2701 def validate(self
, others
):
2702 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2703 raise ValueError("source-mask on non-twin predicate")
2705 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2708 if isinstance(spec
, SpecifierDM
):
2712 raise ValueError("missing dest-mask in CR twin predication")
2713 if self
.pred
.mode
!= twin
.pred
.mode
:
2714 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2716 def assemble(self
, insn
):
2717 selector
= insn
.select(record
=self
.record
)
2718 selector
.smask
= int(self
.pred
)
2719 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2722 @_dataclasses.dataclass(eq
=True, frozen
=True)
2723 class SpecifierDM(SpecifierMask
):
2725 def match(cls
, desc
, record
):
2726 return super().match(desc
=desc
, record
=record
, mode
="dm")
2728 def validate(self
, others
):
2729 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2730 raise ValueError("dest-mask on non-twin predicate")
2732 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2735 if isinstance(spec
, SpecifierSM
):
2739 raise ValueError("missing source-mask in CR twin predication")
2740 if self
.pred
.mode
!= twin
.pred
.mode
:
2741 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2743 def assemble(self
, insn
):
2744 selector
= insn
.select(record
=self
.record
)
2745 selector
.mask
= int(self
.pred
)
2746 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2749 @_dataclasses.dataclass(eq
=True, frozen
=True)
2750 class SpecifierZZ(Specifier
):
2752 def match(cls
, desc
, record
):
2756 return cls(record
=record
)
2758 def validate(self
, others
):
2760 # Since zz takes precedence (overrides) sz and dz,
2761 # treat them as mutually exclusive.
2762 if isinstance(spec
, (SpecifierSZ
, SpecifierDZ
)):
2763 raise ValueError("mutually exclusive predicate masks")
2765 def assemble(self
, insn
):
2766 selector
= insn
.select(record
=self
.record
)
2767 if hasattr(selector
, "zz"): # this should be done in a different way
2774 @_dataclasses.dataclass(eq
=True, frozen
=True)
2775 class SpecifierXZ(Specifier
):
2777 hint
: str = _dataclasses
.field(repr=False)
2780 def match(cls
, desc
, record
, etalon
, hint
):
2784 return cls(desc
=desc
, record
=record
, hint
=hint
)
2786 def validate(self
, others
):
2787 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2788 raise ValueError(f
"{self.hint} on non-twin predicate")
2790 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2793 if isinstance(spec
, SpecifierXZ
):
2797 raise ValueError(f
"missing {self.hint} in CR twin predication")
2798 if self
.pred
!= twin
.pred
:
2799 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2801 def assemble(self
, insn
):
2802 selector
= insn
.select(record
=self
.record
)
2803 setattr(selector
, self
.desc
, 1)
2806 @_dataclasses.dataclass(eq
=True, frozen
=True)
2807 class SpecifierSZ(SpecifierXZ
):
2809 def match(cls
, desc
, record
):
2810 return super().match(desc
=desc
, record
=record
,
2811 etalon
="sz", hint
="source-mask")
2813 def validate(self
, others
):
2815 if self
.record
.svp64
.mode
is not _SVMode
.CROP
:
2816 if isinstance(spec
, SpecifierFF
):
2817 raise ValueError("source-zero not allowed in ff mode")
2818 elif isinstance(spec
, SpecifierPR
):
2819 raise ValueError("source-zero not allowed in pr mode")
2822 @_dataclasses.dataclass(eq
=True, frozen
=True)
2823 class SpecifierDZ(SpecifierXZ
):
2825 def match(cls
, desc
, record
):
2826 return super().match(desc
=desc
, record
=record
,
2827 etalon
="dz", hint
="dest-mask")
2829 def validate(self
, others
):
2831 if ((self
.record
.svp64
.mode
is not _SVMode
.CROP
) and
2832 isinstance(spec
, (SpecifierFF
, SpecifierPR
)) and
2833 (spec
.pred
.mode
is _SVP64PredMode
.RC1
)):
2834 mode
= "ff" if isinstance(spec
, SpecifierFF
) else "pr"
2835 raise ValueError(f
"dest-zero not allowed in {mode} mode BO")
2838 @_dataclasses.dataclass(eq
=True, frozen
=True)
2839 class SpecifierEls(Specifier
):
2841 def match(cls
, desc
, record
):
2845 if record
.svp64
.mode
not in (_SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
):
2846 raise ValueError("els is only valid in ld/st modes")
2848 return cls(record
=record
)
2850 def assemble(self
, insn
):
2851 if self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
: # stride mode
2852 insn
.prefix
.rm
.mode
[0] = 0
2853 insn
.prefix
.rm
.mode
[1] = 1
2855 selector
= insn
.select(record
=self
.record
)
2856 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
: # stride mode
2861 @_dataclasses.dataclass(eq
=True, frozen
=True)
2862 class SpecifierSEA(Specifier
):
2864 def match(cls
, desc
, record
):
2868 return cls(record
=record
)
2870 def validate(self
, others
):
2871 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
:
2872 raise ValueError("sea is only valid in ld/st modes")
2875 if isinstance(spec
, SpecifierFF
):
2876 raise ValueError(f
"sea cannot be used in ff mode")
2878 def assemble(self
, insn
):
2879 selector
= insn
.select(record
=self
.record
)
2880 if selector
.mode
.sel
not in (0b00, 0b01):
2881 raise ValueError("sea is only valid for normal and els modes")
2885 @_dataclasses.dataclass(eq
=True, frozen
=True)
2886 class SpecifierSat(Specifier
):
2891 def match(cls
, desc
, record
, etalon
, sign
):
2895 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
):
2896 raise ValueError("only normal, ld/st imm and ld/st idx modes supported")
2898 return cls(record
=record
, desc
=desc
, sign
=sign
)
2900 def assemble(self
, insn
):
2901 selector
= insn
.select(record
=self
.record
)
2902 selector
.mode
[0] = 0b1
2903 selector
.mode
[1] = 0b0
2904 selector
.N
= int(self
.sign
)
2907 @_dataclasses.dataclass(eq
=True, frozen
=True)
2908 class SpecifierSatS(SpecifierSat
):
2910 def match(cls
, desc
, record
):
2911 return super().match(desc
=desc
, record
=record
,
2912 etalon
="sats", sign
=True)
2915 @_dataclasses.dataclass(eq
=True, frozen
=True)
2916 class SpecifierSatU(SpecifierSat
):
2918 def match(cls
, desc
, record
):
2919 return super().match(desc
=desc
, record
=record
,
2920 etalon
="satu", sign
=False)
2923 @_dataclasses.dataclass(eq
=True, frozen
=True)
2924 class SpecifierMapReduce(Specifier
):
2928 def match(cls
, record
, RG
):
2929 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2930 raise ValueError("only normal and crop modes supported")
2932 return cls(record
=record
, RG
=RG
)
2934 def assemble(self
, insn
):
2935 selector
= insn
.select(record
=self
.record
)
2936 if self
.record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2937 raise ValueError("only normal and crop modes supported")
2938 selector
.mode
[0] = 0
2939 selector
.mode
[1] = 0
2940 selector
.mode
[2] = 1
2941 selector
.RG
= self
.RG
2944 @_dataclasses.dataclass(eq
=True, frozen
=True)
2945 class SpecifierMR(SpecifierMapReduce
):
2947 def match(cls
, desc
, record
):
2951 return super().match(record
=record
, RG
=False)
2954 @_dataclasses.dataclass(eq
=True, frozen
=True)
2955 class SpecifierMRR(SpecifierMapReduce
):
2957 def match(cls
, desc
, record
):
2961 return super().match(record
=record
, RG
=True)
2964 @_dataclasses.dataclass(eq
=True, frozen
=True)
2965 class SpecifierBranch(Specifier
):
2967 def match(cls
, desc
, record
, etalon
):
2971 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
2972 raise ValueError("only branch modes supported")
2974 return cls(record
=record
)
2977 @_dataclasses.dataclass(eq
=True, frozen
=True)
2978 class SpecifierAll(SpecifierBranch
):
2980 def match(cls
, desc
, record
):
2981 return super().match(desc
=desc
, record
=record
, etalon
="all")
2983 def assemble(self
, insn
):
2984 selector
= insn
.select(record
=self
.record
)
2988 @_dataclasses.dataclass(eq
=True, frozen
=True)
2989 class SpecifierSNZ(Specifier
):
2991 def match(cls
, desc
, record
):
2995 if record
.svp64
.mode
not in (_SVMode
.BRANCH
, _SVMode
.CROP
):
2996 raise ValueError("only branch and crop modes supported")
2998 return cls(record
=record
)
3000 def assemble(self
, insn
):
3001 selector
= insn
.select(record
=self
.record
)
3002 if self
.record
.svp64
.mode
in (_SVMode
.CROP
, _SVMode
.BRANCH
):
3004 if self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
3007 raise ValueError("only branch and crop modes supported")
3010 @_dataclasses.dataclass(eq
=True, frozen
=True)
3011 class SpecifierSL(SpecifierBranch
):
3013 def match(cls
, desc
, record
):
3014 return super().match(desc
=desc
, record
=record
, etalon
="sl")
3016 def assemble(self
, insn
):
3017 selector
= insn
.select(record
=self
.record
)
3021 @_dataclasses.dataclass(eq
=True, frozen
=True)
3022 class SpecifierSLu(SpecifierBranch
):
3024 def match(cls
, desc
, record
):
3025 return super().match(desc
=desc
, record
=record
, etalon
="slu")
3027 def assemble(self
, insn
):
3028 selector
= insn
.select(record
=self
.record
)
3032 @_dataclasses.dataclass(eq
=True, frozen
=True)
3033 class SpecifierLRu(SpecifierBranch
):
3035 def match(cls
, desc
, record
):
3036 return super().match(desc
=desc
, record
=record
, etalon
="lru")
3038 def assemble(self
, insn
):
3039 selector
= insn
.select(record
=self
.record
)
3043 @_dataclasses.dataclass(eq
=True, frozen
=True)
3044 class SpecifierVSXX(SpecifierBranch
):
3049 def match(cls
, desc
, record
, etalon
, VSb
, VLi
):
3053 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3054 raise ValueError("only branch modes supported")
3056 return cls(record
=record
, VSb
=VSb
, VLi
=VLi
)
3058 def assemble(self
, insn
):
3059 selector
= insn
.select(record
=self
.record
)
3061 selector
.VSb
= int(self
.VSb
)
3062 selector
.VLi
= int(self
.VLi
)
3065 @_dataclasses.dataclass(eq
=True, frozen
=True)
3066 class SpecifierVS(SpecifierVSXX
):
3068 def match(cls
, desc
, record
):
3069 return super().match(desc
=desc
, record
=record
,
3070 etalon
="vs", VSb
=False, VLi
=False)
3073 @_dataclasses.dataclass(eq
=True, frozen
=True)
3074 class SpecifierVSi(SpecifierVSXX
):
3076 def match(cls
, desc
, record
):
3077 return super().match(desc
=desc
, record
=record
,
3078 etalon
="vsi", VSb
=False, VLi
=True)
3081 @_dataclasses.dataclass(eq
=True, frozen
=True)
3082 class SpecifierVSb(SpecifierVSXX
):
3084 def match(cls
, desc
, record
):
3085 return super().match(desc
=desc
, record
=record
,
3086 etalon
="vsb", VSb
=True, VLi
=False)
3089 @_dataclasses.dataclass(eq
=True, frozen
=True)
3090 class SpecifierVSbi(SpecifierVSXX
):
3092 def match(cls
, desc
, record
):
3093 return super().match(desc
=desc
, record
=record
,
3094 etalon
="vsbi", VSb
=True, VLi
=True)
3097 @_dataclasses.dataclass(eq
=True, frozen
=True)
3098 class SpecifierCTX(Specifier
):
3102 def match(cls
, desc
, record
, etalon
, CTi
):
3106 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3107 raise ValueError("only branch modes supported")
3109 return cls(record
=record
, CTi
=CTi
)
3111 def assemble(self
, insn
):
3112 selector
= insn
.select(record
=self
.record
)
3114 selector
.CTi
= int(self
.CTi
)
3117 @_dataclasses.dataclass(eq
=True, frozen
=True)
3118 class SpecifierCTR(SpecifierCTX
):
3120 def match(cls
, desc
, record
):
3121 return super().match(desc
=desc
, record
=record
,
3122 etalon
="ctr", CTi
=False)
3125 @_dataclasses.dataclass(eq
=True, frozen
=True)
3126 class SpecifierCTi(SpecifierCTX
):
3128 def match(cls
, desc
, record
):
3129 return super().match(desc
=desc
, record
=record
,
3130 etalon
="cti", CTi
=True)
3133 @_dataclasses.dataclass(eq
=True, frozen
=True)
3134 class SpecifierPI(Specifier
):
3136 def match(cls
, desc
, record
):
3140 if record
.svp64
.mode
is not _SVMode
.LDST_IMM
:
3141 raise ValueError("only ld/st imm mode supported")
3143 return cls(record
=record
)
3145 def assemble(self
, insn
):
3146 selector
= insn
.select(record
=self
.record
)
3147 selector
.mode
[0] = 0b0
3148 selector
.mode
[1] = 0b0
3149 selector
.mode
[2] = 0b1
3153 @_dataclasses.dataclass(eq
=True, frozen
=True)
3154 class SpecifierLF(Specifier
):
3156 def match(cls
, desc
, record
):
3160 if record
.svp64
.mode
is not _SVMode
.LDST_IMM
:
3161 raise ValueError("only ld/st imm mode supported")
3163 return cls(record
=record
)
3165 def assemble(self
, insn
):
3166 selector
= insn
.select(record
=self
.record
)
3167 selector
.mode
[2] = 1
3171 @_dataclasses.dataclass(eq
=True, frozen
=True)
3172 class SpecifierVLi(Specifier
):
3174 def match(cls
, desc
, record
):
3178 return cls(record
=record
)
3180 def validate(self
, others
):
3182 if isinstance(spec
, SpecifierFF
):
3185 raise ValueError("VLi only allowed in failfirst")
3187 def assemble(self
, insn
):
3188 selector
= insn
.select(record
=self
.record
)
3192 class Specifiers(tuple):
3228 def __new__(cls
, items
, record
):
3229 def transform(item
):
3230 for spec_cls
in cls
.SPECS
:
3231 spec
= spec_cls
.match(item
, record
=record
)
3232 if spec
is not None:
3234 raise ValueError(item
)
3236 # TODO: remove this hack
3237 items
= dict.fromkeys(items
)
3241 items
= tuple(items
)
3243 specs
= tuple(map(transform
, items
))
3244 for (index
, spec
) in enumerate(specs
):
3245 head
= specs
[:index
]
3246 tail
= specs
[index
+ 1:]
3247 spec
.validate(others
=(head
+ tail
))
3249 return super().__new
__(cls
, specs
)
3252 class SVP64OperandMeta(type):
3253 class SVP64NonZeroOperand(NonZeroOperand
):
3254 def assemble(self
, insn
, value
):
3255 if isinstance(value
, str):
3256 value
= int(value
, 0)
3257 if not isinstance(value
, int):
3258 raise ValueError("non-integer operand")
3260 # FIXME: this is really weird
3261 if self
.record
.name
in ("svstep", "svstep."):
3262 value
+= 1 # compensation
3264 return super().assemble(value
=value
, insn
=insn
)
3266 class SVP64XOStaticOperand(SpanStaticOperand
):
3267 def __init__(self
, record
, value
, span
):
3268 return super().__init
__(record
=record
, name
="XO", value
=value
, span
=span
)
3271 NonZeroOperand
: SVP64NonZeroOperand
,
3272 XOStaticOperand
: SVP64XOStaticOperand
,
3275 def __new__(metacls
, name
, bases
, ns
):
3277 for (index
, base_cls
) in enumerate(bases
):
3278 bases
[index
] = metacls
.__TRANSFORM
.get(base_cls
, base_cls
)
3280 bases
= tuple(bases
)
3282 return super().__new
__(metacls
, name
, bases
, ns
)
3285 class SVP64Operand(Operand
, metaclass
=SVP64OperandMeta
):
3288 return tuple(map(lambda bit
: (bit
+ 32), super().span
))
3292 def __init__(self
, insn
, record
):
3294 self
.__record
= record
3295 return super().__init
__()
3298 return self
.rm
.__doc
__
3301 return repr(self
.rm
)
3309 return self
.__record
3313 rm
= getattr(self
.insn
.prefix
.rm
, self
.record
.svp64
.mode
.name
.lower())
3315 # The idea behind these tables is that they are now literally
3316 # in identical format to insndb.csv and minor_xx.csv and can
3317 # be done precisely as that. The only thing to watch out for
3318 # is the insertion of Rc=1 as a "mask/value" bit and likewise
3319 # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
3322 if self
.record
.svp64
.mode
is _SVMode
.NORMAL
:
3323 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3324 # mode Rc mask Rc member
3326 (0b000000, 0b111000, "simple"), # simple (no Rc)
3327 (0b001000, 0b111000, "mr"), # mapreduce (no Rc)
3328 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
3329 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
3330 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3331 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3332 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3334 search
= ((int(self
.insn
.prefix
.rm
.normal
.mode
) << 1) | self
.record
.Rc
)
3336 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IMM
:
3337 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3338 # mode Rc mask Rc member
3339 # ironically/coincidentally this table is identical to NORMAL
3340 # mode except reserved in place of mr
3342 (0b000000, 0b111000, "simple"), # simple (no Rc)
3343 (0b001000, 0b111000, "post"), # post (no Rc)
3344 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
3345 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
3346 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3347 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3348 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3350 search
= ((int(self
.insn
.prefix
.rm
.ldst_imm
.mode
) << 1) | self
.record
.Rc
)
3352 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
3353 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3354 # mode Rc mask Rc member
3356 (0b000000, 0b110000, "simple"), # simple (no Rc)
3357 (0b010000, 0b110000, "stride"), # strided, (no Rc)
3358 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3359 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3360 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3362 search
= ((int(self
.insn
.prefix
.rm
.ldst_idx
.mode
) << 1) | self
.record
.Rc
)
3364 elif self
.record
.svp64
.mode
is _SVMode
.CROP
:
3365 # concatenate mode 5-bit with regtype (LSB) then do mask/map search
3366 # mode 3b mask 3b member
3368 (0b000000, 0b111000, "simple"), # simple
3369 (0b001000, 0b111000, "mr"), # mapreduce
3370 (0b100001, 0b100001, "ff3"), # ffirst, 3-bit CR
3371 (0b100000, 0b100000, "ff5"), # ffirst, 5-bit CR
3373 search
= ((int(self
.insn
.prefix
.rm
.crop
.mode
) << 1) |
int(self
.record
.svp64
.extra_CR_3bit
))
3375 elif self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
3379 (0b00, 0b11, "simple"), # simple
3380 (0b01, 0b11, "vls"), # VLset
3381 (0b10, 0b11, "ctr"), # CTR mode
3382 (0b11, 0b11, "ctrvls"), # CTR+VLset mode
3384 # slightly weird: doesn't have a 5-bit "mode" field like others
3385 search
= int(self
.insn
.prefix
.rm
.branch
.mode
.sel
)
3388 if table
is not None:
3389 for (value
, mask
, field
) in table
:
3390 if ((value
& mask
) == (search
& mask
)):
3391 return getattr(rm
, field
)
3395 def __getattr__(self
, key
):
3396 if key
.startswith(f
"_{self.__class__.__name__}__"):
3397 return super().__getattribute
__(key
)
3399 return getattr(self
.rm
, key
)
3401 def __setattr__(self
, key
, value
):
3402 if key
.startswith(f
"_{self.__class__.__name__}__"):
3403 return super().__setattr
__(key
, value
)
3406 if not hasattr(rm
, key
):
3407 raise AttributeError(key
)
3409 return setattr(rm
, key
, value
)
3412 class SVP64Instruction(PrefixedInstruction
):
3413 """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
3414 class Prefix(PrefixedInstruction
.Prefix
):
3416 rm
: RM
.remap((6, 8) + tuple(range(10, 32)))
3420 def select(self
, record
):
3421 return RMSelector(insn
=self
, record
=record
)
3426 for idx
in range(64):
3427 bit
= int(self
[idx
])
3429 return "".join(map(str, bits
))
3432 def assemble(cls
, record
, arguments
=None, specifiers
=None):
3433 insn
= super().assemble(record
=record
, arguments
=arguments
)
3435 specifiers
= Specifiers(items
=specifiers
, record
=record
)
3436 for specifier
in specifiers
:
3437 specifier
.assemble(insn
=insn
)
3439 insn
.prefix
.PO
= 0x1
3440 insn
.prefix
.id = 0x3
3444 def disassemble(self
, record
,
3446 style
=Style
.NORMAL
):
3448 if style
<= Style
.SHORT
:
3451 blob
= insn
.bytes(byteorder
=byteorder
)
3452 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
3455 blob_prefix
= blob(self
.prefix
)
3456 blob_suffix
= blob(self
.suffix
)
3458 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3459 yield f
"{blob_suffix}.long 0x{int(self.suffix):08x}"
3462 assert record
.svp64
is not None
3464 name
= f
"sv.{record.name}"
3466 rm
= self
.select(record
=record
)
3468 # convert specifiers to /x/y/z (sorted lexicographically)
3469 specifiers
= sorted(rm
.specifiers(record
=record
))
3470 if specifiers
: # if any add one extra to get the extra "/"
3471 specifiers
= ([""] + specifiers
)
3472 specifiers
= "/".join(specifiers
)
3474 # convert operands to " ,x,y,z"
3475 operands
= tuple(map(_operator
.itemgetter(1),
3476 self
.spec_dynamic_operands(record
=record
, style
=style
)))
3477 operands
= ",".join(operands
)
3478 if len(operands
) > 0: # if any separate with a space
3479 operands
= (" " + operands
)
3481 if style
<= Style
.LEGACY
:
3482 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3483 suffix
= WordInstruction
.integer(value
=int(self
.suffix
))
3484 yield from suffix
.disassemble(record
=record
,
3485 byteorder
=byteorder
, style
=style
)
3487 yield f
"{blob_prefix}{name}{specifiers}{operands}"
3489 yield f
"{blob_suffix}"
3491 if style
>= Style
.VERBOSE
:
3493 binary
= self
.binary
3494 spec
= self
.spec(record
=record
, prefix
="sv.")
3496 yield f
"{indent}spec"
3497 yield f
"{indent}{indent}{spec}"
3498 yield f
"{indent}pcode"
3499 for stmt
in record
.mdwn
.pcode
:
3500 yield f
"{indent}{indent}{stmt}"
3501 yield f
"{indent}binary"
3502 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
3503 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
3504 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
3505 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
3506 yield f
"{indent}{indent}[32:40] {binary[32:40]}"
3507 yield f
"{indent}{indent}[40:48] {binary[40:48]}"
3508 yield f
"{indent}{indent}[48:56] {binary[48:56]}"
3509 yield f
"{indent}{indent}[56:64] {binary[56:64]}"
3510 yield f
"{indent}opcodes"
3511 for opcode
in record
.opcodes
:
3512 yield f
"{indent}{indent}{opcode!r}"
3513 for operand
in self
.operands(record
=record
):
3514 yield from operand
.disassemble(insn
=self
,
3515 style
=style
, indent
=indent
)
3517 yield f
"{indent}{indent}{str(rm)}"
3518 for line
in rm
.disassemble(style
=style
):
3519 yield f
"{indent}{indent}{line}"
3523 def operands(cls
, record
):
3524 for operand
in super().operands(record
=record
):
3525 parent
= operand
.__class
__
3526 name
= f
"SVP64{parent.__name__}"
3527 bases
= (SVP64Operand
, parent
)
3528 child
= type(name
, bases
, {})
3529 yield child(**dict(operand
))
3532 def parse(stream
, factory
):
3534 return ("TODO" not in frozenset(entry
.values()))
3536 lines
= filter(lambda line
: not line
.strip().startswith("#"), stream
)
3537 entries
= _csv
.DictReader(lines
)
3538 entries
= filter(match
, entries
)
3539 return tuple(map(factory
, entries
))
3542 class MarkdownDatabase
:
3545 for (name
, desc
) in _ISA():
3548 (dynamic
, *static
) = desc
.regs
3549 operands
.extend(dynamic
)
3550 operands
.extend(static
)
3551 pcode
= PCode(iterable
=desc
.pcode
)
3552 operands
= Operands(insn
=name
, iterable
=operands
)
3553 db
[name
] = MarkdownRecord(pcode
=pcode
, operands
=operands
)
3555 self
.__db
= dict(sorted(db
.items()))
3557 return super().__init
__()
3560 yield from self
.__db
.items()
3562 def __contains__(self
, key
):
3563 return self
.__db
.__contains
__(key
)
3565 def __getitem__(self
, key
):
3566 return self
.__db
.__getitem
__(key
)
3569 class FieldsDatabase
:
3572 df
= _DecodeFields()
3574 for (form
, fields
) in df
.instrs
.items():
3575 if form
in {"DQE", "TX"}:
3579 db
[_Form
[form
]] = Fields(fields
)
3583 return super().__init
__()
3585 def __getitem__(self
, key
):
3586 return self
.__db
.__getitem
__(key
)
3590 def __init__(self
, root
, mdwndb
):
3591 # The code below groups the instructions by name:section.
3592 # There can be multiple names for the same instruction.
3593 # The point is to capture different opcodes for the same instruction.
3595 records
= _collections
.defaultdict(set)
3596 path
= (root
/ "insndb.csv")
3597 with
open(path
, "r", encoding
="UTF-8") as stream
:
3598 for section
in sorted(parse(stream
, Section
.CSV
)):
3599 path
= (root
/ section
.path
)
3601 section
.Mode
.INTEGER
: IntegerOpcode
,
3602 section
.Mode
.PATTERN
: PatternOpcode
,
3604 factory
= _functools
.partial(
3605 PPCRecord
.CSV
, opcode_cls
=opcode_cls
)
3606 with
open(path
, "r", encoding
="UTF-8") as stream
:
3607 for insn
in parse(stream
, factory
):
3608 for name
in insn
.names
:
3609 records
[name
].add(insn
)
3610 sections
[name
] = section
3612 items
= sorted(records
.items())
3614 for (name
, multirecord
) in items
:
3615 records
[name
] = PPCMultiRecord(sorted(multirecord
))
3617 def exact_match(name
):
3618 record
= records
.get(name
)
3624 if not name
.endswith("l"):
3626 alias
= exact_match(name
[:-1])
3629 record
= records
[alias
]
3630 if "lk" not in record
.flags
:
3631 raise ValueError(record
)
3635 if not name
.endswith("a"):
3637 alias
= LK_match(name
[:-1])
3640 record
= records
[alias
]
3641 if record
.intop
not in {_MicrOp
.OP_B
, _MicrOp
.OP_BC
}:
3642 raise ValueError(record
)
3643 if "AA" not in mdwndb
[name
].operands
:
3644 raise ValueError(record
)
3648 if not name
.endswith("."):
3650 alias
= exact_match(name
[:-1])
3653 record
= records
[alias
]
3654 if record
.Rc
is _RCOE
.NONE
:
3655 raise ValueError(record
)
3659 matches
= (exact_match
, LK_match
, AA_match
, Rc_match
)
3660 for (name
, _
) in mdwndb
:
3661 if name
.startswith("sv."):
3664 for match
in matches
:
3666 if alias
is not None:
3670 section
= sections
[alias
]
3671 record
= records
[alias
]
3672 db
[name
] = (section
, record
)
3674 self
.__db
= dict(sorted(db
.items()))
3676 return super().__init
__()
3678 @_functools.lru_cache(maxsize
=512, typed
=False)
3679 def __getitem__(self
, key
):
3680 return self
.__db
.get(key
, (None, None))
3683 class SVP64Database
:
3684 def __init__(self
, root
, ppcdb
):
3686 pattern
= _re
.compile(r
"^(?:LDST)?RM-(1P|2P)-.*?\.csv$")
3687 for (prefix
, _
, names
) in _os
.walk(root
):
3688 prefix
= _pathlib
.Path(prefix
)
3689 for name
in filter(lambda name
: pattern
.match(name
), names
):
3690 path
= (prefix
/ _pathlib
.Path(name
))
3691 with
open(path
, "r", encoding
="UTF-8") as stream
:
3692 db
.update(parse(stream
, SVP64Record
.CSV
))
3693 db
= {record
.name
:record
for record
in db
}
3695 self
.__db
= dict(sorted(db
.items()))
3696 self
.__ppcdb
= ppcdb
3698 return super().__init
__()
3700 def __getitem__(self
, key
):
3701 (_
, record
) = self
.__ppcdb
[key
]
3705 for name
in record
.names
:
3706 record
= self
.__db
.get(name
, None)
3707 if record
is not None:
3714 def __init__(self
, root
):
3715 root
= _pathlib
.Path(root
)
3716 mdwndb
= MarkdownDatabase()
3717 fieldsdb
= FieldsDatabase()
3718 ppcdb
= PPCDatabase(root
=root
, mdwndb
=mdwndb
)
3719 svp64db
= SVP64Database(root
=root
, ppcdb
=ppcdb
)
3723 opcodes
= _collections
.defaultdict(
3724 lambda: _collections
.defaultdict(set))
3726 for (name
, mdwn
) in mdwndb
:
3727 if name
.startswith("sv."):
3729 (section
, ppc
) = ppcdb
[name
]
3732 svp64
= svp64db
[name
]
3733 fields
= fieldsdb
[ppc
.form
]
3734 record
= Record(name
=name
,
3735 section
=section
, ppc
=ppc
, svp64
=svp64
,
3736 mdwn
=mdwn
, fields
=fields
)
3738 names
[record
.name
] = record
3739 opcodes
[section
][record
.PO
].add(record
)
3741 self
.__db
= sorted(db
)
3742 self
.__names
= dict(sorted(names
.items()))
3743 self
.__opcodes
= dict(sorted(opcodes
.items()))
3745 return super().__init
__()
3748 return repr(self
.__db
)
3751 yield from self
.__db
3753 @_functools.lru_cache(maxsize
=None)
3754 def __contains__(self
, key
):
3755 return self
.__getitem
__(key
) is not None
3757 @_functools.lru_cache(maxsize
=None)
3758 def __getitem__(self
, key
):
3759 if isinstance(key
, SVP64Instruction
):
3762 if isinstance(key
, Instruction
):
3765 sections
= sorted(self
.__opcodes
)
3766 for section
in sections
:
3767 group
= self
.__opcodes
[section
]
3768 for record
in group
[PO
]:
3769 if record
.match(key
=key
):
3774 elif isinstance(key
, str):
3775 return self
.__names
.get(key
)
3777 raise ValueError("instruction or name expected")